diff --git a/.gitignore b/.gitignore index 43537b136..7286a98ba 100644 --- a/.gitignore +++ b/.gitignore @@ -24,6 +24,7 @@ *.c128 *.c64 *.cc2538dk +*.ev-aducrf101mkxz *.report summary *.summary diff --git a/.travis.yml b/.travis.yml index f50de9382..2ebcdf4b3 100644 --- a/.travis.yml +++ b/.travis.yml @@ -29,6 +29,15 @@ before_script: arm-none-eabi-gcc --version ; fi + ## Install mainline ARM toolchain. gcc-arm-none-eabi is available + ## in Ubuntu >= 14.04, but this external PPA is needed for 12.04. + - if [ ${BUILD_ARCH:-0} = arm ] ; then + sudo add-apt-repository -y ppa:terry.guo/gcc-arm-embedded && + sudo apt-get -qq update && + sudo apt-get -qq install gcc-arm-none-eabi && + arm-none-eabi-gcc --version ; + fi + ## Install RL78 GCC toolchain - sudo apt-get install libncurses5:i386 zlib1g:i386 - $WGET http://adamdunkels.github.io/contiki-fork/gnurl78-v13.02-elf_1-2_i386.deb && @@ -67,7 +76,7 @@ script: after_script: ## Print cooja test logs - "[ ${BUILD_CATEGORY:-sim} = sim ] && tail regression-tests/??-$BUILD_TYPE/*.testlog" - ## Print a basic summary + ## Print a basic summary - "echo 'Summary:'; cat regression-tests/??-$BUILD_TYPE/summary" - "FAILS=`grep -c -i 'fail' regression-tests/??-$BUILD_TYPE/summary`" ## This will detect whether the build should pass or fail @@ -95,4 +104,5 @@ env: - BUILD_TYPE='compile-8051-ports' BUILD_CATEGORY='compile' BUILD_ARCH='8051' - BUILD_TYPE='compile-arm-apcs-ports' BUILD_CATEGORY='compile' BUILD_ARCH='arm-apcs' - BUILD_TYPE='compile-6502-ports' BUILD_CATEGORY='compile' BUILD_ARCH='6502' + - BUILD_TYPE='compile-arm-ports' BUILD_CATEGORY='compile' BUILD_ARCH='arm' - BUILD_TYPE='slip-radio' MAKE_TARGETS='cooja' diff --git a/cpu/arm/aducrf101/Common/ADuCRF101.h b/cpu/arm/aducrf101/Common/ADuCRF101.h new file mode 100644 index 000000000..7126fdae3 --- /dev/null +++ b/cpu/arm/aducrf101/Common/ADuCRF101.h @@ -0,0 +1,9879 @@ +/** + * Copyright (c) 2014, Analog Devices, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/****************************************************************************************************//** + * @file ADUCRF101.h + * + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for + * default ADUCRF101 Device Series + * + * @version V1.0 + * @date Thursday January 10 2013 15:30 + * + *******************************************************************************************************/ + + + +/** @addtogroup Analog Devices Inc. + * @{ + */ + +/** @addtogroup ADUCRF101 + * @{ + */ + +#ifndef __ADUCRF101_H__ +#define __ADUCRF101_H__ + +#ifndef __NO_MMR_STRUCTS__ +// The new style CMSIS structure definitions for MMRs clash with +// the old style defs. If the old style are required for compilation +// then set __NO_MMR_STRUCTS__ to 0x1 +#define __NO_MMR_STRUCTS__ 0x0 +#endif + +#ifdef __cplusplus +extern "C" { +#endif + + +/* ------------------------- Interrupt Number Definition ------------------------ */ + +typedef enum { +/* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */ + Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ + PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ + SysTick_IRQn = -1, /*!< 15 System Tick Timer */ +// -------------------------- ADUCRF101 Specific Interrupt Numbers ------------------------------ + WUT_IRQn = 0, /*!< 0 WUT */ + EINT0_IRQn = 1, /*!< 1 EINT0 */ + EINT1_IRQn = 2, /*!< 2 EINT1 */ + EINT2_IRQn = 3, /*!< 3 EINT2 */ + EINT3_IRQn = 4, /*!< 4 EINT3 */ + EINT4_IRQn = 5, /*!< 5 EINT4 */ + EINT5_IRQn = 6, /*!< 6 EINT5 */ + EINT6_IRQn = 7, /*!< 7 EINT6 */ + EINT7_IRQn = 8, /*!< 8 EINT7 */ + EINT8_IRQn = 9, /*!< 9 EINT8 */ + UHFTRX_IRQn = 9, /*!< 9 UHFTRX */ + WDT_IRQn = 10, /*!< 10 WDT */ + TIMER0_IRQn = 12, /*!< 12 TIMER0 */ + TIMER1_IRQn = 13, /*!< 13 TIMER1 */ + ADC0_IRQn = 14, /*!< 14 ADC0 */ + FLASH_IRQn = 15, /*!< 15 FLASH */ + UART_IRQn = 16, /*!< 16 UART */ + SPI0_IRQn = 17, /*!< 17 SPI0 */ + SPI1_IRQn = 18, /*!< 18 SPI1 */ + I2CS_IRQn = 19, /*!< 19 I2CS */ + I2CM_IRQn = 20, /*!< 20 I2CM */ + DMA_ERR_IRQn = 23, /*!< 23 DMA_ERR */ + DMA_SPI1_TX_IRQn = 24, /*!< 24 DMA_SPI1_TX */ + DMA_SPI1_RX_IRQn = 25, /*!< 25 DMA_SPI1_RX */ + DMA_UART_TX_IRQn = 26, /*!< 26 DMA_UART_TX */ + DMA_UART_RX_IRQn = 27, /*!< 27 DMA_UART_RX */ + DMA_I2CS_TX_IRQn = 28, /*!< 28 DMA_I2CS_TX */ + DMA_I2CS_RX_IRQn = 29, /*!< 29 DMA_I2CS_RX */ + DMA_I2CM_TX_IRQn = 30, /*!< 30 DMA_I2CM_TX */ + DMA_I2CM_RX_IRQn = 31, /*!< 31 DMA_I2CM_RX */ + DMA_ADC0_IRQn = 35, /*!< 35 DMA_ADC0 */ + DMA_SPI0_TX_IRQn = 36, /*!< 36 DMA_SPI0_TX */ + DMA_SPI0_RX_IRQn = 37, /*!< 37 DMA_SPI0_RX */ + PWM_TRIP_IRQn = 38, /*!< 38 PWM_TRIP */ + PWM_PAIR0_IRQn = 39, /*!< 39 PWM_PAIR0 */ + PWM_PAIR1_IRQn = 40, /*!< 40 PWM_PAIR1 */ + PWM_PAIR2_IRQn = 41, /*!< 41 PWM_PAIR2 */ + PWM_PAIR3_IRQn = 42 /*!< 42 PWM_PAIR3 */ +} IRQn_Type; + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +/* ----------------Configuration of the cm3 Processor and Core Peripherals---------------- */ + +#define __CM3_REV 0x0200 /*!< Cortex-M3 Core Revision */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include /*!< Cortex-M3 processor and core peripherals */ +#include "system_ADuCRF101.h" /*!< ADUCRF101 System */ + + +/* ================================================================================ */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================ */ + + +/** @addtogroup Device_Peripheral_Registers + * @{ + */ + + +/* ------------------- Start of section using anonymous unions ------------------ */ +#if defined(__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined(__ICCARM__) + #pragma language=extended +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__TMS470__) +/* anonymous unions are enabled by default */ +#elif defined(__TASKING__) + #pragma warning 586 +#else + #warning Not supported compiler type +#endif + + + + +/* TCON[EVENTEN] - Enable event bit. */ +#define TCON_EVENTEN_MSK (0x1 << 12 ) +#define TCON_EVENTEN (0x1 << 12 ) +#define TCON_EVENTEN_DIS (0x0 << 12 ) /* DIS. Cleared by user. */ +#define TCON_EVENTEN_EN (0x1 << 12 ) /* EN. Enable time capture of an event. */ + +/* TCON[EVENT] - Event select bits. Settings not described are reserved and should not be used. */ +#define TCON_EVENT_MSK (0xF << 8 ) + +/* TCON[RLD] - Reload control bit for periodic mode. */ +#define TCON_RLD_MSK (0x1 << 7 ) +#define TCON_RLD (0x1 << 7 ) +#define TCON_RLD_DIS (0x0 << 7 ) /* DIS. Reload on a time out. */ +#define TCON_RLD_EN (0x1 << 7 ) /* EN. Reload the counter on a write to T0CLRI. */ + +/* TCON[CLK] - Clock select. */ +#define TCON_CLK_MSK (0x3 << 5 ) +#define TCON_CLK_UCLK (0x0 << 5 ) /* UCLK. Undivided system clock. */ +#define TCON_CLK_PCLK (0x1 << 5 ) /* PCLK. Peripheral clock. */ +#define TCON_CLK_LFOSC (0x2 << 5 ) /* LFOSC. 32 kHz internal oscillator. */ +#define TCON_CLK_LFXTAL (0x3 << 5 ) /* LFXTAL. 32 kHz external crystal. */ + +/* TCON[ENABLE] - Timer enable bit. */ +#define TCON_ENABLE_MSK (0x1 << 4 ) +#define TCON_ENABLE (0x1 << 4 ) +#define TCON_ENABLE_DIS (0x0 << 4 ) /* DIS. Disable the timer. Clearing this bit resets the timer, including the T0VAL register. */ +#define TCON_ENABLE_EN (0x1 << 4 ) /* EN. Enable the timer. The timer starts counting from its initial value, 0 if count-up mode or 0xFFFF if count-down mode. */ + +/* TCON[MOD] - Timer mode. */ +#define TCON_MOD_MSK (0x1 << 3 ) +#define TCON_MOD (0x1 << 3 ) +#define TCON_MOD_FREERUN (0x0 << 3 ) /* FREERUN. Operate in free running mode. */ +#define TCON_MOD_PERIODIC (0x1 << 3 ) /* PERIODIC. Operate in periodic mode. */ + +/* TCON[UP] - Count down/up. */ +#define TCON_UP_MSK (0x1 << 2 ) +#define TCON_UP (0x1 << 2 ) +#define TCON_UP_DIS (0x0 << 2 ) /* DIS. Timer to count down. */ +#define TCON_UP_EN (0x1 << 2 ) /* EN. Timer to count up. */ + +/* TCON[PRE] - Prescaler. */ +#define TCON_PRE_MSK (0x3 << 0 ) +#define TCON_PRE_DIV1 (0x0 << 0 ) /* DIV1. Source clock/1.If the selected clock source is UCLK or PCLK this setting results in a prescaler of 4. */ +#define TCON_PRE_DIV16 (0x1 << 0 ) /* DIV16. Source clock/16. */ +#define TCON_PRE_DIV256 (0x2 << 0 ) /* DIV256. Source clock/256. */ +#define TCON_PRE_DIV32768 (0x3 << 0 ) /* DIV32768. Source clock/32768. */ + +/* TCLRI[CAP] - Clear captured event interrupt. */ +#define TCLRI_CAP_MSK (0x1 << 1 ) +#define TCLRI_CAP (0x1 << 1 ) +#define TCLRI_CAP_CLR (0x1 << 1 ) /* CLR. Clear a captured event interrupt. This bit always reads 0. */ + +/* TCLRI[TMOUT] - Clear timeout interrupt. */ +#define TCLRI_TMOUT_MSK (0x1 << 0 ) +#define TCLRI_TMOUT (0x1 << 0 ) +#define TCLRI_TMOUT_CLR (0x1 << 0 ) /* CLR. Clear a timeout interrupt. This bit always reads 0. */ + +/* TSTA[CLRI] - T0CLRI write sync in progress.. */ +#define TSTA_CLRI_MSK (0x1 << 7 ) +#define TSTA_CLRI (0x1 << 7 ) +#define TSTA_CLRI_CLR (0x0 << 7 ) /* CLR. Cleared when the interrupt is cleared in the timer clock domain. */ +#define TSTA_CLRI_SET (0x1 << 7 ) /* SET. Set automatically when the T0CLRI value is being updated in the timer clock domain, indicating that the timer’s configuration is not yet valid. */ + +/* TSTA[CON] - T0CON write sync in progress. */ +#define TSTA_CON_MSK (0x1 << 6 ) +#define TSTA_CON (0x1 << 6 ) +#define TSTA_CON_CLR (0x0 << 6 ) /* CLR. Timer ready to receive commands to T0CON. The previous change of T0CON has been synchronized in the timer clock domain. */ +#define TSTA_CON_SET (0x1 << 6 ) /* SET. Timer not ready to receive commands to T0CON. Previous change of the T0CON value has not been synchronized in the timer clock domain. */ + +/* TSTA[CAP] - Capture event pending. */ +#define TSTA_CAP_MSK (0x1 << 1 ) +#define TSTA_CAP (0x1 << 1 ) +#define TSTA_CAP_CLR (0x0 << 1 ) /* CLR. No capture event is pending. */ +#define TSTA_CAP_SET (0x1 << 1 ) /* SET. Capture event is pending. */ + +/* TSTA[TMOUT] - Time out event occurred. */ +#define TSTA_TMOUT_MSK (0x1 << 0 ) +#define TSTA_TMOUT (0x1 << 0 ) +#define TSTA_TMOUT_CLR (0x0 << 0 ) /* CLR. No timeout event has occurred. */ +#define TSTA_TMOUT_SET (0x1 << 0 ) /* SET. Timeout event has occurred. For count-up mode, this is when the counter reaches full scale. For count-down mode, this is when the counter reaches 0. */ + +/* GPCON[CON7] - Configuration bits for Px.7 (not available for port 1). */ +#define GPCON_CON7_MSK (0x3 << 14 ) + +/* GPCON[CON6] - Configuration bits for Px.6 (not available for port 1). */ +#define GPCON_CON6_MSK (0x3 << 12 ) + +/* GPCON[CON5] - Configuration bits for Px.5. */ +#define GPCON_CON5_MSK (0x3 << 10 ) + +/* GPCON[CON4] - Configuration bits for Px.4. */ +#define GPCON_CON4_MSK (0x3 << 8 ) + +/* GPCON[CON3] - Configuration bits for Px.3. */ +#define GPCON_CON3_MSK (0x3 << 6 ) + +/* GPCON[CON2] - Configuration bits for Px.2. */ +#define GPCON_CON2_MSK (0x3 << 4 ) + +/* GPCON[CON1] - Configuration bits for Px.1. */ +#define GPCON_CON1_MSK (0x3 << 2 ) + +/* GPCON[CON0] - Configuration bits for Px.0. */ +#define GPCON_CON0_MSK (0x3 << 0 ) + +/* GPOEN[OEN7] - Port pin direction. */ +#define GPOEN_OEN7_MSK (0x1 << 7 ) +#define GPOEN_OEN7 (0x1 << 7 ) +#define GPOEN_OEN7_IN (0x0 << 7 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ +#define GPOEN_OEN7_OUT (0x1 << 7 ) /* OUT. Enables the output on corresponding port pin. */ + +/* GPOEN[OEN6] - Port pin direction. */ +#define GPOEN_OEN6_MSK (0x1 << 6 ) +#define GPOEN_OEN6 (0x1 << 6 ) +#define GPOEN_OEN6_IN (0x0 << 6 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ +#define GPOEN_OEN6_OUT (0x1 << 6 ) /* OUT. Enables the output on corresponding port pin. */ + +/* GPOEN[OEN5] - Port pin direction. */ +#define GPOEN_OEN5_MSK (0x1 << 5 ) +#define GPOEN_OEN5 (0x1 << 5 ) +#define GPOEN_OEN5_IN (0x0 << 5 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ +#define GPOEN_OEN5_OUT (0x1 << 5 ) /* OUT. Enables the output on corresponding port pin. */ + +/* GPOEN[OEN4] - Port pin direction. */ +#define GPOEN_OEN4_MSK (0x1 << 4 ) +#define GPOEN_OEN4 (0x1 << 4 ) +#define GPOEN_OEN4_IN (0x0 << 4 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ +#define GPOEN_OEN4_OUT (0x1 << 4 ) /* OUT. Enables the output on corresponding port pin. */ + +/* GPOEN[OEN3] - Port pin direction. */ +#define GPOEN_OEN3_MSK (0x1 << 3 ) +#define GPOEN_OEN3 (0x1 << 3 ) +#define GPOEN_OEN3_IN (0x0 << 3 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ +#define GPOEN_OEN3_OUT (0x1 << 3 ) /* OUT. Enables the output on corresponding port pin. */ + +/* GPOEN[OEN2] - Port pin direction. */ +#define GPOEN_OEN2_MSK (0x1 << 2 ) +#define GPOEN_OEN2 (0x1 << 2 ) +#define GPOEN_OEN2_IN (0x0 << 2 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ +#define GPOEN_OEN2_OUT (0x1 << 2 ) /* OUT. Enables the output on corresponding port pin. */ + +/* GPOEN[OEN1] - Port pin direction. */ +#define GPOEN_OEN1_MSK (0x1 << 1 ) +#define GPOEN_OEN1 (0x1 << 1 ) +#define GPOEN_OEN1_IN (0x0 << 1 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ +#define GPOEN_OEN1_OUT (0x1 << 1 ) /* OUT. Enables the output on corresponding port pin. */ + +/* GPOEN[OEN0] - Port pin direction. */ +#define GPOEN_OEN0_MSK (0x1 << 0 ) +#define GPOEN_OEN0 (0x1 << 0 ) +#define GPOEN_OEN0_IN (0x0 << 0 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ +#define GPOEN_OEN0_OUT (0x1 << 0 ) /* OUT. Enables the output on corresponding port pin.. */ + +/* GPIN[IN7] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ +#define GPIN_IN7_MSK (0x1 << 7 ) +#define GPIN_IN7 (0x1 << 7 ) +#define GPIN_IN7_LOW (0x0 << 7 ) /* LOW */ +#define GPIN_IN7_HIGH (0x1 << 7 ) /* HIGH */ + +/* GPIN[IN6] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ +#define GPIN_IN6_MSK (0x1 << 6 ) +#define GPIN_IN6 (0x1 << 6 ) +#define GPIN_IN6_LOW (0x0 << 6 ) /* LOW */ +#define GPIN_IN6_HIGH (0x1 << 6 ) /* HIGH */ + +/* GPIN[IN5] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ +#define GPIN_IN5_MSK (0x1 << 5 ) +#define GPIN_IN5 (0x1 << 5 ) +#define GPIN_IN5_LOW (0x0 << 5 ) /* LOW */ +#define GPIN_IN5_HIGH (0x1 << 5 ) /* HIGH */ + +/* GPIN[IN4] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ +#define GPIN_IN4_MSK (0x1 << 4 ) +#define GPIN_IN4 (0x1 << 4 ) +#define GPIN_IN4_LOW (0x0 << 4 ) /* LOW */ +#define GPIN_IN4_HIGH (0x1 << 4 ) /* HIGH */ + +/* GPIN[IN3] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ +#define GPIN_IN3_MSK (0x1 << 3 ) +#define GPIN_IN3 (0x1 << 3 ) +#define GPIN_IN3_LOW (0x0 << 3 ) /* LOW */ +#define GPIN_IN3_HIGH (0x1 << 3 ) /* HIGH */ + +/* GPIN[IN2] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ +#define GPIN_IN2_MSK (0x1 << 2 ) +#define GPIN_IN2 (0x1 << 2 ) +#define GPIN_IN2_LOW (0x0 << 2 ) /* LOW */ +#define GPIN_IN2_HIGH (0x1 << 2 ) /* HIGH */ + +/* GPIN[IN1] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ +#define GPIN_IN1_MSK (0x1 << 1 ) +#define GPIN_IN1 (0x1 << 1 ) +#define GPIN_IN1_LOW (0x0 << 1 ) /* LOW */ +#define GPIN_IN1_HIGH (0x1 << 1 ) /* HIGH */ + +/* GPIN[IN0] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ +#define GPIN_IN0_MSK (0x1 << 0 ) +#define GPIN_IN0 (0x1 << 0 ) +#define GPIN_IN0_LOW (0x0 << 0 ) /* LOW */ +#define GPIN_IN0_HIGH (0x1 << 0 ) /* HIGH */ + +/* GPOUT[OUT7] - Data out register. */ +#define GPOUT_OUT7_MSK (0x1 << 7 ) +#define GPOUT_OUT7 (0x1 << 7 ) +#define GPOUT_OUT7_LOW (0x0 << 7 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ +#define GPOUT_OUT7_HIGH (0x1 << 7 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ + +/* GPOUT[OUT6] - Data out register. */ +#define GPOUT_OUT6_MSK (0x1 << 6 ) +#define GPOUT_OUT6 (0x1 << 6 ) +#define GPOUT_OUT6_LOW (0x0 << 6 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ +#define GPOUT_OUT6_HIGH (0x1 << 6 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ + +/* GPOUT[OUT5] - Data out register. */ +#define GPOUT_OUT5_MSK (0x1 << 5 ) +#define GPOUT_OUT5 (0x1 << 5 ) +#define GPOUT_OUT5_LOW (0x0 << 5 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ +#define GPOUT_OUT5_HIGH (0x1 << 5 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ + +/* GPOUT[OUT4] - Data out register. */ +#define GPOUT_OUT4_MSK (0x1 << 4 ) +#define GPOUT_OUT4 (0x1 << 4 ) +#define GPOUT_OUT4_LOW (0x0 << 4 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ +#define GPOUT_OUT4_HIGH (0x1 << 4 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ + +/* GPOUT[OUT3] - Data out register. */ +#define GPOUT_OUT3_MSK (0x1 << 3 ) +#define GPOUT_OUT3 (0x1 << 3 ) +#define GPOUT_OUT3_LOW (0x0 << 3 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ +#define GPOUT_OUT3_HIGH (0x1 << 3 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ + +/* GPOUT[OUT2] - Data out register. */ +#define GPOUT_OUT2_MSK (0x1 << 2 ) +#define GPOUT_OUT2 (0x1 << 2 ) +#define GPOUT_OUT2_LOW (0x0 << 2 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ +#define GPOUT_OUT2_HIGH (0x1 << 2 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ + +/* GPOUT[OUT1] - Data out register. */ +#define GPOUT_OUT1_MSK (0x1 << 1 ) +#define GPOUT_OUT1 (0x1 << 1 ) +#define GPOUT_OUT1_LOW (0x0 << 1 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ +#define GPOUT_OUT1_HIGH (0x1 << 1 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ + +/* GPOUT[OUT0] - Data out register. */ +#define GPOUT_OUT0_MSK (0x1 << 0 ) +#define GPOUT_OUT0 (0x1 << 0 ) +#define GPOUT_OUT0_LOW (0x0 << 0 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ +#define GPOUT_OUT0_HIGH (0x1 << 0 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ + +/* GPSET[SET7] - Set output high for corresponding port pin. */ +#define GPSET_SET7_MSK (0x1 << 7 ) +#define GPSET_SET7 (0x1 << 7 ) +#define GPSET_SET7_SET (0x1 << 7 ) /* SET. Set by user code to drive the corresponding GPIO high. */ + +/* GPSET[SET6] - Set output high for corresponding port pin. */ +#define GPSET_SET6_MSK (0x1 << 6 ) +#define GPSET_SET6 (0x1 << 6 ) +#define GPSET_SET6_SET (0x1 << 6 ) /* SET. Set by user code to drive the corresponding GPIO high. */ + +/* GPSET[SET5] - Set output high for corresponding port pin. */ +#define GPSET_SET5_MSK (0x1 << 5 ) +#define GPSET_SET5 (0x1 << 5 ) +#define GPSET_SET5_SET (0x1 << 5 ) /* SET. Set by user code to drive the corresponding GPIO high. */ + +/* GPSET[SET4] - Set output high for corresponding port pin. */ +#define GPSET_SET4_MSK (0x1 << 4 ) +#define GPSET_SET4 (0x1 << 4 ) +#define GPSET_SET4_SET (0x1 << 4 ) /* SET. Set by user code to drive the corresponding GPIO high. */ + +/* GPSET[SET3] - Set output high for corresponding port pin. */ +#define GPSET_SET3_MSK (0x1 << 3 ) +#define GPSET_SET3 (0x1 << 3 ) +#define GPSET_SET3_SET (0x1 << 3 ) /* SET. Set by user code to drive the corresponding GPIO high. */ + +/* GPSET[SET2] - Set output high for corresponding port pin. */ +#define GPSET_SET2_MSK (0x1 << 2 ) +#define GPSET_SET2 (0x1 << 2 ) +#define GPSET_SET2_SET (0x1 << 2 ) /* SET. Set by user code to drive the corresponding GPIO high. */ + +/* GPSET[SET1] - Set output high for corresponding port pin. */ +#define GPSET_SET1_MSK (0x1 << 1 ) +#define GPSET_SET1 (0x1 << 1 ) +#define GPSET_SET1_SET (0x1 << 1 ) /* SET. Set by user code to drive the corresponding GPIO high. */ + +/* GPSET[SET0] - Set output high for corresponding port pin. */ +#define GPSET_SET0_MSK (0x1 << 0 ) +#define GPSET_SET0 (0x1 << 0 ) +#define GPSET_SET0_SET (0x1 << 0 ) /* SET. Set by user code to drive the corresponding GPIO high. */ + +/* GPCLR[CLR7] - Set by user code to drive the corresponding GPIO low. */ +#define GPCLR_CLR7_MSK (0x1 << 7 ) +#define GPCLR_CLR7 (0x1 << 7 ) +#define GPCLR_CLR7_CLR (0x1 << 7 ) /* CLR */ + +/* GPCLR[CLR6] - Set by user code to drive the corresponding GPIO low. */ +#define GPCLR_CLR6_MSK (0x1 << 6 ) +#define GPCLR_CLR6 (0x1 << 6 ) +#define GPCLR_CLR6_CLR (0x1 << 6 ) /* CLR */ + +/* GPCLR[CLR5] - Set by user code to drive the corresponding GPIO low. */ +#define GPCLR_CLR5_MSK (0x1 << 5 ) +#define GPCLR_CLR5 (0x1 << 5 ) +#define GPCLR_CLR5_CLR (0x1 << 5 ) /* CLR */ + +/* GPCLR[CLR4] - Set by user code to drive the corresponding GPIO low. */ +#define GPCLR_CLR4_MSK (0x1 << 4 ) +#define GPCLR_CLR4 (0x1 << 4 ) +#define GPCLR_CLR4_CLR (0x1 << 4 ) /* CLR */ + +/* GPCLR[CLR3] - Set by user code to drive the corresponding GPIO low. */ +#define GPCLR_CLR3_MSK (0x1 << 3 ) +#define GPCLR_CLR3 (0x1 << 3 ) +#define GPCLR_CLR3_CLR (0x1 << 3 ) /* CLR */ + +/* GPCLR[CLR2] - Set by user code to drive the corresponding GPIO low. */ +#define GPCLR_CLR2_MSK (0x1 << 2 ) +#define GPCLR_CLR2 (0x1 << 2 ) +#define GPCLR_CLR2_CLR (0x1 << 2 ) /* CLR */ + +/* GPCLR[CLR1] - Set by user code to drive the corresponding GPIO low. */ +#define GPCLR_CLR1_MSK (0x1 << 1 ) +#define GPCLR_CLR1 (0x1 << 1 ) +#define GPCLR_CLR1_CLR (0x1 << 1 ) /* CLR */ + +/* GPCLR[CLR0] - Set by user code to drive the corresponding GPIO low. */ +#define GPCLR_CLR0_MSK (0x1 << 0 ) +#define GPCLR_CLR0 (0x1 << 0 ) +#define GPCLR_CLR0_CLR (0x1 << 0 ) /* CLR */ + +/* GPTGL[TGL7] - Toggle for corresponding port pin. */ +#define GPTGL_TGL7_MSK (0x1 << 7 ) +#define GPTGL_TGL7 (0x1 << 7 ) +#define GPTGL_TGL7_TGL (0x1 << 7 ) /* TGL. Set by user code to invert the corresponding GPIO. */ + +/* GPTGL[TGL6] - Toggle for corresponding port pin. */ +#define GPTGL_TGL6_MSK (0x1 << 6 ) +#define GPTGL_TGL6 (0x1 << 6 ) +#define GPTGL_TGL6_TGL (0x1 << 6 ) /* TGL. Set by user code to invert the corresponding GPIO. */ + +/* GPTGL[TGL5] - Toggle for corresponding port pin. */ +#define GPTGL_TGL5_MSK (0x1 << 5 ) +#define GPTGL_TGL5 (0x1 << 5 ) +#define GPTGL_TGL5_TGL (0x1 << 5 ) /* TGL. Set by user code to invert the corresponding GPIO. */ + +/* GPTGL[TGL4] - Toggle for corresponding port pin. */ +#define GPTGL_TGL4_MSK (0x1 << 4 ) +#define GPTGL_TGL4 (0x1 << 4 ) +#define GPTGL_TGL4_TGL (0x1 << 4 ) /* TGL. Set by user code to invert the corresponding GPIO. */ + +/* GPTGL[TGL3] - Toggle for corresponding port pin. */ +#define GPTGL_TGL3_MSK (0x1 << 3 ) +#define GPTGL_TGL3 (0x1 << 3 ) +#define GPTGL_TGL3_TGL (0x1 << 3 ) /* TGL. Set by user code to invert the corresponding GPIO. */ + +/* GPTGL[TGL2] - Toggle for corresponding port pin. */ +#define GPTGL_TGL2_MSK (0x1 << 2 ) +#define GPTGL_TGL2 (0x1 << 2 ) +#define GPTGL_TGL2_TGL (0x1 << 2 ) /* TGL. Set by user code to invert the corresponding GPIO. */ + +/* GPTGL[TGL1] - Toggle for corresponding port pin. */ +#define GPTGL_TGL1_MSK (0x1 << 1 ) +#define GPTGL_TGL1 (0x1 << 1 ) +#define GPTGL_TGL1_TGL (0x1 << 1 ) /* TGL. Set by user code to invert the corresponding GPIO. */ + +/* GPTGL[TGL0] - Toggle for corresponding port pin. */ +#define GPTGL_TGL0_MSK (0x1 << 0 ) +#define GPTGL_TGL0 (0x1 << 0 ) +#define GPTGL_TGL0_TGL (0x1 << 0 ) /* TGL. Set by user code to invert the corresponding GPIO. */ + +/* CLK[T1] - T1 clocks enable bit. */ +#define CLK_T1_MSK (0x1 << 11 ) +#define CLK_T1 (0x1 << 11 ) +#define CLK_T1_DIS (0x0 << 11 ) /* DIS. Disable T1 clocks. */ +#define CLK_T1_EN (0x1 << 11 ) /* EN. Enable T1 clocks. */ + +/* CLK[T0] - T0 clocks enable bit. */ +#define CLK_T0_MSK (0x1 << 10 ) +#define CLK_T0 (0x1 << 10 ) +#define CLK_T0_DIS (0x0 << 10 ) /* DIS. Disable T0 clocks. */ +#define CLK_T0_EN (0x1 << 10 ) /* EN. Enable T0 clocks. */ + +/* CLK[PWM] - PWM clocks enable bit. */ +#define CLK_PWM_MSK (0x1 << 9 ) +#define CLK_PWM (0x1 << 9 ) +#define CLK_PWM_DIS (0x0 << 9 ) /* DIS. Disable PWM clocks. */ +#define CLK_PWM_EN (0x1 << 9 ) /* EN. Enable PWM clocks. */ + +/* CLK[I2C] - I2C clocks enable bit. */ +#define CLK_I2C_MSK (0x1 << 8 ) +#define CLK_I2C (0x1 << 8 ) +#define CLK_I2C_DIS (0x0 << 8 ) /* DIS. Disable I2C clocks. */ +#define CLK_I2C_EN (0x1 << 8 ) /* EN. Enable I2C clocks. */ + +/* CLK[COM] - UART clocks enable bit. */ +#define CLK_COM_MSK (0x1 << 7 ) +#define CLK_COM (0x1 << 7 ) +#define CLK_COM_DIS (0x0 << 7 ) /* DIS. Disable UART clocks. */ +#define CLK_COM_EN (0x1 << 7 ) /* EN. Enable UART clocks. */ + +/* CLK[SPI1] - SPI1 clocks enable bit. */ +#define CLK_SPI1_MSK (0x1 << 6 ) +#define CLK_SPI1 (0x1 << 6 ) +#define CLK_SPI1_DIS (0x0 << 6 ) /* DIS. Disable SPI1 clocks. */ +#define CLK_SPI1_EN (0x1 << 6 ) /* EN. Enable SPI1 clocks. */ + +/* CLK[SPI0] - SPI0 clocks enable bit. */ +#define CLK_SPI0_MSK (0x1 << 5 ) +#define CLK_SPI0 (0x1 << 5 ) +#define CLK_SPI0_DIS (0x0 << 5 ) /* DIS. Disable SPI0 clocks. */ +#define CLK_SPI0_EN (0x1 << 5 ) /* EN. Enable SPI0 clocks. */ + +/* CLK[T2] - T2 clocks enable bit. */ +#define CLK_T2_MSK (0x1 << 4 ) +#define CLK_T2 (0x1 << 4 ) +#define CLK_T2_DIS (0x0 << 4 ) /* DIS. Disable T2 clocks. */ +#define CLK_T2_EN (0x1 << 4 ) /* EN. Enable T2 clocks. */ + +/* CLK[ADC] - ADC clocks enable bit. */ +#define CLK_ADC_MSK (0x1 << 3 ) +#define CLK_ADC (0x1 << 3 ) +#define CLK_ADC_DIS (0x0 << 3 ) /* DIS. Disable ADC clocks. */ +#define CLK_ADC_EN (0x1 << 3 ) /* EN. Enable ADC clocks. */ + +/* CLK[SRAM] - SRAM clocks enable bit. */ +#define CLK_SRAM_MSK (0x1 << 2 ) +#define CLK_SRAM (0x1 << 2 ) +#define CLK_SRAM_DIS (0x0 << 2 ) /* DIS. Disable SRAM memory clocks. */ +#define CLK_SRAM_EN (0x1 << 2 ) /* EN. Enable SRAM memory clocks. */ + +/* CLK[FEE] - Flash clocks enable bit. */ +#define CLK_FEE_MSK (0x1 << 1 ) +#define CLK_FEE (0x1 << 1 ) +#define CLK_FEE_DIS (0x0 << 1 ) /* DIS. Disable Flash memory clocks. */ +#define CLK_FEE_EN (0x1 << 1 ) /* EN. Enable Flash memory clocks. */ + +/* CLK[DMA] - DMA clock enable bit. */ +#define CLK_DMA_MSK (0x1 << 0 ) +#define CLK_DMA (0x1 << 0 ) +#define CLK_DMA_DIS (0x0 << 0 ) /* DIS. Disable DMA clock. */ +#define CLK_DMA_EN (0x1 << 0 ) /* EN. Enable DMA clock. */ + +/* SPIDIV[BCRST] - Configures the behavior of SPI communication after an abrupt deassertion of CS. This bit should be set in slave and master mode. */ +#define SPIDIV_BCRST_MSK (0x1 << 7 ) +#define SPIDIV_BCRST (0x1 << 7 ) +#define SPIDIV_BCRST_DIS (0x0 << 7 ) /* DIS. Resumes communication from where it stopped when the CS is deasserted. The rest of the bits are then received/ transmitted when CS returns low. User code should ignore the CSERR interrupt. */ +#define SPIDIV_BCRST_EN (0x1 << 7 ) /* EN. Enabled for a clean restart of SPI transfer after a CSERR condition. User code must also clear the SPI enable bit in SPI0CON during the CSERR interrupt. */ + +/* SPIDIV[DIV] - Factor used to divide UCLK in the generation of the master mode serial clock. */ +#define SPIDIV_DIV_MSK (0x3F << 0 ) + +/* SPICON[MOD] - IRQ mode bits. When TIM is set these bits configure when the Tx/Rx interrupts occur in a transfer. For a DMA Rx transfer, these bits should be 00. */ +#define SPICON_MOD_MSK (0x3 << 14 ) +#define SPICON_MOD_TX1RX1 (0x0 << 14 ) /* TX1RX1. Tx/Rx interrupt occurs when 1 byte has been transmitted/received from/into the FIFO. */ +#define SPICON_MOD_TX2RX2 (0x1 << 14 ) /* TX2RX2. Tx/Rx interrupt occurs when 2 bytes have been transmitted/received from/into the FIFO. */ +#define SPICON_MOD_TX3RX3 (0x2 << 14 ) /* TX3RX3. Tx/Rx interrupt occurs when 3 bytes have been transmitted/received from/into the FIFO. */ +#define SPICON_MOD_TX4RX4 (0x3 << 14 ) /* TX4RX4. Tx/Rx interrupt occurs when 4 bytes have been transmitted/received from/into the FIFO. */ + +/* SPICON[TFLUSH] - Tx FIFO flush enable bit. */ +#define SPICON_TFLUSH_MSK (0x1 << 13 ) +#define SPICON_TFLUSH (0x1 << 13 ) +#define SPICON_TFLUSH_DIS (0x0 << 13 ) /* DIS. Disable Tx FIFO flushing. */ +#define SPICON_TFLUSH_EN (0x1 << 13 ) /* EN. Flush the Tx FIFO. This bit does not clear itself and should be toggled if a single flush is required. If this bit is left high, then either the last transmitted value or 0x00 is transmitted depending on the ZEN bit (SPI0CON[7]). Any writes to the Tx FIFO are ignored while this bit is set. */ + +/* SPICON[RFLUSH] - Rx FIFO flush enable bit. */ +#define SPICON_RFLUSH_MSK (0x1 << 12 ) +#define SPICON_RFLUSH (0x1 << 12 ) +#define SPICON_RFLUSH_DIS (0x0 << 12 ) /* DIS. Disable Rx FIFO flushing. */ +#define SPICON_RFLUSH_EN (0x1 << 12 ) /* EN. If this bit is set, all incoming data is ignored and no interrupts are generated. If set and TIM = 0 (SPI0CON[6]), a read of the Rx FIFO initiates a transfer. */ + +/* SPICON[CON] - Continuous transfer enable bit. */ +#define SPICON_CON_MSK (0x1 << 11 ) +#define SPICON_CON (0x1 << 11 ) +#define SPICON_CON_DIS (0x0 << 11 ) /* DIS. Disable continuous transfer. Each transfer consists of a single 8-bit serial transfer. If valid data exists in the SPIxTX register, then a new transfer is initiated after a stall period of one serial clock cycle. The CS line is deactivated for this one serial clock cycle. */ +#define SPICON_CON_EN (0x1 << 11 ) /* EN. Enable continuous transfer. In master mode, the transfer continues until no valid data is available in the Tx register. CS is asserted and remains asserted for the duration of each 8-bit serial transfer until Tx is empty. */ + +/* SPICON[LOOPBACK] - Loopback enable bit. */ +#define SPICON_LOOPBACK_MSK (0x1 << 10 ) +#define SPICON_LOOPBACK (0x1 << 10 ) +#define SPICON_LOOPBACK_DIS (0x0 << 10 ) /* DIS. Normal mode. */ +#define SPICON_LOOPBACK_EN (0x1 << 10 ) /* EN. Connect MISO to MOSI, thus, data transmitted from Tx register is looped back to the Rx register. SPI must be configured in master mode. */ + +/* SPICON[SOEN] - Slave output enable bit. */ +#define SPICON_SOEN_MSK (0x1 << 9 ) +#define SPICON_SOEN (0x1 << 9 ) +#define SPICON_SOEN_DIS (0x0 << 9 ) /* DIS. Disable the output driver on the MISO pin. The MISO pin is open-circuit when this bit is clear. */ +#define SPICON_SOEN_EN (0x1 << 9 ) /* EN. MISO operates as normal. */ + +/* SPICON[RXOF] - RX overflow overwrite enable bit. */ +#define SPICON_RXOF_MSK (0x1 << 8 ) +#define SPICON_RXOF (0x1 << 8 ) +#define SPICON_RXOF_DIS (0x0 << 8 ) /* DIS. The new serial byte received is discarded when there is no space left in the FIFO */ +#define SPICON_RXOF_EN (0x1 << 8 ) /* EN. The valid data in the Rx register is overwritten by the new serial byte received when there is no space left in the FIFO. */ + +/* SPICON[ZEN] - Transmit underrun: Transmit 0s when the Tx FIFO is empty */ +#define SPICON_ZEN_MSK (0x1 << 7 ) +#define SPICON_ZEN (0x1 << 7 ) +#define SPICON_ZEN_DIS (0x0 << 7 ) /* DIS. The last byte from the previous transmission is shifted out when a transfer is initiated with no valid data in the FIFO. */ +#define SPICON_ZEN_EN (0x1 << 7 ) /* EN. Transmit 0x00 when a transfer is initiated with no valid data in the FIFO. */ + +/* SPICON[TIM] - Transfer and interrupt mode bit. */ +#define SPICON_TIM_MSK (0x1 << 6 ) +#define SPICON_TIM (0x1 << 6 ) +#define SPICON_TIM_TXWR (0x1 << 6 ) /* TXWR. Initiate transfer with a write to the SPIxTX register. Interrupt only occurs when Tx is empty. */ +#define SPICON_TIM_RXRD (0x0 << 6 ) /* RXRD. Initiate transfer with a read of the SPIxRX register. The read must be done while the SPI interface is idle. Interrupt only occurs when Rx is full. */ + +/* SPICON[LSB] - LSB first transfer enable bit. */ +#define SPICON_LSB_MSK (0x1 << 5 ) +#define SPICON_LSB (0x1 << 5 ) +#define SPICON_LSB_DIS (0x0 << 5 ) /* DIS. MSB is transmitted first. */ +#define SPICON_LSB_EN (0x1 << 5 ) /* EN. LSB is transmitted first. */ + +/* SPICON[WOM] - Wired OR enable bit. */ +#define SPICON_WOM_MSK (0x1 << 4 ) +#define SPICON_WOM (0x1 << 4 ) +#define SPICON_WOM_DIS (0x0 << 4 ) /* DIS. Normal driver output operation. */ +#define SPICON_WOM_EN (0x1 << 4 ) /* EN. Enable open circuit data output for multimaster/multislave configuration. */ + +/* SPICON[CPOL] - Serial clock polarity mode bit. */ +#define SPICON_CPOL_MSK (0x1 << 3 ) +#define SPICON_CPOL (0x1 << 3 ) +#define SPICON_CPOL_LOW (0x0 << 3 ) /* LOW. Serial clock idles low. */ +#define SPICON_CPOL_HIGH (0x1 << 3 ) /* HIGH. Serial clock idles high. */ + +/* SPICON[CPHA] - Serial clock phase mode bit. */ +#define SPICON_CPHA_MSK (0x1 << 2 ) +#define SPICON_CPHA (0x1 << 2 ) +#define SPICON_CPHA_SAMPLELEADING (0x0 << 2 ) /* SAMPLELEADING. Serial clock pulses at the middle of the first data bit transfer. */ +#define SPICON_CPHA_SAMPLETRAILING (0x1 << 2 ) /* SAMPLETRAILING. Serial clock pulses at the start of the first data bit. */ + +/* SPICON[MASEN] - Master mode enable bit. */ +#define SPICON_MASEN_MSK (0x1 << 1 ) +#define SPICON_MASEN (0x1 << 1 ) +#define SPICON_MASEN_DIS (0x0 << 1 ) /* DIS. Configure in slave mode. */ +#define SPICON_MASEN_EN (0x1 << 1 ) /* EN. Configure in master mode. */ + +/* SPICON[ENABLE] - SPI enable bit. */ +#define SPICON_ENABLE_MSK (0x1 << 0 ) +#define SPICON_ENABLE (0x1 << 0 ) +#define SPICON_ENABLE_DIS (0x0 << 0 ) /* DIS. Disable the SPI. Clearing this bit will also reset all the FIFO related logic to enable a clean start. */ +#define SPICON_ENABLE_EN (0x1 << 0 ) /* EN. Enable the SPI. */ + +/* SPIDMA[IENRXDMA] - Receive DMA request enable bit. */ +#define SPIDMA_IENRXDMA_MSK (0x1 << 2 ) +#define SPIDMA_IENRXDMA (0x1 << 2 ) +#define SPIDMA_IENRXDMA_DIS (0x0 << 2 ) /* DIS. Disable Rx DMA requests. */ +#define SPIDMA_IENRXDMA_EN (0x1 << 2 ) /* EN. Enable Rx DMA requests. */ + +/* SPIDMA[IENTXDMA] - Transmit DMA request enable bit. */ +#define SPIDMA_IENTXDMA_MSK (0x1 << 1 ) +#define SPIDMA_IENTXDMA (0x1 << 1 ) +#define SPIDMA_IENTXDMA_DIS (0x0 << 1 ) /* DIS. Disable Tx DMA requests. */ +#define SPIDMA_IENTXDMA_EN (0x1 << 1 ) /* EN. Enable Tx DMA requests. */ + +/* SPIDMA[ENABLE] - DMA data transfer enable bit. */ +#define SPIDMA_ENABLE_MSK (0x1 << 0 ) +#define SPIDMA_ENABLE (0x1 << 0 ) +#define SPIDMA_ENABLE_DIS (0x0 << 0 ) /* DIS. Disable DMA transfer. This bit needs to be cleared to prevent extra DMA request to the µDMA controller. */ +#define SPIDMA_ENABLE_EN (0x1 << 0 ) /* EN. Enable a DMA transfer. Starts the transfer of a master configured to initiate transfer on transmit. */ + +/* SPISTA[CSERR] - CS error status bit. This bit generates an interrupt when detecting an abrupt CS desassertion before the full byte of data is transmitted completely. */ +#define SPISTA_CSERR_MSK (0x1 << 12 ) +#define SPISTA_CSERR (0x1 << 12 ) +#define SPISTA_CSERR_CLR (0x0 << 12 ) /* CLR: Cleared when no CS error is detected. Cleared to 0 on a read of SPI0STA register. */ +#define SPISTA_CSERR_SET (0x1 << 12 ) /* SET: Set when the CS line is deasserted abruptly. */ + +/* SPISTA[RXS] - Rx FIFO excess bytes present. */ +#define SPISTA_RXS_MSK (0x1 << 11 ) +#define SPISTA_RXS (0x1 << 11 ) +#define SPISTA_RXS_CLR (0x0 << 11 ) /* CLR. When the number of bytes in the FIFO is equal or less than the number in SPI0CON[15:14]. This bit is not cleared on a read of SPI0STA register. */ +#define SPISTA_RXS_SET (0x1 << 11 ) /* SET. When there are more bytes in the Rx FIFO than configured in MOD (SPI0CON[15:14]). For example if MOD = TX1RX1, RXS is set when there are 2 or more bytes in the Rx FIFO. This bit does not dependent on SPI0CON[6] and does not cause an interrupt. */ + +/* SPISTA[RXFSTA] - Rx FIFO status bits, indicates how many valid bytes are in the Rx FIFO. */ +#define SPISTA_RXFSTA_MSK (0x7 << 8 ) +#define SPISTA_RXFSTA_EMPTY (0x0 << 8 ) /* EMPTY. When Rx FIFO is empty. */ +#define SPISTA_RXFSTA_ONEBYTE (0x1 << 8 ) /* ONEBYTE. When 1 valid byte is in the FIFO. */ +#define SPISTA_RXFSTA_TWOBYTES (0x2 << 8 ) /* TWOBYTES. When 2 valid bytes are in the FIFO. */ +#define SPISTA_RXFSTA_THREEBYTES (0x3 << 8 ) /* THREEBYTES. When 3 valid bytes are in the FIFO. */ +#define SPISTA_RXFSTA_FOURBYTES (0x4 << 8 ) /* FOURBYTES. When 4 valid bytes are in the FIFO. */ + +/* SPISTA[RXOF] - Rx FIFO overflow status bit. This bit generates an interrupt. */ +#define SPISTA_RXOF_MSK (0x1 << 7 ) +#define SPISTA_RXOF (0x1 << 7 ) +#define SPISTA_RXOF_CLR (0x0 << 7 ) /* CLR. Cleared to 0 on a read of SPI0STA register. */ +#define SPISTA_RXOF_SET (0x1 << 7 ) /* SET. Set when the Rx FIFO is already full when new data is loaded to the FIFO. This bit generates an interrupt except when RFLUSH is set. (SPI0CON[12]). */ + +/* SPISTA[RX] - Rx interrupt status bit. This bit generates an interrupt, except when DMA transfer is enabled. */ +#define SPISTA_RX_MSK (0x1 << 6 ) +#define SPISTA_RX (0x1 << 6 ) +#define SPISTA_RX_CLR (0x0 << 6 ) /* CLR. Cleared to 0 on a read of SPI0STA register. */ +#define SPISTA_RX_SET (0x1 << 6 ) /* SET. Set when a receive interrupt occurs. This bit is set when TIM (SPI0CON[6]) is cleared and the required number of bytes have been received. */ + +/* SPISTA[TX] - Tx interrupt status bit. This bit generates an interrupt, except when DMA transfer is enabled. */ +#define SPISTA_TX_MSK (0x1 << 5 ) +#define SPISTA_TX (0x1 << 5 ) +#define SPISTA_TX_CLR (0x0 << 5 ) /* CLR. Cleared to 0 on a read of SPI0STA register. */ +#define SPISTA_TX_SET (0x1 << 5 ) /* SET. Set when a transmit interrupt occurs. This bit is set when TIM (SPI0CON[6]) set and the required number of bytes have been transmitted. */ + +/* SPISTA[TXUR] - Tx FIFO Underrun. This bit generates an interrupt. */ +#define SPISTA_TXUR_MSK (0x1 << 4 ) +#define SPISTA_TXUR (0x1 << 4 ) +#define SPISTA_TXUR_CLR (0x0 << 4 ) /* CLR. Cleared to 0 on a read of SPI0STA register. */ +#define SPISTA_TXUR_SET (0x1 << 4 ) /* SET. Set when a transmit is initiated without any valid data in the Tx FIFO. This bit generates an interrupt except when TFLUSH is set in SPI0CON. */ + +/* SPISTA[TXFSTA] - Tx FIFO status bits, indicates how many valid bytes are in the Tx FIFO. */ +#define SPISTA_TXFSTA_MSK (0x7 << 1 ) +#define SPISTA_TXFSTA_EMPTY (0x0 << 1 ) /* EMPTY. Tx FIFO is empty. */ +#define SPISTA_TXFSTA_ONEBYTE (0x1 << 1 ) /* ONEBYTE. 1 valid byte is in the FIFO. */ +#define SPISTA_TXFSTA_TWOBYTES (0x2 << 1 ) /* TWOBYTES. 2 valid bytes are in the FIFO. */ +#define SPISTA_TXFSTA_THREEBYTES (0x3 << 1 ) /* THREEBYTES. 3 valid bytes are in the FIFO. */ +#define SPISTA_TXFSTA_FOURBYTES (0x4 << 1 ) /* FOURBYTES . 4 valid bytes are in the FIFO. */ + +/* SPISTA[IRQ] - Interrupt status bit. */ +#define SPISTA_IRQ_MSK (0x1 << 0 ) +#define SPISTA_IRQ (0x1 << 0 ) +#define SPISTA_IRQ_CLR (0x0 << 0 ) /* CLR. Cleared to 0 on a read of SPI0STA register. */ +#define SPISTA_IRQ_SET (0x1 << 0 ) /* SET. Set to 1 when an SPI0 based interrupt occurs. */ + +/* SPIDIV[BCRST] - Configures the behavior of SPI communication after an abrupt deassertion of CS. This bit should be set in slave and master mode. */ +#define SPIDIV_BCRST_MSK (0x1 << 7 ) +#define SPIDIV_BCRST (0x1 << 7 ) +#define SPIDIV_BCRST_DIS (0x0 << 7 ) /* DIS. Resumes communication from where it stopped when the CS is deasserted. The rest of the bits are then received/ transmitted when CS returns low. User code should ignore the CSERR interrupt. */ +#define SPIDIV_BCRST_EN (0x1 << 7 ) /* EN. Enabled for a clean restart of SPI transfer after a CSERR condition. User code must also clear the SPI enable bit in SPI0CON during the CSERR interrupt. */ + +/* SPIDIV[DIV] - Factor used to divide UCLK in the generation of the master mode serial clock. */ +#define SPIDIV_DIV_MSK (0x3F << 0 ) +// ------------------------------------------------------------------------------------------------ +// ----- ADC0 ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief Analog to Digital Converter (pADI_ADC0) + */ + +#if (__NO_MMR_STRUCTS__==0) +typedef struct { /*!< pADI_ADC0 Structure */ + __IO uint16_t ADCCFG; /*!< ADC Configuration Register */ + __I uint16_t RESERVED0; + __IO uint8_t ADCCON; /*!< ADC Control Register */ + __I uint8_t RESERVED1[3]; + __IO uint8_t ADCSTA; /*!< ADC Status Register */ + __I uint8_t RESERVED2[3]; + __IO uint16_t ADCDAT; /*!< ADC Data Register */ + __I uint16_t RESERVED3; + __IO uint16_t ADCGN; /*!< ADC Gain Register */ + __I uint16_t RESERVED4; + __IO uint16_t ADCOF; /*!< ADC Offset Register */ +} ADI_ADC_TypeDef; +#else // (__NO_MMR_STRUCTS__==0) +#define ADCCFG (*(volatile unsigned short int *) 0x40050000) +#define ADCCON (*(volatile unsigned char *) 0x40050004) +#define ADCSTA (*(volatile unsigned char *) 0x40050008) +#define ADCDAT (*(volatile unsigned short int *) 0x4005000C) +#define ADCGN (*(volatile unsigned short int *) 0x40050010) +#define ADCOF (*(volatile unsigned short int *) 0x40050014) +#endif // (__NO_MMR_STRUCTS__==0) + +/* Reset Value for ADCCFG*/ +#define ADCCFG_RVAL 0xA00 + +/* ADCCFG[REF] - Reference select */ +#define ADCCFG_REF_BBA (*(volatile unsigned long *) 0x42A00034) +#define ADCCFG_REF_MSK (0x1 << 13 ) +#define ADCCFG_REF (0x1 << 13 ) +#define ADCCFG_REF_INTERNAL125V (0x0 << 13 ) /* INTERNAL125V. Select the internal 1.25 V reference as the ADC reference. */ +#define ADCCFG_REF_LVDD (0x1 << 13 ) /* LVDD. Select the 1.8V regulator output (LVDD1) as the ADC reference. */ + +/* ADCCFG[CLK] - ADC clock frequency */ +#define ADCCFG_CLK_MSK (0x7 << 10 ) +#define ADCCFG_CLK_FCORE (0x0 << 10 ) /* FCORE. */ +#define ADCCFG_CLK_FCOREDIV2 (0x1 << 10 ) /* FCOREDIV2. */ +#define ADCCFG_CLK_FCOREDIV4 (0x2 << 10 ) /* FCOREDIV4. */ +#define ADCCFG_CLK_FCOREDIV8 (0x3 << 10 ) /* FCOREDIV8. */ +#define ADCCFG_CLK_FCOREDIV16 (0x4 << 10 ) /* FCOREDIV16. */ +#define ADCCFG_CLK_FCOREDIV32 (0x5 << 10 ) /* FCOREDIV32. */ + +/* ADCCFG[ACQ] - Acquisition clocks */ +#define ADCCFG_ACQ_MSK (0x3 << 8 ) +#define ADCCFG_ACQ_2 (0x0 << 8 ) /* 2. */ +#define ADCCFG_ACQ_4 (0x1 << 8 ) /* 4. */ +#define ADCCFG_ACQ_8 (0x2 << 8 ) /* 8. */ +#define ADCCFG_ACQ_16 (0x3 << 8 ) /* 16. */ + +/* ADCCFG[CHSEL] - Channel select */ +#define ADCCFG_CHSEL_MSK (0xF << 0 ) +#define ADCCFG_CHSEL_ADC0 (0x0 << 0 ) /* ADC0. Single ended ADC0 input. */ +#define ADCCFG_CHSEL_ADC1 (0x1 << 0 ) /* ADC1. Single ended ADC1 input. */ +#define ADCCFG_CHSEL_ADC2 (0x2 << 0 ) /* ADC2. Single ended ADC2 input. */ +#define ADCCFG_CHSEL_ADC3 (0x3 << 0 ) /* ADC3. Single ended ADC3 input. */ +#define ADCCFG_CHSEL_ADC4 (0x4 << 0 ) /* ADC4. Single ended ADC4 input. */ +#define ADCCFG_CHSEL_ADC5 (0x5 << 0 ) /* ADC5. Single ended ADC5 input. */ +#define ADCCFG_CHSEL_DIFF0 (0x6 << 0 ) /* DIFF0. Differential ADC0 - ADC1 inputs. */ +#define ADCCFG_CHSEL_DIFF1 (0x7 << 0 ) /* DIFF1. Differential ADC2 - ADC3 inputs. */ +#define ADCCFG_CHSEL_DIFF2 (0x8 << 0 ) /* DIFF2. Differential ADC4 - ADC5 inputs. */ +#define ADCCFG_CHSEL_TEMP (0x9 << 0 ) /* TEMP. Internal temperature sensor. */ +#define ADCCFG_CHSEL_VBATDIV4 (0xA << 0 ) /* VBATDIV4. Internal supply divided by 4. */ +#define ADCCFG_CHSEL_LVDDDIV2 (0xB << 0 ) /* LVDDDIV2. Internal 1.8V regulator output (LVDD1) divided by 2. */ +#define ADCCFG_CHSEL_VREF (0xC << 0 ) /* VREF. Internal ADC reference input for gain calibration. */ +#define ADCCFG_CHSEL_AGND (0xD << 0 ) /* AGND. Internal ADC ground input for offset calibration. */ + +/* Reset Value for ADCCON*/ +#define ADCCON_RVAL 0x90 + +/* ADCCON[REFBUF] - Reference buffer enable bit. */ +#define ADCCON_REFBUF_BBA (*(volatile unsigned long *) 0x42A0009C) +#define ADCCON_REFBUF_MSK (0x1 << 7 ) +#define ADCCON_REFBUF (0x1 << 7 ) +#define ADCCON_REFBUF_EN (0x0 << 7 ) /* EN. Turn on the reference buffer. The reference buffer takes 5 ms to settle and consumes approximately 210 μA. */ +#define ADCCON_REFBUF_DIS (0x1 << 7 ) /* DIS. Turn off the reference buffer. The internal reference buffer must be turned off if using an external reference. */ + +/* ADCCON[DMA] - DMA transfer enable bit. */ +#define ADCCON_DMA_BBA (*(volatile unsigned long *) 0x42A00098) +#define ADCCON_DMA_MSK (0x1 << 6 ) +#define ADCCON_DMA (0x1 << 6 ) +#define ADCCON_DMA_DIS (0x0 << 6 ) /* DIS. Disable DMA transfer. */ +#define ADCCON_DMA_EN (0x1 << 6 ) /* EN. Enable DMA transfer. */ + +/* ADCCON[IEN] - Interrupt enable. */ +#define ADCCON_IEN_BBA (*(volatile unsigned long *) 0x42A00094) +#define ADCCON_IEN_MSK (0x1 << 5 ) +#define ADCCON_IEN (0x1 << 5 ) +#define ADCCON_IEN_DIS (0x0 << 5 ) /* DIS. Disable the ADC interrupt. */ +#define ADCCON_IEN_EN (0x1 << 5 ) /* EN. Enable the ADC interrupt. An interrupt is generated when new data is available. */ + +/* ADCCON[ENABLE] - ADC enable. */ +#define ADCCON_ENABLE_BBA (*(volatile unsigned long *) 0x42A00090) +#define ADCCON_ENABLE_MSK (0x1 << 4 ) +#define ADCCON_ENABLE (0x1 << 4 ) +#define ADCCON_ENABLE_EN (0x0 << 4 ) /* EN. Enable the ADC. */ +#define ADCCON_ENABLE_DIS (0x1 << 4 ) /* DIS. Disable the ADC. */ + +/* ADCCON[MOD] - Conversion mode. */ +#define ADCCON_MOD_MSK (0x7 << 1 ) +#define ADCCON_MOD_SOFT (0x0 << 1 ) /* SOFT. Software trigger, used in conjunction with the START bit. */ +#define ADCCON_MOD_CONT (0x1 << 1 ) /* CONT. Continuous convert mode. */ +#define ADCCON_MOD_T0OVF (0x3 << 1 ) /* T0OVF. Timer0 overflow. */ +#define ADCCON_MOD_T1OVF (0x4 << 1 ) /* T1OVF. Timer1 overflow. */ +#define ADCCON_MOD_GPIO (0x5 << 1 ) /* GPIO. ADC conversion triggered by P0.3 input. */ + +/* ADCCON[START] - ADC conversion start. */ +#define ADCCON_START_BBA (*(volatile unsigned long *) 0x42A00080) +#define ADCCON_START_MSK (0x1 << 0 ) +#define ADCCON_START (0x1 << 0 ) +#define ADCCON_START_DIS (0x0 << 0 ) /* DIS. Has no effect. */ +#define ADCCON_START_EN (0x1 << 0 ) /* EN. Start conversion when SOFT conversion mode is selected. This bit does not clear after a single software conversion. */ + +/* Reset Value for ADCSTA*/ +#define ADCSTA_RVAL 0x0 + +/* ADCSTA[READY] - ADC Ready bit */ +#define ADCSTA_READY_BBA (*(volatile unsigned long *) 0x42A00100) +#define ADCSTA_READY_MSK (0x1 << 0 ) +#define ADCSTA_READY (0x1 << 0 ) +#define ADCSTA_READY_CLR (0x0 << 0 ) /* CLR. Cleared automatically when ADCDAT is read. */ +#define ADCSTA_READY_EN (0x1 << 0 ) /* EN. Set by the ADC when a conversion is complete. This bit generates an interrupt if enabled (IEN set in ADCCON). */ + +/* Reset Value for ADCDAT*/ +#define ADCDAT_RVAL 0x0 + +/* ADCDAT[VALUE] - ADC result */ +#define ADCDAT_VALUE_MSK (0xFFF << 2 ) + +/* ADCDAT[Value_Reserved] - ADC result / Reserved */ +#define ADCDAT_Value_Reserved_MSK (0x3 << 0 ) + +/* Reset Value for ADCGN*/ +#define ADCGN_RVAL 0x0 + +/* ADCGN[VALUE] - Gain */ +#define ADCGN_VALUE_MSK (0xFFFF << 0 ) + +/* Reset Value for ADCOF*/ +#define ADCOF_RVAL 0x0 + +/* ADCOF[VALUE] - Offset */ +#define ADCOF_VALUE_MSK (0xFFFF << 0 ) +// ------------------------------------------------------------------------------------------------ +// ----- CLKCTL ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief Clock Control (pADI_CLKCTL) + */ + +#if (__NO_MMR_STRUCTS__==0) +typedef struct { /*!< pADI_CLKCTL Structure */ + __IO uint16_t CLKCON; /*!< System Clocking Architecture Control Register */ + __I uint16_t RESERVED0[519]; + __IO uint8_t XOSCCON; /*!< Crystal Oscillator Control Register */ + __I uint8_t RESERVED1[111]; + __IO uint16_t CLKACT; /*!< Clock in Active Mode Enable Register */ + __I uint16_t RESERVED2; + __IO uint16_t CLKPD; /*!< Clock in Power-Down Mode Enable Register */ +} ADI_CLKCTL_TypeDef; +#else // (__NO_MMR_STRUCTS__==0) +#define CLKCON (*(volatile unsigned short int *) 0x40002000) +#define XOSCCON (*(volatile unsigned char *) 0x40002410) +#define CLKACT (*(volatile unsigned short int *) 0x40002480) +#define CLKPD (*(volatile unsigned short int *) 0x40002484) +#endif // (__NO_MMR_STRUCTS__==0) + +/* Reset Value for CLKCON*/ +#define CLKCON_RVAL 0x0 + +/* CLKCON[CLKOUT] - GPIO output clock multiplexer select bits. */ +#define CLKCON_CLKOUT_MSK (0x7 << 5 ) +#define CLKCON_CLKOUT_UCLKCG (0x0 << 5 ) /* UCLKCG. */ +#define CLKCON_CLKOUT_UCLK (0x1 << 5 ) /* UCLK. */ +#define CLKCON_CLKOUT_PCLK (0x2 << 5 ) /* PCLK. */ +#define CLKCON_CLKOUT_HFOSC (0x5 << 5 ) /* HFOSC. */ +#define CLKCON_CLKOUT_LFOSC (0x6 << 5 ) /* LFOSC. */ +#define CLKCON_CLKOUT_LFXTAL (0x7 << 5 ) /* LFXTAL. */ + +/* CLKCON[CLKMUX] - Digital subsystem clock source select bits. */ +#define CLKCON_CLKMUX_MSK (0x3 << 3 ) +#define CLKCON_CLKMUX_HFOSC (0x0 << 3 ) /* HFOSC. 16MHz internal oscillator. */ +#define CLKCON_CLKMUX_LFXTAL (0x1 << 3 ) /* LFXTAL. 32.768kHz external crystal. */ +#define CLKCON_CLKMUX_LFOSC (0x2 << 3 ) /* LFOSC. 32.768kHz internal oscillator. */ +#define CLKCON_CLKMUX_ECLKIN (0x3 << 3 ) /* ECLKIN. External clock on P0.5. */ + +/* CLKCON[CD] - Clock divide bits. */ +#define CLKCON_CD_MSK (0x7 << 0 ) +#define CLKCON_CD_DIV1 (0x0 << 0 ) /* DIV1. */ +#define CLKCON_CD_DIV2 (0x1 << 0 ) /* DIV2. */ +#define CLKCON_CD_DIV4 (0x2 << 0 ) /* DIV4. */ +#define CLKCON_CD_DIV8 (0x3 << 0 ) /* DIV8. */ +#define CLKCON_CD_DIV16 (0x4 << 0 ) /* DIV16. */ +#define CLKCON_CD_DIV32 (0x5 << 0 ) /* DIV32. */ +#define CLKCON_CD_DIV64 (0x6 << 0 ) /* DIV64. */ +#define CLKCON_CD_DIV128 (0x7 << 0 ) /* DIV128. */ + +/* Reset Value for XOSCCON*/ +#define XOSCCON_RVAL 0x0 + +/* XOSCCON[ENABLE] - Crystal oscillator circuit enable bit. */ +#define XOSCCON_ENABLE_BBA (*(volatile unsigned long *) 0x42048200) +#define XOSCCON_ENABLE_MSK (0x1 << 0 ) +#define XOSCCON_ENABLE (0x1 << 0 ) +#define XOSCCON_ENABLE_DIS (0x0 << 0 ) /* DIS. Disables the watch crystal circuitry.(LFXTAL) */ +#define XOSCCON_ENABLE_EN (0x1 << 0 ) /* EN. Enables the watch crystal circuitry.(LFXTAL) */ + +/* Reset Value for CLKACT*/ +#define CLKACT_RVAL 0x3FFF + +/* CLKACT[T1] - T1 clocks enable bit. */ +#define CLKACT_T1_BBA (*(volatile unsigned long *) 0x4204902C) +#define CLKACT_T1_MSK (0x1 << 11 ) +#define CLKACT_T1 (0x1 << 11 ) +#define CLKACT_T1_DIS (0x0 << 11 ) /* DIS. Disable T1 clocks. */ +#define CLKACT_T1_EN (0x1 << 11 ) /* EN. Enable T1 clocks. */ + +/* CLKACT[T0] - T0 clocks enable bit. */ +#define CLKACT_T0_BBA (*(volatile unsigned long *) 0x42049028) +#define CLKACT_T0_MSK (0x1 << 10 ) +#define CLKACT_T0 (0x1 << 10 ) +#define CLKACT_T0_DIS (0x0 << 10 ) /* DIS. Disable T0 clocks. */ +#define CLKACT_T0_EN (0x1 << 10 ) /* EN. Enable T0 clocks. */ + +/* CLKACT[PWM] - PWM clocks enable bit. */ +#define CLKACT_PWM_BBA (*(volatile unsigned long *) 0x42049024) +#define CLKACT_PWM_MSK (0x1 << 9 ) +#define CLKACT_PWM (0x1 << 9 ) +#define CLKACT_PWM_DIS (0x0 << 9 ) /* DIS. Disable PWM clocks. */ +#define CLKACT_PWM_EN (0x1 << 9 ) /* EN. Enable PWM clocks. */ + +/* CLKACT[I2C] - I2C clocks enable bit. */ +#define CLKACT_I2C_BBA (*(volatile unsigned long *) 0x42049020) +#define CLKACT_I2C_MSK (0x1 << 8 ) +#define CLKACT_I2C (0x1 << 8 ) +#define CLKACT_I2C_DIS (0x0 << 8 ) /* DIS. Disable I2C clocks. */ +#define CLKACT_I2C_EN (0x1 << 8 ) /* EN. Enable I2C clocks. */ + +/* CLKACT[COM] - UART clocks enable bit. */ +#define CLKACT_COM_BBA (*(volatile unsigned long *) 0x4204901C) +#define CLKACT_COM_MSK (0x1 << 7 ) +#define CLKACT_COM (0x1 << 7 ) +#define CLKACT_COM_DIS (0x0 << 7 ) /* DIS. Disable UART clocks. */ +#define CLKACT_COM_EN (0x1 << 7 ) /* EN. Enable UART clocks. */ + +/* CLKACT[SPI1] - SPI1 clocks enable bit. */ +#define CLKACT_SPI1_BBA (*(volatile unsigned long *) 0x42049018) +#define CLKACT_SPI1_MSK (0x1 << 6 ) +#define CLKACT_SPI1 (0x1 << 6 ) +#define CLKACT_SPI1_DIS (0x0 << 6 ) /* DIS. Disable SPI1 clocks. */ +#define CLKACT_SPI1_EN (0x1 << 6 ) /* EN. Enable SPI1 clocks. */ + +/* CLKACT[SPI0] - SPI0 clocks enable bit. */ +#define CLKACT_SPI0_BBA (*(volatile unsigned long *) 0x42049014) +#define CLKACT_SPI0_MSK (0x1 << 5 ) +#define CLKACT_SPI0 (0x1 << 5 ) +#define CLKACT_SPI0_DIS (0x0 << 5 ) /* DIS. Disable SPI0 clocks. */ +#define CLKACT_SPI0_EN (0x1 << 5 ) /* EN. Enable SPI0 clocks. */ + +/* CLKACT[T2] - T2 clocks enable bit. */ +#define CLKACT_T2_BBA (*(volatile unsigned long *) 0x42049010) +#define CLKACT_T2_MSK (0x1 << 4 ) +#define CLKACT_T2 (0x1 << 4 ) +#define CLKACT_T2_DIS (0x0 << 4 ) /* DIS. Disable T2 clocks. */ +#define CLKACT_T2_EN (0x1 << 4 ) /* EN. Enable T2 clocks. */ + +/* CLKACT[ADC] - ADC clocks enable bit. */ +#define CLKACT_ADC_BBA (*(volatile unsigned long *) 0x4204900C) +#define CLKACT_ADC_MSK (0x1 << 3 ) +#define CLKACT_ADC (0x1 << 3 ) +#define CLKACT_ADC_DIS (0x0 << 3 ) /* DIS. Disable ADC clocks. */ +#define CLKACT_ADC_EN (0x1 << 3 ) /* EN. Enable ADC clocks. */ + +/* CLKACT[SRAM] - SRAM clocks enable bit. */ +#define CLKACT_SRAM_BBA (*(volatile unsigned long *) 0x42049008) +#define CLKACT_SRAM_MSK (0x1 << 2 ) +#define CLKACT_SRAM (0x1 << 2 ) +#define CLKACT_SRAM_DIS (0x0 << 2 ) /* DIS. Disable SRAM memory clocks. */ +#define CLKACT_SRAM_EN (0x1 << 2 ) /* EN. Enable SRAM memory clocks. */ + +/* CLKACT[FEE] - Flash clocks enable bit. */ +#define CLKACT_FEE_BBA (*(volatile unsigned long *) 0x42049004) +#define CLKACT_FEE_MSK (0x1 << 1 ) +#define CLKACT_FEE (0x1 << 1 ) +#define CLKACT_FEE_DIS (0x0 << 1 ) /* DIS. Disable Flash memory clocks. */ +#define CLKACT_FEE_EN (0x1 << 1 ) /* EN. Enable Flash memory clocks. */ + +/* CLKACT[DMA] - DMA clock enable bit. */ +#define CLKACT_DMA_BBA (*(volatile unsigned long *) 0x42049000) +#define CLKACT_DMA_MSK (0x1 << 0 ) +#define CLKACT_DMA (0x1 << 0 ) +#define CLKACT_DMA_DIS (0x0 << 0 ) /* DIS.Disable DMA clock. */ +#define CLKACT_DMA_EN (0x1 << 0 ) /* EN. Enable DMA clock. */ + +/* Reset Value for CLKPD*/ +#define CLKPD_RVAL 0x3FFF + +/* CLKPD[T1] - T1 clocks enable bit. */ +#define CLKPD_T1_BBA (*(volatile unsigned long *) 0x420490AC) +#define CLKPD_T1_MSK (0x1 << 11 ) +#define CLKPD_T1 (0x1 << 11 ) +#define CLKPD_T1_DIS (0x0 << 11 ) /* DIS. Disable T1 clocks. */ +#define CLKPD_T1_EN (0x1 << 11 ) /* EN. Enable T1 clocks. */ + +/* CLKPD[T0] - T0 clocks enable bit. */ +#define CLKPD_T0_BBA (*(volatile unsigned long *) 0x420490A8) +#define CLKPD_T0_MSK (0x1 << 10 ) +#define CLKPD_T0 (0x1 << 10 ) +#define CLKPD_T0_DIS (0x0 << 10 ) /* DIS. Disable T0 clocks. */ +#define CLKPD_T0_EN (0x1 << 10 ) /* EN. Enable T0 clocks. */ + +/* CLKPD[PWM] - PWM clocks enable bit. */ +#define CLKPD_PWM_BBA (*(volatile unsigned long *) 0x420490A4) +#define CLKPD_PWM_MSK (0x1 << 9 ) +#define CLKPD_PWM (0x1 << 9 ) +#define CLKPD_PWM_DIS (0x0 << 9 ) /* DIS. Disable PWM clocks. */ +#define CLKPD_PWM_EN (0x1 << 9 ) /* EN. Enable PWM clocks. */ + +/* CLKPD[I2C] - I2C clocks enable bit. */ +#define CLKPD_I2C_BBA (*(volatile unsigned long *) 0x420490A0) +#define CLKPD_I2C_MSK (0x1 << 8 ) +#define CLKPD_I2C (0x1 << 8 ) +#define CLKPD_I2C_DIS (0x0 << 8 ) /* DIS. Disable I2C clocks. */ +#define CLKPD_I2C_EN (0x1 << 8 ) /* EN. Enable I2C clocks. */ + +/* CLKPD[COM] - UART clocks enable bit. */ +#define CLKPD_COM_BBA (*(volatile unsigned long *) 0x4204909C) +#define CLKPD_COM_MSK (0x1 << 7 ) +#define CLKPD_COM (0x1 << 7 ) +#define CLKPD_COM_DIS (0x0 << 7 ) /* DIS. Disable UART clocks. */ +#define CLKPD_COM_EN (0x1 << 7 ) /* EN. Enable UART clocks. */ + +/* CLKPD[SPI1] - SPI1 clocks enable bit. */ +#define CLKPD_SPI1_BBA (*(volatile unsigned long *) 0x42049098) +#define CLKPD_SPI1_MSK (0x1 << 6 ) +#define CLKPD_SPI1 (0x1 << 6 ) +#define CLKPD_SPI1_DIS (0x0 << 6 ) /* DIS. Disable SPI1 clocks. */ +#define CLKPD_SPI1_EN (0x1 << 6 ) /* EN. Enable SPI1 clocks. */ + +/* CLKPD[SPI0] - SPI0 clocks enable bit. */ +#define CLKPD_SPI0_BBA (*(volatile unsigned long *) 0x42049094) +#define CLKPD_SPI0_MSK (0x1 << 5 ) +#define CLKPD_SPI0 (0x1 << 5 ) +#define CLKPD_SPI0_DIS (0x0 << 5 ) /* DIS. Disable SPI0 clocks. */ +#define CLKPD_SPI0_EN (0x1 << 5 ) /* EN. Enable SPI0 clocks. */ + +/* CLKPD[T2] - T2 clocks enable bit. */ +#define CLKPD_T2_BBA (*(volatile unsigned long *) 0x42049090) +#define CLKPD_T2_MSK (0x1 << 4 ) +#define CLKPD_T2 (0x1 << 4 ) +#define CLKPD_T2_DIS (0x0 << 4 ) /* DIS. Disable T2 clocks. */ +#define CLKPD_T2_EN (0x1 << 4 ) /* EN. Enable T2 clocks. */ + +/* CLKPD[ADC] - ADC clocks enable bit. */ +#define CLKPD_ADC_BBA (*(volatile unsigned long *) 0x4204908C) +#define CLKPD_ADC_MSK (0x1 << 3 ) +#define CLKPD_ADC (0x1 << 3 ) +#define CLKPD_ADC_DIS (0x0 << 3 ) /* DIS. Disable ADC clocks. */ +#define CLKPD_ADC_EN (0x1 << 3 ) /* EN. Enable ADC clocks. */ + +/* CLKPD[SRAM] - SRAM clocks enable bit. */ +#define CLKPD_SRAM_BBA (*(volatile unsigned long *) 0x42049088) +#define CLKPD_SRAM_MSK (0x1 << 2 ) +#define CLKPD_SRAM (0x1 << 2 ) +#define CLKPD_SRAM_DIS (0x0 << 2 ) /* DIS. Disable SRAM memory clocks. */ +#define CLKPD_SRAM_EN (0x1 << 2 ) /* EN. Enable SRAM memory clocks. */ + +/* CLKPD[FEE] - Flash clocks enable bit. */ +#define CLKPD_FEE_BBA (*(volatile unsigned long *) 0x42049084) +#define CLKPD_FEE_MSK (0x1 << 1 ) +#define CLKPD_FEE (0x1 << 1 ) +#define CLKPD_FEE_DIS (0x0 << 1 ) /* DIS. Disable Flash memory clocks. */ +#define CLKPD_FEE_EN (0x1 << 1 ) /* EN. Enable Flash memory clocks. */ + +/* CLKPD[DMA] - DMA clock enable bit. */ +#define CLKPD_DMA_BBA (*(volatile unsigned long *) 0x42049080) +#define CLKPD_DMA_MSK (0x1 << 0 ) +#define CLKPD_DMA (0x1 << 0 ) +#define CLKPD_DMA_DIS (0x0 << 0 ) /* DIS. Disable DMA clock. */ +#define CLKPD_DMA_EN (0x1 << 0 ) /* EN. Enable DMA clock. */ +// ------------------------------------------------------------------------------------------------ +// ----- DMA ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief Direct Memory Access (pADI_DMA) + */ + +#if (__NO_MMR_STRUCTS__==0) +typedef struct { /*!< pADI_DMA Structure */ + __IO uint32_t DMASTA; /*!< Status Register */ + __IO uint32_t DMACFG; /*!< Configuration Register */ + __IO uint32_t DMAPDBPTR; /*!< Primary Control Database Pointer Register */ + __IO uint32_t DMAADBPTR; /*!< Alternate Control Database Pointer Register */ + __I uint32_t RESERVED0; + __IO uint32_t DMASWREQ; /*!< Channel Software Request Register */ + __I uint32_t RESERVED1[2]; + __IO uint32_t DMARMSKSET; /*!< Channel Request Mask Set Register */ + __IO uint32_t DMARMSKCLR; /*!< Channel Request Mask Clear Register */ + __IO uint32_t DMAENSET; /*!< Channel Enable Set Register */ + __IO uint32_t DMAENCLR; /*!< Channel Enable Clear Register */ + __IO uint32_t DMAALTSET; /*!< Channel Primary-Alternate Set Register */ + __IO uint32_t DMAALTCLR; /*!< Channel Primary-Alternate Clear Register */ + __IO uint32_t DMAPRISET; /*!< Channel Priority Set Register */ + __IO uint32_t DMAPRICLR; /*!< Channel Priority Clear Register */ + __I uint32_t RESERVED2[3]; + __IO uint32_t DMAERRCLR; /*!< Bus Error Clear Register */ +} ADI_DMA_TypeDef; +#else // (__NO_MMR_STRUCTS__==0) +#define DMASTA (*(volatile unsigned long *) 0x40010000) +#define DMACFG (*(volatile unsigned long *) 0x40010004) +#define DMAPDBPTR (*(volatile unsigned long *) 0x40010008) +#define DMAADBPTR (*(volatile unsigned long *) 0x4001000C) +#define DMASWREQ (*(volatile unsigned long *) 0x40010014) +#define DMARMSKSET (*(volatile unsigned long *) 0x40010020) +#define DMARMSKCLR (*(volatile unsigned long *) 0x40010024) +#define DMAENSET (*(volatile unsigned long *) 0x40010028) +#define DMAENCLR (*(volatile unsigned long *) 0x4001002C) +#define DMAALTSET (*(volatile unsigned long *) 0x40010030) +#define DMAALTCLR (*(volatile unsigned long *) 0x40010034) +#define DMAPRISET (*(volatile unsigned long *) 0x40010038) +#define DMAPRICLR (*(volatile unsigned long *) 0x4001003C) +#define DMAERRCLR (*(volatile unsigned long *) 0x4001004C) +#endif // (__NO_MMR_STRUCTS__==0) + +/* Reset Value for DMASTA*/ +#define DMASTA_RVAL 0xD0000 + +/* DMASTA[CHNLSMINUS1] - Number of available DMA channels minus 1. For example, if there are 14 channels available, the register reads back 0xD for these bits. */ +#define DMASTA_CHNLSMINUS1_MSK (0x1F << 16 ) +#define DMASTA_CHNLSMINUS1_FOURTEENCHNLS (0xD << 16 ) /* FOURTEENCHNLS - Controller configured to use 14 DMA channels. */ + +/* DMASTA[STATE] - Current state of DMA controller state machine. Provides insight into the operation performed by the DMA at the time this register is read. */ +#define DMASTA_STATE_MSK (0xF << 4 ) +#define DMASTA_STATE_IDLE (0x0 << 4 ) /* IDL. Idle. */ +#define DMASTA_STATE_RDCHNLDATA (0x1 << 4 ) /* RDCHNLDATA. Reading channel controller data. */ +#define DMASTA_STATE_RDSRCENDPTR (0x2 << 4 ) /* RDSRCENDPTR. Reading source data end pointer. */ +#define DMASTA_STATE_RDDSTENDPTR (0x3 << 4 ) /* RDDSTENDPTR. Reading destination end pointer. */ +#define DMASTA_STATE_RDSRCDATA (0x4 << 4 ) /* RDSRCDATA. Reading source data. */ +#define DMASTA_STATE_WRDSTDATA (0x5 << 4 ) /* WRDSTDATA. Writing destination data. */ +#define DMASTA_STATE_WAITDMAREQCLR (0x6 << 4 ) /* WAITDMAREQCLR. Waiting for DMA request to clear. */ +#define DMASTA_STATE_WRCHNLDATA (0x7 << 4 ) /* WRCHNLDATA. Writing channel controller data. */ +#define DMASTA_STATE_STALLED (0x8 << 4 ) /* STALLED. Stalled. */ +#define DMASTA_STATE_DONE (0x9 << 4 ) /* DONE. Done. */ +#define DMASTA_STATE_SCATRGATHR (0xA << 4 ) /* SCATRGATHR. Peripheral scatter-gather transition. */ + +/* DMASTA[ENABLE] - Enable status of the controller. */ +#define DMASTA_ENABLE_BBA (*(volatile unsigned long *) 0x42200000) +#define DMASTA_ENABLE_MSK (0x1 << 0 ) +#define DMASTA_ENABLE (0x1 << 0 ) +#define DMASTA_ENABLE_CLR (0x0 << 0 ) /* CLR. Controller is disabled. */ +#define DMASTA_ENABLE_SET (0x1 << 0 ) /* SET. Controller is enabled. */ + +/* Reset Value for DMACFG*/ +#define DMACFG_RVAL 0x0 + +/* DMACFG[ENABLE] - Controller enable. */ +#define DMACFG_ENABLE_BBA (*(volatile unsigned long *) 0x42200080) +#define DMACFG_ENABLE_MSK (0x1 << 0 ) +#define DMACFG_ENABLE (0x1 << 0 ) +#define DMACFG_ENABLE_DIS (0x0 << 0 ) /* DIS. Controller is disabled. */ +#define DMACFG_ENABLE_EN (0x1 << 0 ) /* EN. Controller is enabled. */ + +/* Reset Value for DMAPDBPTR*/ +#define DMAPDBPTR_RVAL 0x0 + +/* DMAPDBPTR[CTRLBASEPTR] - Pointer to the base address of the primary data structure. 5 + log (2)M LSBs are reserved and must be written 0. M is the number of channels. */ +#define DMAPDBPTR_CTRLBASEPTR_MSK (0xFFFFFFFF << 0 ) + +/* Reset Value for DMAADBPTR*/ +#define DMAADBPTR_RVAL 0x100 + +/* DMAADBPTR[ALTCBPTR] - Base address of the alternate data structure. */ +#define DMAADBPTR_ALTCBPTR_MSK (0xFFFFFFFF << 0 ) + +/* Reset Value for DMASWREQ*/ +#define DMASWREQ_RVAL 0x0 + +/* DMASWREQ[SPI0RX] - DMA SPI0 RX. */ +#define DMASWREQ_SPI0RX_BBA (*(volatile unsigned long *) 0x422002B4) +#define DMASWREQ_SPI0RX_MSK (0x1 << 13 ) +#define DMASWREQ_SPI0RX (0x1 << 13 ) +#define DMASWREQ_SPI0RX_DIS (0x0 << 13 ) /* DIS. Does not create a DMA request for SPI0RX. */ +#define DMASWREQ_SPI0RX_EN (0x1 << 13 ) /* EN. Generates a DMA request for SPI0RX. */ + +/* DMASWREQ[SPI0TX] - DMA SPI0 TX. */ +#define DMASWREQ_SPI0TX_BBA (*(volatile unsigned long *) 0x422002B0) +#define DMASWREQ_SPI0TX_MSK (0x1 << 12 ) +#define DMASWREQ_SPI0TX (0x1 << 12 ) +#define DMASWREQ_SPI0TX_DIS (0x0 << 12 ) /* DIS. Does not create a DMA request for SPI0TX. */ +#define DMASWREQ_SPI0TX_EN (0x1 << 12 ) /* EN. Generates a DMA request for SPI0TX. */ + +/* DMASWREQ[ADC] - DMA ADC. */ +#define DMASWREQ_ADC_BBA (*(volatile unsigned long *) 0x422002AC) +#define DMASWREQ_ADC_MSK (0x1 << 11 ) +#define DMASWREQ_ADC (0x1 << 11 ) +#define DMASWREQ_ADC_DIS (0x0 << 11 ) /* DIS. Does not create a DMA request for ADC. */ +#define DMASWREQ_ADC_EN (0x1 << 11 ) /* EN. Generates a DMA request for ADC. */ + +/* DMASWREQ[I2CMRX] - DMA I2C Master RX. */ +#define DMASWREQ_I2CMRX_BBA (*(volatile unsigned long *) 0x4220029C) +#define DMASWREQ_I2CMRX_MSK (0x1 << 7 ) +#define DMASWREQ_I2CMRX (0x1 << 7 ) +#define DMASWREQ_I2CMRX_DIS (0x0 << 7 ) /* DIS. Does not create a DMA request for I2CMRX. */ +#define DMASWREQ_I2CMRX_EN (0x1 << 7 ) /* EN. Generates a DMA request for I2CMRX. */ + +/* DMASWREQ[I2CMTX] - DMA I2C Master TX. */ +#define DMASWREQ_I2CMTX_BBA (*(volatile unsigned long *) 0x42200298) +#define DMASWREQ_I2CMTX_MSK (0x1 << 6 ) +#define DMASWREQ_I2CMTX (0x1 << 6 ) +#define DMASWREQ_I2CMTX_DIS (0x0 << 6 ) /* DIS. Does not create a DMA request for I2CMTX. */ +#define DMASWREQ_I2CMTX_EN (0x1 << 6 ) /* EN. Generates a DMA request for I2CMTX. */ + +/* DMASWREQ[I2CSRX] - DMA I2C Slave RX. */ +#define DMASWREQ_I2CSRX_BBA (*(volatile unsigned long *) 0x42200294) +#define DMASWREQ_I2CSRX_MSK (0x1 << 5 ) +#define DMASWREQ_I2CSRX (0x1 << 5 ) +#define DMASWREQ_I2CSRX_DIS (0x0 << 5 ) /* DIS. Does not create a DMA request for I2CSRX. */ +#define DMASWREQ_I2CSRX_EN (0x1 << 5 ) /* EN. Generates a DMA request for I2CSRX. */ + +/* DMASWREQ[I2CSTX] - DMA I2C Slave TX. */ +#define DMASWREQ_I2CSTX_BBA (*(volatile unsigned long *) 0x42200290) +#define DMASWREQ_I2CSTX_MSK (0x1 << 4 ) +#define DMASWREQ_I2CSTX (0x1 << 4 ) +#define DMASWREQ_I2CSTX_DIS (0x0 << 4 ) /* DIS. Does not create a DMA request for I2CSTX. */ +#define DMASWREQ_I2CSTX_EN (0x1 << 4 ) /* EN. Generates a DMA request for I2CSTX. */ + +/* DMASWREQ[UARTRX] - DMA UART RX. */ +#define DMASWREQ_UARTRX_BBA (*(volatile unsigned long *) 0x4220028C) +#define DMASWREQ_UARTRX_MSK (0x1 << 3 ) +#define DMASWREQ_UARTRX (0x1 << 3 ) +#define DMASWREQ_UARTRX_DIS (0x0 << 3 ) /* DIS. Does not create a DMA request for UARTRX. */ +#define DMASWREQ_UARTRX_EN (0x1 << 3 ) /* EN. Generates a DMA request for UARTRX. */ + +/* DMASWREQ[UARTTX] - DMA UART TX. */ +#define DMASWREQ_UARTTX_BBA (*(volatile unsigned long *) 0x42200288) +#define DMASWREQ_UARTTX_MSK (0x1 << 2 ) +#define DMASWREQ_UARTTX (0x1 << 2 ) +#define DMASWREQ_UARTTX_DIS (0x0 << 2 ) /* DIS. Does not create a DMA request for UARTTX. */ +#define DMASWREQ_UARTTX_EN (0x1 << 2 ) /* EN. Generates a DMA request for UARTTX. */ + +/* DMASWREQ[SPI1RX] - DMA SPI 1 RX. */ +#define DMASWREQ_SPI1RX_BBA (*(volatile unsigned long *) 0x42200284) +#define DMASWREQ_SPI1RX_MSK (0x1 << 1 ) +#define DMASWREQ_SPI1RX (0x1 << 1 ) +#define DMASWREQ_SPI1RX_DIS (0x0 << 1 ) /* DIS. Does not create a DMA request for SPI1RX. */ +#define DMASWREQ_SPI1RX_EN (0x1 << 1 ) /* EN. Generates a DMA request for SPI1RX. */ + +/* DMASWREQ[SPI1TX] - DMA SPI 1 TX. */ +#define DMASWREQ_SPI1TX_BBA (*(volatile unsigned long *) 0x42200280) +#define DMASWREQ_SPI1TX_MSK (0x1 << 0 ) +#define DMASWREQ_SPI1TX (0x1 << 0 ) +#define DMASWREQ_SPI1TX_DIS (0x0 << 0 ) /* DIS. Does not create a DMA request for SPI1TX. */ +#define DMASWREQ_SPI1TX_EN (0x1 << 0 ) /* EN. Generates a DMA request for SPI1TX. */ + +/* Reset Value for DMARMSKSET*/ +#define DMARMSKSET_RVAL 0x0 + +/* DMARMSKSET[SPI0RX] - DMA SPI0 RX. */ +#define DMARMSKSET_SPI0RX_BBA (*(volatile unsigned long *) 0x42200434) +#define DMARMSKSET_SPI0RX_MSK (0x1 << 13 ) +#define DMARMSKSET_SPI0RX (0x1 << 13 ) +#define DMARMSKSET_SPI0RX_DIS (0x0 << 13 ) /* DIS. When read: Requests are enabled for SPI0RX. When written: No effect. Use the DMARMSKCLR register to enable DMA requests. */ +#define DMARMSKSET_SPI0RX_EN (0x1 << 13 ) /* EN. When read: Requests are disabled for SPI0RX. When written: Disables peripheral associated with SPI0RX from generating DMA requests. */ + +/* DMARMSKSET[SPI0TX] - DMA SPI0 TX. */ +#define DMARMSKSET_SPI0TX_BBA (*(volatile unsigned long *) 0x42200430) +#define DMARMSKSET_SPI0TX_MSK (0x1 << 12 ) +#define DMARMSKSET_SPI0TX (0x1 << 12 ) +#define DMARMSKSET_SPI0TX_DIS (0x0 << 12 ) /* DIS. When read: Requests are enabled for SPI0TX. When written: No effect. Use the DMARMSKCLR register to enable DMA requests. */ +#define DMARMSKSET_SPI0TX_EN (0x1 << 12 ) /* EN. When read: Requests are disabled for SPI0TX. When written: Disables peripheral associated with SPI0TX from generating DMA requests. */ + +/* DMARMSKSET[ADC] - DMA ADC. */ +#define DMARMSKSET_ADC_BBA (*(volatile unsigned long *) 0x4220042C) +#define DMARMSKSET_ADC_MSK (0x1 << 11 ) +#define DMARMSKSET_ADC (0x1 << 11 ) +#define DMARMSKSET_ADC_DIS (0x0 << 11 ) /* DIS. When read: Requests are enabled for ADC. When written: No effect. Use the DMARMSKCLR register to enable DMA requests. */ +#define DMARMSKSET_ADC_EN (0x1 << 11 ) /* EN. When read: Requests are disabled for ADC. When written: Disables peripheral associated with ADC from generating DMA requests. */ + +/* DMARMSKSET[I2CMRX] - DMA I2C Master RX. */ +#define DMARMSKSET_I2CMRX_BBA (*(volatile unsigned long *) 0x4220041C) +#define DMARMSKSET_I2CMRX_MSK (0x1 << 7 ) +#define DMARMSKSET_I2CMRX (0x1 << 7 ) +#define DMARMSKSET_I2CMRX_DIS (0x0 << 7 ) /* DIS. When read: Requests are enabled for I2CMRX. When written: No effect. Use the DMARMSKCLR register to enable DMA requests. */ +#define DMARMSKSET_I2CMRX_EN (0x1 << 7 ) /* EN. When read: Requests are disabled for I2CMRX. When written: Disables peripheral associated with I2CMRX from generating DMA requests. */ + +/* DMARMSKSET[I2CMTX] - DMA I2C Master TX. */ +#define DMARMSKSET_I2CMTX_BBA (*(volatile unsigned long *) 0x42200418) +#define DMARMSKSET_I2CMTX_MSK (0x1 << 6 ) +#define DMARMSKSET_I2CMTX (0x1 << 6 ) +#define DMARMSKSET_I2CMTX_DIS (0x0 << 6 ) /* DIS. When read: Requests are enabled for I2CMTX. When written: No effect. Use the DMARMSKCLR register to enable DMA requests. */ +#define DMARMSKSET_I2CMTX_EN (0x1 << 6 ) /* EN. When read: Requests are disabled for I2CMTX. When written: Disables peripheral associated with I2CMTX from generating DMA requests. */ + +/* DMARMSKSET[I2CSRX] - DMA I2C Slave RX. */ +#define DMARMSKSET_I2CSRX_BBA (*(volatile unsigned long *) 0x42200414) +#define DMARMSKSET_I2CSRX_MSK (0x1 << 5 ) +#define DMARMSKSET_I2CSRX (0x1 << 5 ) +#define DMARMSKSET_I2CSRX_DIS (0x0 << 5 ) /* DIS. When read: Requests are enabled for I2CSRX. When written: No effect. Use the DMARMSKCLR register to enable DMA requests. */ +#define DMARMSKSET_I2CSRX_EN (0x1 << 5 ) /* EN. When read: Requests are disabled for I2CSRX. When written: Disables peripheral associated with I2CSRX from generating DMA requests. */ + +/* DMARMSKSET[I2CSTX] - DMA I2C Slave TX. */ +#define DMARMSKSET_I2CSTX_BBA (*(volatile unsigned long *) 0x42200410) +#define DMARMSKSET_I2CSTX_MSK (0x1 << 4 ) +#define DMARMSKSET_I2CSTX (0x1 << 4 ) +#define DMARMSKSET_I2CSTX_DIS (0x0 << 4 ) /* DIS. When read: Requests are enabled forI2CSTX. When written: No effect. Use the DMARMSKCLR register to enable DMA requests. */ +#define DMARMSKSET_I2CSTX_EN (0x1 << 4 ) /* EN. When read: Requests are disabled for I2CSTX. When written: Disables peripheral associated with I2CSTX from generating DMA requests. */ + +/* DMARMSKSET[UARTRX] - DMA UART RX. */ +#define DMARMSKSET_UARTRX_BBA (*(volatile unsigned long *) 0x4220040C) +#define DMARMSKSET_UARTRX_MSK (0x1 << 3 ) +#define DMARMSKSET_UARTRX (0x1 << 3 ) +#define DMARMSKSET_UARTRX_DIS (0x0 << 3 ) /* DIS. When read: Requests are enabled for UARTRX. When written: No effect. Use the DMARMSKCLR register to enable DMA requests. */ +#define DMARMSKSET_UARTRX_EN (0x1 << 3 ) /* EN. When read: Requests are disabled for UARTRX. When written: Disables peripheral associated with UARTRX from generating DMA requests. */ + +/* DMARMSKSET[UARTTX] - DMA UART TX. */ +#define DMARMSKSET_UARTTX_BBA (*(volatile unsigned long *) 0x42200408) +#define DMARMSKSET_UARTTX_MSK (0x1 << 2 ) +#define DMARMSKSET_UARTTX (0x1 << 2 ) +#define DMARMSKSET_UARTTX_DIS (0x0 << 2 ) /* DIS. When read: Requests are enabled for UARTTX. When written: No effect. Use the DMARMSKCLR register to enable DMA requests. */ +#define DMARMSKSET_UARTTX_EN (0x1 << 2 ) /* EN. When read: Requests are disabled for UARTTX. When written: Disables peripheral associated with UARTTX from generating DMA requests. */ + +/* DMARMSKSET[SPI1RX] - DMA SPI 1 RX. */ +#define DMARMSKSET_SPI1RX_BBA (*(volatile unsigned long *) 0x42200404) +#define DMARMSKSET_SPI1RX_MSK (0x1 << 1 ) +#define DMARMSKSET_SPI1RX (0x1 << 1 ) +#define DMARMSKSET_SPI1RX_DIS (0x0 << 1 ) /* DIS. When read: Requests are enabled for SPI1RX. When written: No effect. Use the DMARMSKCLR register to enable DMA requests. */ +#define DMARMSKSET_SPI1RX_EN (0x1 << 1 ) /* EN. When read: Requests are disabled for SPI1RX. When written: Disables peripheral associated with SPI1RX from generating DMA requests. */ + +/* DMARMSKSET[SPI1TX] - DMA SPI 1 TX. */ +#define DMARMSKSET_SPI1TX_BBA (*(volatile unsigned long *) 0x42200400) +#define DMARMSKSET_SPI1TX_MSK (0x1 << 0 ) +#define DMARMSKSET_SPI1TX (0x1 << 0 ) +#define DMARMSKSET_SPI1TX_DIS (0x0 << 0 ) /* DIS. When read: Requests are enabled for SPI1TX. When written: No effect. Use the DMARMSKCLR register to enable DMA requests. */ +#define DMARMSKSET_SPI1TX_EN (0x1 << 0 ) /* EN. When read: Requests are disabled for SPI1TX When written: Disables peripheral associated with SPI1TX from generating DMA requests. */ + +/* Reset Value for DMARMSKCLR*/ +#define DMARMSKCLR_RVAL 0x0 + +/* DMARMSKCLR[SPI0RX] - DMA SPI0 RX. */ +#define DMARMSKCLR_SPI0RX_BBA (*(volatile unsigned long *) 0x422004B4) +#define DMARMSKCLR_SPI0RX_MSK (0x1 << 13 ) +#define DMARMSKCLR_SPI0RX (0x1 << 13 ) +#define DMARMSKCLR_SPI0RX_DIS (0x0 << 13 ) /* DIS. No effect. Use the DMARMSKSET register to disable DMA requests. */ +#define DMARMSKCLR_SPI0RX_EN (0x1 << 13 ) /* EN. Enables peripheral associated with SPI0RX to generate DMA requests. */ + +/* DMARMSKCLR[SPI0TX] - DMA SPI0 TX. */ +#define DMARMSKCLR_SPI0TX_BBA (*(volatile unsigned long *) 0x422004B0) +#define DMARMSKCLR_SPI0TX_MSK (0x1 << 12 ) +#define DMARMSKCLR_SPI0TX (0x1 << 12 ) +#define DMARMSKCLR_SPI0TX_DIS (0x0 << 12 ) /* DIS. No effect. Use the DMARMSKSET register to disable DMA requests. */ +#define DMARMSKCLR_SPI0TX_EN (0x1 << 12 ) /* EN. Enables peripheral associated with SPI0TX to generate DMA requests. */ + +/* DMARMSKCLR[ADC] - DMA ADC. */ +#define DMARMSKCLR_ADC_BBA (*(volatile unsigned long *) 0x422004AC) +#define DMARMSKCLR_ADC_MSK (0x1 << 11 ) +#define DMARMSKCLR_ADC (0x1 << 11 ) +#define DMARMSKCLR_ADC_DIS (0x0 << 11 ) /* DIS. No effect. Use the DMARMSKSET register to disable DMA requests. */ +#define DMARMSKCLR_ADC_EN (0x1 << 11 ) /* EN. Enables peripheral associated with ADC to generate DMA requests. */ + +/* DMARMSKCLR[I2CMRX] - DMA I2C Master RX. */ +#define DMARMSKCLR_I2CMRX_BBA (*(volatile unsigned long *) 0x4220049C) +#define DMARMSKCLR_I2CMRX_MSK (0x1 << 7 ) +#define DMARMSKCLR_I2CMRX (0x1 << 7 ) +#define DMARMSKCLR_I2CMRX_DIS (0x0 << 7 ) /* DIS. No effect. Use the DMARMSKSET register to disable DMA requests. */ +#define DMARMSKCLR_I2CMRX_EN (0x1 << 7 ) /* EN. Enables peripheral associated with I2CMRX to generate DMA requests. */ + +/* DMARMSKCLR[I2CMTX] - DMA I2C Master TX. */ +#define DMARMSKCLR_I2CMTX_BBA (*(volatile unsigned long *) 0x42200498) +#define DMARMSKCLR_I2CMTX_MSK (0x1 << 6 ) +#define DMARMSKCLR_I2CMTX (0x1 << 6 ) +#define DMARMSKCLR_I2CMTX_DIS (0x0 << 6 ) /* DIS. No effect. Use the DMARMSKSET register to disable DMA requests. */ +#define DMARMSKCLR_I2CMTX_EN (0x1 << 6 ) /* EN. Enables peripheral associated with I2CMTX to generate DMA requests. */ + +/* DMARMSKCLR[I2CSRX] - DMA I2C Slave RX. */ +#define DMARMSKCLR_I2CSRX_BBA (*(volatile unsigned long *) 0x42200494) +#define DMARMSKCLR_I2CSRX_MSK (0x1 << 5 ) +#define DMARMSKCLR_I2CSRX (0x1 << 5 ) +#define DMARMSKCLR_I2CSRX_DIS (0x0 << 5 ) /* DIS. No effect. Use the DMARMSKSET register to disable DMA requests. */ +#define DMARMSKCLR_I2CSRX_EN (0x1 << 5 ) /* EN. Enables peripheral associated with I2CSRX to generate DMA requests. */ + +/* DMARMSKCLR[I2CSTX] - DMA I2C Slave TX. */ +#define DMARMSKCLR_I2CSTX_BBA (*(volatile unsigned long *) 0x42200490) +#define DMARMSKCLR_I2CSTX_MSK (0x1 << 4 ) +#define DMARMSKCLR_I2CSTX (0x1 << 4 ) +#define DMARMSKCLR_I2CSTX_DIS (0x0 << 4 ) /* DIS. No effect. Use the DMARMSKSET register to disable DMA requests. */ +#define DMARMSKCLR_I2CSTX_EN (0x1 << 4 ) /* EN. Enables peripheral associated with I2CSTX to generate DMA requests. */ + +/* DMARMSKCLR[UARTRX] - DMA UART RX. */ +#define DMARMSKCLR_UARTRX_BBA (*(volatile unsigned long *) 0x4220048C) +#define DMARMSKCLR_UARTRX_MSK (0x1 << 3 ) +#define DMARMSKCLR_UARTRX (0x1 << 3 ) +#define DMARMSKCLR_UARTRX_DIS (0x0 << 3 ) /* DIS. No effect. Use the DMARMSKSET register to disable DMA requests. */ +#define DMARMSKCLR_UARTRX_EN (0x1 << 3 ) /* EN. Enables peripheral associated with UARTRX to generate DMA requests. */ + +/* DMARMSKCLR[UARTTX] - DMA UART TX. */ +#define DMARMSKCLR_UARTTX_BBA (*(volatile unsigned long *) 0x42200488) +#define DMARMSKCLR_UARTTX_MSK (0x1 << 2 ) +#define DMARMSKCLR_UARTTX (0x1 << 2 ) +#define DMARMSKCLR_UARTTX_DIS (0x0 << 2 ) /* DIS. No effect. Use the DMARMSKSET register to disable DMA requests. */ +#define DMARMSKCLR_UARTTX_EN (0x1 << 2 ) /* EN. Enables peripheral associated with UARTTX to generate DMA requests. */ + +/* DMARMSKCLR[SPI1RX] - DMA SPI 1 RX. */ +#define DMARMSKCLR_SPI1RX_BBA (*(volatile unsigned long *) 0x42200484) +#define DMARMSKCLR_SPI1RX_MSK (0x1 << 1 ) +#define DMARMSKCLR_SPI1RX (0x1 << 1 ) +#define DMARMSKCLR_SPI1RX_DIS (0x0 << 1 ) /* DIS. No effect. Use the DMARMSKSET register to disable DMA requests. */ +#define DMARMSKCLR_SPI1RX_EN (0x1 << 1 ) /* EN. Enables peripheral associated with SPI1RX to generate DMA requests. */ + +/* DMARMSKCLR[SPI1TX] - DMA SPI 1 TX. */ +#define DMARMSKCLR_SPI1TX_BBA (*(volatile unsigned long *) 0x42200480) +#define DMARMSKCLR_SPI1TX_MSK (0x1 << 0 ) +#define DMARMSKCLR_SPI1TX (0x1 << 0 ) +#define DMARMSKCLR_SPI1TX_DIS (0x0 << 0 ) /* DIS. No effect. Use the DMARMSKSET register to disable DMA requests. */ +#define DMARMSKCLR_SPI1TX_EN (0x1 << 0 ) /* EN. Enables peripheral associated with SPI1TX to generate DMA requests. */ + +/* Reset Value for DMAENSET*/ +#define DMAENSET_RVAL 0x0 + +/* DMAENSET[SPI0RX] - DMA SPI0 RX */ +#define DMAENSET_SPI0RX_BBA (*(volatile unsigned long *) 0x42200534) +#define DMAENSET_SPI0RX_MSK (0x1 << 13 ) +#define DMAENSET_SPI0RX (0x1 << 13 ) +#define DMAENSET_SPI0RX_DIS (0x0 << 13 ) /* DIS. No effect. Use the DMAENCLR register to disable the channel. */ +#define DMAENSET_SPI0RX_EN (0x1 << 13 ) /* EN. Enables SPI0RX. */ + +/* DMAENSET[SPI0TX] - DMA SPI0 TX. */ +#define DMAENSET_SPI0TX_BBA (*(volatile unsigned long *) 0x42200530) +#define DMAENSET_SPI0TX_MSK (0x1 << 12 ) +#define DMAENSET_SPI0TX (0x1 << 12 ) +#define DMAENSET_SPI0TX_DIS (0x0 << 12 ) /* DIS. No effect. Use the DMAENCLR register to disable the channel. */ +#define DMAENSET_SPI0TX_EN (0x1 << 12 ) /* EN. Enables SPI0TX. */ + +/* DMAENSET[ADC] - DMA ADC. */ +#define DMAENSET_ADC_BBA (*(volatile unsigned long *) 0x4220052C) +#define DMAENSET_ADC_MSK (0x1 << 11 ) +#define DMAENSET_ADC (0x1 << 11 ) +#define DMAENSET_ADC_DIS (0x0 << 11 ) /* DIS. No effect. Use the DMAENCLR register to disable the channel. */ +#define DMAENSET_ADC_EN (0x1 << 11 ) /* EN. Enables ADC. */ + +/* DMAENSET[I2CMRX] - DMA I2C Master RX. */ +#define DMAENSET_I2CMRX_BBA (*(volatile unsigned long *) 0x4220051C) +#define DMAENSET_I2CMRX_MSK (0x1 << 7 ) +#define DMAENSET_I2CMRX (0x1 << 7 ) +#define DMAENSET_I2CMRX_DIS (0x0 << 7 ) /* DIS. No effect. Use the DMAENCLR register to disable the channel. */ +#define DMAENSET_I2CMRX_EN (0x1 << 7 ) /* EN. . Enables I2CMRX. */ + +/* DMAENSET[I2CMTX] - DMA I2C Master TX. */ +#define DMAENSET_I2CMTX_BBA (*(volatile unsigned long *) 0x42200518) +#define DMAENSET_I2CMTX_MSK (0x1 << 6 ) +#define DMAENSET_I2CMTX (0x1 << 6 ) +#define DMAENSET_I2CMTX_DIS (0x0 << 6 ) /* DIS. No effect. Use the DMAENCLR register to disable the channel. */ +#define DMAENSET_I2CMTX_EN (0x1 << 6 ) /* EN. . Enables I2CMTX. */ + +/* DMAENSET[I2CSRX] - DMA I2C Slave RX. */ +#define DMAENSET_I2CSRX_BBA (*(volatile unsigned long *) 0x42200514) +#define DMAENSET_I2CSRX_MSK (0x1 << 5 ) +#define DMAENSET_I2CSRX (0x1 << 5 ) +#define DMAENSET_I2CSRX_DIS (0x0 << 5 ) /* DIS. No effect. Use the DMAENCLR register to disable the channel. */ +#define DMAENSET_I2CSRX_EN (0x1 << 5 ) /* EN. Enables I2CSRX. */ + +/* DMAENSET[I2CSTX] - DMA I2C Slave TX. */ +#define DMAENSET_I2CSTX_BBA (*(volatile unsigned long *) 0x42200510) +#define DMAENSET_I2CSTX_MSK (0x1 << 4 ) +#define DMAENSET_I2CSTX (0x1 << 4 ) +#define DMAENSET_I2CSTX_DIS (0x0 << 4 ) /* DIS. No effect. Use the DMAENCLR register to disable the channel. */ +#define DMAENSET_I2CSTX_EN (0x1 << 4 ) /* EN. Enables I2CSTX. */ + +/* DMAENSET[UARTRX] - DMA UART RX. */ +#define DMAENSET_UARTRX_BBA (*(volatile unsigned long *) 0x4220050C) +#define DMAENSET_UARTRX_MSK (0x1 << 3 ) +#define DMAENSET_UARTRX (0x1 << 3 ) +#define DMAENSET_UARTRX_DIS (0x0 << 3 ) /* DIS. No effect. Use the DMAENCLR register to disable the channel. */ +#define DMAENSET_UARTRX_EN (0x1 << 3 ) /* EN. Enables UARTRX. */ + +/* DMAENSET[UARTTX] - DMA UART TX. */ +#define DMAENSET_UARTTX_BBA (*(volatile unsigned long *) 0x42200508) +#define DMAENSET_UARTTX_MSK (0x1 << 2 ) +#define DMAENSET_UARTTX (0x1 << 2 ) +#define DMAENSET_UARTTX_DIS (0x0 << 2 ) /* DIS. No effect. Use the DMAENCLR register to disable the channel. */ +#define DMAENSET_UARTTX_EN (0x1 << 2 ) /* EN. Enables UARTTX. */ + +/* DMAENSET[SPI1RX] - DMA SPI 1 RX. */ +#define DMAENSET_SPI1RX_BBA (*(volatile unsigned long *) 0x42200504) +#define DMAENSET_SPI1RX_MSK (0x1 << 1 ) +#define DMAENSET_SPI1RX (0x1 << 1 ) +#define DMAENSET_SPI1RX_DIS (0x0 << 1 ) /* DIS. No effect. Use the DMAENCLR register to disable the channel. */ +#define DMAENSET_SPI1RX_EN (0x1 << 1 ) /* EN. Enables SPI1RX. */ + +/* DMAENSET[SPI1TX] - DMA SPI 1 TX. */ +#define DMAENSET_SPI1TX_BBA (*(volatile unsigned long *) 0x42200500) +#define DMAENSET_SPI1TX_MSK (0x1 << 0 ) +#define DMAENSET_SPI1TX (0x1 << 0 ) +#define DMAENSET_SPI1TX_DIS (0x0 << 0 ) /* DIS. No effect. Use the DMAENCLR register to disable the channel. */ +#define DMAENSET_SPI1TX_EN (0x1 << 0 ) /* EN. Enables SPI1TX. */ + +/* Reset Value for DMAENCLR*/ +#define DMAENCLR_RVAL 0x0 + +/* DMAENCLR[SPI0RX] - DMA SPI0 RX */ +#define DMAENCLR_SPI0RX_BBA (*(volatile unsigned long *) 0x422005B4) +#define DMAENCLR_SPI0RX_MSK (0x1 << 13 ) +#define DMAENCLR_SPI0RX (0x1 << 13 ) +#define DMAENCLR_SPI0RX_DIS (0x0 << 13 ) /* DIS. No effect. Use the DMAENSET register to enable the channel. */ +#define DMAENCLR_SPI0RX_EN (0x1 << 13 ) /* EN. Disables SPI0RX. */ + +/* DMAENCLR[SPI0TX] - DMA SPI0 TX */ +#define DMAENCLR_SPI0TX_BBA (*(volatile unsigned long *) 0x422005B0) +#define DMAENCLR_SPI0TX_MSK (0x1 << 12 ) +#define DMAENCLR_SPI0TX (0x1 << 12 ) +#define DMAENCLR_SPI0TX_DIS (0x0 << 12 ) /* DIS. No effect. Use the DMAENSET register to enable the channel. */ +#define DMAENCLR_SPI0TX_EN (0x1 << 12 ) /* EN. Disables SPI0TX. */ + +/* DMAENCLR[ADC] - DMA ADC. */ +#define DMAENCLR_ADC_BBA (*(volatile unsigned long *) 0x422005AC) +#define DMAENCLR_ADC_MSK (0x1 << 11 ) +#define DMAENCLR_ADC (0x1 << 11 ) +#define DMAENCLR_ADC_DIS (0x0 << 11 ) /* DIS. No effect. Use the DMAENSET register to enable the channel. */ +#define DMAENCLR_ADC_EN (0x1 << 11 ) /* EN. Disables ADC. */ + +/* DMAENCLR[I2CMRX] - DMA I2C Master RX. */ +#define DMAENCLR_I2CMRX_BBA (*(volatile unsigned long *) 0x4220059C) +#define DMAENCLR_I2CMRX_MSK (0x1 << 7 ) +#define DMAENCLR_I2CMRX (0x1 << 7 ) +#define DMAENCLR_I2CMRX_DIS (0x0 << 7 ) /* DIS. No effect. Use the DMAENSET register to enable the channel. */ +#define DMAENCLR_I2CMRX_EN (0x1 << 7 ) /* EN. Disables I2CMRX. */ + +/* DMAENCLR[I2CMTX] - DMA I2C Master TX. */ +#define DMAENCLR_I2CMTX_BBA (*(volatile unsigned long *) 0x42200598) +#define DMAENCLR_I2CMTX_MSK (0x1 << 6 ) +#define DMAENCLR_I2CMTX (0x1 << 6 ) +#define DMAENCLR_I2CMTX_DIS (0x0 << 6 ) /* DIS. No effect. Use the DMAENSET register to enable the channel. */ +#define DMAENCLR_I2CMTX_EN (0x1 << 6 ) /* EN. Disables I2CMTX. */ + +/* DMAENCLR[I2CSRX] - DMA I2C Slave RX. */ +#define DMAENCLR_I2CSRX_BBA (*(volatile unsigned long *) 0x42200594) +#define DMAENCLR_I2CSRX_MSK (0x1 << 5 ) +#define DMAENCLR_I2CSRX (0x1 << 5 ) +#define DMAENCLR_I2CSRX_DIS (0x0 << 5 ) /* DIS. No effect. Use the DMAENSET register to enable the channel. */ +#define DMAENCLR_I2CSRX_EN (0x1 << 5 ) /* EN. Disables I2CSRX. */ + +/* DMAENCLR[I2CSTX] - DMA I2C Slave TX. */ +#define DMAENCLR_I2CSTX_BBA (*(volatile unsigned long *) 0x42200590) +#define DMAENCLR_I2CSTX_MSK (0x1 << 4 ) +#define DMAENCLR_I2CSTX (0x1 << 4 ) +#define DMAENCLR_I2CSTX_DIS (0x0 << 4 ) /* DIS. No effect. Use the DMAENSET register to enable the channel. */ +#define DMAENCLR_I2CSTX_EN (0x1 << 4 ) /* EN. Disables I2CSTX. */ + +/* DMAENCLR[UARTRX] - DMA UART RX. */ +#define DMAENCLR_UARTRX_BBA (*(volatile unsigned long *) 0x4220058C) +#define DMAENCLR_UARTRX_MSK (0x1 << 3 ) +#define DMAENCLR_UARTRX (0x1 << 3 ) +#define DMAENCLR_UARTRX_DIS (0x0 << 3 ) /* DIS. No effect. Use the DMAENSET register to enable the channel. */ +#define DMAENCLR_UARTRX_EN (0x1 << 3 ) /* EN. Disables UARTRX. */ + +/* DMAENCLR[UARTTX] - DMA UART TX. */ +#define DMAENCLR_UARTTX_BBA (*(volatile unsigned long *) 0x42200588) +#define DMAENCLR_UARTTX_MSK (0x1 << 2 ) +#define DMAENCLR_UARTTX (0x1 << 2 ) +#define DMAENCLR_UARTTX_DIS (0x0 << 2 ) /* DIS. No effect. Use the DMAENSET register to enable the channel. */ +#define DMAENCLR_UARTTX_EN (0x1 << 2 ) /* EN. Disables UARTTX. */ + +/* DMAENCLR[SPI1RX] - DMA SPI 1 RX. */ +#define DMAENCLR_SPI1RX_BBA (*(volatile unsigned long *) 0x42200584) +#define DMAENCLR_SPI1RX_MSK (0x1 << 1 ) +#define DMAENCLR_SPI1RX (0x1 << 1 ) +#define DMAENCLR_SPI1RX_DIS (0x0 << 1 ) /* DIS. No effect. Use the DMAENSET register to enable the channel. */ +#define DMAENCLR_SPI1RX_EN (0x1 << 1 ) /* EN. Disables SPI1RX. */ + +/* DMAENCLR[SPI1TX] - DMA SPI 1 TX. */ +#define DMAENCLR_SPI1TX_BBA (*(volatile unsigned long *) 0x42200580) +#define DMAENCLR_SPI1TX_MSK (0x1 << 0 ) +#define DMAENCLR_SPI1TX (0x1 << 0 ) +#define DMAENCLR_SPI1TX_DIS (0x0 << 0 ) /* DIS. No effect. Use the DMAENSET register to enable the channel. */ +#define DMAENCLR_SPI1TX_EN (0x1 << 0 ) /* EN. Disables SPI1TX. */ + +/* Reset Value for DMAALTSET*/ +#define DMAALTSET_RVAL 0x0 + +/* DMAALTSET[SPI0RX] - DMA SPI0 RX. */ +#define DMAALTSET_SPI0RX_BBA (*(volatile unsigned long *) 0x42200634) +#define DMAALTSET_SPI0RX_MSK (0x1 << 13 ) +#define DMAALTSET_SPI0RX (0x1 << 13 ) +#define DMAALTSET_SPI0RX_DIS (0x0 << 13 ) /* DIS. When read: DMA SPI0RX is using the primary data structure. When written: No effect. Use the DMAALTCLR register to set SPI0RX to 0. */ +#define DMAALTSET_SPI0RX_EN (0x1 << 13 ) /* EN. When read: DMA SPI0RX is using the alternate data structure. When written: Selects the alternate data structure for SPI0RX. */ + +/* DMAALTSET[SPI0TX] - DMA SPI0 TX. */ +#define DMAALTSET_SPI0TX_BBA (*(volatile unsigned long *) 0x42200630) +#define DMAALTSET_SPI0TX_MSK (0x1 << 12 ) +#define DMAALTSET_SPI0TX (0x1 << 12 ) +#define DMAALTSET_SPI0TX_DIS (0x0 << 12 ) /* DIS. When read: DMA SPI0TX is using the primary data structure. When written: No effect. Use the DMAALTCLR register to set SPI0TX to 0. */ +#define DMAALTSET_SPI0TX_EN (0x1 << 12 ) /* EN. When read: DMA SPI0TX is using the alternate data structure. When written: Selects the alternate data structure for SPI0TX. */ + +/* DMAALTSET[ADC] - DMA ADC. */ +#define DMAALTSET_ADC_BBA (*(volatile unsigned long *) 0x4220062C) +#define DMAALTSET_ADC_MSK (0x1 << 11 ) +#define DMAALTSET_ADC (0x1 << 11 ) +#define DMAALTSET_ADC_DIS (0x0 << 11 ) /* DIS. When read: DMA ADC is using the primary data structure. When written: No effect. Use the DMAALTCLR register to set ADC to 0. */ +#define DMAALTSET_ADC_EN (0x1 << 11 ) /* EN. When read: DMA ADC is using the alternate data structure. When written: Selects the alternate data structure for ADC. */ + +/* DMAALTSET[I2CMRX] - DMA I2C Master RX. */ +#define DMAALTSET_I2CMRX_BBA (*(volatile unsigned long *) 0x4220061C) +#define DMAALTSET_I2CMRX_MSK (0x1 << 7 ) +#define DMAALTSET_I2CMRX (0x1 << 7 ) +#define DMAALTSET_I2CMRX_DIS (0x0 << 7 ) /* DIS. When read: DMA I2CMRX is using the primary data structure. When written: No effect. Use the DMAALTCLR register to set I2CMRX to 0. */ +#define DMAALTSET_I2CMRX_EN (0x1 << 7 ) /* EN. When read: DMA I2CMRX is using the alternate data structure. When written: Selects the alternate data structure for I2CMRX. */ + +/* DMAALTSET[I2CMTX] - DMA I2C Master TX. */ +#define DMAALTSET_I2CMTX_BBA (*(volatile unsigned long *) 0x42200618) +#define DMAALTSET_I2CMTX_MSK (0x1 << 6 ) +#define DMAALTSET_I2CMTX (0x1 << 6 ) +#define DMAALTSET_I2CMTX_DIS (0x0 << 6 ) /* DIS. When read: DMA I2CMTX is using the primary data structure. When written: No effect. Use the DMAALTCLR register to set I2CMTX to 0. */ +#define DMAALTSET_I2CMTX_EN (0x1 << 6 ) /* EN. When read: DMA I2CMTX is using the alternate data structure. When written: Selects the alternate data structure forI2CMTX. */ + +/* DMAALTSET[I2CSRX] - DMA I2C Slave RX. */ +#define DMAALTSET_I2CSRX_BBA (*(volatile unsigned long *) 0x42200614) +#define DMAALTSET_I2CSRX_MSK (0x1 << 5 ) +#define DMAALTSET_I2CSRX (0x1 << 5 ) +#define DMAALTSET_I2CSRX_DIS (0x0 << 5 ) /* DIS. When read: DMA I2CSRX is using the primary data structure. When written: No effect. Use the DMAALTCLR register to set I2CSRX to 0. */ +#define DMAALTSET_I2CSRX_EN (0x1 << 5 ) /* EN. When read: DMA I2CSRX is using the alternate data structure. When written: Selects the alternate data structure for I2CSRX. */ + +/* DMAALTSET[I2CSTX] - DMA I2C Slave TX. */ +#define DMAALTSET_I2CSTX_BBA (*(volatile unsigned long *) 0x42200610) +#define DMAALTSET_I2CSTX_MSK (0x1 << 4 ) +#define DMAALTSET_I2CSTX (0x1 << 4 ) +#define DMAALTSET_I2CSTX_DIS (0x0 << 4 ) /* DIS. When read: DMA I2CSTX is using the primary data structure. When written: No effect. Use the DMAALTCLR register to set I2CSTX to 0. */ +#define DMAALTSET_I2CSTX_EN (0x1 << 4 ) /* EN. When read: DMA I2CSTX is using the alternate data structure. When written: Selects the alternate data structure for I2CSTX. */ + +/* DMAALTSET[UARTRX] - DMA UART RX. */ +#define DMAALTSET_UARTRX_BBA (*(volatile unsigned long *) 0x4220060C) +#define DMAALTSET_UARTRX_MSK (0x1 << 3 ) +#define DMAALTSET_UARTRX (0x1 << 3 ) +#define DMAALTSET_UARTRX_DIS (0x0 << 3 ) /* DIS. When read: DMA UARTRX is using the primary data structure. When written: No effect. Use the DMAALTCLR register to set UARTRX to 0. */ +#define DMAALTSET_UARTRX_EN (0x1 << 3 ) /* EN. When read: DMA UARTRX is using the alternate data structure. When written: Selects the alternate data structure for UARTRX. */ + +/* DMAALTSET[UARTTX] - DMA UART TX. */ +#define DMAALTSET_UARTTX_BBA (*(volatile unsigned long *) 0x42200608) +#define DMAALTSET_UARTTX_MSK (0x1 << 2 ) +#define DMAALTSET_UARTTX (0x1 << 2 ) +#define DMAALTSET_UARTTX_DIS (0x0 << 2 ) /* DIS. When read: DMA UARTTX is using the primary data structure. When written: No effect. Use the DMAALTCLR register to set UARTTX to 0. */ +#define DMAALTSET_UARTTX_EN (0x1 << 2 ) /* EN. When read: DMA UARTTX is using the alternate data structure. When written: Selects the alternate data structure for UARTTX. */ + +/* DMAALTSET[SPI1RX] - DMA SPI 1 RX. */ +#define DMAALTSET_SPI1RX_BBA (*(volatile unsigned long *) 0x42200604) +#define DMAALTSET_SPI1RX_MSK (0x1 << 1 ) +#define DMAALTSET_SPI1RX (0x1 << 1 ) +#define DMAALTSET_SPI1RX_DIS (0x0 << 1 ) /* DIS. When read: DMA SPI1RX is using the primary data structure. When written: No effect. Use the DMAALTCLR register to set SPI1RX to 0. */ +#define DMAALTSET_SPI1RX_EN (0x1 << 1 ) /* EN. When read: DMA SPI1RX is using the alternate data structure. When written: Selects the alternate data structure for SPI1RX. */ + +/* DMAALTSET[SPI1TX] - DMA SPI 1 TX. */ +#define DMAALTSET_SPI1TX_BBA (*(volatile unsigned long *) 0x42200600) +#define DMAALTSET_SPI1TX_MSK (0x1 << 0 ) +#define DMAALTSET_SPI1TX (0x1 << 0 ) +#define DMAALTSET_SPI1TX_DIS (0x0 << 0 ) /* DIS. When read: DMA SPI1TX is using the primary data structure. When written: No effect. Use the DMAALTCLR register to set SPI1TX to 0. */ +#define DMAALTSET_SPI1TX_EN (0x1 << 0 ) /* EN. When read: DMA SPI1TX is using the alternate data structure. When written: Selects the alternate data structure for SPI1TX. */ + +/* Reset Value for DMAALTCLR*/ +#define DMAALTCLR_RVAL 0x0 + +/* DMAALTCLR[SPI0RX] - DMA SPI0 RX. */ +#define DMAALTCLR_SPI0RX_BBA (*(volatile unsigned long *) 0x422006B4) +#define DMAALTCLR_SPI0RX_MSK (0x1 << 13 ) +#define DMAALTCLR_SPI0RX (0x1 << 13 ) +#define DMAALTCLR_SPI0RX_DIS (0x0 << 13 ) /* DIS. No effect. Use the DMAALTSET register to select the alternate data structure. */ +#define DMAALTCLR_SPI0RX_EN (0x1 << 13 ) /* EN. Selects the primary data structure for SPI0RX. */ + +/* DMAALTCLR[SPI0TX] - DMA SPI0 TX. */ +#define DMAALTCLR_SPI0TX_BBA (*(volatile unsigned long *) 0x422006B0) +#define DMAALTCLR_SPI0TX_MSK (0x1 << 12 ) +#define DMAALTCLR_SPI0TX (0x1 << 12 ) +#define DMAALTCLR_SPI0TX_DIS (0x0 << 12 ) /* DIS. No effect. Use the DMAALTSET register to select the alternate data structure. */ +#define DMAALTCLR_SPI0TX_EN (0x1 << 12 ) /* EN. Selects the primary data structure for SPI0TX. */ + +/* DMAALTCLR[ADC] - DMA ADC. */ +#define DMAALTCLR_ADC_BBA (*(volatile unsigned long *) 0x422006AC) +#define DMAALTCLR_ADC_MSK (0x1 << 11 ) +#define DMAALTCLR_ADC (0x1 << 11 ) +#define DMAALTCLR_ADC_DIS (0x0 << 11 ) /* DIS. No effect. Use the DMAALTSET register to select the alternate data structure. */ +#define DMAALTCLR_ADC_EN (0x1 << 11 ) /* EN. Selects the primary data structure for ADC. */ + +/* DMAALTCLR[I2CMRX] - DMA I2C Master RX. */ +#define DMAALTCLR_I2CMRX_BBA (*(volatile unsigned long *) 0x4220069C) +#define DMAALTCLR_I2CMRX_MSK (0x1 << 7 ) +#define DMAALTCLR_I2CMRX (0x1 << 7 ) +#define DMAALTCLR_I2CMRX_DIS (0x0 << 7 ) /* DIS. No effect. Use the DMAALTSET register to select the alternate data structure. */ +#define DMAALTCLR_I2CMRX_EN (0x1 << 7 ) /* EN. Selects the primary data structure for I2CMRX. */ + +/* DMAALTCLR[I2CMTX] - DMA I2C Master TX. */ +#define DMAALTCLR_I2CMTX_BBA (*(volatile unsigned long *) 0x42200698) +#define DMAALTCLR_I2CMTX_MSK (0x1 << 6 ) +#define DMAALTCLR_I2CMTX (0x1 << 6 ) +#define DMAALTCLR_I2CMTX_DIS (0x0 << 6 ) /* DIS. No effect. Use the DMAALTSET register to select the alternate data structure. */ +#define DMAALTCLR_I2CMTX_EN (0x1 << 6 ) /* EN. Selects the primary data structure for I2CMTX. */ + +/* DMAALTCLR[I2CSRX] - DMA I2C Slave RX. */ +#define DMAALTCLR_I2CSRX_BBA (*(volatile unsigned long *) 0x42200694) +#define DMAALTCLR_I2CSRX_MSK (0x1 << 5 ) +#define DMAALTCLR_I2CSRX (0x1 << 5 ) +#define DMAALTCLR_I2CSRX_DIS (0x0 << 5 ) /* DIS. No effect. Use the DMAALTSET register to select the alternate data structure. */ +#define DMAALTCLR_I2CSRX_EN (0x1 << 5 ) /* EN. Selects the primary data structure for I2CSRX. */ + +/* DMAALTCLR[I2CSTX] - DMA I2C Slave TX. */ +#define DMAALTCLR_I2CSTX_BBA (*(volatile unsigned long *) 0x42200690) +#define DMAALTCLR_I2CSTX_MSK (0x1 << 4 ) +#define DMAALTCLR_I2CSTX (0x1 << 4 ) +#define DMAALTCLR_I2CSTX_DIS (0x0 << 4 ) /* DIS. No effect. Use the DMAALTSET register to select the alternate data structure. */ +#define DMAALTCLR_I2CSTX_EN (0x1 << 4 ) /* EN. Selects the primary data structure for I2CSTX. */ + +/* DMAALTCLR[UARTRX] - DMA UART RX. */ +#define DMAALTCLR_UARTRX_BBA (*(volatile unsigned long *) 0x4220068C) +#define DMAALTCLR_UARTRX_MSK (0x1 << 3 ) +#define DMAALTCLR_UARTRX (0x1 << 3 ) +#define DMAALTCLR_UARTRX_DIS (0x0 << 3 ) /* DIS. No effect. Use the DMAALTSET register to select the alternate data structure. */ +#define DMAALTCLR_UARTRX_EN (0x1 << 3 ) /* EN. Selects the primary data structure for UARTRX. */ + +/* DMAALTCLR[UARTTX] - DMA UART TX. */ +#define DMAALTCLR_UARTTX_BBA (*(volatile unsigned long *) 0x42200688) +#define DMAALTCLR_UARTTX_MSK (0x1 << 2 ) +#define DMAALTCLR_UARTTX (0x1 << 2 ) +#define DMAALTCLR_UARTTX_DIS (0x0 << 2 ) /* DIS. No effect. Use the DMAALTSET register to select the alternate data structure. */ +#define DMAALTCLR_UARTTX_EN (0x1 << 2 ) /* EN. Selects the primary data structure for UARTTX. */ + +/* DMAALTCLR[SPI1RX] - DMA SPI 1 RX. */ +#define DMAALTCLR_SPI1RX_BBA (*(volatile unsigned long *) 0x42200684) +#define DMAALTCLR_SPI1RX_MSK (0x1 << 1 ) +#define DMAALTCLR_SPI1RX (0x1 << 1 ) +#define DMAALTCLR_SPI1RX_DIS (0x0 << 1 ) /* DIS. No effect. Use the DMAALTSET register to select the alternate data structure. */ +#define DMAALTCLR_SPI1RX_EN (0x1 << 1 ) /* EN. Selects the primary data structure for SPI1RX. */ + +/* DMAALTCLR[SPI1TX] - DMA SPI 1 TX. */ +#define DMAALTCLR_SPI1TX_BBA (*(volatile unsigned long *) 0x42200680) +#define DMAALTCLR_SPI1TX_MSK (0x1 << 0 ) +#define DMAALTCLR_SPI1TX (0x1 << 0 ) +#define DMAALTCLR_SPI1TX_DIS (0x0 << 0 ) /* DIS. No effect. Use the DMAALTSET register to select the alternate data structure. */ +#define DMAALTCLR_SPI1TX_EN (0x1 << 0 ) /* EN. Selects the primary data structure for SPI1TX. */ + +/* Reset Value for DMAPRISET*/ +#define DMAPRISET_RVAL 0x0 + +/* DMAPRISET[SPI0RX] - DMA SPI0 RX. */ +#define DMAPRISET_SPI0RX_BBA (*(volatile unsigned long *) 0x42200734) +#define DMAPRISET_SPI0RX_MSK (0x1 << 13 ) +#define DMAPRISET_SPI0RX (0x1 << 13 ) +#define DMAPRISET_SPI0RX_DIS (0x0 << 13 ) /* DIS. When read: DMA SPI0RX is using the default priority level. When written: No effect. Use the DMAPRICLR register to set SPI0RX to the default priority level. */ +#define DMAPRISET_SPI0RX_EN (0x1 << 13 ) /* EN. When read: DMA SPI0RX is using a high priority level. When written: SPI0RX uses the high priority level. */ + +/* DMAPRISET[SPI0TX] - DMA SPI0 TX. */ +#define DMAPRISET_SPI0TX_BBA (*(volatile unsigned long *) 0x42200730) +#define DMAPRISET_SPI0TX_MSK (0x1 << 12 ) +#define DMAPRISET_SPI0TX (0x1 << 12 ) +#define DMAPRISET_SPI0TX_DIS (0x0 << 12 ) /* DIS. When read: DMA SPI0TX is using the default priority level. When written: No effect. Use the DMAPRICLR register to set SPI0TX to the default priority level. */ +#define DMAPRISET_SPI0TX_EN (0x1 << 12 ) /* EN. When read: DMA SPI0TX is using a high priority level. When written: SPI0TX uses the high priority level. */ + +/* DMAPRISET[ADC] - DMA ADC. */ +#define DMAPRISET_ADC_BBA (*(volatile unsigned long *) 0x4220072C) +#define DMAPRISET_ADC_MSK (0x1 << 11 ) +#define DMAPRISET_ADC (0x1 << 11 ) +#define DMAPRISET_ADC_DIS (0x0 << 11 ) /* DIS. When read: DMA ADC is using the default priority level. When written: No effect. Use the DMAPRICLR register to set ADC to the default priority level. */ +#define DMAPRISET_ADC_EN (0x1 << 11 ) /* EN. When read: DMA ADCs using a high priority level. When written: ADC uses the high priority level. */ + +/* DMAPRISET[I2CMRX] - DMA I2C Master RX. */ +#define DMAPRISET_I2CMRX_BBA (*(volatile unsigned long *) 0x4220071C) +#define DMAPRISET_I2CMRX_MSK (0x1 << 7 ) +#define DMAPRISET_I2CMRX (0x1 << 7 ) +#define DMAPRISET_I2CMRX_DIS (0x0 << 7 ) /* DIS. When read: DMA I2CMRX is using the default priority level. When written: No effect. Use the DMAPRICLR register to set I2CMRX to the default priority level. */ +#define DMAPRISET_I2CMRX_EN (0x1 << 7 ) /* EN. When read: DMA I2CMRX is using a high priority level. When written: I2CMRX uses the high priority level. */ + +/* DMAPRISET[I2CMTX] - DMA I2C Master TX. */ +#define DMAPRISET_I2CMTX_BBA (*(volatile unsigned long *) 0x42200718) +#define DMAPRISET_I2CMTX_MSK (0x1 << 6 ) +#define DMAPRISET_I2CMTX (0x1 << 6 ) +#define DMAPRISET_I2CMTX_DIS (0x0 << 6 ) /* DIS. When read: DMA I2CMTX is using the default priority level. When written: No effect. Use the DMAPRICLR register to set I2CMTX to the default priority level. */ +#define DMAPRISET_I2CMTX_EN (0x1 << 6 ) /* EN. When read: DMA I2CMTX is using a high priority level. When written: I2CMTX uses the high priority level. */ + +/* DMAPRISET[I2CSRX] - DMA I2C Slave RX. */ +#define DMAPRISET_I2CSRX_BBA (*(volatile unsigned long *) 0x42200714) +#define DMAPRISET_I2CSRX_MSK (0x1 << 5 ) +#define DMAPRISET_I2CSRX (0x1 << 5 ) +#define DMAPRISET_I2CSRX_DIS (0x0 << 5 ) /* DIS. When read: DMA I2CSRX is using the default priority level. When written: No effect. Use the DMAPRICLR register to set I2CSRX to the default priority level. */ +#define DMAPRISET_I2CSRX_EN (0x1 << 5 ) /* EN. When read: DMA I2CSRX is using a high priority level. When written: I2CSRX uses the high priority level. */ + +/* DMAPRISET[I2CSTX] - DMA I2C Slave TX. */ +#define DMAPRISET_I2CSTX_BBA (*(volatile unsigned long *) 0x42200710) +#define DMAPRISET_I2CSTX_MSK (0x1 << 4 ) +#define DMAPRISET_I2CSTX (0x1 << 4 ) +#define DMAPRISET_I2CSTX_DIS (0x0 << 4 ) /* DIS. When read: DMA I2CSTX is using the default priority level. When written: No effect. Use the DMAPRICLR register to set I2CSTX to the default priority level. */ +#define DMAPRISET_I2CSTX_EN (0x1 << 4 ) /* EN. When read: DMA I2CSTX is using a high priority level. When written: I2CSTX uses the high priority level. */ + +/* DMAPRISET[UARTRX] - DMA UART RX. */ +#define DMAPRISET_UARTRX_BBA (*(volatile unsigned long *) 0x4220070C) +#define DMAPRISET_UARTRX_MSK (0x1 << 3 ) +#define DMAPRISET_UARTRX (0x1 << 3 ) +#define DMAPRISET_UARTRX_DIS (0x0 << 3 ) /* DIS. When read: DMA UARTRX is using the default priority level. When written: No effect. Use the DMAPRICLR register to set UARTRX to the default priority level. */ +#define DMAPRISET_UARTRX_EN (0x1 << 3 ) /* EN. When read: DMA UARTRX is using a high priority level. When written: UARTRX uses the high priority level. */ + +/* DMAPRISET[UARTTX] - DMA UART TX. */ +#define DMAPRISET_UARTTX_BBA (*(volatile unsigned long *) 0x42200708) +#define DMAPRISET_UARTTX_MSK (0x1 << 2 ) +#define DMAPRISET_UARTTX (0x1 << 2 ) +#define DMAPRISET_UARTTX_DIS (0x0 << 2 ) /* DIS. When read: DMA UARTTX is using the default priority level. When written: No effect. Use the DMAPRICLR register to set UARTTX to the default priority level. */ +#define DMAPRISET_UARTTX_EN (0x1 << 2 ) /* EN. When read: DMA UARTTX is using a high priority level. When written: UARTTX uses the high priority level. */ + +/* DMAPRISET[SPI1RX] - DMA SPI 1 RX. */ +#define DMAPRISET_SPI1RX_BBA (*(volatile unsigned long *) 0x42200704) +#define DMAPRISET_SPI1RX_MSK (0x1 << 1 ) +#define DMAPRISET_SPI1RX (0x1 << 1 ) +#define DMAPRISET_SPI1RX_DIS (0x0 << 1 ) /* DIS. When read: DMA SPI1RX is using the default priority level. When written: No effect. Use the DMAPRICLR register to set SPI1RX to the default priority level. */ +#define DMAPRISET_SPI1RX_EN (0x1 << 1 ) /* EN. When read: DMA SPI1RX is using a high priority level. When written: SPI1RX uses the high priority level. */ + +/* DMAPRISET[SPI1TX] - DMA SPI 1 TX. */ +#define DMAPRISET_SPI1TX_BBA (*(volatile unsigned long *) 0x42200700) +#define DMAPRISET_SPI1TX_MSK (0x1 << 0 ) +#define DMAPRISET_SPI1TX (0x1 << 0 ) +#define DMAPRISET_SPI1TX_DIS (0x0 << 0 ) /* DIS. When read: DMA SPI1TX is using the default priority level. When written: No effect. Use the DMAPRICLR register to set SPI1TX to the default priority level. */ +#define DMAPRISET_SPI1TX_EN (0x1 << 0 ) /* EN. When read: DMA SPI1TX is using a high priority level. When written: SPI1TX uses the high priority level. */ + +/* Reset Value for DMAPRICLR*/ +#define DMAPRICLR_RVAL 0x0 + +/* DMAPRICLR[SPI0RX] - DMA SPI0 RX. */ +#define DMAPRICLR_SPI0RX_BBA (*(volatile unsigned long *) 0x422007B4) +#define DMAPRICLR_SPI0RX_MSK (0x1 << 13 ) +#define DMAPRICLR_SPI0RX (0x1 << 13 ) +#define DMAPRICLR_SPI0RX_DIS (0x0 << 13 ) /* DIS. No effect. Use the DMAPRISET register to set SPI0RX to the high priority level. */ +#define DMAPRICLR_SPI0RX_EN (0x1 << 13 ) /* EN. SPI0RX uses the default priority level. */ + +/* DMAPRICLR[SPI0TX] - DMA SPI0 TX. */ +#define DMAPRICLR_SPI0TX_BBA (*(volatile unsigned long *) 0x422007B0) +#define DMAPRICLR_SPI0TX_MSK (0x1 << 12 ) +#define DMAPRICLR_SPI0TX (0x1 << 12 ) +#define DMAPRICLR_SPI0TX_DIS (0x0 << 12 ) /* DIS. No effect. Use the DMAPRISET register to set SPI0TX to the high priority level. */ +#define DMAPRICLR_SPI0TX_EN (0x1 << 12 ) /* EN. SPI0TX uses the default priority level. */ + +/* DMAPRICLR[ADC] - DMA ADC. */ +#define DMAPRICLR_ADC_BBA (*(volatile unsigned long *) 0x422007AC) +#define DMAPRICLR_ADC_MSK (0x1 << 11 ) +#define DMAPRICLR_ADC (0x1 << 11 ) +#define DMAPRICLR_ADC_DIS (0x0 << 11 ) /* DIS. No effect. Use the DMAPRISET register to set ADC to the high priority level. */ +#define DMAPRICLR_ADC_EN (0x1 << 11 ) /* EN. ADC uses the default priority level. */ + +/* DMAPRICLR[I2CMRX] - DMA I2C Master RX. */ +#define DMAPRICLR_I2CMRX_BBA (*(volatile unsigned long *) 0x4220079C) +#define DMAPRICLR_I2CMRX_MSK (0x1 << 7 ) +#define DMAPRICLR_I2CMRX (0x1 << 7 ) +#define DMAPRICLR_I2CMRX_DIS (0x0 << 7 ) /* DIS. No effect. Use the DMAPRISET register to set I2CMRX to the high priority level. */ +#define DMAPRICLR_I2CMRX_EN (0x1 << 7 ) /* EN. I2CMRX uses the default priority level. */ + +/* DMAPRICLR[I2CMTX] - DMA I2C Master TX. */ +#define DMAPRICLR_I2CMTX_BBA (*(volatile unsigned long *) 0x42200798) +#define DMAPRICLR_I2CMTX_MSK (0x1 << 6 ) +#define DMAPRICLR_I2CMTX (0x1 << 6 ) +#define DMAPRICLR_I2CMTX_DIS (0x0 << 6 ) /* DIS. No effect. Use the DMAPRISET register to set I2CMTX to the high priority level. */ +#define DMAPRICLR_I2CMTX_EN (0x1 << 6 ) /* EN. I2CMTX uses the default priority level. */ + +/* DMAPRICLR[I2CSRX] - DMA I2C Slave RX. */ +#define DMAPRICLR_I2CSRX_BBA (*(volatile unsigned long *) 0x42200794) +#define DMAPRICLR_I2CSRX_MSK (0x1 << 5 ) +#define DMAPRICLR_I2CSRX (0x1 << 5 ) +#define DMAPRICLR_I2CSRX_DIS (0x0 << 5 ) /* DIS. No effect. Use the DMAPRISET register to set I2CSRX to the high priority level. */ +#define DMAPRICLR_I2CSRX_EN (0x1 << 5 ) /* EN. I2CSRX uses the default priority level. */ + +/* DMAPRICLR[I2CSTX] - DMA I2C Slave TX. */ +#define DMAPRICLR_I2CSTX_BBA (*(volatile unsigned long *) 0x42200790) +#define DMAPRICLR_I2CSTX_MSK (0x1 << 4 ) +#define DMAPRICLR_I2CSTX (0x1 << 4 ) +#define DMAPRICLR_I2CSTX_DIS (0x0 << 4 ) /* DIS. No effect. Use the DMAPRISET register to set I2CSTX to the high priority level. */ +#define DMAPRICLR_I2CSTX_EN (0x1 << 4 ) /* EN. I2CSTX uses the default priority level. */ + +/* DMAPRICLR[UARTRX] - DMA UART RX. */ +#define DMAPRICLR_UARTRX_BBA (*(volatile unsigned long *) 0x4220078C) +#define DMAPRICLR_UARTRX_MSK (0x1 << 3 ) +#define DMAPRICLR_UARTRX (0x1 << 3 ) +#define DMAPRICLR_UARTRX_DIS (0x0 << 3 ) /* DIS. No effect. Use the DMAPRISET register to set UARTRX to the high priority level. */ +#define DMAPRICLR_UARTRX_EN (0x1 << 3 ) /* EN. UARTRX uses the default priority level. */ + +/* DMAPRICLR[UARTTX] - DMA UART TX. */ +#define DMAPRICLR_UARTTX_BBA (*(volatile unsigned long *) 0x42200788) +#define DMAPRICLR_UARTTX_MSK (0x1 << 2 ) +#define DMAPRICLR_UARTTX (0x1 << 2 ) +#define DMAPRICLR_UARTTX_DIS (0x0 << 2 ) /* DIS. No effect. Use the DMAPRISET register to set UARTTX to the high priority level. */ +#define DMAPRICLR_UARTTX_EN (0x1 << 2 ) /* EN. UARTTX uses the default priority level. */ + +/* DMAPRICLR[SPI1RX] - DMA SPI 1 RX. */ +#define DMAPRICLR_SPI1RX_BBA (*(volatile unsigned long *) 0x42200784) +#define DMAPRICLR_SPI1RX_MSK (0x1 << 1 ) +#define DMAPRICLR_SPI1RX (0x1 << 1 ) +#define DMAPRICLR_SPI1RX_DIS (0x0 << 1 ) /* DIS. No effect. Use the DMAPRISET register to set SPI1RX to the high priority level. */ +#define DMAPRICLR_SPI1RX_EN (0x1 << 1 ) /* EN. SPI1RX uses the default priority level. */ + +/* DMAPRICLR[SPI1TX] - DMA SPI 1 TX. */ +#define DMAPRICLR_SPI1TX_BBA (*(volatile unsigned long *) 0x42200780) +#define DMAPRICLR_SPI1TX_MSK (0x1 << 0 ) +#define DMAPRICLR_SPI1TX (0x1 << 0 ) +#define DMAPRICLR_SPI1TX_DIS (0x0 << 0 ) /* DIS. No effect. Use the DMAPRISET register to set SPI1TX to the high priority level. */ +#define DMAPRICLR_SPI1TX_EN (0x1 << 0 ) /* EN. SPI1TX uses the default priority level. */ + +/* Reset Value for DMAERRCLR*/ +#define DMAERRCLR_RVAL 0x0 + +/* DMAERRCLR[ERROR] - DMA Bus Error status. */ +#define DMAERRCLR_ERROR_BBA (*(volatile unsigned long *) 0x42200980) +#define DMAERRCLR_ERROR_MSK (0x1 << 0 ) +#define DMAERRCLR_ERROR (0x1 << 0 ) +#define DMAERRCLR_ERROR_DIS (0x0 << 0 ) /* DIS. When Read: No bus error occurred. When Written: No effect. */ +#define DMAERRCLR_ERROR_EN (0x1 << 0 ) /* EN. When Read: A bus error is pending. When Written: Bit is cleared. */ +// ------------------------------------------------------------------------------------------------ +// ----- FEE ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief Flash Controller (pADI_FEE) + */ + +#if (__NO_MMR_STRUCTS__==0) +typedef struct { /*!< pADI_FEE Structure */ + __IO uint16_t FEESTA; /*!< Status Register */ + __I uint16_t RESERVED0; + __IO uint16_t FEECON0; /*!< Command Control Register */ + __I uint16_t RESERVED1; + __IO uint16_t FEECMD; /*!< Command Register */ + __I uint16_t RESERVED2[3]; + __IO uint16_t FEEADR0L; /*!< Address 0 LSB */ + __I uint16_t RESERVED3; + __IO uint16_t FEEADR0H; /*!< Address 0 MSB */ + __I uint16_t RESERVED4; + __IO uint16_t FEEADR1L; /*!< Address1 LSB */ + __I uint16_t RESERVED5; + __IO uint16_t FEEADR1H; /*!< Address1 MSB */ + __I uint16_t RESERVED6; + __IO uint16_t FEEKEY; /*!< Key Register */ + __I uint16_t RESERVED7[3]; + __IO uint16_t FEEPROL; /*!< Write Protection Register LSB */ + __I uint16_t RESERVED8; + __IO uint16_t FEEPROH; /*!< Write Protection Register MSB */ + __I uint16_t RESERVED9; + __IO uint16_t FEESIGL; /*!< Signature LSB */ + __I uint16_t RESERVED10; + __IO uint16_t FEESIGH; /*!< Signature MSB */ + __I uint16_t RESERVED11; + __IO uint16_t FEECON1; /*!< User Setup Register */ + __I uint16_t RESERVED12[7]; + __IO uint16_t FEEADRAL; /*!< Abort Address Register LSB */ + __I uint16_t RESERVED13; + __IO uint16_t FEEADRAH; /*!< Abort Address Register MSB */ + __I uint16_t RESERVED14[21]; + __IO uint16_t FEEAEN0; /*!< Interrupt Abort Register (Interrupt 15 to Interrupt 0) */ + __I uint16_t RESERVED15; + __IO uint16_t FEEAEN1; /*!< Interrupt Abort Register (Interrupt 31 to Interrupt 16) */ + __I uint16_t RESERVED16; + __IO uint16_t FEEAEN2; /*!< Interrupt Abort Register (Interrupt 42 to Interrupt 32) */ +} ADI_FEE_TypeDef; +#else // (__NO_MMR_STRUCTS__==0) +#define FEESTA (*(volatile unsigned short int *) 0x40002800) +#define FEECON0 (*(volatile unsigned short int *) 0x40002804) +#define FEECMD (*(volatile unsigned short int *) 0x40002808) +#define FEEADR0L (*(volatile unsigned short int *) 0x40002810) +#define FEEADR0H (*(volatile unsigned short int *) 0x40002814) +#define FEEADR1L (*(volatile unsigned short int *) 0x40002818) +#define FEEADR1H (*(volatile unsigned short int *) 0x4000281C) +#define FEEKEY (*(volatile unsigned short int *) 0x40002820) +#define FEEPROL (*(volatile unsigned short int *) 0x40002828) +#define FEEPROH (*(volatile unsigned short int *) 0x4000282C) +#define FEESIGL (*(volatile unsigned short int *) 0x40002830) +#define FEESIGH (*(volatile unsigned short int *) 0x40002834) +#define FEECON1 (*(volatile unsigned short int *) 0x40002838) +#define FEEADRAL (*(volatile unsigned short int *) 0x40002848) +#define FEEADRAH (*(volatile unsigned short int *) 0x4000284C) +#define FEEAEN0 (*(volatile unsigned short int *) 0x40002878) +#define FEEAEN1 (*(volatile unsigned short int *) 0x4000287C) +#define FEEAEN2 (*(volatile unsigned short int *) 0x40002880) +#endif // (__NO_MMR_STRUCTS__==0) + +/* Reset Value for FEESTA*/ +#define FEESTA_RVAL 0x0 + +/* FEESTA[SIGNERR] - Kernel space signature check on reset error */ +#define FEESTA_SIGNERR_BBA (*(volatile unsigned long *) 0x42050018) +#define FEESTA_SIGNERR_MSK (0x1 << 6 ) +#define FEESTA_SIGNERR (0x1 << 6 ) +#define FEESTA_SIGNERR_CLR (0x0 << 6 ) /* CLR. Cleared, if the signature check of the kernel passes. */ +#define FEESTA_SIGNERR_SET (0x1 << 6 ) /* SET. Set, if the signature check of the kernel fails. User code does not execute. */ + +/* FEESTA[CMDRES] - These two bits indicate the status of a command on completion or the status of a write. If multiple commands are executed or there are multiple writes via the AHB bus without a read of the status register, then the first error encountered is stored. */ +#define FEESTA_CMDRES_MSK (0x3 << 4 ) +#define FEESTA_CMDRES_SUCCESS (0x0 << 4 ) /* SUCCESS. Indicates a successful completion of a command or a write. Also cleared after a read of FEESTA. */ +#define FEESTA_CMDRES_PROTECTED (0x1 << 4 ) /* PROTECTED. Indicates an attempted erase of a protected location. */ +#define FEESTA_CMDRES_VERIFYERR (0x2 << 4 ) /* VERIFYERR. Indicates a read verify error. After an erase the controller reads the corresponding word(s) to verify that the transaction completed successfully. If data read is not all 'F's this is the resulting status. If the Sign command is executed and the resulting signature does not match the data in the upper 4 bytes of the upper page in a block then this is the resulting status. */ +#define FEESTA_CMDRES_ABORT (0x3 << 4 ) /* ABORT. Indicates that a command or a write was aborted by an abort command or a system interrupt has caused an abort. */ + +/* FEESTA[WRDONE] - Write complete. */ +#define FEESTA_WRDONE_BBA (*(volatile unsigned long *) 0x4205000C) +#define FEESTA_WRDONE_MSK (0x1 << 3 ) +#define FEESTA_WRDONE (0x1 << 3 ) +#define FEESTA_WRDONE_CLR (0x0 << 3 ) /* CLR. Cleared after a read of FEESTA. */ +#define FEESTA_WRDONE_SET (0x1 << 3 ) /* SET. Set when a write completes. If there are multiple writes or a burst write, this status bit asserts after the first long word written and stays asserted until read. If there is a burst write to flash, then this bit asserts after every long word written, assuming that user code read FEESTA after every long word written. */ + +/* FEESTA[CMDDONE] - Command complete. */ +#define FEESTA_CMDDONE_BBA (*(volatile unsigned long *) 0x42050008) +#define FEESTA_CMDDONE_MSK (0x1 << 2 ) +#define FEESTA_CMDDONE (0x1 << 2 ) +#define FEESTA_CMDDONE_CLR (0x0 << 2 ) /* CLR. Cleared after a read of FEESTA. */ +#define FEESTA_CMDDONE_SET (0x1 << 2 ) /* SET. Set when a command completes. If there are multiple commands, this status bit asserts after the first command completes and stays asserted until read. */ + +/* FEESTA[WRBUSY] - Write busy. */ +#define FEESTA_WRBUSY_BBA (*(volatile unsigned long *) 0x42050004) +#define FEESTA_WRBUSY_MSK (0x1 << 1 ) +#define FEESTA_WRBUSY (0x1 << 1 ) +#define FEESTA_WRBUSY_CLR (0x0 << 1 ) /* CLR. Cleared after a read of FEESTA. */ +#define FEESTA_WRBUSY_SET (0x1 << 1 ) /* SET. Set when the flash block is executing a write. */ + +/* FEESTA[CMDBUSY] - Command busy. */ +#define FEESTA_CMDBUSY_BBA (*(volatile unsigned long *) 0x42050000) +#define FEESTA_CMDBUSY_MSK (0x1 << 0 ) +#define FEESTA_CMDBUSY (0x1 << 0 ) +#define FEESTA_CMDBUSY_CLR (0x0 << 0 ) /* CLR. Cleared after a read of FEESTA. */ +#define FEESTA_CMDBUSY_SET (0x1 << 0 ) /* SET. Set when the flash block is executing any command entered via the command register. */ + +/* Reset Value for FEECON0*/ +#define FEECON0_RVAL 0x0 + +/* FEECON0[WREN] - Write enable bit. */ +#define FEECON0_WREN_BBA (*(volatile unsigned long *) 0x42050088) +#define FEECON0_WREN_MSK (0x1 << 2 ) +#define FEECON0_WREN (0x1 << 2 ) +#define FEECON0_WREN_DIS (0x0 << 2 ) /* DIS. Disables Flash writes. A flash write when this bit is 0 results in a hard fault system exception error and the write does not take place. */ +#define FEECON0_WREN_EN (0x1 << 2 ) /* EN. Enables Flash writes. */ + +/* FEECON0[IENERR] - Error interrupt enable bit. */ +#define FEECON0_IENERR_BBA (*(volatile unsigned long *) 0x42050084) +#define FEECON0_IENERR_MSK (0x1 << 1 ) +#define FEECON0_IENERR (0x1 << 1 ) +#define FEECON0_IENERR_DIS (0x0 << 1 ) /* DIS. Disables the Flash error interrupt. */ +#define FEECON0_IENERR_EN (0x1 << 1 ) /* EN. An interrupt is generated when a command or flash write completes with an error status. */ + +/* FEECON0[IENCMD] - Command complete interrupt enable bit. */ +#define FEECON0_IENCMD_BBA (*(volatile unsigned long *) 0x42050080) +#define FEECON0_IENCMD_MSK (0x1 << 0 ) +#define FEECON0_IENCMD (0x1 << 0 ) +#define FEECON0_IENCMD_DIS (0x0 << 0 ) /* DIS. Disables the Flash command complete interrupt. */ +#define FEECON0_IENCMD_EN (0x1 << 0 ) /* EN. An interrupt is generated when a command or flash write completes. */ + +/* Reset Value for FEECMD*/ +#define FEECMD_RVAL 0x0 + +/* FEECMD[CMD] - Commands supported by the flash controller. */ +#define FEECMD_CMD_MSK (0xF << 0 ) +#define FEECMD_CMD_IDLE (0x0 << 0 ) /* IDLE. No command executed. */ +#define FEECMD_CMD_ERASEPAGE (0x1 << 0 ) /* ERASEPAGE. Write the address of the page to be erased to FEEADR0L/H, then write this code to the FEECMD register and the flash will erase the page. When the erase has completed, the flash reads every location in the page to verify that all words in the page are erased. If there is a read verify error, this is indicated in FEESTA. To erase multiple pages, wait until a previous page erase has completed. Check the status, and then issue a command to start the next page erase. Before entering this command, 0xF456 followed by 0xF123 must be written to the key register. */ +#define FEECMD_CMD_SIGN (0x2 << 0 ) /* SIGN. Use this command to generate a signature for a block of data. The signature is generated on a page-by-page basis. To generate a signature, the address of the first page of the block is entered in FEEADR0L/FEEADR0H. The address of the last page is written to FEEADR1L/FEEADR1H. Then write this code to the FEECMD register. When the command has completed, the signature is available for reading in FEESIGL/FEESIGH. The last four bytes of the last page in a block is reserved for storing the signature. Before entering this command, 0xF456 followed 0xF123 must be written to the key register. */ +#define FEECMD_CMD_MASSERASE (0x3 << 0 ) /* MASSERASE. Erase all of user space. To enable this operation, 0xF456 followed by 0xF123 must first be written to FEEKEY (this is to prevent accidental erases). When the mass erase has completed, the controller reads every location to verify that all locations are 0xFFFFFFFF. If there is a read verify error this is indicated in FEESTA. */ +#define FEECMD_CMD_ABORT (0x4 << 0 ) /* ABORT. If this command is issued, then any command currently in progress is stopped. The status indicates command completed with an error status in FEESTA[5:4]. Note that this is the only command that can be issued while another command is already in progress. This command can also be used to stop a write that may be in progress. If a write is aborted, the address of the location being written can be read via the FEEADRAL/FEEADRAH register. While the flash controller is writing one longword, another longword write may be in the pipeline from the Cortex-M3 or DMA engine (depending on how the software implements writes). Therefore, both writes may need to be aborted. If a write or erase is aborted, then the flash timing is violated and it is not possible to determine if the write or erase completed successfully. To enable this operation, 0xF456 followed by 0xF123 must first be written to FEEKEY (this is to prevent accidental aborts). */ + +/* Reset Value for FEEADR0L*/ +#define FEEADR0L_RVAL 0x0 + +/* FEEADR0L[VALUE] - Used in conjunction with FEEADR0H, to indicate the page to be erased, or the start of a section to be signed. The address of a memory location inside the page should be stored in FEEADR0L/H, bits[15:0] in FEEADR0L, and bits[17:16] in FEEADR0H. The 9 LSBs of the address are ignored. */ +#define FEEADR0L_VALUE_MSK (0xFFFF << 0 ) + +/* Reset Value for FEEADR0H*/ +#define FEEADR0H_RVAL 0x0 + +/* FEEADR0H[VALUE] - Used in conjunction with FEEADR0L, to indicate the page to be erased, or the start of a section to be signed. The address of a memory location inside the page should be stored in FEEADR0L/H, bits[15:0] in FEEADR0L, and bits[17:16] in FEEADR0H. */ +#define FEEADR0H_VALUE_MSK (0x3 << 0 ) + +/* Reset Value for FEEADR1L*/ +#define FEEADR1L_RVAL 0x0 + +/* FEEADR1L[VALUE] - Used in conjunction with FEEADR1H, to identify the last page used by the Sign command. The address of a memory location inside the page should be stored in FEEADR1L/H, bits[15:0] in FEEADR1L, and bits[17:16] in FEEADR1H. The 9 LSBs of the address are ignored. */ +#define FEEADR1L_VALUE_MSK (0xFFFF << 0 ) + +/* Reset Value for FEEADR1H*/ +#define FEEADR1H_RVAL 0x0 + +/* FEEADR1H[VALUE] - Used in conjunction with FEEADR1L, to identify the last page used by the Sign command. The address of a memory location inside the page should be stored in FEEADR1L/H, bits[15:0] in FEEADR1L, and bits[17:16] in FEEADR1H. */ +#define FEEADR1H_VALUE_MSK (0x3 << 0 ) + +/* Reset Value for FEEKEY*/ +#define FEEKEY_RVAL 0x0 + +/* FEEKEY[VALUE] - Enter 0xF456 followed by 0xF123. Returns 0x0 if read. */ +#define FEEKEY_VALUE_MSK (0xFFFF << 0 ) +#define FEEKEY_VALUE_USERKEY1 (0xF456 << 0 ) /* USERKEY1 */ +#define FEEKEY_VALUE_USERKEY2 (0xF123 << 0 ) /* USERKEY2 */ + +/* Reset Value for FEEPROL*/ +#define FEEPROL_RVAL 0xFFFF + +/* FEEPROL[VALUE] - Lower 16 bits of the write protection. This register is read only if the write protection in flash has been programmed, i.e. FEEPROH/L have previously been configured to protect pages. */ +#define FEEPROL_VALUE_MSK (0xFFFF << 0 ) + +/* Reset Value for FEEPROH*/ +#define FEEPROH_RVAL 0xFFFF + +/* FEEPROH[VALUE] - Upper 16 bits of the write protection. This register is read only if the write protection in flash has been programmed, i.e. FEEPROH/L have previously been configured to protect pages. */ +#define FEEPROH_VALUE_MSK (0xFFFF << 0 ) + +/* Reset Value for FEESIGL*/ +#define FEESIGL_RVAL 0xFFFF + +/* FEESIGL[VALUE] - Lower 16 bits of the signature. Signature[15:0]. */ +#define FEESIGL_VALUE_MSK (0xFFFF << 0 ) + +/* Reset Value for FEESIGH*/ +#define FEESIGH_RVAL 0xFFFF + +/* FEESIGH[VALUE] - Upper eight bits of the signature. Signature[23:16]. */ +#define FEESIGH_VALUE_MSK (0xFF << 0 ) + +/* Reset Value for FEECON1*/ +#define FEECON1_RVAL 0x1 + +/* FEECON1[DBG] - Serial Wire debug enable. */ +#define FEECON1_DBG_BBA (*(volatile unsigned long *) 0x42050700) +#define FEECON1_DBG_MSK (0x1 << 0 ) +#define FEECON1_DBG (0x1 << 0 ) +#define FEECON1_DBG_DIS (0x0 << 0 ) /* DIS. Disable access via the serial wire debug interface. */ +#define FEECON1_DBG_EN (0x1 << 0 ) /* EN. Enable access via the serial wire debug interface. */ + +/* Reset Value for FEEADRAL*/ +#define FEEADRAL_RVAL 0x800 + +/* FEEADRAL[VALUE] - Lower 16 bits of the FEEADRA register. If a write is aborted then this will contain the address of the location been written when the write was aborted. */ +#define FEEADRAL_VALUE_MSK (0xFFFF << 0 ) + +/* Reset Value for FEEADRAH*/ +#define FEEADRAH_RVAL 0x2 + +/* FEEADRAH[VALUE] - Upper 16 bits of the FEEADRA register. */ +#define FEEADRAH_VALUE_MSK (0xFFFF << 0 ) + +/* Reset Value for FEEAEN0*/ +#define FEEAEN0_RVAL 0x0 + +/* FEEAEN0[FEE] - Flash controller interrupt abort enable bit */ +#define FEEAEN0_FEE_BBA (*(volatile unsigned long *) 0x42050F3C) +#define FEEAEN0_FEE_MSK (0x1 << 15 ) +#define FEEAEN0_FEE (0x1 << 15 ) +#define FEEAEN0_FEE_DIS (0x0 << 15 ) /* DIS. Flash controller interrupt abort disabled. */ +#define FEEAEN0_FEE_EN (0x1 << 15 ) /* EN. Flash controller interrupt abort enabled. */ + +/* FEEAEN0[ADC] - ADC interrupt abort enable bit */ +#define FEEAEN0_ADC_BBA (*(volatile unsigned long *) 0x42050F38) +#define FEEAEN0_ADC_MSK (0x1 << 14 ) +#define FEEAEN0_ADC (0x1 << 14 ) +#define FEEAEN0_ADC_DIS (0x0 << 14 ) /* DIS. ADC interrupt abort disabled. */ +#define FEEAEN0_ADC_EN (0x1 << 14 ) /* EN. ADC interrupt abort enabled. */ + +/* FEEAEN0[T1] - Timer1 interrupt abort enable bit */ +#define FEEAEN0_T1_BBA (*(volatile unsigned long *) 0x42050F34) +#define FEEAEN0_T1_MSK (0x1 << 13 ) +#define FEEAEN0_T1 (0x1 << 13 ) +#define FEEAEN0_T1_DIS (0x0 << 13 ) /* DIS. Timer1 interrupt abort disabled. */ +#define FEEAEN0_T1_EN (0x1 << 13 ) /* EN. Timer1 interrupt abort enabled. */ + +/* FEEAEN0[T0] - Timer0 interrupt abort enable bit */ +#define FEEAEN0_T0_BBA (*(volatile unsigned long *) 0x42050F30) +#define FEEAEN0_T0_MSK (0x1 << 12 ) +#define FEEAEN0_T0 (0x1 << 12 ) +#define FEEAEN0_T0_DIS (0x0 << 12 ) /* DIS. Timer0 interrupt abort disabled. */ +#define FEEAEN0_T0_EN (0x1 << 12 ) /* EN. Timer0 interrupt abort enabled. */ + +/* FEEAEN0[T3] - Timer3 interrupt abort enable bit */ +#define FEEAEN0_T3_BBA (*(volatile unsigned long *) 0x42050F28) +#define FEEAEN0_T3_MSK (0x1 << 10 ) +#define FEEAEN0_T3 (0x1 << 10 ) +#define FEEAEN0_T3_DIS (0x0 << 10 ) /* DIS. Timer3 interrupt abort disabled. */ +#define FEEAEN0_T3_EN (0x1 << 10 ) /* EN. Timer3 interrupt abort enabled. */ + +/* FEEAEN0[EXTINT8] - External interrupt 8 abort enable bit */ +#define FEEAEN0_EXTINT8_BBA (*(volatile unsigned long *) 0x42050F24) +#define FEEAEN0_EXTINT8_MSK (0x1 << 9 ) +#define FEEAEN0_EXTINT8 (0x1 << 9 ) +#define FEEAEN0_EXTINT8_DIS (0x0 << 9 ) /* DIS. External interrupt 8 abort disabled. */ +#define FEEAEN0_EXTINT8_EN (0x1 << 9 ) /* EN. External interrupt 8 abort enabled. */ + +/* FEEAEN0[EXTINT7] - External interrupt 7 abort enable bit */ +#define FEEAEN0_EXTINT7_BBA (*(volatile unsigned long *) 0x42050F20) +#define FEEAEN0_EXTINT7_MSK (0x1 << 8 ) +#define FEEAEN0_EXTINT7 (0x1 << 8 ) +#define FEEAEN0_EXTINT7_DIS (0x0 << 8 ) /* DIS. External interrupt 7 abort disabled. */ +#define FEEAEN0_EXTINT7_EN (0x1 << 8 ) /* EN. External interrupt 7 abort enabled. */ + +/* FEEAEN0[EXTINT6] - External interrupt 6 abort enable bit */ +#define FEEAEN0_EXTINT6_BBA (*(volatile unsigned long *) 0x42050F1C) +#define FEEAEN0_EXTINT6_MSK (0x1 << 7 ) +#define FEEAEN0_EXTINT6 (0x1 << 7 ) +#define FEEAEN0_EXTINT6_DIS (0x0 << 7 ) /* DIS. External interrupt 6 abort disabled. */ +#define FEEAEN0_EXTINT6_EN (0x1 << 7 ) /* EN. External interrupt 6 abort enabled. */ + +/* FEEAEN0[EXTINT5] - External interrupt 5 abort enable bit */ +#define FEEAEN0_EXTINT5_BBA (*(volatile unsigned long *) 0x42050F18) +#define FEEAEN0_EXTINT5_MSK (0x1 << 6 ) +#define FEEAEN0_EXTINT5 (0x1 << 6 ) +#define FEEAEN0_EXTINT5_DIS (0x0 << 6 ) /* DIS. External interrupt 5 abort disabled. */ +#define FEEAEN0_EXTINT5_EN (0x1 << 6 ) /* EN. External interrupt 5 abort enabled. */ + +/* FEEAEN0[EXTINT4] - External interrupt 4 abort enable bit */ +#define FEEAEN0_EXTINT4_BBA (*(volatile unsigned long *) 0x42050F14) +#define FEEAEN0_EXTINT4_MSK (0x1 << 5 ) +#define FEEAEN0_EXTINT4 (0x1 << 5 ) +#define FEEAEN0_EXTINT4_DIS (0x0 << 5 ) /* DIS. External interrupt 4 abort disabled. */ +#define FEEAEN0_EXTINT4_EN (0x1 << 5 ) /* EN. External interrupt 4 abort enabled. */ + +/* FEEAEN0[EXTINT3] - External interrupt 3 abort enable bit */ +#define FEEAEN0_EXTINT3_BBA (*(volatile unsigned long *) 0x42050F10) +#define FEEAEN0_EXTINT3_MSK (0x1 << 4 ) +#define FEEAEN0_EXTINT3 (0x1 << 4 ) +#define FEEAEN0_EXTINT3_DIS (0x0 << 4 ) /* DIS. External interrupt 3 abort disabled. */ +#define FEEAEN0_EXTINT3_EN (0x1 << 4 ) /* EN. External interrupt 3 abort enabled. */ + +/* FEEAEN0[EXTINT2] - External interrupt 2 abort enable bit */ +#define FEEAEN0_EXTINT2_BBA (*(volatile unsigned long *) 0x42050F0C) +#define FEEAEN0_EXTINT2_MSK (0x1 << 3 ) +#define FEEAEN0_EXTINT2 (0x1 << 3 ) +#define FEEAEN0_EXTINT2_DIS (0x0 << 3 ) /* DIS. External interrupt 2 abort disabled. */ +#define FEEAEN0_EXTINT2_EN (0x1 << 3 ) /* EN. External interrupt 2 abort enabled. */ + +/* FEEAEN0[EXTINT1] - External interrupt 1 abort enable bit */ +#define FEEAEN0_EXTINT1_BBA (*(volatile unsigned long *) 0x42050F08) +#define FEEAEN0_EXTINT1_MSK (0x1 << 2 ) +#define FEEAEN0_EXTINT1 (0x1 << 2 ) +#define FEEAEN0_EXTINT1_DIS (0x0 << 2 ) /* DIS. External interrupt 1 abort disabled. */ +#define FEEAEN0_EXTINT1_EN (0x1 << 2 ) /* EN. External interrupt 1 abort enabled. */ + +/* FEEAEN0[EXTINT0] - External interrupt 0 abort enable bit */ +#define FEEAEN0_EXTINT0_BBA (*(volatile unsigned long *) 0x42050F04) +#define FEEAEN0_EXTINT0_MSK (0x1 << 1 ) +#define FEEAEN0_EXTINT0 (0x1 << 1 ) +#define FEEAEN0_EXTINT0_DIS (0x0 << 1 ) /* DIS. External interrupt 0 abort disabled. */ +#define FEEAEN0_EXTINT0_EN (0x1 << 1 ) /* EN. External interrupt 0 abort enabled. */ + +/* FEEAEN0[T2] - Timer2 interrupt abort enable bit */ +#define FEEAEN0_T2_BBA (*(volatile unsigned long *) 0x42050F00) +#define FEEAEN0_T2_MSK (0x1 << 0 ) +#define FEEAEN0_T2 (0x1 << 0 ) +#define FEEAEN0_T2_DIS (0x0 << 0 ) /* DIS. Timer2 interrupt abort disabled. */ +#define FEEAEN0_T2_EN (0x1 << 0 ) /* EN. Timer2 interrupt abort enabled */ + +/* Reset Value for FEEAEN1*/ +#define FEEAEN1_RVAL 0x0 + +/* FEEAEN1[DMAI2CMRX] - I2C master RX DMA interrupt abort enable bit */ +#define FEEAEN1_DMAI2CMRX_BBA (*(volatile unsigned long *) 0x42050FBC) +#define FEEAEN1_DMAI2CMRX_MSK (0x1 << 15 ) +#define FEEAEN1_DMAI2CMRX (0x1 << 15 ) +#define FEEAEN1_DMAI2CMRX_DIS (0x0 << 15 ) /* DIS. I2C master RX DMA interrupt abort disabled. */ +#define FEEAEN1_DMAI2CMRX_EN (0x1 << 15 ) /* EN. I2C master RX DMA interrupt abort enabled. */ + +/* FEEAEN1[DMAI2CMTX] - I2C master TX DMA interrupt abort enable bit */ +#define FEEAEN1_DMAI2CMTX_BBA (*(volatile unsigned long *) 0x42050FB8) +#define FEEAEN1_DMAI2CMTX_MSK (0x1 << 14 ) +#define FEEAEN1_DMAI2CMTX (0x1 << 14 ) +#define FEEAEN1_DMAI2CMTX_DIS (0x0 << 14 ) /* DIS. I2C master TX DMA interrupt abort disabled. */ +#define FEEAEN1_DMAI2CMTX_EN (0x1 << 14 ) /* EN. I2C master TX DMA interrupt abort enabled. */ + +/* FEEAEN1[DMAI2CSRX] - I2C slave RX DMA interrupt abort enable bit */ +#define FEEAEN1_DMAI2CSRX_BBA (*(volatile unsigned long *) 0x42050FB4) +#define FEEAEN1_DMAI2CSRX_MSK (0x1 << 13 ) +#define FEEAEN1_DMAI2CSRX (0x1 << 13 ) +#define FEEAEN1_DMAI2CSRX_DIS (0x0 << 13 ) /* DIS. I2C slave RX DMA interrupt abort disabled. */ +#define FEEAEN1_DMAI2CSRX_EN (0x1 << 13 ) /* EN. I2C slave RX DMA interrupt abort enabled. */ + +/* FEEAEN1[DMAI2CSTX] - I2C slave TX DMA interrupt abort enable bit */ +#define FEEAEN1_DMAI2CSTX_BBA (*(volatile unsigned long *) 0x42050FB0) +#define FEEAEN1_DMAI2CSTX_MSK (0x1 << 12 ) +#define FEEAEN1_DMAI2CSTX (0x1 << 12 ) +#define FEEAEN1_DMAI2CSTX_DIS (0x0 << 12 ) /* DIS. I2C slave TX DMA interrupt abort disabled. */ +#define FEEAEN1_DMAI2CSTX_EN (0x1 << 12 ) /* EN. I2C slave TX DMA interrupt abort enabled. */ + +/* FEEAEN1[DMAUARTRX] - UARTRX DMA interrupt abort enable bit */ +#define FEEAEN1_DMAUARTRX_BBA (*(volatile unsigned long *) 0x42050FAC) +#define FEEAEN1_DMAUARTRX_MSK (0x1 << 11 ) +#define FEEAEN1_DMAUARTRX (0x1 << 11 ) +#define FEEAEN1_DMAUARTRX_DIS (0x0 << 11 ) /* DIS. UARTRX DMA interrupt abort disabled. */ +#define FEEAEN1_DMAUARTRX_EN (0x1 << 11 ) /* EN. UARTRX DMA interrupt abort enabled. */ + +/* FEEAEN1[DMAUARTTX] - UARTTX DMA interrupt abort enable bit */ +#define FEEAEN1_DMAUARTTX_BBA (*(volatile unsigned long *) 0x42050FA8) +#define FEEAEN1_DMAUARTTX_MSK (0x1 << 10 ) +#define FEEAEN1_DMAUARTTX (0x1 << 10 ) +#define FEEAEN1_DMAUARTTX_DIS (0x0 << 10 ) /* DIS. UARTTX DMA interrupt abort disabled. */ +#define FEEAEN1_DMAUARTTX_EN (0x1 << 10 ) /* EN. UARTTX DMA interrupt abort enabled. */ + +/* FEEAEN1[DMASPI1RX] - SPI1RX DMA interrupt abort enable bit */ +#define FEEAEN1_DMASPI1RX_BBA (*(volatile unsigned long *) 0x42050FA4) +#define FEEAEN1_DMASPI1RX_MSK (0x1 << 9 ) +#define FEEAEN1_DMASPI1RX (0x1 << 9 ) +#define FEEAEN1_DMASPI1RX_DIS (0x0 << 9 ) /* DIS. SPI1RX DMA interrupt abort disabled. */ +#define FEEAEN1_DMASPI1RX_EN (0x1 << 9 ) /* EN. SPI1RX DMA interrupt abort enabled. */ + +/* FEEAEN1[DMASPI1TX] - SPI1TX DMA interrupt abort enable bit */ +#define FEEAEN1_DMASPI1TX_BBA (*(volatile unsigned long *) 0x42050FA0) +#define FEEAEN1_DMASPI1TX_MSK (0x1 << 8 ) +#define FEEAEN1_DMASPI1TX (0x1 << 8 ) +#define FEEAEN1_DMASPI1TX_DIS (0x0 << 8 ) /* DIS. SPI1TX DMA interrupt abort disabled. */ +#define FEEAEN1_DMASPI1TX_EN (0x1 << 8 ) /* EN. SPI1TX DMA interrupt abort enabled. */ + +/* FEEAEN1[DMAERROR] - DMA error interrupt abort enable bit */ +#define FEEAEN1_DMAERROR_BBA (*(volatile unsigned long *) 0x42050F9C) +#define FEEAEN1_DMAERROR_MSK (0x1 << 7 ) +#define FEEAEN1_DMAERROR (0x1 << 7 ) +#define FEEAEN1_DMAERROR_DIS (0x0 << 7 ) /* DIS. DMA error interrupt abort disabled. */ +#define FEEAEN1_DMAERROR_EN (0x1 << 7 ) /* EN. DMA error interrupt abort enabled. */ + +/* FEEAEN1[I2CM] - I2C master interrupt abort enable bit */ +#define FEEAEN1_I2CM_BBA (*(volatile unsigned long *) 0x42050F90) +#define FEEAEN1_I2CM_MSK (0x1 << 4 ) +#define FEEAEN1_I2CM (0x1 << 4 ) +#define FEEAEN1_I2CM_DIS (0x0 << 4 ) /* DIS. I2C slave interrupt abort disabled. */ +#define FEEAEN1_I2CM_EN (0x1 << 4 ) /* EN. I2C master interrupt abort enabled. */ + +/* FEEAEN1[I2CS] - I2C slave interrupt abort enable bit */ +#define FEEAEN1_I2CS_BBA (*(volatile unsigned long *) 0x42050F8C) +#define FEEAEN1_I2CS_MSK (0x1 << 3 ) +#define FEEAEN1_I2CS (0x1 << 3 ) +#define FEEAEN1_I2CS_DIS (0x0 << 3 ) /* DIS. I2C slave interrupt abort disabled. */ +#define FEEAEN1_I2CS_EN (0x1 << 3 ) /* EN. I2C slave interrupt abort enabled. */ + +/* FEEAEN1[SPI1] - SPI1 interrupt abort enable bit */ +#define FEEAEN1_SPI1_BBA (*(volatile unsigned long *) 0x42050F88) +#define FEEAEN1_SPI1_MSK (0x1 << 2 ) +#define FEEAEN1_SPI1 (0x1 << 2 ) +#define FEEAEN1_SPI1_DIS (0x0 << 2 ) /* DIS. SPI1 interrupt abort disabled. */ +#define FEEAEN1_SPI1_EN (0x1 << 2 ) /* EN. SPI1 interrupt abort enabled. */ + +/* FEEAEN1[SPI0] - SPI0 interrupt abort enable bit */ +#define FEEAEN1_SPI0_BBA (*(volatile unsigned long *) 0x42050F84) +#define FEEAEN1_SPI0_MSK (0x1 << 1 ) +#define FEEAEN1_SPI0 (0x1 << 1 ) +#define FEEAEN1_SPI0_DIS (0x0 << 1 ) /* DIS. SPI0 interrupt abort disabled. */ +#define FEEAEN1_SPI0_EN (0x1 << 1 ) /* EN. SPI0 interrupt abort enabled. */ + +/* FEEAEN1[UART] - UART interrupt abort enable bit */ +#define FEEAEN1_UART_BBA (*(volatile unsigned long *) 0x42050F80) +#define FEEAEN1_UART_MSK (0x1 << 0 ) +#define FEEAEN1_UART (0x1 << 0 ) +#define FEEAEN1_UART_DIS (0x0 << 0 ) /* DIS. UART interrupt abort disabled. */ +#define FEEAEN1_UART_EN (0x1 << 0 ) /* EN. UART interrupt abort enabled. */ + +/* Reset Value for FEEAEN2*/ +#define FEEAEN2_RVAL 0x0 + +/* FEEAEN2[PWM3] - PWM3 interrupt abort enable bit */ +#define FEEAEN2_PWM3_BBA (*(volatile unsigned long *) 0x42051028) +#define FEEAEN2_PWM3_MSK (0x1 << 10 ) +#define FEEAEN2_PWM3 (0x1 << 10 ) +#define FEEAEN2_PWM3_DIS (0x0 << 10 ) /* DIS. PWM3 interrupt abort disabled. */ +#define FEEAEN2_PWM3_EN (0x1 << 10 ) /* EN. PWM3 interrupt abort enabled. */ + +/* FEEAEN2[PWM2] - PWM2 interrupt abort enable bit */ +#define FEEAEN2_PWM2_BBA (*(volatile unsigned long *) 0x42051024) +#define FEEAEN2_PWM2_MSK (0x1 << 9 ) +#define FEEAEN2_PWM2 (0x1 << 9 ) +#define FEEAEN2_PWM2_DIS (0x0 << 9 ) /* DIS. PWM2 interrupt abort disabled. */ +#define FEEAEN2_PWM2_EN (0x1 << 9 ) /* EN. PWM2 interrupt abort enabled. */ + +/* FEEAEN2[PWM1] - PWM1 interrupt abort enable bit */ +#define FEEAEN2_PWM1_BBA (*(volatile unsigned long *) 0x42051020) +#define FEEAEN2_PWM1_MSK (0x1 << 8 ) +#define FEEAEN2_PWM1 (0x1 << 8 ) +#define FEEAEN2_PWM1_DIS (0x0 << 8 ) /* DIS. PWM1 interrupt abort disabled. */ +#define FEEAEN2_PWM1_EN (0x1 << 8 ) /* EN. PWM1 interrupt abort enabled. */ + +/* FEEAEN2[PWM0] - PWM0 interrupt abort enable bit */ +#define FEEAEN2_PWM0_BBA (*(volatile unsigned long *) 0x4205101C) +#define FEEAEN2_PWM0_MSK (0x1 << 7 ) +#define FEEAEN2_PWM0 (0x1 << 7 ) +#define FEEAEN2_PWM0_DIS (0x0 << 7 ) /* DIS. PWM0 interrupt abort disabled. */ +#define FEEAEN2_PWM0_EN (0x1 << 7 ) /* EN. PWM0 interrupt abort enabled. */ + +/* FEEAEN2[PWMTRIP] - PWMTRIP interrupt abort enable bit */ +#define FEEAEN2_PWMTRIP_BBA (*(volatile unsigned long *) 0x42051018) +#define FEEAEN2_PWMTRIP_MSK (0x1 << 6 ) +#define FEEAEN2_PWMTRIP (0x1 << 6 ) +#define FEEAEN2_PWMTRIP_DIS (0x0 << 6 ) /* DIS. PWMTRIP interrupt abort disabled. */ +#define FEEAEN2_PWMTRIP_EN (0x1 << 6 ) /* EN. PWMTRIP interrupt abort enabled. */ + +/* FEEAEN2[DMASPI0RX] - SPI0RX DMA interrupt abort enable bit */ +#define FEEAEN2_DMASPI0RX_BBA (*(volatile unsigned long *) 0x42051014) +#define FEEAEN2_DMASPI0RX_MSK (0x1 << 5 ) +#define FEEAEN2_DMASPI0RX (0x1 << 5 ) +#define FEEAEN2_DMASPI0RX_DIS (0x0 << 5 ) /* DIS. SPI0RX DMA interrupt abort disabled. */ +#define FEEAEN2_DMASPI0RX_EN (0x1 << 5 ) /* EN. SPI0RX DMA interrupt abort enabled. */ + +/* FEEAEN2[DMASPI0TX] - SPI0TX DMA interrupt abort enable bit */ +#define FEEAEN2_DMASPI0TX_BBA (*(volatile unsigned long *) 0x42051010) +#define FEEAEN2_DMASPI0TX_MSK (0x1 << 4 ) +#define FEEAEN2_DMASPI0TX (0x1 << 4 ) +#define FEEAEN2_DMASPI0TX_DIS (0x0 << 4 ) /* DIS. SPI0TX DMA interrupt abort disabled. */ +#define FEEAEN2_DMASPI0TX_EN (0x1 << 4 ) /* EN. SPI0TX DMA interrupt abort enabled. */ + +/* FEEAEN2[DMAADC] - ADC DMA interrupt abort enable bit */ +#define FEEAEN2_DMAADC_BBA (*(volatile unsigned long *) 0x4205100C) +#define FEEAEN2_DMAADC_MSK (0x1 << 3 ) +#define FEEAEN2_DMAADC (0x1 << 3 ) +#define FEEAEN2_DMAADC_DIS (0x0 << 3 ) /* DIS. ADC DMA interrupt abort disabled. */ +#define FEEAEN2_DMAADC_EN (0x1 << 3 ) /* EN. ADC DMA interrupt abort enabled. */ +// ------------------------------------------------------------------------------------------------ +// ----- GPIO0 ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief General Purpose Input Output (pADI_GP0) + */ + +#if (__NO_MMR_STRUCTS__==0) +typedef struct { /*!< pADI_GP0 Structure */ + __IO uint16_t GPCON; /*!< GPIO Port 0 Configuration */ + __I uint16_t RESERVED0; + __IO uint8_t GPOEN; /*!< GPIO Port 0 Output Enable */ + __I uint8_t RESERVED1[3]; + __IO uint8_t GPPUL; /*!< GPIO Port 0 Pull Up Enable */ + __I uint8_t RESERVED2[3]; + __IO uint8_t GPOCE; /*!< GPIO Port 0 Tri State */ + __I uint8_t RESERVED3[7]; + __IO uint8_t GPIN; /*!< GPIO Port 0 Data Input */ + __I uint8_t RESERVED4[3]; + __IO uint8_t GPOUT; /*!< GPIO Port 0 Data Out */ + __I uint8_t RESERVED5[3]; + __IO uint8_t GPSET; /*!< GPIO Port 0 Data Out Set */ + __I uint8_t RESERVED6[3]; + __IO uint8_t GPCLR; /*!< GPIO Port 0 Data Out Clear */ + __I uint8_t RESERVED7[3]; + __IO uint8_t GPTGL; /*!< GPIO Port 0 Pin Toggle */ +} ADI_GPIO_TypeDef; +#else // (__NO_MMR_STRUCTS__==0) +#define GP0CON (*(volatile unsigned short int *) 0x40006000) +#define GP0OEN (*(volatile unsigned char *) 0x40006004) +#define GP0PUL (*(volatile unsigned char *) 0x40006008) +#define GP0OCE (*(volatile unsigned char *) 0x4000600C) +#define GP0IN (*(volatile unsigned char *) 0x40006014) +#define GP0OUT (*(volatile unsigned char *) 0x40006018) +#define GP0SET (*(volatile unsigned char *) 0x4000601C) +#define GP0CLR (*(volatile unsigned char *) 0x40006020) +#define GP0TGL (*(volatile unsigned char *) 0x40006024) +#endif // (__NO_MMR_STRUCTS__==0) + +/* Reset Value for GP0CON*/ +#define GP0CON_RVAL 0x0 + +/* GP0CON[CON7] - Configuration bits for Px.7 (not available for port 1). */ +#define GP0CON_CON7_MSK (0x3 << 14 ) +#define GP0CON_CON7_GPIOIRQ3 (0x0 << 14 ) /* GPIOIRQ3. GPIO/IRQ3. */ +#define GP0CON_CON7_SPI1CS4 (0x1 << 14 ) /* SPI1CS4. SPI1 CS4 (SPI1). */ +#define GP0CON_CON7_UARTCTS (0x2 << 14 ) /* UARTCTS. UART CTS. */ + +/* GP0CON[CON6] - Configuration bits for Px.6 (not available for port 1). */ +#define GP0CON_CON6_MSK (0x3 << 12 ) +#define GP0CON_CON6_GPIOIRQ2 (0x0 << 12 ) /* GPIOIRQ2. GPIO/IRQ2. */ +#define GP0CON_CON6_SPI1CS3 (0x1 << 12 ) /* SPI1CS3. SPI1 CS3 (SPI1). */ +#define GP0CON_CON6_UARTRTS (0x2 << 12 ) /* UARTRTS. UART RTS. */ +#define GP0CON_CON6_PWM0 (0x3 << 12 ) /* PWM0. PWM0. */ + +/* GP0CON[CON5] - Configuration bits for Px.5. */ +#define GP0CON_CON5_MSK (0x3 << 10 ) +#define GP0CON_CON5_GPIO (0x0 << 10 ) /* GPIO. GPIO. */ +#define GP0CON_CON5_SPI1CS2 (0x1 << 10 ) /* SPI1CS2. SPI1 CS2 (SPI1). */ +#define GP0CON_CON5_ECLKIN (0x2 << 10 ) /* ECLKIN. ECLKIN. */ + +/* GP0CON[CON4] - Configuration bits for Px.4. */ +#define GP0CON_CON4_MSK (0x3 << 8 ) +#define GP0CON_CON4_GPIO (0x0 << 8 ) /* GPIO. GPIO */ +#define GP0CON_CON4_SPI1CS1 (0x1 << 8 ) /* SPI1CS1. SPI1 CS1 (SPI1). */ +#define GP0CON_CON4_ECLKOUT (0x2 << 8 ) /* ECLKOUT. ECLK OUT. */ + +/* GP0CON[CON3] - Configuration bits for Px.3. */ +#define GP0CON_CON3_MSK (0x3 << 6 ) +#define GP0CON_CON3_GPIOIRQ1 (0x0 << 6 ) /* GPIOIRQ1. GPIO/IRQ1. */ +#define GP0CON_CON3_SPI1CS0 (0x1 << 6 ) /* SPI1CS0. SPI1 CS0 (SPI1). */ +#define GP0CON_CON3_ADCCONVST (0x2 << 6 ) /* ADCCONVST. ADCCONVST. */ +#define GP0CON_CON3_PWM1 (0x3 << 6 ) /* PWM1. PWM1. */ + +/* GP0CON[CON2] - Configuration bits for Px.2. */ +#define GP0CON_CON2_MSK (0x3 << 4 ) +#define GP0CON_CON2_GPIO (0x0 << 4 ) /* GPIO. GPIO */ +#define GP0CON_CON2_SPI1MOSI (0x1 << 4 ) /* SPI1MOSI. SPI MOSI (SPI1). */ +#define GP0CON_CON2_PWM0 (0x3 << 4 ) /* PWM0. PWM0 */ + +/* GP0CON[CON1] - Configuration bits for Px.1. */ +#define GP0CON_CON1_MSK (0x3 << 2 ) +#define GP0CON_CON1_GPIO (0x0 << 2 ) /* GPIO. GPIO. */ +#define GP0CON_CON1_SPI1SCLK (0x1 << 2 ) /* SPI1SCLK. SPI SCLK (SPI1). */ + +/* GP0CON[CON0] - Configuration bits for Px.0. */ +#define GP0CON_CON0_MSK (0x3 << 0 ) +#define GP0CON_CON0_GPIO (0x0 << 0 ) /* GPIO. GPIO */ +#define GP0CON_CON0_SPI1MISO (0x1 << 0 ) /* SPI1MISO. SPI MISO (SPI1) */ + +/* Reset Value for GP0OEN*/ +#define GP0OEN_RVAL 0x0 + +/* GP0OEN[OEN7] - Port pin direction. */ +#define GP0OEN_OEN7_BBA (*(volatile unsigned long *) 0x420C009C) +#define GP0OEN_OEN7_MSK (0x1 << 7 ) +#define GP0OEN_OEN7 (0x1 << 7 ) +#define GP0OEN_OEN7_IN (0x0 << 7 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ +#define GP0OEN_OEN7_OUT (0x1 << 7 ) /* OUT. Enables the output on corresponding port pin. */ + +/* GP0OEN[OEN6] - Port pin direction. */ +#define GP0OEN_OEN6_BBA (*(volatile unsigned long *) 0x420C0098) +#define GP0OEN_OEN6_MSK (0x1 << 6 ) +#define GP0OEN_OEN6 (0x1 << 6 ) +#define GP0OEN_OEN6_IN (0x0 << 6 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ +#define GP0OEN_OEN6_OUT (0x1 << 6 ) /* OUT. Enables the output on corresponding port pin. */ + +/* GP0OEN[OEN5] - Port pin direction. */ +#define GP0OEN_OEN5_BBA (*(volatile unsigned long *) 0x420C0094) +#define GP0OEN_OEN5_MSK (0x1 << 5 ) +#define GP0OEN_OEN5 (0x1 << 5 ) +#define GP0OEN_OEN5_IN (0x0 << 5 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ +#define GP0OEN_OEN5_OUT (0x1 << 5 ) /* OUT. Enables the output on corresponding port pin. */ + +/* GP0OEN[OEN4] - Port pin direction. */ +#define GP0OEN_OEN4_BBA (*(volatile unsigned long *) 0x420C0090) +#define GP0OEN_OEN4_MSK (0x1 << 4 ) +#define GP0OEN_OEN4 (0x1 << 4 ) +#define GP0OEN_OEN4_IN (0x0 << 4 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ +#define GP0OEN_OEN4_OUT (0x1 << 4 ) /* OUT. Enables the output on corresponding port pin. */ + +/* GP0OEN[OEN3] - Port pin direction. */ +#define GP0OEN_OEN3_BBA (*(volatile unsigned long *) 0x420C008C) +#define GP0OEN_OEN3_MSK (0x1 << 3 ) +#define GP0OEN_OEN3 (0x1 << 3 ) +#define GP0OEN_OEN3_IN (0x0 << 3 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ +#define GP0OEN_OEN3_OUT (0x1 << 3 ) /* OUT. Enables the output on corresponding port pin. */ + +/* GP0OEN[OEN2] - Port pin direction. */ +#define GP0OEN_OEN2_BBA (*(volatile unsigned long *) 0x420C0088) +#define GP0OEN_OEN2_MSK (0x1 << 2 ) +#define GP0OEN_OEN2 (0x1 << 2 ) +#define GP0OEN_OEN2_IN (0x0 << 2 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ +#define GP0OEN_OEN2_OUT (0x1 << 2 ) /* OUT. Enables the output on corresponding port pin. */ + +/* GP0OEN[OEN1] - Port pin direction. */ +#define GP0OEN_OEN1_BBA (*(volatile unsigned long *) 0x420C0084) +#define GP0OEN_OEN1_MSK (0x1 << 1 ) +#define GP0OEN_OEN1 (0x1 << 1 ) +#define GP0OEN_OEN1_IN (0x0 << 1 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ +#define GP0OEN_OEN1_OUT (0x1 << 1 ) /* OUT. Enables the output on corresponding port pin. */ + +/* GP0OEN[OEN0] - Port pin direction. */ +#define GP0OEN_OEN0_BBA (*(volatile unsigned long *) 0x420C0080) +#define GP0OEN_OEN0_MSK (0x1 << 0 ) +#define GP0OEN_OEN0 (0x1 << 0 ) +#define GP0OEN_OEN0_IN (0x0 << 0 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ +#define GP0OEN_OEN0_OUT (0x1 << 0 ) /* OUT. Enables the output on corresponding port pin.. */ + +/* Reset Value for GP0PUL*/ +#define GP0PUL_RVAL 0xFF + +/* GP0PUL[PUL7] - Pull Up Enable for port pin. */ +#define GP0PUL_PUL7_BBA (*(volatile unsigned long *) 0x420C011C) +#define GP0PUL_PUL7_MSK (0x1 << 7 ) +#define GP0PUL_PUL7 (0x1 << 7 ) +#define GP0PUL_PUL7_DIS (0x0 << 7 ) /* DIS. Disables the internal pull up on corresponding port pin. */ +#define GP0PUL_PUL7_EN (0x1 << 7 ) /* EN. Enables the internal pull up on corresponding port pin. */ + +/* GP0PUL[PUL6] - Pull Up Enable for port pin. */ +#define GP0PUL_PUL6_BBA (*(volatile unsigned long *) 0x420C0118) +#define GP0PUL_PUL6_MSK (0x1 << 6 ) +#define GP0PUL_PUL6 (0x1 << 6 ) +#define GP0PUL_PUL6_DIS (0x0 << 6 ) /* DIS. Disables the internal pull up on corresponding port pin. */ +#define GP0PUL_PUL6_EN (0x1 << 6 ) /* EN. Enables the internal pull up on corresponding port pin. */ + +/* GP0PUL[PUL5] - Pull Up Enable for port pin. */ +#define GP0PUL_PUL5_BBA (*(volatile unsigned long *) 0x420C0114) +#define GP0PUL_PUL5_MSK (0x1 << 5 ) +#define GP0PUL_PUL5 (0x1 << 5 ) +#define GP0PUL_PUL5_DIS (0x0 << 5 ) /* DIS. Disables the internal pull up on corresponding port pin. */ +#define GP0PUL_PUL5_EN (0x1 << 5 ) /* EN. Enables the internal pull up on corresponding port pin. */ + +/* GP0PUL[PUL4] - Pull Up Enable for port pin. */ +#define GP0PUL_PUL4_BBA (*(volatile unsigned long *) 0x420C0110) +#define GP0PUL_PUL4_MSK (0x1 << 4 ) +#define GP0PUL_PUL4 (0x1 << 4 ) +#define GP0PUL_PUL4_DIS (0x0 << 4 ) /* DIS. Disables the internal pull up on corresponding port pin. */ +#define GP0PUL_PUL4_EN (0x1 << 4 ) /* EN. Enables the internal pull up on corresponding port pin. */ + +/* GP0PUL[PUL3] - Pull Up Enable for port pin. */ +#define GP0PUL_PUL3_BBA (*(volatile unsigned long *) 0x420C010C) +#define GP0PUL_PUL3_MSK (0x1 << 3 ) +#define GP0PUL_PUL3 (0x1 << 3 ) +#define GP0PUL_PUL3_DIS (0x0 << 3 ) /* DIS. Disables the internal pull up on corresponding port pin. */ +#define GP0PUL_PUL3_EN (0x1 << 3 ) /* EN. Enables the internal pull up on corresponding port pin. */ + +/* GP0PUL[PUL2] - Pull Up Enable for port pin. */ +#define GP0PUL_PUL2_BBA (*(volatile unsigned long *) 0x420C0108) +#define GP0PUL_PUL2_MSK (0x1 << 2 ) +#define GP0PUL_PUL2 (0x1 << 2 ) +#define GP0PUL_PUL2_DIS (0x0 << 2 ) /* DIS. Disables the internal pull up on corresponding port pin. */ +#define GP0PUL_PUL2_EN (0x1 << 2 ) /* EN. Enables the internal pull up on corresponding port pin. */ + +/* GP0PUL[PUL1] - Pull Up Enable for port pin. */ +#define GP0PUL_PUL1_BBA (*(volatile unsigned long *) 0x420C0104) +#define GP0PUL_PUL1_MSK (0x1 << 1 ) +#define GP0PUL_PUL1 (0x1 << 1 ) +#define GP0PUL_PUL1_DIS (0x0 << 1 ) /* DIS. Disables the internal pull up on corresponding port pin. */ +#define GP0PUL_PUL1_EN (0x1 << 1 ) /* EN. Enables the internal pull up on corresponding port pin. */ + +/* GP0PUL[PUL0] - Pull Up Enable for port pin. */ +#define GP0PUL_PUL0_BBA (*(volatile unsigned long *) 0x420C0100) +#define GP0PUL_PUL0_MSK (0x1 << 0 ) +#define GP0PUL_PUL0 (0x1 << 0 ) +#define GP0PUL_PUL0_DIS (0x0 << 0 ) /* DIS. Disables the internal pull up on corresponding port pin. */ +#define GP0PUL_PUL0_EN (0x1 << 0 ) /* EN. Enables the internal pull up on corresponding port pin. */ + +/* Reset Value for GP0OCE*/ +#define GP0OCE_RVAL 0x0 + +/* GP0OCE[OCE7] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ +#define GP0OCE_OCE7_BBA (*(volatile unsigned long *) 0x420C019C) +#define GP0OCE_OCE7_MSK (0x1 << 7 ) +#define GP0OCE_OCE7 (0x1 << 7 ) +#define GP0OCE_OCE7_DIS (0x0 << 7 ) /* DIS */ +#define GP0OCE_OCE7_EN (0x1 << 7 ) /* EN */ + +/* GP0OCE[OCE6] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ +#define GP0OCE_OCE6_BBA (*(volatile unsigned long *) 0x420C0198) +#define GP0OCE_OCE6_MSK (0x1 << 6 ) +#define GP0OCE_OCE6 (0x1 << 6 ) +#define GP0OCE_OCE6_DIS (0x0 << 6 ) /* DIS */ +#define GP0OCE_OCE6_EN (0x1 << 6 ) /* EN */ + +/* GP0OCE[OCE5] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ +#define GP0OCE_OCE5_BBA (*(volatile unsigned long *) 0x420C0194) +#define GP0OCE_OCE5_MSK (0x1 << 5 ) +#define GP0OCE_OCE5 (0x1 << 5 ) +#define GP0OCE_OCE5_DIS (0x0 << 5 ) /* DIS */ +#define GP0OCE_OCE5_EN (0x1 << 5 ) /* EN */ + +/* GP0OCE[OCE4] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ +#define GP0OCE_OCE4_BBA (*(volatile unsigned long *) 0x420C0190) +#define GP0OCE_OCE4_MSK (0x1 << 4 ) +#define GP0OCE_OCE4 (0x1 << 4 ) +#define GP0OCE_OCE4_DIS (0x0 << 4 ) /* DIS */ +#define GP0OCE_OCE4_EN (0x1 << 4 ) /* EN */ + +/* GP0OCE[OCE3] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ +#define GP0OCE_OCE3_BBA (*(volatile unsigned long *) 0x420C018C) +#define GP0OCE_OCE3_MSK (0x1 << 3 ) +#define GP0OCE_OCE3 (0x1 << 3 ) +#define GP0OCE_OCE3_DIS (0x0 << 3 ) /* DIS */ +#define GP0OCE_OCE3_EN (0x1 << 3 ) /* EN */ + +/* GP0OCE[OCE2] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ +#define GP0OCE_OCE2_BBA (*(volatile unsigned long *) 0x420C0188) +#define GP0OCE_OCE2_MSK (0x1 << 2 ) +#define GP0OCE_OCE2 (0x1 << 2 ) +#define GP0OCE_OCE2_DIS (0x0 << 2 ) /* DIS */ +#define GP0OCE_OCE2_EN (0x1 << 2 ) /* EN */ + +/* GP0OCE[OCE1] - Output enable. Sets the GPIO pads oncorresponding port to open circuit mode. */ +#define GP0OCE_OCE1_BBA (*(volatile unsigned long *) 0x420C0184) +#define GP0OCE_OCE1_MSK (0x1 << 1 ) +#define GP0OCE_OCE1 (0x1 << 1 ) +#define GP0OCE_OCE1_DIS (0x0 << 1 ) /* DIS */ +#define GP0OCE_OCE1_EN (0x1 << 1 ) /* EN */ + +/* GP0OCE[OCE0] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ +#define GP0OCE_OCE0_BBA (*(volatile unsigned long *) 0x420C0180) +#define GP0OCE_OCE0_MSK (0x1 << 0 ) +#define GP0OCE_OCE0 (0x1 << 0 ) +#define GP0OCE_OCE0_DIS (0x0 << 0 ) /* DIS */ +#define GP0OCE_OCE0_EN (0x1 << 0 ) /* EN */ + +/* Reset Value for GP0IN*/ +#define GP0IN_RVAL 0xFF + +/* GP0IN[IN7] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ +#define GP0IN_IN7_BBA (*(volatile unsigned long *) 0x420C029C) +#define GP0IN_IN7_MSK (0x1 << 7 ) +#define GP0IN_IN7 (0x1 << 7 ) +#define GP0IN_IN7_LOW (0x0 << 7 ) /* LOW */ +#define GP0IN_IN7_HIGH (0x1 << 7 ) /* HIGH */ + +/* GP0IN[IN6] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ +#define GP0IN_IN6_BBA (*(volatile unsigned long *) 0x420C0298) +#define GP0IN_IN6_MSK (0x1 << 6 ) +#define GP0IN_IN6 (0x1 << 6 ) +#define GP0IN_IN6_LOW (0x0 << 6 ) /* LOW */ +#define GP0IN_IN6_HIGH (0x1 << 6 ) /* HIGH */ + +/* GP0IN[IN5] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ +#define GP0IN_IN5_BBA (*(volatile unsigned long *) 0x420C0294) +#define GP0IN_IN5_MSK (0x1 << 5 ) +#define GP0IN_IN5 (0x1 << 5 ) +#define GP0IN_IN5_LOW (0x0 << 5 ) /* LOW */ +#define GP0IN_IN5_HIGH (0x1 << 5 ) /* HIGH */ + +/* GP0IN[IN4] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ +#define GP0IN_IN4_BBA (*(volatile unsigned long *) 0x420C0290) +#define GP0IN_IN4_MSK (0x1 << 4 ) +#define GP0IN_IN4 (0x1 << 4 ) +#define GP0IN_IN4_LOW (0x0 << 4 ) /* LOW */ +#define GP0IN_IN4_HIGH (0x1 << 4 ) /* HIGH */ + +/* GP0IN[IN3] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ +#define GP0IN_IN3_BBA (*(volatile unsigned long *) 0x420C028C) +#define GP0IN_IN3_MSK (0x1 << 3 ) +#define GP0IN_IN3 (0x1 << 3 ) +#define GP0IN_IN3_LOW (0x0 << 3 ) /* LOW */ +#define GP0IN_IN3_HIGH (0x1 << 3 ) /* HIGH */ + +/* GP0IN[IN2] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ +#define GP0IN_IN2_BBA (*(volatile unsigned long *) 0x420C0288) +#define GP0IN_IN2_MSK (0x1 << 2 ) +#define GP0IN_IN2 (0x1 << 2 ) +#define GP0IN_IN2_LOW (0x0 << 2 ) /* LOW */ +#define GP0IN_IN2_HIGH (0x1 << 2 ) /* HIGH */ + +/* GP0IN[IN1] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ +#define GP0IN_IN1_BBA (*(volatile unsigned long *) 0x420C0284) +#define GP0IN_IN1_MSK (0x1 << 1 ) +#define GP0IN_IN1 (0x1 << 1 ) +#define GP0IN_IN1_LOW (0x0 << 1 ) /* LOW */ +#define GP0IN_IN1_HIGH (0x1 << 1 ) /* HIGH */ + +/* GP0IN[IN0] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ +#define GP0IN_IN0_BBA (*(volatile unsigned long *) 0x420C0280) +#define GP0IN_IN0_MSK (0x1 << 0 ) +#define GP0IN_IN0 (0x1 << 0 ) +#define GP0IN_IN0_LOW (0x0 << 0 ) /* LOW */ +#define GP0IN_IN0_HIGH (0x1 << 0 ) /* HIGH */ + +/* Reset Value for GP0OUT*/ +#define GP0OUT_RVAL 0x0 + +/* GP0OUT[OUT7] - Data out register. */ +#define GP0OUT_OUT7_BBA (*(volatile unsigned long *) 0x420C031C) +#define GP0OUT_OUT7_MSK (0x1 << 7 ) +#define GP0OUT_OUT7 (0x1 << 7 ) +#define GP0OUT_OUT7_LOW (0x0 << 7 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ +#define GP0OUT_OUT7_HIGH (0x1 << 7 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ + +/* GP0OUT[OUT6] - Data out register. */ +#define GP0OUT_OUT6_BBA (*(volatile unsigned long *) 0x420C0318) +#define GP0OUT_OUT6_MSK (0x1 << 6 ) +#define GP0OUT_OUT6 (0x1 << 6 ) +#define GP0OUT_OUT6_LOW (0x0 << 6 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ +#define GP0OUT_OUT6_HIGH (0x1 << 6 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ + +/* GP0OUT[OUT5] - Data out register. */ +#define GP0OUT_OUT5_BBA (*(volatile unsigned long *) 0x420C0314) +#define GP0OUT_OUT5_MSK (0x1 << 5 ) +#define GP0OUT_OUT5 (0x1 << 5 ) +#define GP0OUT_OUT5_LOW (0x0 << 5 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ +#define GP0OUT_OUT5_HIGH (0x1 << 5 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ + +/* GP0OUT[OUT4] - Data out register. */ +#define GP0OUT_OUT4_BBA (*(volatile unsigned long *) 0x420C0310) +#define GP0OUT_OUT4_MSK (0x1 << 4 ) +#define GP0OUT_OUT4 (0x1 << 4 ) +#define GP0OUT_OUT4_LOW (0x0 << 4 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ +#define GP0OUT_OUT4_HIGH (0x1 << 4 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ + +/* GP0OUT[OUT3] - Data out register. */ +#define GP0OUT_OUT3_BBA (*(volatile unsigned long *) 0x420C030C) +#define GP0OUT_OUT3_MSK (0x1 << 3 ) +#define GP0OUT_OUT3 (0x1 << 3 ) +#define GP0OUT_OUT3_LOW (0x0 << 3 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ +#define GP0OUT_OUT3_HIGH (0x1 << 3 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ + +/* GP0OUT[OUT2] - Data out register. */ +#define GP0OUT_OUT2_BBA (*(volatile unsigned long *) 0x420C0308) +#define GP0OUT_OUT2_MSK (0x1 << 2 ) +#define GP0OUT_OUT2 (0x1 << 2 ) +#define GP0OUT_OUT2_LOW (0x0 << 2 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ +#define GP0OUT_OUT2_HIGH (0x1 << 2 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ + +/* GP0OUT[OUT1] - Data out register. */ +#define GP0OUT_OUT1_BBA (*(volatile unsigned long *) 0x420C0304) +#define GP0OUT_OUT1_MSK (0x1 << 1 ) +#define GP0OUT_OUT1 (0x1 << 1 ) +#define GP0OUT_OUT1_LOW (0x0 << 1 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ +#define GP0OUT_OUT1_HIGH (0x1 << 1 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ + +/* GP0OUT[OUT0] - Data out register. */ +#define GP0OUT_OUT0_BBA (*(volatile unsigned long *) 0x420C0300) +#define GP0OUT_OUT0_MSK (0x1 << 0 ) +#define GP0OUT_OUT0 (0x1 << 0 ) +#define GP0OUT_OUT0_LOW (0x0 << 0 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ +#define GP0OUT_OUT0_HIGH (0x1 << 0 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ + +/* Reset Value for GP0SET*/ +#define GP0SET_RVAL 0x0 + +/* GP0SET[SET7] - Set output high for corresponding port pin. */ +#define GP0SET_SET7_BBA (*(volatile unsigned long *) 0x420C039C) +#define GP0SET_SET7_MSK (0x1 << 7 ) +#define GP0SET_SET7 (0x1 << 7 ) +#define GP0SET_SET7_SET (0x1 << 7 ) /* SET. Set by user code to drive the corresponding GPIO high. */ + +/* GP0SET[SET6] - Set output high for corresponding port pin. */ +#define GP0SET_SET6_BBA (*(volatile unsigned long *) 0x420C0398) +#define GP0SET_SET6_MSK (0x1 << 6 ) +#define GP0SET_SET6 (0x1 << 6 ) +#define GP0SET_SET6_SET (0x1 << 6 ) /* SET. Set by user code to drive the corresponding GPIO high. */ + +/* GP0SET[SET5] - Set output high for corresponding port pin. */ +#define GP0SET_SET5_BBA (*(volatile unsigned long *) 0x420C0394) +#define GP0SET_SET5_MSK (0x1 << 5 ) +#define GP0SET_SET5 (0x1 << 5 ) +#define GP0SET_SET5_SET (0x1 << 5 ) /* SET. Set by user code to drive the corresponding GPIO high. */ + +/* GP0SET[SET4] - Set output high for corresponding port pin. */ +#define GP0SET_SET4_BBA (*(volatile unsigned long *) 0x420C0390) +#define GP0SET_SET4_MSK (0x1 << 4 ) +#define GP0SET_SET4 (0x1 << 4 ) +#define GP0SET_SET4_SET (0x1 << 4 ) /* SET. Set by user code to drive the corresponding GPIO high. */ + +/* GP0SET[SET3] - Set output high for corresponding port pin. */ +#define GP0SET_SET3_BBA (*(volatile unsigned long *) 0x420C038C) +#define GP0SET_SET3_MSK (0x1 << 3 ) +#define GP0SET_SET3 (0x1 << 3 ) +#define GP0SET_SET3_SET (0x1 << 3 ) /* SET. Set by user code to drive the corresponding GPIO high. */ + +/* GP0SET[SET2] - Set output high for corresponding port pin. */ +#define GP0SET_SET2_BBA (*(volatile unsigned long *) 0x420C0388) +#define GP0SET_SET2_MSK (0x1 << 2 ) +#define GP0SET_SET2 (0x1 << 2 ) +#define GP0SET_SET2_SET (0x1 << 2 ) /* SET. Set by user code to drive the corresponding GPIO high. */ + +/* GP0SET[SET1] - Set output high for corresponding port pin. */ +#define GP0SET_SET1_BBA (*(volatile unsigned long *) 0x420C0384) +#define GP0SET_SET1_MSK (0x1 << 1 ) +#define GP0SET_SET1 (0x1 << 1 ) +#define GP0SET_SET1_SET (0x1 << 1 ) /* SET. Set by user code to drive the corresponding GPIO high. */ + +/* GP0SET[SET0] - Set output high for corresponding port pin. */ +#define GP0SET_SET0_BBA (*(volatile unsigned long *) 0x420C0380) +#define GP0SET_SET0_MSK (0x1 << 0 ) +#define GP0SET_SET0 (0x1 << 0 ) +#define GP0SET_SET0_SET (0x1 << 0 ) /* SET. Set by user code to drive the corresponding GPIO high. */ + +/* Reset Value for GP0CLR*/ +#define GP0CLR_RVAL 0x0 + +/* GP0CLR[CLR7] - Set by user code to drive the corresponding GPIO low. */ +#define GP0CLR_CLR7_BBA (*(volatile unsigned long *) 0x420C041C) +#define GP0CLR_CLR7_MSK (0x1 << 7 ) +#define GP0CLR_CLR7 (0x1 << 7 ) +#define GP0CLR_CLR7_CLR (0x1 << 7 ) /* CLR */ + +/* GP0CLR[CLR6] - Set by user code to drive the corresponding GPIO low. */ +#define GP0CLR_CLR6_BBA (*(volatile unsigned long *) 0x420C0418) +#define GP0CLR_CLR6_MSK (0x1 << 6 ) +#define GP0CLR_CLR6 (0x1 << 6 ) +#define GP0CLR_CLR6_CLR (0x1 << 6 ) /* CLR */ + +/* GP0CLR[CLR5] - Set by user code to drive the corresponding GPIO low. */ +#define GP0CLR_CLR5_BBA (*(volatile unsigned long *) 0x420C0414) +#define GP0CLR_CLR5_MSK (0x1 << 5 ) +#define GP0CLR_CLR5 (0x1 << 5 ) +#define GP0CLR_CLR5_CLR (0x1 << 5 ) /* CLR */ + +/* GP0CLR[CLR4] - Set by user code to drive the corresponding GPIO low. */ +#define GP0CLR_CLR4_BBA (*(volatile unsigned long *) 0x420C0410) +#define GP0CLR_CLR4_MSK (0x1 << 4 ) +#define GP0CLR_CLR4 (0x1 << 4 ) +#define GP0CLR_CLR4_CLR (0x1 << 4 ) /* CLR */ + +/* GP0CLR[CLR3] - Set by user code to drive the corresponding GPIO low. */ +#define GP0CLR_CLR3_BBA (*(volatile unsigned long *) 0x420C040C) +#define GP0CLR_CLR3_MSK (0x1 << 3 ) +#define GP0CLR_CLR3 (0x1 << 3 ) +#define GP0CLR_CLR3_CLR (0x1 << 3 ) /* CLR */ + +/* GP0CLR[CLR2] - Set by user code to drive the corresponding GPIO low. */ +#define GP0CLR_CLR2_BBA (*(volatile unsigned long *) 0x420C0408) +#define GP0CLR_CLR2_MSK (0x1 << 2 ) +#define GP0CLR_CLR2 (0x1 << 2 ) +#define GP0CLR_CLR2_CLR (0x1 << 2 ) /* CLR */ + +/* GP0CLR[CLR1] - Set by user code to drive the corresponding GPIO low. */ +#define GP0CLR_CLR1_BBA (*(volatile unsigned long *) 0x420C0404) +#define GP0CLR_CLR1_MSK (0x1 << 1 ) +#define GP0CLR_CLR1 (0x1 << 1 ) +#define GP0CLR_CLR1_CLR (0x1 << 1 ) /* CLR */ + +/* GP0CLR[CLR0] - Set by user code to drive the corresponding GPIO low. */ +#define GP0CLR_CLR0_BBA (*(volatile unsigned long *) 0x420C0400) +#define GP0CLR_CLR0_MSK (0x1 << 0 ) +#define GP0CLR_CLR0 (0x1 << 0 ) +#define GP0CLR_CLR0_CLR (0x1 << 0 ) /* CLR */ + +/* Reset Value for GP0TGL*/ +#define GP0TGL_RVAL 0x0 + +/* GP0TGL[TGL7] - Toggle for corresponding port pin. */ +#define GP0TGL_TGL7_BBA (*(volatile unsigned long *) 0x420C049C) +#define GP0TGL_TGL7_MSK (0x1 << 7 ) +#define GP0TGL_TGL7 (0x1 << 7 ) +#define GP0TGL_TGL7_TGL (0x1 << 7 ) /* TGL. Set by user code to invert the corresponding GPIO. */ + +/* GP0TGL[TGL6] - Toggle for corresponding port pin. */ +#define GP0TGL_TGL6_BBA (*(volatile unsigned long *) 0x420C0498) +#define GP0TGL_TGL6_MSK (0x1 << 6 ) +#define GP0TGL_TGL6 (0x1 << 6 ) +#define GP0TGL_TGL6_TGL (0x1 << 6 ) /* TGL. Set by user code to invert the corresponding GPIO. */ + +/* GP0TGL[TGL5] - Toggle for corresponding port pin. */ +#define GP0TGL_TGL5_BBA (*(volatile unsigned long *) 0x420C0494) +#define GP0TGL_TGL5_MSK (0x1 << 5 ) +#define GP0TGL_TGL5 (0x1 << 5 ) +#define GP0TGL_TGL5_TGL (0x1 << 5 ) /* TGL. Set by user code to invert the corresponding GPIO. */ + +/* GP0TGL[TGL4] - Toggle for corresponding port pin. */ +#define GP0TGL_TGL4_BBA (*(volatile unsigned long *) 0x420C0490) +#define GP0TGL_TGL4_MSK (0x1 << 4 ) +#define GP0TGL_TGL4 (0x1 << 4 ) +#define GP0TGL_TGL4_TGL (0x1 << 4 ) /* TGL. Set by user code to invert the corresponding GPIO. */ + +/* GP0TGL[TGL3] - Toggle for corresponding port pin. */ +#define GP0TGL_TGL3_BBA (*(volatile unsigned long *) 0x420C048C) +#define GP0TGL_TGL3_MSK (0x1 << 3 ) +#define GP0TGL_TGL3 (0x1 << 3 ) +#define GP0TGL_TGL3_TGL (0x1 << 3 ) /* TGL. Set by user code to invert the corresponding GPIO. */ + +/* GP0TGL[TGL2] - Toggle for corresponding port pin. */ +#define GP0TGL_TGL2_BBA (*(volatile unsigned long *) 0x420C0488) +#define GP0TGL_TGL2_MSK (0x1 << 2 ) +#define GP0TGL_TGL2 (0x1 << 2 ) +#define GP0TGL_TGL2_TGL (0x1 << 2 ) /* TGL. Set by user code to invert the corresponding GPIO. */ + +/* GP0TGL[TGL1] - Toggle for corresponding port pin. */ +#define GP0TGL_TGL1_BBA (*(volatile unsigned long *) 0x420C0484) +#define GP0TGL_TGL1_MSK (0x1 << 1 ) +#define GP0TGL_TGL1 (0x1 << 1 ) +#define GP0TGL_TGL1_TGL (0x1 << 1 ) /* TGL. Set by user code to invert the corresponding GPIO. */ + +/* GP0TGL[TGL0] - Toggle for corresponding port pin. */ +#define GP0TGL_TGL0_BBA (*(volatile unsigned long *) 0x420C0480) +#define GP0TGL_TGL0_MSK (0x1 << 0 ) +#define GP0TGL_TGL0 (0x1 << 0 ) +#define GP0TGL_TGL0_TGL (0x1 << 0 ) /* TGL. Set by user code to invert the corresponding GPIO. */ +#if (__NO_MMR_STRUCTS__==1) + +#define GP1CON (*(volatile unsigned short int *) 0x40006030) +#define GP1OEN (*(volatile unsigned char *) 0x40006034) +#define GP1PUL (*(volatile unsigned char *) 0x40006038) +#define GP1OCE (*(volatile unsigned char *) 0x4000603C) +#define GP1IN (*(volatile unsigned char *) 0x40006044) +#define GP1OUT (*(volatile unsigned char *) 0x40006048) +#define GP1SET (*(volatile unsigned char *) 0x4000604C) +#define GP1CLR (*(volatile unsigned char *) 0x40006050) +#define GP1TGL (*(volatile unsigned char *) 0x40006054) +#endif // (__NO_MMR_STRUCTS__==1) + +/* Reset Value for GP1CON*/ +#define GP1CON_RVAL 0x0 + +/* GP1CON[CON6] - Configuration bits for P1.6 */ +#define GP1CON_CON6_MSK (0x3 << 12 ) +#define GP1CON_CON6_GPIO (0x0 << 12 ) /* GPIO */ +#define GP1CON_CON6_ADCCONVST (0x1 << 12 ) /* ADCCONVST */ +#define GP1CON_CON6_PWMSYNC (0x3 << 12 ) /* PWMSYNC */ + +/* GP1CON[CON5] - Configuration bits for P1.5 */ +#define GP1CON_CON5_MSK (0x3 << 10 ) +#define GP1CON_CON5_GPIOIRQ6 (0x0 << 10 ) /* GPIOIRQ6 */ +#define GP1CON_CON5_I2C0SDA (0x1 << 10 ) /* I2C0SDA */ +#define GP1CON_CON5_PWM7 (0x2 << 10 ) /* PWM7 */ + +/* GP1CON[CON4] - Configuration bits for P1.4 */ +#define GP1CON_CON4_MSK (0x3 << 8 ) +#define GP1CON_CON4_GPIOIRQ5 (0x0 << 8 ) /* GPIOIRQ5 */ +#define GP1CON_CON4_I2C0SCL (0x1 << 8 ) /* I2C0SCL */ +#define GP1CON_CON4_PWM6 (0x2 << 8 ) /* PWM6 */ + +/* GP1CON[CON3] - Configuration bits for P1.3 */ +#define GP1CON_CON3_MSK (0x3 << 6 ) +#define GP1CON_CON3_GPIO (0x1 << 6 ) /* GPIO */ +#define GP1CON_CON3_PWM5 (0x3 << 6 ) /* PWM5 */ + +/* GP1CON[CON2] - Configuration bits for P1.2 */ +#define GP1CON_CON2_MSK (0x3 << 4 ) +#define GP1CON_CON2_GPIO (0x1 << 4 ) /* GPIO */ +#define GP1CON_CON2_PWM4 (0x3 << 4 ) /* PWM4 */ + +/* GP1CON[CON1] - Configuration bits for P1.1 */ +#define GP1CON_CON1_MSK (0x3 << 2 ) +#define GP1CON_CON1_PORB (0x0 << 2 ) /* PORB */ +#define GP1CON_CON1_GPIO (0x1 << 2 ) /* GPIO */ +#define GP1CON_CON1_UART0TXD (0x2 << 2 ) /* UART0TXD */ +#define GP1CON_CON1_PWM3 (0x3 << 2 ) /* PWM3 */ + +/* GP1CON[CON0] - Configuration bits for P1.0 */ +#define GP1CON_CON0_MSK (0x3 << 0 ) +#define GP1CON_CON0_GPIOIRQ4 (0x0 << 0 ) /* GPIOIRQ4 */ +#define GP1CON_CON0_UART0RXD (0x1 << 0 ) /* UART0RXD */ +#define GP1CON_CON0_SPI1MOSI (0x2 << 0 ) /* SPI1MOSI */ +#define GP1CON_CON0_PWM2 (0x3 << 0 ) /* PWM2 */ + +/* Reset Value for GP1OEN*/ +#define GP1OEN_RVAL 0x0 + +/* GP1OEN[OEN6] - Port pin direction. */ +#define GP1OEN_OEN6_BBA (*(volatile unsigned long *) 0x420C0698) +#define GP1OEN_OEN6_MSK (0x1 << 6 ) +#define GP1OEN_OEN6 (0x1 << 6 ) +#define GP1OEN_OEN6_IN (0x0 << 6 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ +#define GP1OEN_OEN6_OUT (0x1 << 6 ) /* OUT. Enables the output on corresponding port pin. */ + +/* GP1OEN[OEN5] - Port pin direction. */ +#define GP1OEN_OEN5_BBA (*(volatile unsigned long *) 0x420C0694) +#define GP1OEN_OEN5_MSK (0x1 << 5 ) +#define GP1OEN_OEN5 (0x1 << 5 ) +#define GP1OEN_OEN5_IN (0x0 << 5 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ +#define GP1OEN_OEN5_OUT (0x1 << 5 ) /* OUT. Enables the output on corresponding port pin. */ + +/* GP1OEN[OEN4] - Port pin direction. */ +#define GP1OEN_OEN4_BBA (*(volatile unsigned long *) 0x420C0690) +#define GP1OEN_OEN4_MSK (0x1 << 4 ) +#define GP1OEN_OEN4 (0x1 << 4 ) +#define GP1OEN_OEN4_IN (0x0 << 4 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ +#define GP1OEN_OEN4_OUT (0x1 << 4 ) /* OUT. Enables the output on corresponding port pin. */ + +/* GP1OEN[OEN3] - Port pin direction. */ +#define GP1OEN_OEN3_BBA (*(volatile unsigned long *) 0x420C068C) +#define GP1OEN_OEN3_MSK (0x1 << 3 ) +#define GP1OEN_OEN3 (0x1 << 3 ) +#define GP1OEN_OEN3_IN (0x0 << 3 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ +#define GP1OEN_OEN3_OUT (0x1 << 3 ) /* OUT. Enables the output on corresponding port pin. */ + +/* GP1OEN[OEN2] - Port pin direction. */ +#define GP1OEN_OEN2_BBA (*(volatile unsigned long *) 0x420C0688) +#define GP1OEN_OEN2_MSK (0x1 << 2 ) +#define GP1OEN_OEN2 (0x1 << 2 ) +#define GP1OEN_OEN2_IN (0x0 << 2 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ +#define GP1OEN_OEN2_OUT (0x1 << 2 ) /* OUT. Enables the output on corresponding port pin. */ + +/* GP1OEN[OEN1] - Port pin direction. */ +#define GP1OEN_OEN1_BBA (*(volatile unsigned long *) 0x420C0684) +#define GP1OEN_OEN1_MSK (0x1 << 1 ) +#define GP1OEN_OEN1 (0x1 << 1 ) +#define GP1OEN_OEN1_IN (0x0 << 1 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ +#define GP1OEN_OEN1_OUT (0x1 << 1 ) /* OUT. Enables the output on corresponding port pin. */ + +/* GP1OEN[OEN0] - Port pin direction. */ +#define GP1OEN_OEN0_BBA (*(volatile unsigned long *) 0x420C0680) +#define GP1OEN_OEN0_MSK (0x1 << 0 ) +#define GP1OEN_OEN0 (0x1 << 0 ) +#define GP1OEN_OEN0_IN (0x0 << 0 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ +#define GP1OEN_OEN0_OUT (0x1 << 0 ) /* OUT. Enables the output on corresponding port pin.. */ + +/* Reset Value for GP1PUL*/ +#define GP1PUL_RVAL 0x7F + +/* GP1PUL[PUL6] - Pull Up Enable for port pin. */ +#define GP1PUL_PUL6_BBA (*(volatile unsigned long *) 0x420C0718) +#define GP1PUL_PUL6_MSK (0x1 << 6 ) +#define GP1PUL_PUL6 (0x1 << 6 ) +#define GP1PUL_PUL6_DIS (0x0 << 6 ) /* DIS. Disables the internal pull up on corresponding port pin. */ +#define GP1PUL_PUL6_EN (0x1 << 6 ) /* EN. Enables the internal pull up on corresponding port pin. */ + +/* GP1PUL[PUL5] - Pull Up Enable for port pin. */ +#define GP1PUL_PUL5_BBA (*(volatile unsigned long *) 0x420C0714) +#define GP1PUL_PUL5_MSK (0x1 << 5 ) +#define GP1PUL_PUL5 (0x1 << 5 ) +#define GP1PUL_PUL5_DIS (0x0 << 5 ) /* DIS. Disables the internal pull up on corresponding port pin. */ +#define GP1PUL_PUL5_EN (0x1 << 5 ) /* EN. Enables the internal pull up on corresponding port pin. */ + +/* GP1PUL[PUL4] - Pull Up Enable for port pin. */ +#define GP1PUL_PUL4_BBA (*(volatile unsigned long *) 0x420C0710) +#define GP1PUL_PUL4_MSK (0x1 << 4 ) +#define GP1PUL_PUL4 (0x1 << 4 ) +#define GP1PUL_PUL4_DIS (0x0 << 4 ) /* DIS. Disables the internal pull up on corresponding port pin. */ +#define GP1PUL_PUL4_EN (0x1 << 4 ) /* EN. Enables the internal pull up on corresponding port pin. */ + +/* GP1PUL[PUL3] - Pull Up Enable for port pin. */ +#define GP1PUL_PUL3_BBA (*(volatile unsigned long *) 0x420C070C) +#define GP1PUL_PUL3_MSK (0x1 << 3 ) +#define GP1PUL_PUL3 (0x1 << 3 ) +#define GP1PUL_PUL3_DIS (0x0 << 3 ) /* DIS. Disables the internal pull up on corresponding port pin. */ +#define GP1PUL_PUL3_EN (0x1 << 3 ) /* EN. Enables the internal pull up on corresponding port pin. */ + +/* GP1PUL[PUL2] - Pull Up Enable for port pin. */ +#define GP1PUL_PUL2_BBA (*(volatile unsigned long *) 0x420C0708) +#define GP1PUL_PUL2_MSK (0x1 << 2 ) +#define GP1PUL_PUL2 (0x1 << 2 ) +#define GP1PUL_PUL2_DIS (0x0 << 2 ) /* DIS. Disables the internal pull up on corresponding port pin. */ +#define GP1PUL_PUL2_EN (0x1 << 2 ) /* EN. Enables the internal pull up on corresponding port pin. */ + +/* GP1PUL[PUL1] - Pull Up Enable for port pin. */ +#define GP1PUL_PUL1_BBA (*(volatile unsigned long *) 0x420C0704) +#define GP1PUL_PUL1_MSK (0x1 << 1 ) +#define GP1PUL_PUL1 (0x1 << 1 ) +#define GP1PUL_PUL1_DIS (0x0 << 1 ) /* DIS. Disables the internal pull up on corresponding port pin. */ +#define GP1PUL_PUL1_EN (0x1 << 1 ) /* EN. Enables the internal pull up on corresponding port pin. */ + +/* GP1PUL[PUL0] - Pull Up Enable for port pin. */ +#define GP1PUL_PUL0_BBA (*(volatile unsigned long *) 0x420C0700) +#define GP1PUL_PUL0_MSK (0x1 << 0 ) +#define GP1PUL_PUL0 (0x1 << 0 ) +#define GP1PUL_PUL0_DIS (0x0 << 0 ) /* DIS. Disables the internal pull up on corresponding port pin. */ +#define GP1PUL_PUL0_EN (0x1 << 0 ) /* EN. Enables the internal pull up on corresponding port pin. */ + +/* Reset Value for GP1OCE*/ +#define GP1OCE_RVAL 0x0 + +/* GP1OCE[OCE6] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ +#define GP1OCE_OCE6_BBA (*(volatile unsigned long *) 0x420C0798) +#define GP1OCE_OCE6_MSK (0x1 << 6 ) +#define GP1OCE_OCE6 (0x1 << 6 ) +#define GP1OCE_OCE6_DIS (0x0 << 6 ) /* DIS */ +#define GP1OCE_OCE6_EN (0x1 << 6 ) /* EN */ + +/* GP1OCE[OCE5] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ +#define GP1OCE_OCE5_BBA (*(volatile unsigned long *) 0x420C0794) +#define GP1OCE_OCE5_MSK (0x1 << 5 ) +#define GP1OCE_OCE5 (0x1 << 5 ) +#define GP1OCE_OCE5_DIS (0x0 << 5 ) /* DIS */ +#define GP1OCE_OCE5_EN (0x1 << 5 ) /* EN */ + +/* GP1OCE[OCE4] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ +#define GP1OCE_OCE4_BBA (*(volatile unsigned long *) 0x420C0790) +#define GP1OCE_OCE4_MSK (0x1 << 4 ) +#define GP1OCE_OCE4 (0x1 << 4 ) +#define GP1OCE_OCE4_DIS (0x0 << 4 ) /* DIS */ +#define GP1OCE_OCE4_EN (0x1 << 4 ) /* EN */ + +/* GP1OCE[OCE3] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ +#define GP1OCE_OCE3_BBA (*(volatile unsigned long *) 0x420C078C) +#define GP1OCE_OCE3_MSK (0x1 << 3 ) +#define GP1OCE_OCE3 (0x1 << 3 ) +#define GP1OCE_OCE3_DIS (0x0 << 3 ) /* DIS */ +#define GP1OCE_OCE3_EN (0x1 << 3 ) /* EN */ + +/* GP1OCE[OCE2] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ +#define GP1OCE_OCE2_BBA (*(volatile unsigned long *) 0x420C0788) +#define GP1OCE_OCE2_MSK (0x1 << 2 ) +#define GP1OCE_OCE2 (0x1 << 2 ) +#define GP1OCE_OCE2_DIS (0x0 << 2 ) /* DIS */ +#define GP1OCE_OCE2_EN (0x1 << 2 ) /* EN */ + +/* GP1OCE[OCE1] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ +#define GP1OCE_OCE1_BBA (*(volatile unsigned long *) 0x420C0784) +#define GP1OCE_OCE1_MSK (0x1 << 1 ) +#define GP1OCE_OCE1 (0x1 << 1 ) +#define GP1OCE_OCE1_DIS (0x0 << 1 ) /* DIS */ +#define GP1OCE_OCE1_EN (0x1 << 1 ) /* EN */ + +/* GP1OCE[OCE0] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ +#define GP1OCE_OCE0_BBA (*(volatile unsigned long *) 0x420C0780) +#define GP1OCE_OCE0_MSK (0x1 << 0 ) +#define GP1OCE_OCE0 (0x1 << 0 ) +#define GP1OCE_OCE0_DIS (0x0 << 0 ) /* DIS */ +#define GP1OCE_OCE0_EN (0x1 << 0 ) /* EN */ + +/* Reset Value for GP1IN*/ +#define GP1IN_RVAL 0x7F + +/* GP1IN[IN6] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ +#define GP1IN_IN6_BBA (*(volatile unsigned long *) 0x420C0898) +#define GP1IN_IN6_MSK (0x1 << 6 ) +#define GP1IN_IN6 (0x1 << 6 ) +#define GP1IN_IN6_LOW (0x0 << 6 ) /* LOW */ +#define GP1IN_IN6_HIGH (0x1 << 6 ) /* HIGH */ + +/* GP1IN[IN5] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ +#define GP1IN_IN5_BBA (*(volatile unsigned long *) 0x420C0894) +#define GP1IN_IN5_MSK (0x1 << 5 ) +#define GP1IN_IN5 (0x1 << 5 ) +#define GP1IN_IN5_LOW (0x0 << 5 ) /* LOW */ +#define GP1IN_IN5_HIGH (0x1 << 5 ) /* HIGH */ + +/* GP1IN[IN4] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ +#define GP1IN_IN4_BBA (*(volatile unsigned long *) 0x420C0890) +#define GP1IN_IN4_MSK (0x1 << 4 ) +#define GP1IN_IN4 (0x1 << 4 ) +#define GP1IN_IN4_LOW (0x0 << 4 ) /* LOW */ +#define GP1IN_IN4_HIGH (0x1 << 4 ) /* HIGH */ + +/* GP1IN[IN3] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ +#define GP1IN_IN3_BBA (*(volatile unsigned long *) 0x420C088C) +#define GP1IN_IN3_MSK (0x1 << 3 ) +#define GP1IN_IN3 (0x1 << 3 ) +#define GP1IN_IN3_LOW (0x0 << 3 ) /* LOW */ +#define GP1IN_IN3_HIGH (0x1 << 3 ) /* HIGH */ + +/* GP1IN[IN2] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ +#define GP1IN_IN2_BBA (*(volatile unsigned long *) 0x420C0888) +#define GP1IN_IN2_MSK (0x1 << 2 ) +#define GP1IN_IN2 (0x1 << 2 ) +#define GP1IN_IN2_LOW (0x0 << 2 ) /* LOW */ +#define GP1IN_IN2_HIGH (0x1 << 2 ) /* HIGH */ + +/* GP1IN[IN1] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ +#define GP1IN_IN1_BBA (*(volatile unsigned long *) 0x420C0884) +#define GP1IN_IN1_MSK (0x1 << 1 ) +#define GP1IN_IN1 (0x1 << 1 ) +#define GP1IN_IN1_LOW (0x0 << 1 ) /* LOW */ +#define GP1IN_IN1_HIGH (0x1 << 1 ) /* HIGH */ + +/* GP1IN[IN0] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ +#define GP1IN_IN0_BBA (*(volatile unsigned long *) 0x420C0880) +#define GP1IN_IN0_MSK (0x1 << 0 ) +#define GP1IN_IN0 (0x1 << 0 ) +#define GP1IN_IN0_LOW (0x0 << 0 ) /* LOW */ +#define GP1IN_IN0_HIGH (0x1 << 0 ) /* HIGH */ + +/* Reset Value for GP1OUT*/ +#define GP1OUT_RVAL 0x0 + +/* GP1OUT[OUT6] - Output for port pin. */ +#define GP1OUT_OUT6_BBA (*(volatile unsigned long *) 0x420C0918) +#define GP1OUT_OUT6_MSK (0x1 << 6 ) +#define GP1OUT_OUT6 (0x1 << 6 ) +#define GP1OUT_OUT6_LOW (0x0 << 6 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ +#define GP1OUT_OUT6_HIGH (0x1 << 6 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ + +/* GP1OUT[OUT5] - Output for port pin. */ +#define GP1OUT_OUT5_BBA (*(volatile unsigned long *) 0x420C0914) +#define GP1OUT_OUT5_MSK (0x1 << 5 ) +#define GP1OUT_OUT5 (0x1 << 5 ) +#define GP1OUT_OUT5_LOW (0x0 << 5 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ +#define GP1OUT_OUT5_HIGH (0x1 << 5 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ + +/* GP1OUT[OUT4] - Output for port pin. */ +#define GP1OUT_OUT4_BBA (*(volatile unsigned long *) 0x420C0910) +#define GP1OUT_OUT4_MSK (0x1 << 4 ) +#define GP1OUT_OUT4 (0x1 << 4 ) +#define GP1OUT_OUT4_LOW (0x0 << 4 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ +#define GP1OUT_OUT4_HIGH (0x1 << 4 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ + +/* GP1OUT[OUT3] - Output for port pin. */ +#define GP1OUT_OUT3_BBA (*(volatile unsigned long *) 0x420C090C) +#define GP1OUT_OUT3_MSK (0x1 << 3 ) +#define GP1OUT_OUT3 (0x1 << 3 ) +#define GP1OUT_OUT3_LOW (0x0 << 3 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ +#define GP1OUT_OUT3_HIGH (0x1 << 3 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ + +/* GP1OUT[OUT2] - Output for port pin. */ +#define GP1OUT_OUT2_BBA (*(volatile unsigned long *) 0x420C0908) +#define GP1OUT_OUT2_MSK (0x1 << 2 ) +#define GP1OUT_OUT2 (0x1 << 2 ) +#define GP1OUT_OUT2_LOW (0x0 << 2 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ +#define GP1OUT_OUT2_HIGH (0x1 << 2 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ + +/* GP1OUT[OUT1] - Output for port pin. */ +#define GP1OUT_OUT1_BBA (*(volatile unsigned long *) 0x420C0904) +#define GP1OUT_OUT1_MSK (0x1 << 1 ) +#define GP1OUT_OUT1 (0x1 << 1 ) +#define GP1OUT_OUT1_LOW (0x0 << 1 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ +#define GP1OUT_OUT1_HIGH (0x1 << 1 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ + +/* GP1OUT[OUT0] - Output for port pin. */ +#define GP1OUT_OUT0_BBA (*(volatile unsigned long *) 0x420C0900) +#define GP1OUT_OUT0_MSK (0x1 << 0 ) +#define GP1OUT_OUT0 (0x1 << 0 ) +#define GP1OUT_OUT0_LOW (0x0 << 0 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ +#define GP1OUT_OUT0_HIGH (0x1 << 0 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ + +/* Reset Value for GP1SET*/ +#define GP1SET_RVAL 0x0 + +/* GP1SET[SET6] - Set output high for corresponding port pin. */ +#define GP1SET_SET6_BBA (*(volatile unsigned long *) 0x420C0998) +#define GP1SET_SET6_MSK (0x1 << 6 ) +#define GP1SET_SET6 (0x1 << 6 ) +#define GP1SET_SET6_SET (0x1 << 6 ) /* SET. Set by user code to drive the corresponding GPIO high. */ + +/* GP1SET[SET5] - Set output high for corresponding port pin. */ +#define GP1SET_SET5_BBA (*(volatile unsigned long *) 0x420C0994) +#define GP1SET_SET5_MSK (0x1 << 5 ) +#define GP1SET_SET5 (0x1 << 5 ) +#define GP1SET_SET5_SET (0x1 << 5 ) /* SET. Set by user code to drive the corresponding GPIO high. */ + +/* GP1SET[SET4] - Set output high for corresponding port pin. */ +#define GP1SET_SET4_BBA (*(volatile unsigned long *) 0x420C0990) +#define GP1SET_SET4_MSK (0x1 << 4 ) +#define GP1SET_SET4 (0x1 << 4 ) +#define GP1SET_SET4_SET (0x1 << 4 ) /* SET. Set by user code to drive the corresponding GPIO high. */ + +/* GP1SET[SET3] - Set output high for corresponding port pin. */ +#define GP1SET_SET3_BBA (*(volatile unsigned long *) 0x420C098C) +#define GP1SET_SET3_MSK (0x1 << 3 ) +#define GP1SET_SET3 (0x1 << 3 ) +#define GP1SET_SET3_SET (0x1 << 3 ) /* SET. Set by user code to drive the corresponding GPIO high. */ + +/* GP1SET[SET2] - Set output high for corresponding port pin. */ +#define GP1SET_SET2_BBA (*(volatile unsigned long *) 0x420C0988) +#define GP1SET_SET2_MSK (0x1 << 2 ) +#define GP1SET_SET2 (0x1 << 2 ) +#define GP1SET_SET2_SET (0x1 << 2 ) /* SET. Set by user code to drive the corresponding GPIO high. */ + +/* GP1SET[SET1] - Set output high for corresponding port pin. */ +#define GP1SET_SET1_BBA (*(volatile unsigned long *) 0x420C0984) +#define GP1SET_SET1_MSK (0x1 << 1 ) +#define GP1SET_SET1 (0x1 << 1 ) +#define GP1SET_SET1_SET (0x1 << 1 ) /* SET. Set by user code to drive the corresponding GPIO high. */ + +/* GP1SET[SET0] - Set output high for corresponding port pin. */ +#define GP1SET_SET0_BBA (*(volatile unsigned long *) 0x420C0980) +#define GP1SET_SET0_MSK (0x1 << 0 ) +#define GP1SET_SET0 (0x1 << 0 ) +#define GP1SET_SET0_SET (0x1 << 0 ) /* SET. Set by user code to drive the corresponding GPIO high. */ + +/* Reset Value for GP1CLR*/ +#define GP1CLR_RVAL 0x0 + +/* GP1CLR[CLR6] - Set by user code to drive the corresponding GPIO low. */ +#define GP1CLR_CLR6_BBA (*(volatile unsigned long *) 0x420C0A18) +#define GP1CLR_CLR6_MSK (0x1 << 6 ) +#define GP1CLR_CLR6 (0x1 << 6 ) +#define GP1CLR_CLR6_CLR (0x1 << 6 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ + +/* GP1CLR[CLR5] - Set by user code to drive the corresponding GPIO low. */ +#define GP1CLR_CLR5_BBA (*(volatile unsigned long *) 0x420C0A14) +#define GP1CLR_CLR5_MSK (0x1 << 5 ) +#define GP1CLR_CLR5 (0x1 << 5 ) +#define GP1CLR_CLR5_CLR (0x1 << 5 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ + +/* GP1CLR[CLR4] - Set by user code to drive the corresponding GPIO low. */ +#define GP1CLR_CLR4_BBA (*(volatile unsigned long *) 0x420C0A10) +#define GP1CLR_CLR4_MSK (0x1 << 4 ) +#define GP1CLR_CLR4 (0x1 << 4 ) +#define GP1CLR_CLR4_CLR (0x1 << 4 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ + +/* GP1CLR[CLR3] - Set by user code to drive the corresponding GPIO low. */ +#define GP1CLR_CLR3_BBA (*(volatile unsigned long *) 0x420C0A0C) +#define GP1CLR_CLR3_MSK (0x1 << 3 ) +#define GP1CLR_CLR3 (0x1 << 3 ) +#define GP1CLR_CLR3_CLR (0x1 << 3 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ + +/* GP1CLR[CLR2] - Set by user code to drive the corresponding GPIO low. */ +#define GP1CLR_CLR2_BBA (*(volatile unsigned long *) 0x420C0A08) +#define GP1CLR_CLR2_MSK (0x1 << 2 ) +#define GP1CLR_CLR2 (0x1 << 2 ) +#define GP1CLR_CLR2_CLR (0x1 << 2 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ + +/* GP1CLR[CLR1] - Set by user code to drive the corresponding GPIO low. */ +#define GP1CLR_CLR1_BBA (*(volatile unsigned long *) 0x420C0A04) +#define GP1CLR_CLR1_MSK (0x1 << 1 ) +#define GP1CLR_CLR1 (0x1 << 1 ) +#define GP1CLR_CLR1_CLR (0x1 << 1 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ + +/* GP1CLR[CLR0] - Set by user code to drive the corresponding GPIO low. */ +#define GP1CLR_CLR0_BBA (*(volatile unsigned long *) 0x420C0A00) +#define GP1CLR_CLR0_MSK (0x1 << 0 ) +#define GP1CLR_CLR0 (0x1 << 0 ) +#define GP1CLR_CLR0_CLR (0x1 << 0 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ + +/* Reset Value for GP1TGL*/ +#define GP1TGL_RVAL 0x0 + +/* GP1TGL[TGL6] - Toggle for corresponding port pin. */ +#define GP1TGL_TGL6_BBA (*(volatile unsigned long *) 0x420C0A98) +#define GP1TGL_TGL6_MSK (0x1 << 6 ) +#define GP1TGL_TGL6 (0x1 << 6 ) +#define GP1TGL_TGL6_TGL (0x1 << 6 ) /* TGL. Set by user code to invert the corresponding GPIO. */ + +/* GP1TGL[TGL5] - Toggle for corresponding port pin. */ +#define GP1TGL_TGL5_BBA (*(volatile unsigned long *) 0x420C0A94) +#define GP1TGL_TGL5_MSK (0x1 << 5 ) +#define GP1TGL_TGL5 (0x1 << 5 ) +#define GP1TGL_TGL5_TGL (0x1 << 5 ) /* TGL. Set by user code to invert the corresponding GPIO. */ + +/* GP1TGL[TGL4] - Toggle for corresponding port pin. */ +#define GP1TGL_TGL4_BBA (*(volatile unsigned long *) 0x420C0A90) +#define GP1TGL_TGL4_MSK (0x1 << 4 ) +#define GP1TGL_TGL4 (0x1 << 4 ) +#define GP1TGL_TGL4_TGL (0x1 << 4 ) /* TGL. Set by user code to invert the corresponding GPIO. */ + +/* GP1TGL[TGL3] - Toggle for corresponding port pin. */ +#define GP1TGL_TGL3_BBA (*(volatile unsigned long *) 0x420C0A8C) +#define GP1TGL_TGL3_MSK (0x1 << 3 ) +#define GP1TGL_TGL3 (0x1 << 3 ) +#define GP1TGL_TGL3_TGL (0x1 << 3 ) /* TGL. Set by user code to invert the corresponding GPIO. */ + +/* GP1TGL[TGL2] - Toggle for corresponding port pin. */ +#define GP1TGL_TGL2_BBA (*(volatile unsigned long *) 0x420C0A88) +#define GP1TGL_TGL2_MSK (0x1 << 2 ) +#define GP1TGL_TGL2 (0x1 << 2 ) +#define GP1TGL_TGL2_TGL (0x1 << 2 ) /* TGL. Set by user code to invert the corresponding GPIO. */ + +/* GP1TGL[TGL1] - Toggle for corresponding port pin. */ +#define GP1TGL_TGL1_BBA (*(volatile unsigned long *) 0x420C0A84) +#define GP1TGL_TGL1_MSK (0x1 << 1 ) +#define GP1TGL_TGL1 (0x1 << 1 ) +#define GP1TGL_TGL1_TGL (0x1 << 1 ) /* TGL. Set by user code to invert the corresponding GPIO. */ + +/* GP1TGL[TGL0] - Toggle for corresponding port pin. */ +#define GP1TGL_TGL0_BBA (*(volatile unsigned long *) 0x420C0A80) +#define GP1TGL_TGL0_MSK (0x1 << 0 ) +#define GP1TGL_TGL0 (0x1 << 0 ) +#define GP1TGL_TGL0_TGL (0x1 << 0 ) /* TGL. Set by user code to invert the corresponding GPIO. */ +#if (__NO_MMR_STRUCTS__==1) + +#define GP2CON (*(volatile unsigned short int *) 0x40006060) +#define GP2OEN (*(volatile unsigned char *) 0x40006064) +#define GP2PUL (*(volatile unsigned char *) 0x40006068) +#define GP2OCE (*(volatile unsigned char *) 0x4000606C) +#define GP2IN (*(volatile unsigned char *) 0x40006074) +#define GP2OUT (*(volatile unsigned char *) 0x40006078) +#define GP2SET (*(volatile unsigned char *) 0x4000607C) +#define GP2CLR (*(volatile unsigned char *) 0x40006080) +#define GP2TGL (*(volatile unsigned char *) 0x40006084) +#endif // (__NO_MMR_STRUCTS__==1) + +/* Reset Value for GP2CON*/ +#define GP2CON_RVAL 0x0 + +/* GP2CON[CON7] - Configuration bits for P2.7 */ +#define GP2CON_CON7_MSK (0x3 << 14 ) +#define GP2CON_CON7_GPIOIRQ7 (0x0 << 14 ) /* GPIOIRQ7 */ + +/* GP2CON[CON6] - Configuration bits for P2.6 */ +#define GP2CON_CON6_MSK (0x3 << 12 ) +#define GP2CON_CON6_GPIO (0x1 << 12 ) /* GPIO */ + +/* GP2CON[CON5] - Configuration bits for P2.5 */ +#define GP2CON_CON5_MSK (0x3 << 10 ) +#define GP2CON_CON5_GPIO (0x2 << 10 ) /* GPIO */ +#define GP2CON_CON5_RF32KHZCLK (0x3 << 10 ) /* RF32KHZCLK */ + +/* GP2CON[CON4] - Configuration bits for P2.4 */ +#define GP2CON_CON4_MSK (0x3 << 8 ) +#define GP2CON_CON4_IRQ8 (0x0 << 8 ) /* IRQ8 */ +#define GP2CON_CON4_GPIO (0x1 << 8 ) /* GPIO */ + +/* GP2CON[CON3] - Configuration bits for P2.3 */ +#define GP2CON_CON3_MSK (0x3 << 6 ) +#define GP2CON_CON3_SPI0CS (0x0 << 6 ) /* SPI0CS */ +#define GP2CON_CON3_GPIO (0x1 << 6 ) /* GPIO */ + +/* GP2CON[CON2] - Configuration bits for P2.2 */ +#define GP2CON_CON2_MSK (0x3 << 4 ) +#define GP2CON_CON2_SPI0MOSI (0x0 << 4 ) /* SPI0MOSI */ +#define GP2CON_CON2_GPIO (0x1 << 4 ) /* GPIO */ + +/* GP2CON[CON1] - Configuration bits for P2.1 */ +#define GP2CON_CON1_MSK (0x3 << 2 ) +#define GP2CON_CON1_SPI0SCLK (0x0 << 2 ) /* SPI0SCLK */ +#define GP2CON_CON1_GPIO (0x1 << 2 ) /* GPIO */ + +/* GP2CON[CON0] - Configuration bits for P2.0 */ +#define GP2CON_CON0_MSK (0x3 << 0 ) +#define GP2CON_CON0_SPI0MISO (0x0 << 0 ) /* SPI0MISO */ +#define GP2CON_CON0_GPIO (0x1 << 0 ) /* GPIO */ + +/* Reset Value for GP2OEN*/ +#define GP2OEN_RVAL 0x0 + +/* GP2OEN[OEN7] - Port pin direction. */ +#define GP2OEN_OEN7_BBA (*(volatile unsigned long *) 0x420C0C9C) +#define GP2OEN_OEN7_MSK (0x1 << 7 ) +#define GP2OEN_OEN7 (0x1 << 7 ) +#define GP2OEN_OEN7_IN (0x0 << 7 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ +#define GP2OEN_OEN7_OUT (0x1 << 7 ) /* OUT. Enables the output on corresponding port pin. */ + +/* GP2OEN[OEN6] - Port pin direction. */ +#define GP2OEN_OEN6_BBA (*(volatile unsigned long *) 0x420C0C98) +#define GP2OEN_OEN6_MSK (0x1 << 6 ) +#define GP2OEN_OEN6 (0x1 << 6 ) +#define GP2OEN_OEN6_IN (0x0 << 6 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ +#define GP2OEN_OEN6_OUT (0x1 << 6 ) /* OUT. Enables the output on corresponding port pin. */ + +/* GP2OEN[OEN5] - Port pin direction. */ +#define GP2OEN_OEN5_BBA (*(volatile unsigned long *) 0x420C0C94) +#define GP2OEN_OEN5_MSK (0x1 << 5 ) +#define GP2OEN_OEN5 (0x1 << 5 ) +#define GP2OEN_OEN5_IN (0x0 << 5 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ +#define GP2OEN_OEN5_OUT (0x1 << 5 ) /* OUT. Enables the output on corresponding port pin. */ + +/* GP2OEN[OEN4] - Port pin direction. */ +#define GP2OEN_OEN4_BBA (*(volatile unsigned long *) 0x420C0C90) +#define GP2OEN_OEN4_MSK (0x1 << 4 ) +#define GP2OEN_OEN4 (0x1 << 4 ) +#define GP2OEN_OEN4_IN (0x0 << 4 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ +#define GP2OEN_OEN4_OUT (0x1 << 4 ) /* OUT. Enables the output on corresponding port pin. */ + +/* GP2OEN[OEN3] - Port pin direction. */ +#define GP2OEN_OEN3_BBA (*(volatile unsigned long *) 0x420C0C8C) +#define GP2OEN_OEN3_MSK (0x1 << 3 ) +#define GP2OEN_OEN3 (0x1 << 3 ) +#define GP2OEN_OEN3_IN (0x0 << 3 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ +#define GP2OEN_OEN3_OUT (0x1 << 3 ) /* OUT. Enables the output on corresponding port pin. */ + +/* GP2OEN[OEN2] - Port pin direction. */ +#define GP2OEN_OEN2_BBA (*(volatile unsigned long *) 0x420C0C88) +#define GP2OEN_OEN2_MSK (0x1 << 2 ) +#define GP2OEN_OEN2 (0x1 << 2 ) +#define GP2OEN_OEN2_IN (0x0 << 2 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ +#define GP2OEN_OEN2_OUT (0x1 << 2 ) /* OUT. Enables the output on corresponding port pin. */ + +/* GP2OEN[OEN1] - Port pin direction. */ +#define GP2OEN_OEN1_BBA (*(volatile unsigned long *) 0x420C0C84) +#define GP2OEN_OEN1_MSK (0x1 << 1 ) +#define GP2OEN_OEN1 (0x1 << 1 ) +#define GP2OEN_OEN1_IN (0x0 << 1 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ +#define GP2OEN_OEN1_OUT (0x1 << 1 ) /* OUT. Enables the output on corresponding port pin. */ + +/* GP2OEN[OEN0] - Port pin direction. */ +#define GP2OEN_OEN0_BBA (*(volatile unsigned long *) 0x420C0C80) +#define GP2OEN_OEN0_MSK (0x1 << 0 ) +#define GP2OEN_OEN0 (0x1 << 0 ) +#define GP2OEN_OEN0_IN (0x0 << 0 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ +#define GP2OEN_OEN0_OUT (0x1 << 0 ) /* OUT. Enables the output on corresponding port pin. */ + +/* Reset Value for GP2PUL*/ +#define GP2PUL_RVAL 0xFF + +/* GP2PUL[PUL7] - Pull Up Enable for port pin. */ +#define GP2PUL_PUL7_BBA (*(volatile unsigned long *) 0x420C0D1C) +#define GP2PUL_PUL7_MSK (0x1 << 7 ) +#define GP2PUL_PUL7 (0x1 << 7 ) +#define GP2PUL_PUL7_DIS (0x0 << 7 ) /* DIS. Disables the internal pull up on corresponding port pin. */ +#define GP2PUL_PUL7_EN (0x1 << 7 ) /* EN. Enables the internal pull up on corresponding port pin. */ + +/* GP2PUL[PUL6] - Pull Up Enable for port pin. */ +#define GP2PUL_PUL6_BBA (*(volatile unsigned long *) 0x420C0D18) +#define GP2PUL_PUL6_MSK (0x1 << 6 ) +#define GP2PUL_PUL6 (0x1 << 6 ) +#define GP2PUL_PUL6_DIS (0x0 << 6 ) /* DIS. Disables the internal pull up on corresponding port pin. */ +#define GP2PUL_PUL6_EN (0x1 << 6 ) /* EN. Enables the internal pull up on corresponding port pin. */ + +/* GP2PUL[PUL5] - Pull Up Enable for port pin. */ +#define GP2PUL_PUL5_BBA (*(volatile unsigned long *) 0x420C0D14) +#define GP2PUL_PUL5_MSK (0x1 << 5 ) +#define GP2PUL_PUL5 (0x1 << 5 ) +#define GP2PUL_PUL5_DIS (0x0 << 5 ) /* DIS. Disables the internal pull up on corresponding port pin. */ +#define GP2PUL_PUL5_EN (0x1 << 5 ) /* EN. Enables the internal pull up on corresponding port pin. */ + +/* GP2PUL[PUL4] - Pull Up Enable for port pin. */ +#define GP2PUL_PUL4_BBA (*(volatile unsigned long *) 0x420C0D10) +#define GP2PUL_PUL4_MSK (0x1 << 4 ) +#define GP2PUL_PUL4 (0x1 << 4 ) +#define GP2PUL_PUL4_DIS (0x0 << 4 ) /* DIS. Disables the internal pull up on corresponding port pin. */ +#define GP2PUL_PUL4_EN (0x1 << 4 ) /* EN. Enables the internal pull up on corresponding port pin. */ + +/* GP2PUL[PUL3] - Pull Up Enable for port pin. */ +#define GP2PUL_PUL3_BBA (*(volatile unsigned long *) 0x420C0D0C) +#define GP2PUL_PUL3_MSK (0x1 << 3 ) +#define GP2PUL_PUL3 (0x1 << 3 ) +#define GP2PUL_PUL3_DIS (0x0 << 3 ) /* DIS. Disables the internal pull up on corresponding port pin. */ +#define GP2PUL_PUL3_EN (0x1 << 3 ) /* EN. Enables the internal pull up on corresponding port pin. */ + +/* GP2PUL[PUL2] - Pull Up Enable for port pin. */ +#define GP2PUL_PUL2_BBA (*(volatile unsigned long *) 0x420C0D08) +#define GP2PUL_PUL2_MSK (0x1 << 2 ) +#define GP2PUL_PUL2 (0x1 << 2 ) +#define GP2PUL_PUL2_DIS (0x0 << 2 ) /* DIS. Disables the internal pull up on corresponding port pin. */ +#define GP2PUL_PUL2_EN (0x1 << 2 ) /* EN. Enables the internal pull up on corresponding port pin. */ + +/* GP2PUL[PUL1] - Pull Up Enable for port pin. */ +#define GP2PUL_PUL1_BBA (*(volatile unsigned long *) 0x420C0D04) +#define GP2PUL_PUL1_MSK (0x1 << 1 ) +#define GP2PUL_PUL1 (0x1 << 1 ) +#define GP2PUL_PUL1_DIS (0x0 << 1 ) /* DIS. Disables the internal pull up on corresponding port pin. */ +#define GP2PUL_PUL1_EN (0x1 << 1 ) /* EN. Enables the internal pull up on corresponding port pin. */ + +/* GP2PUL[PUL0] - Pull Up Enable for port pin. */ +#define GP2PUL_PUL0_BBA (*(volatile unsigned long *) 0x420C0D00) +#define GP2PUL_PUL0_MSK (0x1 << 0 ) +#define GP2PUL_PUL0 (0x1 << 0 ) +#define GP2PUL_PUL0_DIS (0x0 << 0 ) /* DIS. Disables the internal pull up on corresponding port pin. */ +#define GP2PUL_PUL0_EN (0x1 << 0 ) /* EN. Enables the internal pull up on corresponding port pin. */ + +/* Reset Value for GP2OCE*/ +#define GP2OCE_RVAL 0x0 + +/* GP2OCE[OCE7] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ +#define GP2OCE_OCE7_BBA (*(volatile unsigned long *) 0x420C0D9C) +#define GP2OCE_OCE7_MSK (0x1 << 7 ) +#define GP2OCE_OCE7 (0x1 << 7 ) +#define GP2OCE_OCE7_DIS (0x0 << 7 ) /* DIS */ +#define GP2OCE_OCE7_EN (0x1 << 7 ) /* EN */ + +/* GP2OCE[OCE6] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ +#define GP2OCE_OCE6_BBA (*(volatile unsigned long *) 0x420C0D98) +#define GP2OCE_OCE6_MSK (0x1 << 6 ) +#define GP2OCE_OCE6 (0x1 << 6 ) +#define GP2OCE_OCE6_DIS (0x0 << 6 ) /* DIS */ +#define GP2OCE_OCE6_EN (0x1 << 6 ) /* EN */ + +/* GP2OCE[OCE5] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ +#define GP2OCE_OCE5_BBA (*(volatile unsigned long *) 0x420C0D94) +#define GP2OCE_OCE5_MSK (0x1 << 5 ) +#define GP2OCE_OCE5 (0x1 << 5 ) +#define GP2OCE_OCE5_DIS (0x0 << 5 ) /* DIS */ +#define GP2OCE_OCE5_EN (0x1 << 5 ) /* EN */ + +/* GP2OCE[OCE4] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ +#define GP2OCE_OCE4_BBA (*(volatile unsigned long *) 0x420C0D90) +#define GP2OCE_OCE4_MSK (0x1 << 4 ) +#define GP2OCE_OCE4 (0x1 << 4 ) +#define GP2OCE_OCE4_DIS (0x0 << 4 ) /* DIS */ +#define GP2OCE_OCE4_EN (0x1 << 4 ) /* EN */ + +/* GP2OCE[OCE3] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ +#define GP2OCE_OCE3_BBA (*(volatile unsigned long *) 0x420C0D8C) +#define GP2OCE_OCE3_MSK (0x1 << 3 ) +#define GP2OCE_OCE3 (0x1 << 3 ) +#define GP2OCE_OCE3_DIS (0x0 << 3 ) /* DIS */ +#define GP2OCE_OCE3_EN (0x1 << 3 ) /* EN */ + +/* GP2OCE[OCE2] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ +#define GP2OCE_OCE2_BBA (*(volatile unsigned long *) 0x420C0D88) +#define GP2OCE_OCE2_MSK (0x1 << 2 ) +#define GP2OCE_OCE2 (0x1 << 2 ) +#define GP2OCE_OCE2_DIS (0x0 << 2 ) /* DIS */ +#define GP2OCE_OCE2_EN (0x1 << 2 ) /* EN */ + +/* GP2OCE[OCE1] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ +#define GP2OCE_OCE1_BBA (*(volatile unsigned long *) 0x420C0D84) +#define GP2OCE_OCE1_MSK (0x1 << 1 ) +#define GP2OCE_OCE1 (0x1 << 1 ) +#define GP2OCE_OCE1_DIS (0x0 << 1 ) /* DIS */ +#define GP2OCE_OCE1_EN (0x1 << 1 ) /* EN */ + +/* GP2OCE[OCE0] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ +#define GP2OCE_OCE0_BBA (*(volatile unsigned long *) 0x420C0D80) +#define GP2OCE_OCE0_MSK (0x1 << 0 ) +#define GP2OCE_OCE0 (0x1 << 0 ) +#define GP2OCE_OCE0_DIS (0x0 << 0 ) /* DIS */ +#define GP2OCE_OCE0_EN (0x1 << 0 ) /* EN */ + +/* Reset Value for GP2IN*/ +#define GP2IN_RVAL 0xFF + +/* GP2IN[IN7] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ +#define GP2IN_IN7_BBA (*(volatile unsigned long *) 0x420C0E9C) +#define GP2IN_IN7_MSK (0x1 << 7 ) +#define GP2IN_IN7 (0x1 << 7 ) +#define GP2IN_IN7_LOW (0x0 << 7 ) /* LOW */ +#define GP2IN_IN7_HIGH (0x1 << 7 ) /* HIGH */ + +/* GP2IN[IN6] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ +#define GP2IN_IN6_BBA (*(volatile unsigned long *) 0x420C0E98) +#define GP2IN_IN6_MSK (0x1 << 6 ) +#define GP2IN_IN6 (0x1 << 6 ) +#define GP2IN_IN6_LOW (0x0 << 6 ) /* LOW */ +#define GP2IN_IN6_HIGH (0x1 << 6 ) /* HIGH */ + +/* GP2IN[IN5] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ +#define GP2IN_IN5_BBA (*(volatile unsigned long *) 0x420C0E94) +#define GP2IN_IN5_MSK (0x1 << 5 ) +#define GP2IN_IN5 (0x1 << 5 ) +#define GP2IN_IN5_LOW (0x0 << 5 ) /* LOW */ +#define GP2IN_IN5_HIGH (0x1 << 5 ) /* HIGH */ + +/* GP2IN[IN4] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ +#define GP2IN_IN4_BBA (*(volatile unsigned long *) 0x420C0E90) +#define GP2IN_IN4_MSK (0x1 << 4 ) +#define GP2IN_IN4 (0x1 << 4 ) +#define GP2IN_IN4_LOW (0x0 << 4 ) /* LOW */ +#define GP2IN_IN4_HIGH (0x1 << 4 ) /* HIGH */ + +/* GP2IN[IN3] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ +#define GP2IN_IN3_BBA (*(volatile unsigned long *) 0x420C0E8C) +#define GP2IN_IN3_MSK (0x1 << 3 ) +#define GP2IN_IN3 (0x1 << 3 ) +#define GP2IN_IN3_LOW (0x0 << 3 ) /* LOW */ +#define GP2IN_IN3_HIGH (0x1 << 3 ) /* HIGH */ + +/* GP2IN[IN2] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ +#define GP2IN_IN2_BBA (*(volatile unsigned long *) 0x420C0E88) +#define GP2IN_IN2_MSK (0x1 << 2 ) +#define GP2IN_IN2 (0x1 << 2 ) +#define GP2IN_IN2_LOW (0x0 << 2 ) /* LOW */ +#define GP2IN_IN2_HIGH (0x1 << 2 ) /* HIGH */ + +/* GP2IN[IN1] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ +#define GP2IN_IN1_BBA (*(volatile unsigned long *) 0x420C0E84) +#define GP2IN_IN1_MSK (0x1 << 1 ) +#define GP2IN_IN1 (0x1 << 1 ) +#define GP2IN_IN1_LOW (0x0 << 1 ) /* LOW */ +#define GP2IN_IN1_HIGH (0x1 << 1 ) /* HIGH */ + +/* GP2IN[IN0] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ +#define GP2IN_IN0_BBA (*(volatile unsigned long *) 0x420C0E80) +#define GP2IN_IN0_MSK (0x1 << 0 ) +#define GP2IN_IN0 (0x1 << 0 ) +#define GP2IN_IN0_LOW (0x0 << 0 ) /* LOW */ +#define GP2IN_IN0_HIGH (0x1 << 0 ) /* HIGH */ + +/* Reset Value for GP2OUT*/ +#define GP2OUT_RVAL 0x0 + +/* GP2OUT[OUT7] - Output for port pin. */ +#define GP2OUT_OUT7_BBA (*(volatile unsigned long *) 0x420C0F1C) +#define GP2OUT_OUT7_MSK (0x1 << 7 ) +#define GP2OUT_OUT7 (0x1 << 7 ) +#define GP2OUT_OUT7_LOW (0x0 << 7 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ +#define GP2OUT_OUT7_HIGH (0x1 << 7 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ + +/* GP2OUT[OUT6] - Output for port pin. */ +#define GP2OUT_OUT6_BBA (*(volatile unsigned long *) 0x420C0F18) +#define GP2OUT_OUT6_MSK (0x1 << 6 ) +#define GP2OUT_OUT6 (0x1 << 6 ) +#define GP2OUT_OUT6_LOW (0x0 << 6 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ +#define GP2OUT_OUT6_HIGH (0x1 << 6 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ + +/* GP2OUT[OUT5] - Output for port pin. */ +#define GP2OUT_OUT5_BBA (*(volatile unsigned long *) 0x420C0F14) +#define GP2OUT_OUT5_MSK (0x1 << 5 ) +#define GP2OUT_OUT5 (0x1 << 5 ) +#define GP2OUT_OUT5_LOW (0x0 << 5 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ +#define GP2OUT_OUT5_HIGH (0x1 << 5 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ + +/* GP2OUT[OUT4] - Output for port pin. */ +#define GP2OUT_OUT4_BBA (*(volatile unsigned long *) 0x420C0F10) +#define GP2OUT_OUT4_MSK (0x1 << 4 ) +#define GP2OUT_OUT4 (0x1 << 4 ) +#define GP2OUT_OUT4_LOW (0x0 << 4 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ +#define GP2OUT_OUT4_HIGH (0x1 << 4 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ + +/* GP2OUT[OUT3] - Output for port pin. */ +#define GP2OUT_OUT3_BBA (*(volatile unsigned long *) 0x420C0F0C) +#define GP2OUT_OUT3_MSK (0x1 << 3 ) +#define GP2OUT_OUT3 (0x1 << 3 ) +#define GP2OUT_OUT3_LOW (0x0 << 3 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ +#define GP2OUT_OUT3_HIGH (0x1 << 3 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ + +/* GP2OUT[OUT2] - Output for port pin. */ +#define GP2OUT_OUT2_BBA (*(volatile unsigned long *) 0x420C0F08) +#define GP2OUT_OUT2_MSK (0x1 << 2 ) +#define GP2OUT_OUT2 (0x1 << 2 ) +#define GP2OUT_OUT2_LOW (0x0 << 2 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ +#define GP2OUT_OUT2_HIGH (0x1 << 2 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ + +/* GP2OUT[OUT1] - Output for port pin. */ +#define GP2OUT_OUT1_BBA (*(volatile unsigned long *) 0x420C0F04) +#define GP2OUT_OUT1_MSK (0x1 << 1 ) +#define GP2OUT_OUT1 (0x1 << 1 ) +#define GP2OUT_OUT1_LOW (0x0 << 1 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ +#define GP2OUT_OUT1_HIGH (0x1 << 1 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ + +/* GP2OUT[OUT0] - Output for port pin. */ +#define GP2OUT_OUT0_BBA (*(volatile unsigned long *) 0x420C0F00) +#define GP2OUT_OUT0_MSK (0x1 << 0 ) +#define GP2OUT_OUT0 (0x1 << 0 ) +#define GP2OUT_OUT0_LOW (0x0 << 0 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ +#define GP2OUT_OUT0_HIGH (0x1 << 0 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ + +/* Reset Value for GP2SET*/ +#define GP2SET_RVAL 0x0 + +/* GP2SET[SET7] - Set output high for corresponding port pin. */ +#define GP2SET_SET7_BBA (*(volatile unsigned long *) 0x420C0F9C) +#define GP2SET_SET7_MSK (0x1 << 7 ) +#define GP2SET_SET7 (0x1 << 7 ) +#define GP2SET_SET7_SET (0x1 << 7 ) /* SET. Set by user code to drive the corresponding GPIO high. */ + +/* GP2SET[SET6] - Set output high for corresponding port pin. */ +#define GP2SET_SET6_BBA (*(volatile unsigned long *) 0x420C0F98) +#define GP2SET_SET6_MSK (0x1 << 6 ) +#define GP2SET_SET6 (0x1 << 6 ) +#define GP2SET_SET6_SET (0x1 << 6 ) /* SET. Set by user code to drive the corresponding GPIO high. */ + +/* GP2SET[SET5] - Set output high for corresponding port pin. */ +#define GP2SET_SET5_BBA (*(volatile unsigned long *) 0x420C0F94) +#define GP2SET_SET5_MSK (0x1 << 5 ) +#define GP2SET_SET5 (0x1 << 5 ) +#define GP2SET_SET5_SET (0x1 << 5 ) /* SET. Set by user code to drive the corresponding GPIO high. */ + +/* GP2SET[SET4] - Set output high for corresponding port pin. */ +#define GP2SET_SET4_BBA (*(volatile unsigned long *) 0x420C0F90) +#define GP2SET_SET4_MSK (0x1 << 4 ) +#define GP2SET_SET4 (0x1 << 4 ) +#define GP2SET_SET4_SET (0x1 << 4 ) /* SET. Set by user code to drive the corresponding GPIO high. */ + +/* GP2SET[SET3] - Set output high for corresponding port pin. */ +#define GP2SET_SET3_BBA (*(volatile unsigned long *) 0x420C0F8C) +#define GP2SET_SET3_MSK (0x1 << 3 ) +#define GP2SET_SET3 (0x1 << 3 ) +#define GP2SET_SET3_SET (0x1 << 3 ) /* SET. Set by user code to drive the corresponding GPIO high. */ + +/* GP2SET[SET2] - Set output high for corresponding port pin. */ +#define GP2SET_SET2_BBA (*(volatile unsigned long *) 0x420C0F88) +#define GP2SET_SET2_MSK (0x1 << 2 ) +#define GP2SET_SET2 (0x1 << 2 ) +#define GP2SET_SET2_SET (0x1 << 2 ) /* SET. Set by user code to drive the corresponding GPIO high. */ + +/* GP2SET[SET1] - Set output high for corresponding port pin. */ +#define GP2SET_SET1_BBA (*(volatile unsigned long *) 0x420C0F84) +#define GP2SET_SET1_MSK (0x1 << 1 ) +#define GP2SET_SET1 (0x1 << 1 ) +#define GP2SET_SET1_SET (0x1 << 1 ) /* SET. Set by user code to drive the corresponding GPIO high. */ + +/* GP2SET[SET0] - Set output high for corresponding port pin. */ +#define GP2SET_SET0_BBA (*(volatile unsigned long *) 0x420C0F80) +#define GP2SET_SET0_MSK (0x1 << 0 ) +#define GP2SET_SET0 (0x1 << 0 ) +#define GP2SET_SET0_SET (0x1 << 0 ) /* SET. Set by user code to drive the corresponding GPIO high. */ + +/* Reset Value for GP2CLR*/ +#define GP2CLR_RVAL 0x0 + +/* GP2CLR[CLR7] - Set by user code to drive the corresponding GPIO low. */ +#define GP2CLR_CLR7_BBA (*(volatile unsigned long *) 0x420C101C) +#define GP2CLR_CLR7_MSK (0x1 << 7 ) +#define GP2CLR_CLR7 (0x1 << 7 ) +#define GP2CLR_CLR7_CLR (0x1 << 7 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ + +/* GP2CLR[CLR6] - Set by user code to drive the corresponding GPIO low. */ +#define GP2CLR_CLR6_BBA (*(volatile unsigned long *) 0x420C1018) +#define GP2CLR_CLR6_MSK (0x1 << 6 ) +#define GP2CLR_CLR6 (0x1 << 6 ) +#define GP2CLR_CLR6_CLR (0x1 << 6 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ + +/* GP2CLR[CLR5] - Set by user code to drive the corresponding GPIO low. */ +#define GP2CLR_CLR5_BBA (*(volatile unsigned long *) 0x420C1014) +#define GP2CLR_CLR5_MSK (0x1 << 5 ) +#define GP2CLR_CLR5 (0x1 << 5 ) +#define GP2CLR_CLR5_CLR (0x1 << 5 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ + +/* GP2CLR[CLR4] - Set by user code to drive the corresponding GPIO low. */ +#define GP2CLR_CLR4_BBA (*(volatile unsigned long *) 0x420C1010) +#define GP2CLR_CLR4_MSK (0x1 << 4 ) +#define GP2CLR_CLR4 (0x1 << 4 ) +#define GP2CLR_CLR4_CLR (0x1 << 4 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ + +/* GP2CLR[CLR3] - Set by user code to drive the corresponding GPIO low. */ +#define GP2CLR_CLR3_BBA (*(volatile unsigned long *) 0x420C100C) +#define GP2CLR_CLR3_MSK (0x1 << 3 ) +#define GP2CLR_CLR3 (0x1 << 3 ) +#define GP2CLR_CLR3_CLR (0x1 << 3 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ + +/* GP2CLR[CLR2] - Set by user code to drive the corresponding GPIO low. */ +#define GP2CLR_CLR2_BBA (*(volatile unsigned long *) 0x420C1008) +#define GP2CLR_CLR2_MSK (0x1 << 2 ) +#define GP2CLR_CLR2 (0x1 << 2 ) +#define GP2CLR_CLR2_CLR (0x1 << 2 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ + +/* GP2CLR[CLR1] - Set by user code to drive the corresponding GPIO low. */ +#define GP2CLR_CLR1_BBA (*(volatile unsigned long *) 0x420C1004) +#define GP2CLR_CLR1_MSK (0x1 << 1 ) +#define GP2CLR_CLR1 (0x1 << 1 ) +#define GP2CLR_CLR1_CLR (0x1 << 1 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ + +/* GP2CLR[CLR0] - Set by user code to drive the corresponding GPIO low. */ +#define GP2CLR_CLR0_BBA (*(volatile unsigned long *) 0x420C1000) +#define GP2CLR_CLR0_MSK (0x1 << 0 ) +#define GP2CLR_CLR0 (0x1 << 0 ) +#define GP2CLR_CLR0_CLR (0x1 << 0 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ + +/* Reset Value for GP2TGL*/ +#define GP2TGL_RVAL 0x0 + +/* GP2TGL[TGL7] - Toggle for corresponding port pin. */ +#define GP2TGL_TGL7_BBA (*(volatile unsigned long *) 0x420C109C) +#define GP2TGL_TGL7_MSK (0x1 << 7 ) +#define GP2TGL_TGL7 (0x1 << 7 ) +#define GP2TGL_TGL7_TGL (0x1 << 7 ) /* TGL. Set by user code to invert the corresponding GPIO. */ + +/* GP2TGL[TGL6] - Toggle for corresponding port pin. */ +#define GP2TGL_TGL6_BBA (*(volatile unsigned long *) 0x420C1098) +#define GP2TGL_TGL6_MSK (0x1 << 6 ) +#define GP2TGL_TGL6 (0x1 << 6 ) +#define GP2TGL_TGL6_TGL (0x1 << 6 ) /* TGL. Set by user code to invert the corresponding GPIO. */ + +/* GP2TGL[TGL5] - Toggle for corresponding port pin. */ +#define GP2TGL_TGL5_BBA (*(volatile unsigned long *) 0x420C1094) +#define GP2TGL_TGL5_MSK (0x1 << 5 ) +#define GP2TGL_TGL5 (0x1 << 5 ) +#define GP2TGL_TGL5_TGL (0x1 << 5 ) /* TGL. Set by user code to invert the corresponding GPIO. */ + +/* GP2TGL[TGL4] - Toggle for corresponding port pin. */ +#define GP2TGL_TGL4_BBA (*(volatile unsigned long *) 0x420C1090) +#define GP2TGL_TGL4_MSK (0x1 << 4 ) +#define GP2TGL_TGL4 (0x1 << 4 ) +#define GP2TGL_TGL4_TGL (0x1 << 4 ) /* TGL. Set by user code to invert the corresponding GPIO. */ + +/* GP2TGL[TGL3] - Toggle for corresponding port pin. */ +#define GP2TGL_TGL3_BBA (*(volatile unsigned long *) 0x420C108C) +#define GP2TGL_TGL3_MSK (0x1 << 3 ) +#define GP2TGL_TGL3 (0x1 << 3 ) +#define GP2TGL_TGL3_TGL (0x1 << 3 ) /* TGL. Set by user code to invert the corresponding GPIO. */ + +/* GP2TGL[TGL2] - Toggle for corresponding port pin. */ +#define GP2TGL_TGL2_BBA (*(volatile unsigned long *) 0x420C1088) +#define GP2TGL_TGL2_MSK (0x1 << 2 ) +#define GP2TGL_TGL2 (0x1 << 2 ) +#define GP2TGL_TGL2_TGL (0x1 << 2 ) /* TGL. Set by user code to invert the corresponding GPIO. */ + +/* GP2TGL[TGL1] - Toggle for corresponding port pin. */ +#define GP2TGL_TGL1_BBA (*(volatile unsigned long *) 0x420C1084) +#define GP2TGL_TGL1_MSK (0x1 << 1 ) +#define GP2TGL_TGL1 (0x1 << 1 ) +#define GP2TGL_TGL1_TGL (0x1 << 1 ) /* TGL. Set by user code to invert the corresponding GPIO. */ + +/* GP2TGL[TGL0] - Toggle for corresponding port pin. */ +#define GP2TGL_TGL0_BBA (*(volatile unsigned long *) 0x420C1080) +#define GP2TGL_TGL0_MSK (0x1 << 0 ) +#define GP2TGL_TGL0 (0x1 << 0 ) +#define GP2TGL_TGL0_TGL (0x1 << 0 ) /* TGL. Set by user code to invert the corresponding GPIO. */ +#if (__NO_MMR_STRUCTS__==1) + +#define GP3CON (*(volatile unsigned short int *) 0x40006090) +#define GP3OEN (*(volatile unsigned char *) 0x40006094) +#define GP3PUL (*(volatile unsigned char *) 0x40006098) +#define GP3OCE (*(volatile unsigned char *) 0x4000609C) +#define GP3IN (*(volatile unsigned char *) 0x400060A4) +#define GP3OUT (*(volatile unsigned char *) 0x400060A8) +#define GP3SET (*(volatile unsigned char *) 0x400060AC) +#define GP3CLR (*(volatile unsigned char *) 0x400060B0) +#define GP3TGL (*(volatile unsigned char *) 0x400060B4) +#endif // (__NO_MMR_STRUCTS__==1) + +/* Reset Value for GP3CON*/ +#define GP3CON_RVAL 0x0 + +/* GP3CON[CON7] - Configuration bits for P3.7 */ +#define GP3CON_CON7_MSK (0x3 << 14 ) +#define GP3CON_CON7_GPIOIRQ0 (0x1 << 14 ) /* GPIOIRQ0 */ + +/* GP3CON[CON6] - Configuration bits for P3.6 */ +#define GP3CON_CON6_MSK (0x3 << 12 ) +#define GP3CON_CON6_GPIO (0x1 << 12 ) /* GPIO */ + +/* GP3CON[CON5] - Configuration bits for P3.5 */ +#define GP3CON_CON5_MSK (0x3 << 10 ) +#define GP3CON_CON5_GPIO (0x1 << 10 ) /* GPIO */ +#define GP3CON_CON5_SPI0MOSI (0x3 << 10 ) /* SPI0MOSI */ + +/* GP3CON[CON4] - Configuration bits for P3.4 */ +#define GP3CON_CON4_MSK (0x3 << 8 ) +#define GP3CON_CON4_GPIO (0x1 << 8 ) /* GPIO */ + +/* GP3CON[CON3] - Configuration bits for P3.3 */ +#define GP3CON_CON3_MSK (0x3 << 6 ) +#define GP3CON_CON3_GPIO (0x1 << 6 ) /* GPIO */ +#define GP3CON_CON3_PWMTRIP (0x2 << 6 ) /* PWMTRIP */ +#define GP3CON_CON3_SPI0SCLK (0x3 << 6 ) /* SPI0SCLK */ + +/* GP3CON[CON2] - Configuration bits for P3.2 */ +#define GP3CON_CON2_MSK (0x3 << 4 ) +#define GP3CON_CON2_GPIO (0x1 << 4 ) /* GPIO */ +#define GP3CON_CON2_PWMSYNC (0x2 << 4 ) /* PWMSYNC */ +#define GP3CON_CON2_SPI0MISO (0x3 << 4 ) /* SPI0MISO */ + +/* GP3CON[CON1] - Configuration bits for P3.1 */ +#define GP3CON_CON1_MSK (0x3 << 2 ) +#define GP3CON_CON1_GPIO (0x0 << 2 ) /* GPIO */ + +/* GP3CON[CON0] - Configuration bits for P3.0 */ +#define GP3CON_CON0_MSK (0x3 << 0 ) +#define GP3CON_CON0_GPIO (0x0 << 0 ) /* GPIO */ +#define GP3CON_CON0_PWMTRIP (0x3 << 0 ) /* PWMTRIP */ + +/* Reset Value for GP3OEN*/ +#define GP3OEN_RVAL 0x0 + +/* GP3OEN[OEN7] - Port pin direction. */ +#define GP3OEN_OEN7_BBA (*(volatile unsigned long *) 0x420C129C) +#define GP3OEN_OEN7_MSK (0x1 << 7 ) +#define GP3OEN_OEN7 (0x1 << 7 ) +#define GP3OEN_OEN7_IN (0x0 << 7 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ +#define GP3OEN_OEN7_OUT (0x1 << 7 ) /* OUT. Enables the output on corresponding port pin. */ + +/* GP3OEN[OEN6] - Port pin direction. */ +#define GP3OEN_OEN6_BBA (*(volatile unsigned long *) 0x420C1298) +#define GP3OEN_OEN6_MSK (0x1 << 6 ) +#define GP3OEN_OEN6 (0x1 << 6 ) +#define GP3OEN_OEN6_IN (0x0 << 6 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ +#define GP3OEN_OEN6_OUT (0x1 << 6 ) /* OUT. Enables the output on corresponding port pin. */ + +/* GP3OEN[OEN5] - Port pin direction. */ +#define GP3OEN_OEN5_BBA (*(volatile unsigned long *) 0x420C1294) +#define GP3OEN_OEN5_MSK (0x1 << 5 ) +#define GP3OEN_OEN5 (0x1 << 5 ) +#define GP3OEN_OEN5_IN (0x0 << 5 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ +#define GP3OEN_OEN5_OUT (0x1 << 5 ) /* OUT. Enables the output on corresponding port pin. */ + +/* GP3OEN[OEN4] - Port pin direction. */ +#define GP3OEN_OEN4_BBA (*(volatile unsigned long *) 0x420C1290) +#define GP3OEN_OEN4_MSK (0x1 << 4 ) +#define GP3OEN_OEN4 (0x1 << 4 ) +#define GP3OEN_OEN4_IN (0x0 << 4 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ +#define GP3OEN_OEN4_OUT (0x1 << 4 ) /* OUT. Enables the output on corresponding port pin. */ + +/* GP3OEN[OEN3] - Port pin direction. */ +#define GP3OEN_OEN3_BBA (*(volatile unsigned long *) 0x420C128C) +#define GP3OEN_OEN3_MSK (0x1 << 3 ) +#define GP3OEN_OEN3 (0x1 << 3 ) +#define GP3OEN_OEN3_IN (0x0 << 3 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ +#define GP3OEN_OEN3_OUT (0x1 << 3 ) /* OUT. Enables the output on corresponding port pin. */ + +/* GP3OEN[OEN2] - Port pin direction. */ +#define GP3OEN_OEN2_BBA (*(volatile unsigned long *) 0x420C1288) +#define GP3OEN_OEN2_MSK (0x1 << 2 ) +#define GP3OEN_OEN2 (0x1 << 2 ) +#define GP3OEN_OEN2_IN (0x0 << 2 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ +#define GP3OEN_OEN2_OUT (0x1 << 2 ) /* OUT. Enables the output on corresponding port pin. */ + +/* GP3OEN[OEN1] - Port pin direction. */ +#define GP3OEN_OEN1_BBA (*(volatile unsigned long *) 0x420C1284) +#define GP3OEN_OEN1_MSK (0x1 << 1 ) +#define GP3OEN_OEN1 (0x1 << 1 ) +#define GP3OEN_OEN1_IN (0x0 << 1 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ +#define GP3OEN_OEN1_OUT (0x1 << 1 ) /* OUT. Enables the output on corresponding port pin. */ + +/* GP3OEN[OEN0] - Port pin direction. */ +#define GP3OEN_OEN0_BBA (*(volatile unsigned long *) 0x420C1280) +#define GP3OEN_OEN0_MSK (0x1 << 0 ) +#define GP3OEN_OEN0 (0x1 << 0 ) +#define GP3OEN_OEN0_IN (0x0 << 0 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ +#define GP3OEN_OEN0_OUT (0x1 << 0 ) /* OUT. Enables the output on corresponding port pin. */ + +/* Reset Value for GP3PUL*/ +#define GP3PUL_RVAL 0xFF + +/* GP3PUL[PUL7] - Pull Up Enable for port pin. */ +#define GP3PUL_PUL7_BBA (*(volatile unsigned long *) 0x420C131C) +#define GP3PUL_PUL7_MSK (0x1 << 7 ) +#define GP3PUL_PUL7 (0x1 << 7 ) +#define GP3PUL_PUL7_DIS (0x0 << 7 ) /* DIS. Disables the internal pull up on corresponding port pin. */ +#define GP3PUL_PUL7_EN (0x1 << 7 ) /* EN. Enables the internal pull up on corresponding port pin. */ + +/* GP3PUL[PUL6] - Pull Up Enable for port pin. */ +#define GP3PUL_PUL6_BBA (*(volatile unsigned long *) 0x420C1318) +#define GP3PUL_PUL6_MSK (0x1 << 6 ) +#define GP3PUL_PUL6 (0x1 << 6 ) +#define GP3PUL_PUL6_DIS (0x0 << 6 ) /* DIS. Disables the internal pull up on corresponding port pin. */ +#define GP3PUL_PUL6_EN (0x1 << 6 ) /* EN. Enables the internal pull up on corresponding port pin. */ + +/* GP3PUL[PUL5] - Pull Up Enable for port pin. */ +#define GP3PUL_PUL5_BBA (*(volatile unsigned long *) 0x420C1314) +#define GP3PUL_PUL5_MSK (0x1 << 5 ) +#define GP3PUL_PUL5 (0x1 << 5 ) +#define GP3PUL_PUL5_DIS (0x0 << 5 ) /* DIS. Disables the internal pull up on corresponding port pin. */ +#define GP3PUL_PUL5_EN (0x1 << 5 ) /* EN. Enables the internal pull up on corresponding port pin. */ + +/* GP3PUL[PUL4] - Pull Up Enable for port pin. */ +#define GP3PUL_PUL4_BBA (*(volatile unsigned long *) 0x420C1310) +#define GP3PUL_PUL4_MSK (0x1 << 4 ) +#define GP3PUL_PUL4 (0x1 << 4 ) +#define GP3PUL_PUL4_DIS (0x0 << 4 ) /* DIS. Disables the internal pull up on corresponding port pin. */ +#define GP3PUL_PUL4_EN (0x1 << 4 ) /* EN. Enables the internal pull up on corresponding port pin. */ + +/* GP3PUL[PUL3] - Pull Up Enable for port pin. */ +#define GP3PUL_PUL3_BBA (*(volatile unsigned long *) 0x420C130C) +#define GP3PUL_PUL3_MSK (0x1 << 3 ) +#define GP3PUL_PUL3 (0x1 << 3 ) +#define GP3PUL_PUL3_DIS (0x0 << 3 ) /* DIS. Disables the internal pull up on corresponding port pin. */ +#define GP3PUL_PUL3_EN (0x1 << 3 ) /* EN. Enables the internal pull up oncorresponding port pin. */ + +/* GP3PUL[PUL2] - Pull Up Enable for port pin. */ +#define GP3PUL_PUL2_BBA (*(volatile unsigned long *) 0x420C1308) +#define GP3PUL_PUL2_MSK (0x1 << 2 ) +#define GP3PUL_PUL2 (0x1 << 2 ) +#define GP3PUL_PUL2_DIS (0x0 << 2 ) /* DIS. Disables the internal pull up on corresponding port pin. */ +#define GP3PUL_PUL2_EN (0x1 << 2 ) /* EN. Enables the internal pull up on corresponding port pin. */ + +/* GP3PUL[PUL1] - Pull Up Enable for port pin. */ +#define GP3PUL_PUL1_BBA (*(volatile unsigned long *) 0x420C1304) +#define GP3PUL_PUL1_MSK (0x1 << 1 ) +#define GP3PUL_PUL1 (0x1 << 1 ) +#define GP3PUL_PUL1_DIS (0x0 << 1 ) /* DIS. Disables the internal pull up on corresponding port pin. */ +#define GP3PUL_PUL1_EN (0x1 << 1 ) /* EN. Enables the internal pull up on corresponding port pin. */ + +/* GP3PUL[PUL0] - Pull Up Enable for port pin. */ +#define GP3PUL_PUL0_BBA (*(volatile unsigned long *) 0x420C1300) +#define GP3PUL_PUL0_MSK (0x1 << 0 ) +#define GP3PUL_PUL0 (0x1 << 0 ) +#define GP3PUL_PUL0_DIS (0x0 << 0 ) /* DIS. Disables the internal pull up on corresponding port pin. */ +#define GP3PUL_PUL0_EN (0x1 << 0 ) /* EN. Enables the internal pull up on corresponding port pin. */ + +/* Reset Value for GP3OCE*/ +#define GP3OCE_RVAL 0x0 + +/* GP3OCE[OCE7] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ +#define GP3OCE_OCE7_BBA (*(volatile unsigned long *) 0x420C139C) +#define GP3OCE_OCE7_MSK (0x1 << 7 ) +#define GP3OCE_OCE7 (0x1 << 7 ) +#define GP3OCE_OCE7_DIS (0x0 << 7 ) /* DIS */ +#define GP3OCE_OCE7_EN (0x1 << 7 ) /* EN */ + +/* GP3OCE[OCE6] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ +#define GP3OCE_OCE6_BBA (*(volatile unsigned long *) 0x420C1398) +#define GP3OCE_OCE6_MSK (0x1 << 6 ) +#define GP3OCE_OCE6 (0x1 << 6 ) +#define GP3OCE_OCE6_DIS (0x0 << 6 ) /* DIS */ +#define GP3OCE_OCE6_EN (0x1 << 6 ) /* EN */ + +/* GP3OCE[OCE5] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ +#define GP3OCE_OCE5_BBA (*(volatile unsigned long *) 0x420C1394) +#define GP3OCE_OCE5_MSK (0x1 << 5 ) +#define GP3OCE_OCE5 (0x1 << 5 ) +#define GP3OCE_OCE5_DIS (0x0 << 5 ) /* DIS */ +#define GP3OCE_OCE5_EN (0x1 << 5 ) /* EN */ + +/* GP3OCE[OCE4] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ +#define GP3OCE_OCE4_BBA (*(volatile unsigned long *) 0x420C1390) +#define GP3OCE_OCE4_MSK (0x1 << 4 ) +#define GP3OCE_OCE4 (0x1 << 4 ) +#define GP3OCE_OCE4_DIS (0x0 << 4 ) /* DIS */ +#define GP3OCE_OCE4_EN (0x1 << 4 ) /* EN */ + +/* GP3OCE[OCE3] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ +#define GP3OCE_OCE3_BBA (*(volatile unsigned long *) 0x420C138C) +#define GP3OCE_OCE3_MSK (0x1 << 3 ) +#define GP3OCE_OCE3 (0x1 << 3 ) +#define GP3OCE_OCE3_DIS (0x0 << 3 ) /* DIS */ +#define GP3OCE_OCE3_EN (0x1 << 3 ) /* EN */ + +/* GP3OCE[OCE2] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ +#define GP3OCE_OCE2_BBA (*(volatile unsigned long *) 0x420C1388) +#define GP3OCE_OCE2_MSK (0x1 << 2 ) +#define GP3OCE_OCE2 (0x1 << 2 ) +#define GP3OCE_OCE2_DIS (0x0 << 2 ) /* DIS */ +#define GP3OCE_OCE2_EN (0x1 << 2 ) /* EN */ + +/* GP3OCE[OCE1] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ +#define GP3OCE_OCE1_BBA (*(volatile unsigned long *) 0x420C1384) +#define GP3OCE_OCE1_MSK (0x1 << 1 ) +#define GP3OCE_OCE1 (0x1 << 1 ) +#define GP3OCE_OCE1_DIS (0x0 << 1 ) /* DIS */ +#define GP3OCE_OCE1_EN (0x1 << 1 ) /* EN */ + +/* GP3OCE[OCE0] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ +#define GP3OCE_OCE0_BBA (*(volatile unsigned long *) 0x420C1380) +#define GP3OCE_OCE0_MSK (0x1 << 0 ) +#define GP3OCE_OCE0 (0x1 << 0 ) +#define GP3OCE_OCE0_DIS (0x0 << 0 ) /* DIS */ +#define GP3OCE_OCE0_EN (0x1 << 0 ) /* EN */ + +/* Reset Value for GP3IN*/ +#define GP3IN_RVAL 0xFF + +/* GP3IN[IN7] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ +#define GP3IN_IN7_BBA (*(volatile unsigned long *) 0x420C149C) +#define GP3IN_IN7_MSK (0x1 << 7 ) +#define GP3IN_IN7 (0x1 << 7 ) +#define GP3IN_IN7_LOW (0x0 << 7 ) /* LOW */ +#define GP3IN_IN7_HIGH (0x1 << 7 ) /* HIGH */ + +/* GP3IN[IN6] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ +#define GP3IN_IN6_BBA (*(volatile unsigned long *) 0x420C1498) +#define GP3IN_IN6_MSK (0x1 << 6 ) +#define GP3IN_IN6 (0x1 << 6 ) +#define GP3IN_IN6_LOW (0x0 << 6 ) /* LOW */ +#define GP3IN_IN6_HIGH (0x1 << 6 ) /* HIGH */ + +/* GP3IN[IN5] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ +#define GP3IN_IN5_BBA (*(volatile unsigned long *) 0x420C1494) +#define GP3IN_IN5_MSK (0x1 << 5 ) +#define GP3IN_IN5 (0x1 << 5 ) +#define GP3IN_IN5_LOW (0x0 << 5 ) /* LOW */ +#define GP3IN_IN5_HIGH (0x1 << 5 ) /* HIGH */ + +/* GP3IN[IN4] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ +#define GP3IN_IN4_BBA (*(volatile unsigned long *) 0x420C1490) +#define GP3IN_IN4_MSK (0x1 << 4 ) +#define GP3IN_IN4 (0x1 << 4 ) +#define GP3IN_IN4_LOW (0x0 << 4 ) /* LOW */ +#define GP3IN_IN4_HIGH (0x1 << 4 ) /* HIGH */ + +/* GP3IN[IN3] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ +#define GP3IN_IN3_BBA (*(volatile unsigned long *) 0x420C148C) +#define GP3IN_IN3_MSK (0x1 << 3 ) +#define GP3IN_IN3 (0x1 << 3 ) +#define GP3IN_IN3_LOW (0x0 << 3 ) /* LOW */ +#define GP3IN_IN3_HIGH (0x1 << 3 ) /* HIGH */ + +/* GP3IN[IN2] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ +#define GP3IN_IN2_BBA (*(volatile unsigned long *) 0x420C1488) +#define GP3IN_IN2_MSK (0x1 << 2 ) +#define GP3IN_IN2 (0x1 << 2 ) +#define GP3IN_IN2_LOW (0x0 << 2 ) /* LOW */ +#define GP3IN_IN2_HIGH (0x1 << 2 ) /* HIGH */ + +/* GP3IN[IN1] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ +#define GP3IN_IN1_BBA (*(volatile unsigned long *) 0x420C1484) +#define GP3IN_IN1_MSK (0x1 << 1 ) +#define GP3IN_IN1 (0x1 << 1 ) +#define GP3IN_IN1_LOW (0x0 << 1 ) /* LOW */ +#define GP3IN_IN1_HIGH (0x1 << 1 ) /* HIGH */ + +/* GP3IN[IN0] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ +#define GP3IN_IN0_BBA (*(volatile unsigned long *) 0x420C1480) +#define GP3IN_IN0_MSK (0x1 << 0 ) +#define GP3IN_IN0 (0x1 << 0 ) +#define GP3IN_IN0_LOW (0x0 << 0 ) /* LOW */ +#define GP3IN_IN0_HIGH (0x1 << 0 ) /* HIGH */ + +/* Reset Value for GP3OUT*/ +#define GP3OUT_RVAL 0x0 + +/* GP3OUT[OUT7] - Output for port pin. */ +#define GP3OUT_OUT7_BBA (*(volatile unsigned long *) 0x420C151C) +#define GP3OUT_OUT7_MSK (0x1 << 7 ) +#define GP3OUT_OUT7 (0x1 << 7 ) +#define GP3OUT_OUT7_LOW (0x0 << 7 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ +#define GP3OUT_OUT7_HIGH (0x1 << 7 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ + +/* GP3OUT[OUT6] - Output for port pin. */ +#define GP3OUT_OUT6_BBA (*(volatile unsigned long *) 0x420C1518) +#define GP3OUT_OUT6_MSK (0x1 << 6 ) +#define GP3OUT_OUT6 (0x1 << 6 ) +#define GP3OUT_OUT6_LOW (0x0 << 6 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ +#define GP3OUT_OUT6_HIGH (0x1 << 6 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ + +/* GP3OUT[OUT5] - Output for port pin. */ +#define GP3OUT_OUT5_BBA (*(volatile unsigned long *) 0x420C1514) +#define GP3OUT_OUT5_MSK (0x1 << 5 ) +#define GP3OUT_OUT5 (0x1 << 5 ) +#define GP3OUT_OUT5_LOW (0x0 << 5 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ +#define GP3OUT_OUT5_HIGH (0x1 << 5 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ + +/* GP3OUT[OUT4] - Output for port pin. */ +#define GP3OUT_OUT4_BBA (*(volatile unsigned long *) 0x420C1510) +#define GP3OUT_OUT4_MSK (0x1 << 4 ) +#define GP3OUT_OUT4 (0x1 << 4 ) +#define GP3OUT_OUT4_LOW (0x0 << 4 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ +#define GP3OUT_OUT4_HIGH (0x1 << 4 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ + +/* GP3OUT[OUT3] - Output for port pin. */ +#define GP3OUT_OUT3_BBA (*(volatile unsigned long *) 0x420C150C) +#define GP3OUT_OUT3_MSK (0x1 << 3 ) +#define GP3OUT_OUT3 (0x1 << 3 ) +#define GP3OUT_OUT3_LOW (0x0 << 3 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ +#define GP3OUT_OUT3_HIGH (0x1 << 3 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ + +/* GP3OUT[OUT2] - Output for port pin. */ +#define GP3OUT_OUT2_BBA (*(volatile unsigned long *) 0x420C1508) +#define GP3OUT_OUT2_MSK (0x1 << 2 ) +#define GP3OUT_OUT2 (0x1 << 2 ) +#define GP3OUT_OUT2_LOW (0x0 << 2 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ +#define GP3OUT_OUT2_HIGH (0x1 << 2 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ + +/* GP3OUT[OUT1] - Output for port pin. */ +#define GP3OUT_OUT1_BBA (*(volatile unsigned long *) 0x420C1504) +#define GP3OUT_OUT1_MSK (0x1 << 1 ) +#define GP3OUT_OUT1 (0x1 << 1 ) +#define GP3OUT_OUT1_LOW (0x0 << 1 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ +#define GP3OUT_OUT1_HIGH (0x1 << 1 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ + +/* GP3OUT[OUT0] - Output for port pin. */ +#define GP3OUT_OUT0_BBA (*(volatile unsigned long *) 0x420C1500) +#define GP3OUT_OUT0_MSK (0x1 << 0 ) +#define GP3OUT_OUT0 (0x1 << 0 ) +#define GP3OUT_OUT0_LOW (0x0 << 0 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ +#define GP3OUT_OUT0_HIGH (0x1 << 0 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ + +/* Reset Value for GP3SET*/ +#define GP3SET_RVAL 0x0 + +/* GP3SET[SET7] - Set output high for corresponding port pin. */ +#define GP3SET_SET7_BBA (*(volatile unsigned long *) 0x420C159C) +#define GP3SET_SET7_MSK (0x1 << 7 ) +#define GP3SET_SET7 (0x1 << 7 ) +#define GP3SET_SET7_SET (0x1 << 7 ) /* SET. Set by user code to drive the corresponding GPIO high. */ + +/* GP3SET[SET6] - Set output high for corresponding port pin. */ +#define GP3SET_SET6_BBA (*(volatile unsigned long *) 0x420C1598) +#define GP3SET_SET6_MSK (0x1 << 6 ) +#define GP3SET_SET6 (0x1 << 6 ) +#define GP3SET_SET6_SET (0x1 << 6 ) /* SET. Set by user code to drive the corresponding GPIO high. */ + +/* GP3SET[SET5] - Set output high for corresponding port pin. */ +#define GP3SET_SET5_BBA (*(volatile unsigned long *) 0x420C1594) +#define GP3SET_SET5_MSK (0x1 << 5 ) +#define GP3SET_SET5 (0x1 << 5 ) +#define GP3SET_SET5_SET (0x1 << 5 ) /* SET. Set by user code to drive the corresponding GPIO high. */ + +/* GP3SET[SET4] - Set output high for corresponding port pin. */ +#define GP3SET_SET4_BBA (*(volatile unsigned long *) 0x420C1590) +#define GP3SET_SET4_MSK (0x1 << 4 ) +#define GP3SET_SET4 (0x1 << 4 ) +#define GP3SET_SET4_SET (0x1 << 4 ) /* SET. Set by user code to drive the corresponding GPIO high. */ + +/* GP3SET[SET3] - Set output high for corresponding port pin. */ +#define GP3SET_SET3_BBA (*(volatile unsigned long *) 0x420C158C) +#define GP3SET_SET3_MSK (0x1 << 3 ) +#define GP3SET_SET3 (0x1 << 3 ) +#define GP3SET_SET3_SET (0x1 << 3 ) /* SET. Set by user code to drive the corresponding GPIO high. */ + +/* GP3SET[SET2] - Set output high for corresponding port pin. */ +#define GP3SET_SET2_BBA (*(volatile unsigned long *) 0x420C1588) +#define GP3SET_SET2_MSK (0x1 << 2 ) +#define GP3SET_SET2 (0x1 << 2 ) +#define GP3SET_SET2_SET (0x1 << 2 ) /* SET. Set by user code to drive the corresponding GPIO high. */ + +/* GP3SET[SET1] - Set output high for corresponding port pin. */ +#define GP3SET_SET1_BBA (*(volatile unsigned long *) 0x420C1584) +#define GP3SET_SET1_MSK (0x1 << 1 ) +#define GP3SET_SET1 (0x1 << 1 ) +#define GP3SET_SET1_SET (0x1 << 1 ) /* SET. Set by user code to drive the corresponding GPIO high. */ + +/* GP3SET[SET0] - Set output high for corresponding port pin. */ +#define GP3SET_SET0_BBA (*(volatile unsigned long *) 0x420C1580) +#define GP3SET_SET0_MSK (0x1 << 0 ) +#define GP3SET_SET0 (0x1 << 0 ) +#define GP3SET_SET0_SET (0x1 << 0 ) /* SET. Set by user code to drive the corresponding GPIO high. */ + +/* Reset Value for GP3CLR*/ +#define GP3CLR_RVAL 0x0 + +/* GP3CLR[CLR7] - Set by user code to drive the corresponding GPIO low. */ +#define GP3CLR_CLR7_BBA (*(volatile unsigned long *) 0x420C161C) +#define GP3CLR_CLR7_MSK (0x1 << 7 ) +#define GP3CLR_CLR7 (0x1 << 7 ) +#define GP3CLR_CLR7_CLR (0x1 << 7 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ + +/* GP3CLR[CLR6] - Set by user code to drive the corresponding GPIO low. */ +#define GP3CLR_CLR6_BBA (*(volatile unsigned long *) 0x420C1618) +#define GP3CLR_CLR6_MSK (0x1 << 6 ) +#define GP3CLR_CLR6 (0x1 << 6 ) +#define GP3CLR_CLR6_CLR (0x1 << 6 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ + +/* GP3CLR[CLR5] - Set by user code to drive the corresponding GPIO low. */ +#define GP3CLR_CLR5_BBA (*(volatile unsigned long *) 0x420C1614) +#define GP3CLR_CLR5_MSK (0x1 << 5 ) +#define GP3CLR_CLR5 (0x1 << 5 ) +#define GP3CLR_CLR5_CLR (0x1 << 5 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ + +/* GP3CLR[CLR4] - Set by user code to drive the corresponding GPIO low. */ +#define GP3CLR_CLR4_BBA (*(volatile unsigned long *) 0x420C1610) +#define GP3CLR_CLR4_MSK (0x1 << 4 ) +#define GP3CLR_CLR4 (0x1 << 4 ) +#define GP3CLR_CLR4_CLR (0x1 << 4 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ + +/* GP3CLR[CLR3] - Set by user code to drive the corresponding GPIO low. */ +#define GP3CLR_CLR3_BBA (*(volatile unsigned long *) 0x420C160C) +#define GP3CLR_CLR3_MSK (0x1 << 3 ) +#define GP3CLR_CLR3 (0x1 << 3 ) +#define GP3CLR_CLR3_CLR (0x1 << 3 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ + +/* GP3CLR[CLR2] - Set by user code to drive the corresponding GPIO low. */ +#define GP3CLR_CLR2_BBA (*(volatile unsigned long *) 0x420C1608) +#define GP3CLR_CLR2_MSK (0x1 << 2 ) +#define GP3CLR_CLR2 (0x1 << 2 ) +#define GP3CLR_CLR2_CLR (0x1 << 2 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ + +/* GP3CLR[CLR1] - Set by user code to drive the corresponding GPIO low. */ +#define GP3CLR_CLR1_BBA (*(volatile unsigned long *) 0x420C1604) +#define GP3CLR_CLR1_MSK (0x1 << 1 ) +#define GP3CLR_CLR1 (0x1 << 1 ) +#define GP3CLR_CLR1_CLR (0x1 << 1 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ + +/* GP3CLR[CLR0] - Set by user code to drive the corresponding GPIO low. */ +#define GP3CLR_CLR0_BBA (*(volatile unsigned long *) 0x420C1600) +#define GP3CLR_CLR0_MSK (0x1 << 0 ) +#define GP3CLR_CLR0 (0x1 << 0 ) +#define GP3CLR_CLR0_CLR (0x1 << 0 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ + +/* Reset Value for GP3TGL*/ +#define GP3TGL_RVAL 0x0 + +/* GP3TGL[TGL7] - Toggle for corresponding port pin. */ +#define GP3TGL_TGL7_BBA (*(volatile unsigned long *) 0x420C169C) +#define GP3TGL_TGL7_MSK (0x1 << 7 ) +#define GP3TGL_TGL7 (0x1 << 7 ) +#define GP3TGL_TGL7_TGL (0x1 << 7 ) /* TGL. Set by user code to invert the corresponding GPIO. */ + +/* GP3TGL[TGL6] - Toggle for corresponding port pin. */ +#define GP3TGL_TGL6_BBA (*(volatile unsigned long *) 0x420C1698) +#define GP3TGL_TGL6_MSK (0x1 << 6 ) +#define GP3TGL_TGL6 (0x1 << 6 ) +#define GP3TGL_TGL6_TGL (0x1 << 6 ) /* TGL. Set by user code to invert the corresponding GPIO. */ + +/* GP3TGL[TGL5] - Toggle for corresponding port pin. */ +#define GP3TGL_TGL5_BBA (*(volatile unsigned long *) 0x420C1694) +#define GP3TGL_TGL5_MSK (0x1 << 5 ) +#define GP3TGL_TGL5 (0x1 << 5 ) +#define GP3TGL_TGL5_TGL (0x1 << 5 ) /* TGL. Set by user code to invert the corresponding GPIO. */ + +/* GP3TGL[TGL4] - Toggle for corresponding port pin. */ +#define GP3TGL_TGL4_BBA (*(volatile unsigned long *) 0x420C1690) +#define GP3TGL_TGL4_MSK (0x1 << 4 ) +#define GP3TGL_TGL4 (0x1 << 4 ) +#define GP3TGL_TGL4_TGL (0x1 << 4 ) /* TGL. Set by user code to invert the corresponding GPIO. */ + +/* GP3TGL[TGL3] - Toggle for corresponding port pin. */ +#define GP3TGL_TGL3_BBA (*(volatile unsigned long *) 0x420C168C) +#define GP3TGL_TGL3_MSK (0x1 << 3 ) +#define GP3TGL_TGL3 (0x1 << 3 ) +#define GP3TGL_TGL3_TGL (0x1 << 3 ) /* TGL. Set by user code to invert the corresponding GPIO. */ + +/* GP3TGL[TGL2] - Toggle for corresponding port pin. */ +#define GP3TGL_TGL2_BBA (*(volatile unsigned long *) 0x420C1688) +#define GP3TGL_TGL2_MSK (0x1 << 2 ) +#define GP3TGL_TGL2 (0x1 << 2 ) +#define GP3TGL_TGL2_TGL (0x1 << 2 ) /* TGL. Set by user code to invert the corresponding GPIO. */ + +/* GP3TGL[TGL1] - Toggle for corresponding port pin. */ +#define GP3TGL_TGL1_BBA (*(volatile unsigned long *) 0x420C1684) +#define GP3TGL_TGL1_MSK (0x1 << 1 ) +#define GP3TGL_TGL1 (0x1 << 1 ) +#define GP3TGL_TGL1_TGL (0x1 << 1 ) /* TGL. Set by user code to invert the corresponding GPIO. */ + +/* GP3TGL[TGL0] - Toggle for corresponding port pin. */ +#define GP3TGL_TGL0_BBA (*(volatile unsigned long *) 0x420C1680) +#define GP3TGL_TGL0_MSK (0x1 << 0 ) +#define GP3TGL_TGL0 (0x1 << 0 ) +#define GP3TGL_TGL0_TGL (0x1 << 0 ) /* TGL. Set by user code to invert the corresponding GPIO. */ +#if (__NO_MMR_STRUCTS__==1) + +#define GP4CON (*(volatile unsigned short int *) 0x400060C0) +#define GP4OEN (*(volatile unsigned char *) 0x400060C4) +#define GP4PUL (*(volatile unsigned char *) 0x400060C8) +#define GP4OCE (*(volatile unsigned char *) 0x400060CC) +#define GP4IN (*(volatile unsigned char *) 0x400060D4) +#define GP4OUT (*(volatile unsigned char *) 0x400060D8) +#define GP4SET (*(volatile unsigned char *) 0x400060DC) +#define GP4CLR (*(volatile unsigned char *) 0x400060E0) +#define GP4TGL (*(volatile unsigned char *) 0x400060E4) +#endif // (__NO_MMR_STRUCTS__==1) + +/* Reset Value for GP4CON*/ +#define GP4CON_RVAL 0x0 + +/* GP4CON[CON7] - Configuration bits for P4.7 */ +#define GP4CON_CON7_MSK (0x3 << 14 ) +#define GP4CON_CON7_GPIO (0x1 << 14 ) /* GPIO */ +#define GP4CON_CON7_PWM7 (0x2 << 14 ) /* PWM7 */ + +/* GP4CON[CON6] - Configuration bits for P4.6 */ +#define GP4CON_CON6_MSK (0x3 << 12 ) +#define GP4CON_CON6_GPIO (0x1 << 12 ) /* GPIO */ +#define GP4CON_CON6_PWM6 (0x2 << 12 ) /* PWM6 */ + +/* GP4CON[CON5] - Configuration bits for P4.5 */ +#define GP4CON_CON5_MSK (0x3 << 10 ) +#define GP4CON_CON5_GPIO (0x1 << 10 ) /* GPIO */ +#define GP4CON_CON5_PWM5 (0x2 << 10 ) /* PWM5 */ + +/* GP4CON[CON4] - Configuration bits for P4.4 */ +#define GP4CON_CON4_MSK (0x3 << 8 ) +#define GP4CON_CON4_GPIO (0x1 << 8 ) /* GPIO */ +#define GP4CON_CON4_PWM4 (0x2 << 8 ) /* PWM4 */ + +/* GP4CON[CON3] - Configuration bits for P4.3 */ +#define GP4CON_CON3_MSK (0x3 << 6 ) +#define GP4CON_CON3_GPIO (0x1 << 6 ) /* GPIO */ +#define GP4CON_CON3_PWM3 (0x2 << 6 ) /* PWM3 */ + +/* GP4CON[CON2] - Configuration bits for P4.2 */ +#define GP4CON_CON2_MSK (0x3 << 4 ) +#define GP4CON_CON2_GPIO (0x1 << 4 ) /* GPIO */ +#define GP4CON_CON2_PWM2 (0x2 << 4 ) /* PWM2 */ +#define GP4CON_CON2_SPI0CS (0x3 << 4 ) /* SPI0CS */ + +/* GP4CON[CON1] - Configuration bits for P4.1 */ +#define GP4CON_CON1_MSK (0x3 << 2 ) +#define GP4CON_CON1_GPIO (0x1 << 2 ) /* GPIO */ +#define GP4CON_CON1_PWM1 (0x2 << 2 ) /* PWM1 */ + +/* GP4CON[CON0] - Configuration bits for P4.0 */ +#define GP4CON_CON0_MSK (0x3 << 0 ) +#define GP4CON_CON0_GPIO (0x1 << 0 ) /* GPIO */ +#define GP4CON_CON0_PWM0 (0x2 << 0 ) /* PWM0 */ + +/* Reset Value for GP4OEN*/ +#define GP4OEN_RVAL 0x0 + +/* GP4OEN[OEN7] - Port pin direction. */ +#define GP4OEN_OEN7_BBA (*(volatile unsigned long *) 0x420C189C) +#define GP4OEN_OEN7_MSK (0x1 << 7 ) +#define GP4OEN_OEN7 (0x1 << 7 ) +#define GP4OEN_OEN7_IN (0x0 << 7 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ +#define GP4OEN_OEN7_OUT (0x1 << 7 ) /* OUT. Enables the output on corresponding port pin. */ + +/* GP4OEN[OEN6] - Port pin direction. */ +#define GP4OEN_OEN6_BBA (*(volatile unsigned long *) 0x420C1898) +#define GP4OEN_OEN6_MSK (0x1 << 6 ) +#define GP4OEN_OEN6 (0x1 << 6 ) +#define GP4OEN_OEN6_IN (0x0 << 6 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ +#define GP4OEN_OEN6_OUT (0x1 << 6 ) /* OUT. Enables the output on corresponding port pin. */ + +/* GP4OEN[OEN5] - Port pin direction. */ +#define GP4OEN_OEN5_BBA (*(volatile unsigned long *) 0x420C1894) +#define GP4OEN_OEN5_MSK (0x1 << 5 ) +#define GP4OEN_OEN5 (0x1 << 5 ) +#define GP4OEN_OEN5_IN (0x0 << 5 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ +#define GP4OEN_OEN5_OUT (0x1 << 5 ) /* OUT. Enables the output on corresponding port pin. */ + +/* GP4OEN[OEN4] - Port pin direction. */ +#define GP4OEN_OEN4_BBA (*(volatile unsigned long *) 0x420C1890) +#define GP4OEN_OEN4_MSK (0x1 << 4 ) +#define GP4OEN_OEN4 (0x1 << 4 ) +#define GP4OEN_OEN4_IN (0x0 << 4 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ +#define GP4OEN_OEN4_OUT (0x1 << 4 ) /* OUT. Enables the output on corresponding port pin. */ + +/* GP4OEN[OEN3] - Port pin direction. */ +#define GP4OEN_OEN3_BBA (*(volatile unsigned long *) 0x420C188C) +#define GP4OEN_OEN3_MSK (0x1 << 3 ) +#define GP4OEN_OEN3 (0x1 << 3 ) +#define GP4OEN_OEN3_IN (0x0 << 3 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ +#define GP4OEN_OEN3_OUT (0x1 << 3 ) /* OUT. Enables the output on corresponding port pin. */ + +/* GP4OEN[OEN2] - Port pin direction. */ +#define GP4OEN_OEN2_BBA (*(volatile unsigned long *) 0x420C1888) +#define GP4OEN_OEN2_MSK (0x1 << 2 ) +#define GP4OEN_OEN2 (0x1 << 2 ) +#define GP4OEN_OEN2_IN (0x0 << 2 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ +#define GP4OEN_OEN2_OUT (0x1 << 2 ) /* OUT. Enables the output on corresponding port pin. */ + +/* GP4OEN[OEN1] - Port pin direction. */ +#define GP4OEN_OEN1_BBA (*(volatile unsigned long *) 0x420C1884) +#define GP4OEN_OEN1_MSK (0x1 << 1 ) +#define GP4OEN_OEN1 (0x1 << 1 ) +#define GP4OEN_OEN1_IN (0x0 << 1 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ +#define GP4OEN_OEN1_OUT (0x1 << 1 ) /* OUT. Enables the output on corresponding port pin. */ + +/* GP4OEN[OEN0] - Port pin direction. */ +#define GP4OEN_OEN0_BBA (*(volatile unsigned long *) 0x420C1880) +#define GP4OEN_OEN0_MSK (0x1 << 0 ) +#define GP4OEN_OEN0 (0x1 << 0 ) +#define GP4OEN_OEN0_IN (0x0 << 0 ) /* IN. Configures pin as an input. Disables the output on corresponding port pin. */ +#define GP4OEN_OEN0_OUT (0x1 << 0 ) /* OUT. Enables the output on corresponding port pin. */ + +/* Reset Value for GP4PUL*/ +#define GP4PUL_RVAL 0xFF + +/* GP4PUL[PUL7] - Pull Up Enable for port pin. */ +#define GP4PUL_PUL7_BBA (*(volatile unsigned long *) 0x420C191C) +#define GP4PUL_PUL7_MSK (0x1 << 7 ) +#define GP4PUL_PUL7 (0x1 << 7 ) +#define GP4PUL_PUL7_DIS (0x0 << 7 ) /* DIS. Disables the internal pull up on corresponding port pin. */ +#define GP4PUL_PUL7_EN (0x1 << 7 ) /* EN. Enables the internal pull up on corresponding port pin. */ + +/* GP4PUL[PUL6] - Pull Up Enable for port pin. */ +#define GP4PUL_PUL6_BBA (*(volatile unsigned long *) 0x420C1918) +#define GP4PUL_PUL6_MSK (0x1 << 6 ) +#define GP4PUL_PUL6 (0x1 << 6 ) +#define GP4PUL_PUL6_DIS (0x0 << 6 ) /* DIS. Disables the internal pull up on corresponding port pin. */ +#define GP4PUL_PUL6_EN (0x1 << 6 ) /* EN. Enables the internal pull up on corresponding port pin. */ + +/* GP4PUL[PUL5] - Pull Up Enable for port pin. */ +#define GP4PUL_PUL5_BBA (*(volatile unsigned long *) 0x420C1914) +#define GP4PUL_PUL5_MSK (0x1 << 5 ) +#define GP4PUL_PUL5 (0x1 << 5 ) +#define GP4PUL_PUL5_DIS (0x0 << 5 ) /* DIS. Disables the internal pull up on corresponding port pin. */ +#define GP4PUL_PUL5_EN (0x1 << 5 ) /* EN. Enables the internal pull up on corresponding port pin. */ + +/* GP4PUL[PUL4] - Pull Up Enable for port pin. */ +#define GP4PUL_PUL4_BBA (*(volatile unsigned long *) 0x420C1910) +#define GP4PUL_PUL4_MSK (0x1 << 4 ) +#define GP4PUL_PUL4 (0x1 << 4 ) +#define GP4PUL_PUL4_DIS (0x0 << 4 ) /* DIS. Disables the internal pull up on corresponding port pin. */ +#define GP4PUL_PUL4_EN (0x1 << 4 ) /* EN. Enables the internal pull up on corresponding port pin. */ + +/* GP4PUL[PUL3] - Pull Up Enable for port pin. */ +#define GP4PUL_PUL3_BBA (*(volatile unsigned long *) 0x420C190C) +#define GP4PUL_PUL3_MSK (0x1 << 3 ) +#define GP4PUL_PUL3 (0x1 << 3 ) +#define GP4PUL_PUL3_DIS (0x0 << 3 ) /* DIS. Disables the internal pull up on corresponding port pin. */ +#define GP4PUL_PUL3_EN (0x1 << 3 ) /* EN. Enables the internal pull up on corresponding port pin. */ + +/* GP4PUL[PUL2] - Pull Up Enable for port pin. */ +#define GP4PUL_PUL2_BBA (*(volatile unsigned long *) 0x420C1908) +#define GP4PUL_PUL2_MSK (0x1 << 2 ) +#define GP4PUL_PUL2 (0x1 << 2 ) +#define GP4PUL_PUL2_DIS (0x0 << 2 ) /* DIS. Disables the internal pull up on corresponding port pin. */ +#define GP4PUL_PUL2_EN (0x1 << 2 ) /* EN. Enables the internal pull up on corresponding port pin. */ + +/* GP4PUL[PUL1] - Pull Up Enable for port pin. */ +#define GP4PUL_PUL1_BBA (*(volatile unsigned long *) 0x420C1904) +#define GP4PUL_PUL1_MSK (0x1 << 1 ) +#define GP4PUL_PUL1 (0x1 << 1 ) +#define GP4PUL_PUL1_DIS (0x0 << 1 ) /* DIS. Disables the internal pull up on corresponding port pin. */ +#define GP4PUL_PUL1_EN (0x1 << 1 ) /* EN. Enables the internal pull up on corresponding port pin. */ + +/* GP4PUL[PUL0] - Pull Up Enable for port pin. */ +#define GP4PUL_PUL0_BBA (*(volatile unsigned long *) 0x420C1900) +#define GP4PUL_PUL0_MSK (0x1 << 0 ) +#define GP4PUL_PUL0 (0x1 << 0 ) +#define GP4PUL_PUL0_DIS (0x0 << 0 ) /* DIS. Disables the internal pull up on corresponding port pin. */ +#define GP4PUL_PUL0_EN (0x1 << 0 ) /* EN. Enables the internal pull up on corresponding port pin. */ + +/* Reset Value for GP4OCE*/ +#define GP4OCE_RVAL 0x0 + +/* GP4OCE[OCE7] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ +#define GP4OCE_OCE7_BBA (*(volatile unsigned long *) 0x420C199C) +#define GP4OCE_OCE7_MSK (0x1 << 7 ) +#define GP4OCE_OCE7 (0x1 << 7 ) +#define GP4OCE_OCE7_DIS (0x0 << 7 ) /* DIS */ +#define GP4OCE_OCE7_EN (0x1 << 7 ) /* EN */ + +/* GP4OCE[OCE6] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ +#define GP4OCE_OCE6_BBA (*(volatile unsigned long *) 0x420C1998) +#define GP4OCE_OCE6_MSK (0x1 << 6 ) +#define GP4OCE_OCE6 (0x1 << 6 ) +#define GP4OCE_OCE6_DIS (0x0 << 6 ) /* DIS */ +#define GP4OCE_OCE6_EN (0x1 << 6 ) /* EN */ + +/* GP4OCE[OCE5] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ +#define GP4OCE_OCE5_BBA (*(volatile unsigned long *) 0x420C1994) +#define GP4OCE_OCE5_MSK (0x1 << 5 ) +#define GP4OCE_OCE5 (0x1 << 5 ) +#define GP4OCE_OCE5_DIS (0x0 << 5 ) /* DIS */ +#define GP4OCE_OCE5_EN (0x1 << 5 ) /* EN */ + +/* GP4OCE[OCE4] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ +#define GP4OCE_OCE4_BBA (*(volatile unsigned long *) 0x420C1990) +#define GP4OCE_OCE4_MSK (0x1 << 4 ) +#define GP4OCE_OCE4 (0x1 << 4 ) +#define GP4OCE_OCE4_DIS (0x0 << 4 ) /* DIS */ +#define GP4OCE_OCE4_EN (0x1 << 4 ) /* EN */ + +/* GP4OCE[OCE3] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ +#define GP4OCE_OCE3_BBA (*(volatile unsigned long *) 0x420C198C) +#define GP4OCE_OCE3_MSK (0x1 << 3 ) +#define GP4OCE_OCE3 (0x1 << 3 ) +#define GP4OCE_OCE3_DIS (0x0 << 3 ) /* DIS */ +#define GP4OCE_OCE3_EN (0x1 << 3 ) /* EN */ + +/* GP4OCE[OCE2] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ +#define GP4OCE_OCE2_BBA (*(volatile unsigned long *) 0x420C1988) +#define GP4OCE_OCE2_MSK (0x1 << 2 ) +#define GP4OCE_OCE2 (0x1 << 2 ) +#define GP4OCE_OCE2_DIS (0x0 << 2 ) /* DIS */ +#define GP4OCE_OCE2_EN (0x1 << 2 ) /* EN */ + +/* GP4OCE[OCE1] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ +#define GP4OCE_OCE1_BBA (*(volatile unsigned long *) 0x420C1984) +#define GP4OCE_OCE1_MSK (0x1 << 1 ) +#define GP4OCE_OCE1 (0x1 << 1 ) +#define GP4OCE_OCE1_DIS (0x0 << 1 ) /* DIS */ +#define GP4OCE_OCE1_EN (0x1 << 1 ) /* EN */ + +/* GP4OCE[OCE0] - Output enable. Sets the GPIO pads on corresponding port to open circuit mode. */ +#define GP4OCE_OCE0_BBA (*(volatile unsigned long *) 0x420C1980) +#define GP4OCE_OCE0_MSK (0x1 << 0 ) +#define GP4OCE_OCE0 (0x1 << 0 ) +#define GP4OCE_OCE0_DIS (0x0 << 0 ) /* DIS */ +#define GP4OCE_OCE0_EN (0x1 << 0 ) /* EN */ + +/* Reset Value for GP4IN*/ +#define GP4IN_RVAL 0xFF + +/* GP4IN[IN7] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ +#define GP4IN_IN7_BBA (*(volatile unsigned long *) 0x420C1A9C) +#define GP4IN_IN7_MSK (0x1 << 7 ) +#define GP4IN_IN7 (0x1 << 7 ) +#define GP4IN_IN7_LOW (0x0 << 7 ) /* LOW */ +#define GP4IN_IN7_HIGH (0x1 << 7 ) /* HIGH */ + +/* GP4IN[IN6] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ +#define GP4IN_IN6_BBA (*(volatile unsigned long *) 0x420C1A98) +#define GP4IN_IN6_MSK (0x1 << 6 ) +#define GP4IN_IN6 (0x1 << 6 ) +#define GP4IN_IN6_LOW (0x0 << 6 ) /* LOW */ +#define GP4IN_IN6_HIGH (0x1 << 6 ) /* HIGH */ + +/* GP4IN[IN5] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ +#define GP4IN_IN5_BBA (*(volatile unsigned long *) 0x420C1A94) +#define GP4IN_IN5_MSK (0x1 << 5 ) +#define GP4IN_IN5 (0x1 << 5 ) +#define GP4IN_IN5_LOW (0x0 << 5 ) /* LOW */ +#define GP4IN_IN5_HIGH (0x1 << 5 ) /* HIGH */ + +/* GP4IN[IN4] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ +#define GP4IN_IN4_BBA (*(volatile unsigned long *) 0x420C1A90) +#define GP4IN_IN4_MSK (0x1 << 4 ) +#define GP4IN_IN4 (0x1 << 4 ) +#define GP4IN_IN4_LOW (0x0 << 4 ) /* LOW */ +#define GP4IN_IN4_HIGH (0x1 << 4 ) /* HIGH */ + +/* GP4IN[IN3] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ +#define GP4IN_IN3_BBA (*(volatile unsigned long *) 0x420C1A8C) +#define GP4IN_IN3_MSK (0x1 << 3 ) +#define GP4IN_IN3 (0x1 << 3 ) +#define GP4IN_IN3_LOW (0x0 << 3 ) /* LOW */ +#define GP4IN_IN3_HIGH (0x1 << 3 ) /* HIGH */ + +/* GP4IN[IN2] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ +#define GP4IN_IN2_BBA (*(volatile unsigned long *) 0x420C1A88) +#define GP4IN_IN2_MSK (0x1 << 2 ) +#define GP4IN_IN2 (0x1 << 2 ) +#define GP4IN_IN2_LOW (0x0 << 2 ) /* LOW */ +#define GP4IN_IN2_HIGH (0x1 << 2 ) /* HIGH */ + +/* GP4IN[IN1] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ +#define GP4IN_IN1_BBA (*(volatile unsigned long *) 0x420C1A84) +#define GP4IN_IN1_MSK (0x1 << 1 ) +#define GP4IN_IN1 (0x1 << 1 ) +#define GP4IN_IN1_LOW (0x0 << 1 ) /* LOW */ +#define GP4IN_IN1_HIGH (0x1 << 1 ) /* HIGH */ + +/* GP4IN[IN0] - Reflects the level on the corresponding GPIO pins except when in configured in open circuit. */ +#define GP4IN_IN0_BBA (*(volatile unsigned long *) 0x420C1A80) +#define GP4IN_IN0_MSK (0x1 << 0 ) +#define GP4IN_IN0 (0x1 << 0 ) +#define GP4IN_IN0_LOW (0x0 << 0 ) /* LOW */ +#define GP4IN_IN0_HIGH (0x1 << 0 ) /* HIGH */ + +/* Reset Value for GP4OUT*/ +#define GP4OUT_RVAL 0x0 + +/* GP4OUT[OUT7] - Output for port pin. */ +#define GP4OUT_OUT7_BBA (*(volatile unsigned long *) 0x420C1B1C) +#define GP4OUT_OUT7_MSK (0x1 << 7 ) +#define GP4OUT_OUT7 (0x1 << 7 ) +#define GP4OUT_OUT7_LOW (0x0 << 7 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ +#define GP4OUT_OUT7_HIGH (0x1 << 7 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ + +/* GP4OUT[OUT6] - Output for port pin. */ +#define GP4OUT_OUT6_BBA (*(volatile unsigned long *) 0x420C1B18) +#define GP4OUT_OUT6_MSK (0x1 << 6 ) +#define GP4OUT_OUT6 (0x1 << 6 ) +#define GP4OUT_OUT6_LOW (0x0 << 6 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ +#define GP4OUT_OUT6_HIGH (0x1 << 6 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ + +/* GP4OUT[OUT5] - Output for port pin. */ +#define GP4OUT_OUT5_BBA (*(volatile unsigned long *) 0x420C1B14) +#define GP4OUT_OUT5_MSK (0x1 << 5 ) +#define GP4OUT_OUT5 (0x1 << 5 ) +#define GP4OUT_OUT5_LOW (0x0 << 5 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ +#define GP4OUT_OUT5_HIGH (0x1 << 5 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ + +/* GP4OUT[OUT4] - Output for port pin. */ +#define GP4OUT_OUT4_BBA (*(volatile unsigned long *) 0x420C1B10) +#define GP4OUT_OUT4_MSK (0x1 << 4 ) +#define GP4OUT_OUT4 (0x1 << 4 ) +#define GP4OUT_OUT4_LOW (0x0 << 4 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ +#define GP4OUT_OUT4_HIGH (0x1 << 4 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ + +/* GP4OUT[OUT3] - Output for port pin. */ +#define GP4OUT_OUT3_BBA (*(volatile unsigned long *) 0x420C1B0C) +#define GP4OUT_OUT3_MSK (0x1 << 3 ) +#define GP4OUT_OUT3 (0x1 << 3 ) +#define GP4OUT_OUT3_LOW (0x0 << 3 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ +#define GP4OUT_OUT3_HIGH (0x1 << 3 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ + +/* GP4OUT[OUT2] - Output for port pin. */ +#define GP4OUT_OUT2_BBA (*(volatile unsigned long *) 0x420C1B08) +#define GP4OUT_OUT2_MSK (0x1 << 2 ) +#define GP4OUT_OUT2 (0x1 << 2 ) +#define GP4OUT_OUT2_LOW (0x0 << 2 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ +#define GP4OUT_OUT2_HIGH (0x1 << 2 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ + +/* GP4OUT[OUT1] - Output for port pin. */ +#define GP4OUT_OUT1_BBA (*(volatile unsigned long *) 0x420C1B04) +#define GP4OUT_OUT1_MSK (0x1 << 1 ) +#define GP4OUT_OUT1 (0x1 << 1 ) +#define GP4OUT_OUT1_LOW (0x0 << 1 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ +#define GP4OUT_OUT1_HIGH (0x1 << 1 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ + +/* GP4OUT[OUT0] - Output for port pin. */ +#define GP4OUT_OUT0_BBA (*(volatile unsigned long *) 0x420C1B00) +#define GP4OUT_OUT0_MSK (0x1 << 0 ) +#define GP4OUT_OUT0 (0x1 << 0 ) +#define GP4OUT_OUT0_LOW (0x0 << 0 ) /* LOW. Cleared by user to drive the corresponding GPIO low. */ +#define GP4OUT_OUT0_HIGH (0x1 << 0 ) /* HIGH. Set by user code to drive the corresponding GPIO high. */ + +/* Reset Value for GP4SET*/ +#define GP4SET_RVAL 0x0 + +/* GP4SET[SET7] - Set output high for corresponding port pin. */ +#define GP4SET_SET7_BBA (*(volatile unsigned long *) 0x420C1B9C) +#define GP4SET_SET7_MSK (0x1 << 7 ) +#define GP4SET_SET7 (0x1 << 7 ) +#define GP4SET_SET7_SET (0x1 << 7 ) /* SET. Set by user code to drive the corresponding GPIO high. */ + +/* GP4SET[SET6] - Set output high for corresponding port pin. */ +#define GP4SET_SET6_BBA (*(volatile unsigned long *) 0x420C1B98) +#define GP4SET_SET6_MSK (0x1 << 6 ) +#define GP4SET_SET6 (0x1 << 6 ) +#define GP4SET_SET6_SET (0x1 << 6 ) /* SET. Set by user code to drive the corresponding GPIO high. */ + +/* GP4SET[SET5] - Set output high for corresponding port pin. */ +#define GP4SET_SET5_BBA (*(volatile unsigned long *) 0x420C1B94) +#define GP4SET_SET5_MSK (0x1 << 5 ) +#define GP4SET_SET5 (0x1 << 5 ) +#define GP4SET_SET5_SET (0x1 << 5 ) /* SET. Set by user code to drive the corresponding GPIO high. */ + +/* GP4SET[SET4] - Set output high for corresponding port pin. */ +#define GP4SET_SET4_BBA (*(volatile unsigned long *) 0x420C1B90) +#define GP4SET_SET4_MSK (0x1 << 4 ) +#define GP4SET_SET4 (0x1 << 4 ) +#define GP4SET_SET4_SET (0x1 << 4 ) /* SET. Set by user code to drive the corresponding GPIO high. */ + +/* GP4SET[SET3] - Set output high for corresponding port pin. */ +#define GP4SET_SET3_BBA (*(volatile unsigned long *) 0x420C1B8C) +#define GP4SET_SET3_MSK (0x1 << 3 ) +#define GP4SET_SET3 (0x1 << 3 ) +#define GP4SET_SET3_SET (0x1 << 3 ) /* SET. Set by user code to drive the corresponding GPIO high. */ + +/* GP4SET[SET2] - Set output high for corresponding port pin. */ +#define GP4SET_SET2_BBA (*(volatile unsigned long *) 0x420C1B88) +#define GP4SET_SET2_MSK (0x1 << 2 ) +#define GP4SET_SET2 (0x1 << 2 ) +#define GP4SET_SET2_SET (0x1 << 2 ) /* SET. Set by user code to drive the corresponding GPIO high. */ + +/* GP4SET[SET1] - Set output high for corresponding port pin. */ +#define GP4SET_SET1_BBA (*(volatile unsigned long *) 0x420C1B84) +#define GP4SET_SET1_MSK (0x1 << 1 ) +#define GP4SET_SET1 (0x1 << 1 ) +#define GP4SET_SET1_SET (0x1 << 1 ) /* SET. Set by user code to drive the corresponding GPIO high. */ + +/* GP4SET[SET0] - Set output high for corresponding port pin. */ +#define GP4SET_SET0_BBA (*(volatile unsigned long *) 0x420C1B80) +#define GP4SET_SET0_MSK (0x1 << 0 ) +#define GP4SET_SET0 (0x1 << 0 ) +#define GP4SET_SET0_SET (0x1 << 0 ) /* SET. Set by user code to drive the corresponding GPIO high. */ + +/* Reset Value for GP4CLR*/ +#define GP4CLR_RVAL 0x0 + +/* GP4CLR[CLR7] - Set by user code to drive the corresponding GPIO low. */ +#define GP4CLR_CLR7_BBA (*(volatile unsigned long *) 0x420C1C1C) +#define GP4CLR_CLR7_MSK (0x1 << 7 ) +#define GP4CLR_CLR7 (0x1 << 7 ) +#define GP4CLR_CLR7_CLR (0x1 << 7 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ + +/* GP4CLR[CLR6] - Set by user code to drive the corresponding GPIO low. */ +#define GP4CLR_CLR6_BBA (*(volatile unsigned long *) 0x420C1C18) +#define GP4CLR_CLR6_MSK (0x1 << 6 ) +#define GP4CLR_CLR6 (0x1 << 6 ) +#define GP4CLR_CLR6_CLR (0x1 << 6 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ + +/* GP4CLR[CLR5] - Set by user code to drive the corresponding GPIO low. */ +#define GP4CLR_CLR5_BBA (*(volatile unsigned long *) 0x420C1C14) +#define GP4CLR_CLR5_MSK (0x1 << 5 ) +#define GP4CLR_CLR5 (0x1 << 5 ) +#define GP4CLR_CLR5_CLR (0x1 << 5 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ + +/* GP4CLR[CLR4] - Set by user code to drive the corresponding GPIO low. */ +#define GP4CLR_CLR4_BBA (*(volatile unsigned long *) 0x420C1C10) +#define GP4CLR_CLR4_MSK (0x1 << 4 ) +#define GP4CLR_CLR4 (0x1 << 4 ) +#define GP4CLR_CLR4_CLR (0x1 << 4 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ + +/* GP4CLR[CLR3] - Set by user code to drive the corresponding GPIO low. */ +#define GP4CLR_CLR3_BBA (*(volatile unsigned long *) 0x420C1C0C) +#define GP4CLR_CLR3_MSK (0x1 << 3 ) +#define GP4CLR_CLR3 (0x1 << 3 ) +#define GP4CLR_CLR3_CLR (0x1 << 3 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ + +/* GP4CLR[CLR2] - Set by user code to drive the corresponding GPIO low. */ +#define GP4CLR_CLR2_BBA (*(volatile unsigned long *) 0x420C1C08) +#define GP4CLR_CLR2_MSK (0x1 << 2 ) +#define GP4CLR_CLR2 (0x1 << 2 ) +#define GP4CLR_CLR2_CLR (0x1 << 2 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ + +/* GP4CLR[CLR1] - Set by user code to drive the corresponding GPIO low. */ +#define GP4CLR_CLR1_BBA (*(volatile unsigned long *) 0x420C1C04) +#define GP4CLR_CLR1_MSK (0x1 << 1 ) +#define GP4CLR_CLR1 (0x1 << 1 ) +#define GP4CLR_CLR1_CLR (0x1 << 1 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ + +/* GP4CLR[CLR0] - Set by user code to drive the corresponding GPIO low. */ +#define GP4CLR_CLR0_BBA (*(volatile unsigned long *) 0x420C1C00) +#define GP4CLR_CLR0_MSK (0x1 << 0 ) +#define GP4CLR_CLR0 (0x1 << 0 ) +#define GP4CLR_CLR0_CLR (0x1 << 0 ) /* CLR. Set by user code to drive the corresponding GPIO low. */ + +/* Reset Value for GP4TGL*/ +#define GP4TGL_RVAL 0x0 + +/* GP4TGL[TGL7] - Toggle for corresponding port pin. */ +#define GP4TGL_TGL7_BBA (*(volatile unsigned long *) 0x420C1C9C) +#define GP4TGL_TGL7_MSK (0x1 << 7 ) +#define GP4TGL_TGL7 (0x1 << 7 ) +#define GP4TGL_TGL7_TGL (0x1 << 7 ) /* TGL. Set by user code to invert the corresponding GPIO. */ + +/* GP4TGL[TGL6] - Toggle for corresponding port pin. */ +#define GP4TGL_TGL6_BBA (*(volatile unsigned long *) 0x420C1C98) +#define GP4TGL_TGL6_MSK (0x1 << 6 ) +#define GP4TGL_TGL6 (0x1 << 6 ) +#define GP4TGL_TGL6_TGL (0x1 << 6 ) /* TGL. Set by user code to invert the corresponding GPIO. */ + +/* GP4TGL[TGL5] - Toggle for corresponding port pin. */ +#define GP4TGL_TGL5_BBA (*(volatile unsigned long *) 0x420C1C94) +#define GP4TGL_TGL5_MSK (0x1 << 5 ) +#define GP4TGL_TGL5 (0x1 << 5 ) +#define GP4TGL_TGL5_TGL (0x1 << 5 ) /* TGL. Set by user code to invert the corresponding GPIO. */ + +/* GP4TGL[TGL4] - Toggle for corresponding port pin. */ +#define GP4TGL_TGL4_BBA (*(volatile unsigned long *) 0x420C1C90) +#define GP4TGL_TGL4_MSK (0x1 << 4 ) +#define GP4TGL_TGL4 (0x1 << 4 ) +#define GP4TGL_TGL4_TGL (0x1 << 4 ) /* TGL. Set by user code to invert the corresponding GPIO. */ + +/* GP4TGL[TGL3] - Toggle for corresponding port pin. */ +#define GP4TGL_TGL3_BBA (*(volatile unsigned long *) 0x420C1C8C) +#define GP4TGL_TGL3_MSK (0x1 << 3 ) +#define GP4TGL_TGL3 (0x1 << 3 ) +#define GP4TGL_TGL3_TGL (0x1 << 3 ) /* TGL. Set by user code to invert the corresponding GPIO. */ + +/* GP4TGL[TGL2] - Toggle for corresponding port pin. */ +#define GP4TGL_TGL2_BBA (*(volatile unsigned long *) 0x420C1C88) +#define GP4TGL_TGL2_MSK (0x1 << 2 ) +#define GP4TGL_TGL2 (0x1 << 2 ) +#define GP4TGL_TGL2_TGL (0x1 << 2 ) /* TGL. Set by user code to invert the corresponding GPIO. */ + +/* GP4TGL[TGL1] - Toggle for corresponding port pin. */ +#define GP4TGL_TGL1_BBA (*(volatile unsigned long *) 0x420C1C84) +#define GP4TGL_TGL1_MSK (0x1 << 1 ) +#define GP4TGL_TGL1 (0x1 << 1 ) +#define GP4TGL_TGL1_TGL (0x1 << 1 ) /* TGL. Set by user code to invert the corresponding GPIO. */ + +/* GP4TGL[TGL0] - Toggle for corresponding port pin. */ +#define GP4TGL_TGL0_BBA (*(volatile unsigned long *) 0x420C1C80) +#define GP4TGL_TGL0_MSK (0x1 << 0 ) +#define GP4TGL_TGL0 (0x1 << 0 ) +#define GP4TGL_TGL0_TGL (0x1 << 0 ) /* TGL. Set by user code to invert the corresponding GPIO. */ +// ------------------------------------------------------------------------------------------------ +// ----- GPIOCMN ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief General Purpose Input Output (pADI_GPIOCMN) + */ + +#if (__NO_MMR_STRUCTS__==0) +typedef struct { /*!< pADI_GPIOCMN Structure */ + __IO uint8_t GPDWN; /*!< GPIO P3.4 Pull Down Control */ +} ADI_GPIOCMN_TypeDef; +#else // (__NO_MMR_STRUCTS__==0) +#define GPDWN (*(volatile unsigned char *) 0x400060F0) +#endif // (__NO_MMR_STRUCTS__==0) + +/* Reset Value for GPDWN*/ +#define GPDWN_RVAL 0x1 + +/* GPDWN[DWN1] - Pull down resistor control bit */ +#define GPDWN_DWN1_BBA (*(volatile unsigned long *) 0x420C1E04) +#define GPDWN_DWN1_MSK (0x1 << 1 ) +#define GPDWN_DWN1 (0x1 << 1 ) +#define GPDWN_DWN1_EN (0x0 << 1 ) /* EN to enable the pull down resistor on P3.4 by software. The hardware only enables this pull down automatically at power up. */ +#define GPDWN_DWN1_DIS (0x1 << 1 ) /* DIS to disable the pull down resistor on P3.4. Disabled automatically by hardware if GP3PUL[4] =1 or if GP3OEN[4]=1. */ +// ------------------------------------------------------------------------------------------------ +// ----- MISC ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief General Purpose Input Output (pADI_MISC) + */ + +#if (__NO_MMR_STRUCTS__==0) +typedef struct { /*!< pADI_MISC Structure */ + __I uint32_t RESERVED0; + __IO uint16_t RFTST; /*!< Internal Radio Test Mode Access */ + __I uint16_t RESERVED1[5]; + __IO uint8_t SWACT; /*!< Serial Wire Activity Register */ +} ADI_MISC_TypeDef; +#else // (__NO_MMR_STRUCTS__==0) +#define RFTST (*(volatile unsigned short int *) 0x40008824) +#define SWACT (*(volatile unsigned char *) 0x40008830) +#endif // (__NO_MMR_STRUCTS__==0) + +/* Reset Value for RFTST*/ +#define RFTST_RVAL 0x0 + +/* RFTST[DIR] - Controls the pin direction in RF test mode. */ +#define RFTST_DIR_MSK (0x7FF << 5 ) + +/* RFTST[AN1] - Enable RF Analog test 2 mode. */ +#define RFTST_AN1_BBA (*(volatile unsigned long *) 0x4211048C) +#define RFTST_AN1_MSK (0x1 << 3 ) +#define RFTST_AN1 (0x1 << 3 ) +#define RFTST_AN1_DIS (0x0 << 3 ) /* DIS */ +#define RFTST_AN1_EN (0x1 << 3 ) /* EN */ + +/* RFTST[AN0] - Enable RF Analog test mode. */ +#define RFTST_AN0_BBA (*(volatile unsigned long *) 0x42110488) +#define RFTST_AN0_MSK (0x1 << 2 ) +#define RFTST_AN0 (0x1 << 2 ) +#define RFTST_AN0_DIS (0x0 << 2 ) /* DIS */ +#define RFTST_AN0_EN (0x1 << 2 ) /* EN */ + +/* RFTST[SPI0] - Enable the internal SPI0 signals to P0.0, P0.1, P0.2 and P0.3. */ +#define RFTST_SPI0_BBA (*(volatile unsigned long *) 0x42110484) +#define RFTST_SPI0_MSK (0x1 << 1 ) +#define RFTST_SPI0 (0x1 << 1 ) +#define RFTST_SPI0_DIS (0x0 << 1 ) /* DIS */ +#define RFTST_SPI0_EN (0x1 << 1 ) /* EN */ + +/* RFTST[GPX] - Connect the internal GPIOs GP0-GP5 of the RF transceiver to external GPIOs P0.6, P0.7, P1.0, P1.1, P1.4, P1.5. */ +#define RFTST_GPX_BBA (*(volatile unsigned long *) 0x42110480) +#define RFTST_GPX_MSK (0x1 << 0 ) +#define RFTST_GPX (0x1 << 0 ) +#define RFTST_GPX_DIS (0x0 << 0 ) /* DIS */ +#define RFTST_GPX_EN (0x1 << 0 ) /* EN */ + +/* Reset Value for SWACT*/ +#define SWACT_RVAL 0x0 + +/* SWACT[ACT] - Serial Wire Activity */ +#define SWACT_ACT_BBA (*(volatile unsigned long *) 0x42110600) +#define SWACT_ACT_MSK (0x1 << 0 ) +#define SWACT_ACT (0x1 << 0 ) +#define SWACT_ACT_DIS (0x0 << 0 ) /* DIS */ +#define SWACT_ACT_EN (0x1 << 0 ) /* EN */ +// ------------------------------------------------------------------------------------------------ +// ----- I2C ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief I2C (pADI_I2C) + */ + +#if (__NO_MMR_STRUCTS__==0) +typedef struct { /*!< pADI_I2C Structure */ + __IO uint16_t I2CMCON; /*!< Master Control Register */ + __I uint16_t RESERVED0; + __IO uint16_t I2CMSTA; /*!< Master Status Register */ + __I uint16_t RESERVED1; + __IO uint16_t I2CMRX; /*!< Master Receive Data Register */ + __I uint16_t RESERVED2; + __IO uint16_t I2CMTX; /*!< Master Transmit Data Register */ + __I uint16_t RESERVED3; + __IO uint16_t I2CMRXCNT; /*!< Master Receive Data Count Register */ + __I uint16_t RESERVED4; + __IO uint16_t I2CMCRXCNT; /*!< Master Current Receive Data Count Register */ + __I uint16_t RESERVED5; + __IO uint8_t I2CADR0; /*!< First Master Address Byte Register */ + __I uint8_t RESERVED6[3]; + __IO uint8_t I2CADR1; /*!< Second Master Address Byte Register */ + __I uint8_t RESERVED7[7]; + __IO uint16_t I2CDIV; /*!< Serial Clock Period Divisor Register */ + __I uint16_t RESERVED8; + __IO uint16_t I2CSCON; /*!< Slave Control Register */ + __I uint16_t RESERVED9; + __IO uint16_t I2CSSTA; /*!< Slave I2C Status, Error and Interrupt Register */ + __I uint16_t RESERVED10; + __IO uint16_t I2CSRX; /*!< Slave Receive Data Register */ + __I uint16_t RESERVED11; + __IO uint16_t I2CSTX; /*!< Slave Transmit Data Register */ + __I uint16_t RESERVED12; + __IO uint16_t I2CALT; /*!< Hardware General Call ID Register */ + __I uint16_t RESERVED13; + __IO uint16_t I2CID0; /*!< First Slave Address Device ID */ + __I uint16_t RESERVED14; + __IO uint16_t I2CID1; /*!< Second Slave Address Device ID */ + __I uint16_t RESERVED15; + __IO uint16_t I2CID2; /*!< Third Slave Address Device ID */ + __I uint16_t RESERVED16; + __IO uint16_t I2CID3; /*!< Fourth Slave Address Device ID */ + __I uint16_t RESERVED17; + __IO uint16_t I2CFSTA; /*!< Master and Slave Rx/Tx FIFO Status Register */ +} ADI_I2C_TypeDef; +#else // (__NO_MMR_STRUCTS__==0) +#define I2CMCON (*(volatile unsigned short int *) 0x40003000) +#define I2CMSTA (*(volatile unsigned short int *) 0x40003004) +#define I2CMRX (*(volatile unsigned short int *) 0x40003008) +#define I2CMTX (*(volatile unsigned short int *) 0x4000300C) +#define I2CMRXCNT (*(volatile unsigned short int *) 0x40003010) +#define I2CMCRXCNT (*(volatile unsigned short int *) 0x40003014) +#define I2CADR0 (*(volatile unsigned char *) 0x40003018) +#define I2CADR1 (*(volatile unsigned char *) 0x4000301C) +#define I2CDIV (*(volatile unsigned short int *) 0x40003024) +#define I2CSCON (*(volatile unsigned short int *) 0x40003028) +#define I2CSSTA (*(volatile unsigned short int *) 0x4000302C) +#define I2CSRX (*(volatile unsigned short int *) 0x40003030) +#define I2CSTX (*(volatile unsigned short int *) 0x40003034) +#define I2CALT (*(volatile unsigned short int *) 0x40003038) +#define I2CID0 (*(volatile unsigned short int *) 0x4000303C) +#define I2CID1 (*(volatile unsigned short int *) 0x40003040) +#define I2CID2 (*(volatile unsigned short int *) 0x40003044) +#define I2CID3 (*(volatile unsigned short int *) 0x40003048) +#define I2CFSTA (*(volatile unsigned short int *) 0x4000304C) +#endif // (__NO_MMR_STRUCTS__==0) + +/* Reset Value for I2CMCON*/ +#define I2CMCON_RVAL 0x0 + +/* I2CMCON[TXDMA] - Enable master Tx DMA request. */ +#define I2CMCON_TXDMA_BBA (*(volatile unsigned long *) 0x4206002C) +#define I2CMCON_TXDMA_MSK (0x1 << 11 ) +#define I2CMCON_TXDMA (0x1 << 11 ) +#define I2CMCON_TXDMA_DIS (0x0 << 11 ) /* DIS. Disable Tx DMA mode. */ +#define I2CMCON_TXDMA_EN (0x1 << 11 ) /* EN. Enable I2C master DMA requests. */ + +/* I2CMCON[RXDMA] - Enable master Rx DMA request. */ +#define I2CMCON_RXDMA_BBA (*(volatile unsigned long *) 0x42060028) +#define I2CMCON_RXDMA_MSK (0x1 << 10 ) +#define I2CMCON_RXDMA (0x1 << 10 ) +#define I2CMCON_RXDMA_DIS (0x0 << 10 ) /* DIS. Disable Rx DMA mode. */ +#define I2CMCON_RXDMA_EN (0x1 << 10 ) /* EN. Enable I2C master DMA requests. */ + +/* I2CMCON[IENCMP] - Transaction completed (or stop detected) interrupt enable. */ +#define I2CMCON_IENCMP_BBA (*(volatile unsigned long *) 0x42060020) +#define I2CMCON_IENCMP_MSK (0x1 << 8 ) +#define I2CMCON_IENCMP (0x1 << 8 ) +#define I2CMCON_IENCMP_DIS (0x0 << 8 ) /* DIS. Interrupt disabled. */ +#define I2CMCON_IENCMP_EN (0x1 << 8 ) /* EN. Interrupt enabled. A master I2C interrupt is generated when a STOP is detected. Enables TCOMP to geneerate an interrupt. */ + +/* I2CMCON[IENNACK] - NACK received interrupt enable. */ +#define I2CMCON_IENNACK_BBA (*(volatile unsigned long *) 0x4206001C) +#define I2CMCON_IENNACK_MSK (0x1 << 7 ) +#define I2CMCON_IENNACK (0x1 << 7 ) +#define I2CMCON_IENNACK_DIS (0x0 << 7 ) /* DIS. Interrupt disabled. */ +#define I2CMCON_IENNACK_EN (0x1 << 7 ) /* EN, enables NACKADDR(I2CMSTA[4]) and NACKDATA (I2CMSTA[7]) to generate an interrupt. */ + +/* I2CMCON[IENALOST] - Arbitration lost interrupt enable. */ +#define I2CMCON_IENALOST_BBA (*(volatile unsigned long *) 0x42060018) +#define I2CMCON_IENALOST_MSK (0x1 << 6 ) +#define I2CMCON_IENALOST (0x1 << 6 ) +#define I2CMCON_IENALOST_DIS (0x0 << 6 ) /* DIS. Interrupt disabled. */ +#define I2CMCON_IENALOST_EN (0x1 << 6 ) /* EN. Interrupt enabled. A master I2C interrupt is generated if the master looses arbitration.Enables ALOST to generate an interrupt. */ + +/* I2CMCON[IENTX] - Transmit request interrupt enable. */ +#define I2CMCON_IENTX_BBA (*(volatile unsigned long *) 0x42060014) +#define I2CMCON_IENTX_MSK (0x1 << 5 ) +#define I2CMCON_IENTX (0x1 << 5 ) +#define I2CMCON_IENTX_DIS (0x0 << 5 ) /* DIS. Interrupt disabled. */ +#define I2CMCON_IENTX_EN (0x1 << 5 ) /* EN. Interrupt enabled. A master I2C interrupt is generated when the Tx FIFO is not full and the direction bit is 0. */ + +/* I2CMCON[IENRX] - Receive request interrupt enable. */ +#define I2CMCON_IENRX_BBA (*(volatile unsigned long *) 0x42060010) +#define I2CMCON_IENRX_MSK (0x1 << 4 ) +#define I2CMCON_IENRX (0x1 << 4 ) +#define I2CMCON_IENRX_DIS (0x0 << 4 ) /* DIS. Interrupt disabled. */ +#define I2CMCON_IENRX_EN (0x1 << 4 ) /* EN. Interrupt enabled. A master I2C interrupt is generated when data is in the receive FIFO. */ + +/* I2CMCON[STRETCH] - Stretch I2CSCL enable. */ +#define I2CMCON_STRETCH_BBA (*(volatile unsigned long *) 0x4206000C) +#define I2CMCON_STRETCH_MSK (0x1 << 3 ) +#define I2CMCON_STRETCH (0x1 << 3 ) +#define I2CMCON_STRETCH_DIS (0x0 << 3 ) /* DIS. Disable */ +#define I2CMCON_STRETCH_EN (0x1 << 3 ) /* EN. Setting this bit instructs the device that if I2CSCL is 0, hold it at 0. Or if I2CSCL is 1, then when it next goes to 0, hold it at 0. */ + +/* I2CMCON[LOOPBACK] - Internal loop back enable. */ +#define I2CMCON_LOOPBACK_BBA (*(volatile unsigned long *) 0x42060008) +#define I2CMCON_LOOPBACK_MSK (0x1 << 2 ) +#define I2CMCON_LOOPBACK (0x1 << 2 ) +#define I2CMCON_LOOPBACK_DIS (0x0 << 2 ) /* DIS. Disable. */ +#define I2CMCON_LOOPBACK_EN (0x1 << 2 ) /* EN. I2CSCL and I2CSDA out of the device are muxed onto their corresponding inputs. Note that is also possible for the master to loop back a transfer to the slave as long as the device address corresponds, that is, external loopback. */ + +/* I2CMCON[COMPETE] - Start back-off disable. */ +#define I2CMCON_COMPETE_BBA (*(volatile unsigned long *) 0x42060004) +#define I2CMCON_COMPETE_MSK (0x1 << 1 ) +#define I2CMCON_COMPETE (0x1 << 1 ) +#define I2CMCON_COMPETE_DIS (0x0 << 1 ) /* DIS. Disable. */ +#define I2CMCON_COMPETE_EN (0x1 << 1 ) /* EN. Enables the device to compete for ownership even if another device is currently driving a start condition. */ + +/* I2CMCON[MAS] - Master enable bit. */ +#define I2CMCON_MAS_BBA (*(volatile unsigned long *) 0x42060000) +#define I2CMCON_MAS_MSK (0x1 << 0 ) +#define I2CMCON_MAS (0x1 << 0 ) +#define I2CMCON_MAS_DIS (0x0 << 0 ) /* DIS. The master is disabled. The master state machine is reset.The master should be disabled when not in use. This bit should not be cleared until a transaction has completed. TCOMP in I2CMSTA indicates when a transaction is complete. */ +#define I2CMCON_MAS_EN (0x1 << 0 ) /* EN. Enable master. */ + +/* Reset Value for I2CMSTA*/ +#define I2CMSTA_RVAL 0x0 + +/* I2CMSTA[TXUR] - Master transmit FIFO underrun. */ +#define I2CMSTA_TXUR_BBA (*(volatile unsigned long *) 0x420600B0) +#define I2CMSTA_TXUR_MSK (0x1 << 12 ) +#define I2CMSTA_TXUR (0x1 << 12 ) +#define I2CMSTA_TXUR_CLR (0x0 << 12 ) /* CLR. Cleared. */ +#define I2CMSTA_TXUR_SET (0x1 << 12 ) /* SET. Set when the I2C master ends the transaction due to a Tx FIFO empty condition. This bit is only set when IENTX (I2CSCON[5]) is set. */ + +/* I2CMSTA[MSTOP] - STOP driven by the I2C master. */ +#define I2CMSTA_MSTOP_BBA (*(volatile unsigned long *) 0x420600AC) +#define I2CMSTA_MSTOP_MSK (0x1 << 11 ) +#define I2CMSTA_MSTOP (0x1 << 11 ) +#define I2CMSTA_MSTOP_CLR (0x0 << 11 ) /* CLR. Cleared. */ +#define I2CMSTA_MSTOP_SET (0x1 << 11 ) /* SET. Set when the I2C master drives a stop condition on the I2C bus, therefore indicating a transaction completion, Tx underrun, Rx overflow, or a NACK by the slave. It is different from TCOMP because it is not set when the stop condition occurs due to any other master on the I2C bus. This bit does not generate an interrupt. See the TCOMP description for available interrupts related to the stop condition. */ + +/* I2CMSTA[LINEBUSY] - Line is busy. */ +#define I2CMSTA_LINEBUSY_BBA (*(volatile unsigned long *) 0x420600A8) +#define I2CMSTA_LINEBUSY_MSK (0x1 << 10 ) +#define I2CMSTA_LINEBUSY (0x1 << 10 ) +#define I2CMSTA_LINEBUSY_CLR (0x0 << 10 ) /* CLR. Cleared when a stop is detected on the I2C bus. */ +#define I2CMSTA_LINEBUSY_SET (0x1 << 10 ) /* SET. Set when a start is detected on the I2C bus. */ + +/* I2CMSTA[RXOF] - Receive FIFO overflow. */ +#define I2CMSTA_RXOF_BBA (*(volatile unsigned long *) 0x420600A4) +#define I2CMSTA_RXOF_MSK (0x1 << 9 ) +#define I2CMSTA_RXOF (0x1 << 9 ) +#define I2CMSTA_RXOF_CLR (0x0 << 9 ) /* CLR. CLeared. */ +#define I2CMSTA_RXOF_SET (0x1 << 9 ) /* SET. Set when a byte is written to the receive FIFO when the FIFO is already full. */ + +/* I2CMSTA[TCOMP] - Transaction completed (or stop detected). (Can drive an interrupt). */ +#define I2CMSTA_TCOMP_BBA (*(volatile unsigned long *) 0x420600A0) +#define I2CMSTA_TCOMP_MSK (0x1 << 8 ) +#define I2CMSTA_TCOMP (0x1 << 8 ) +#define I2CMSTA_TCOMP_CLR (0x0 << 8 ) /* CLR. Cleared. */ +#define I2CMSTA_TCOMP_SET (0x1 << 8 ) /* SET. Set when a STOP condition is detected on the I2C bus. If IENCMP is 1, an interrupt is generated when this bit asserts. This bit only asserts if the master is enabled (MASEN = 1). This bit should be used to determine when it is safe to disable the master. It can also be used to wait for another master's transaction to complete on the I2C bus when this master loses arbitration. */ + +/* I2CMSTA[NACKDATA] - NACK received in response to data write. (Can drive an interrupt). */ +#define I2CMSTA_NACKDATA_BBA (*(volatile unsigned long *) 0x4206009C) +#define I2CMSTA_NACKDATA_MSK (0x1 << 7 ) +#define I2CMSTA_NACKDATA (0x1 << 7 ) +#define I2CMSTA_NACKDATA_CLR (0x0 << 7 ) /* CLR. Cleared on a read of the I2CMSTA register. */ +#define I2CMSTA_NACKDATA_SET (0x1 << 7 ) /* SET. Set when a NACK is received in response to a data write transfer. If IENNACK is 1, an interrupt is generated when this bit asserts. */ + +/* I2CMSTA[BUSY] - Master busy. */ +#define I2CMSTA_BUSY_BBA (*(volatile unsigned long *) 0x42060098) +#define I2CMSTA_BUSY_MSK (0x1 << 6 ) +#define I2CMSTA_BUSY (0x1 << 6 ) +#define I2CMSTA_BUSY_CLR (0x0 << 6 ) /* CLR. Cleared if the state machine is idle or another device has control of the I2C bus. */ +#define I2CMSTA_BUSY_SET (0x1 << 6 ) /* SET. Set when the master state machine is servicing a transaction. */ + +/* I2CMSTA[ALOST] - Arbitration lost. (Can drive an interrupt). */ +#define I2CMSTA_ALOST_BBA (*(volatile unsigned long *) 0x42060094) +#define I2CMSTA_ALOST_MSK (0x1 << 5 ) +#define I2CMSTA_ALOST (0x1 << 5 ) +#define I2CMSTA_ALOST_CLR (0x0 << 5 ) /* CLR. Cleared on a read of the I2CMSTA register. */ +#define I2CMSTA_ALOST_SET (0x1 << 5 ) /* SET. Set if the master looses arbitration. If IENALOST is 1, an interrupt is generated when this bit asserts. */ + +/* I2CMSTA[NACKADDR] - NACK received in response to an address. (Can drive an interrupt). */ +#define I2CMSTA_NACKADDR_BBA (*(volatile unsigned long *) 0x42060090) +#define I2CMSTA_NACKADDR_MSK (0x1 << 4 ) +#define I2CMSTA_NACKADDR (0x1 << 4 ) +#define I2CMSTA_NACKADDR_CLR (0x0 << 4 ) /* CLR. Cleared on a read of the I2CMSTA register. */ +#define I2CMSTA_NACKADDR_SET (0x1 << 4 ) /* SET. Set if a NACK received in response to an address. If IENNACK is 1, an interrupt is generated when this bit asserts. */ + +/* I2CMSTA[RXREQ] - Receive Request. (Can drive an interrupt). */ +#define I2CMSTA_RXREQ_BBA (*(volatile unsigned long *) 0x4206008C) +#define I2CMSTA_RXREQ_MSK (0x1 << 3 ) +#define I2CMSTA_RXREQ (0x1 << 3 ) +#define I2CMSTA_RXREQ_CLR (0x0 << 3 ) /* CLR. Cleared. */ +#define I2CMSTA_RXREQ_SET (0x1 << 3 ) /* SET. Set when there is data in the receive FIFO. If IENRX is 1, an interrupt is generated when this bit asserts. */ + +/* I2CMSTA[TXREQ] - Transmit Request. (Can drive an interrupt). */ +#define I2CMSTA_TXREQ_BBA (*(volatile unsigned long *) 0x42060088) +#define I2CMSTA_TXREQ_MSK (0x1 << 2 ) +#define I2CMSTA_TXREQ (0x1 << 2 ) +#define I2CMSTA_TXREQ_CLR (0x0 << 2 ) /* CLR. Cleared when the transmit FIFO underrun condition is not met. */ +#define I2CMSTA_TXREQ_SET (0x1 << 2 ) /* SET. Set when the direction bit is 0 and the transmit FIFO is either empty or not full. If IENTX is 1, an interrupt is generated when this bit asserts. */ + +/* I2CMSTA[TXFSTA] - Transmit FIFO Status. */ +#define I2CMSTA_TXFSTA_MSK (0x3 << 0 ) +#define I2CMSTA_TXFSTA_EMPTY (0x0 << 0 ) /* EMPTY. FIFO empty. */ +#define I2CMSTA_TXFSTA_ONEBYTE (0x2 << 0 ) /* ONEBYTE. 1 byte in FIFO. */ +#define I2CMSTA_TXFSTA_FULL (0x3 << 0 ) /* FULL. FIFO full. */ + +/* Reset Value for I2CMRX*/ +#define I2CMRX_RVAL 0x0 + +/* I2CMRX[VALUE] - Receive register. This register allows access to the receive data FIFO. The FIFO can hold two bytes. */ +#define I2CMRX_VALUE_MSK (0xFF << 0 ) + +/* Reset Value for I2CMTX*/ +#define I2CMTX_RVAL 0x0 + +/* I2CMTX[VALUE] - Transmit register. This register allows access to the transmit data FIFO. The FIFO can hold two bytes. */ +#define I2CMTX_VALUE_MSK (0xFF << 0 ) + +/* Reset Value for I2CMRXCNT*/ +#define I2CMRXCNT_RVAL 0x0 + +/* I2CMRXCNT[EXTEND] - Extended read: Use this bit if greater than 256 bytes are required on a read. For example: To receive 412 bytes, write 0x100 (EXTEND = 1) to this register (I2CMRXCNT). Wait for the first byte to be received, then check the I2CMCRXCNT register for every byte received thereafter. When I2CMCRXCNT returns to 0, 256 bytes have been received. Then, write 0x09C (412 - 256 = 156 decimal (equal to 0x9C) – with the EXTEND bit set to 0) to this register (I2CMRXCNT). */ +#define I2CMRXCNT_EXTEND_BBA (*(volatile unsigned long *) 0x42060220) +#define I2CMRXCNT_EXTEND_MSK (0x1 << 8 ) +#define I2CMRXCNT_EXTEND (0x1 << 8 ) +#define I2CMRXCNT_EXTEND_DIS (0x0 << 8 ) /* DIS */ +#define I2CMRXCNT_EXTEND_EN (0x1 << 8 ) /* EN */ + +/* I2CMRXCNT[COUNT] - Receive count. Program the number of bytes required minus one to this register. If just one byte is required write 0 to this register. If greater than 256 bytes are required, then use EXTEND. */ +#define I2CMRXCNT_COUNT_MSK (0xFF << 0 ) + +/* Reset Value for I2CMCRXCNT*/ +#define I2CMCRXCNT_RVAL 0x0 + +/* I2CMCRXCNT[VALUE] - Current receive count. This register gives the total number of bytes received so far. If 256 bytes are requested, then this register reads 0 when the transaction has completed. */ +#define I2CMCRXCNT_VALUE_MSK (0xFF << 0 ) + +/* Reset Value for I2CADR0*/ +#define I2CADR0_RVAL 0x0 + +/* I2CADR0[VALUE] - Address byte. If a 7-bit address is required, then I2CADR0[7:1] is programmed with the address and I2CADR0[0] is programmed with the direction (read or write). If a 10-bit address is required then I2CADR0[7:3] is programmed with '11110', I2CADR0[2:1] is programmed with the two MSBs of the address, and, again, I2CADR0[0] is programmed with the direction bit (read or write). */ +#define I2CADR0_VALUE_MSK (0xFF << 0 ) + +/* Reset Value for I2CADR1*/ +#define I2CADR1_RVAL 0x0 + +/* I2CADR1[VALUE] - Address byte. This register is only required when addressing a slave with 10-bit addressing. I2CADR1[7:0] is programmed with the lower eight bits of the address. */ +#define I2CADR1_VALUE_MSK (0xFF << 0 ) + +/* Reset Value for I2CDIV*/ +#define I2CDIV_RVAL 0x1F1F + +/* I2CDIV[HIGH] - Serial clock high time. This register controls the clock high time. See the serial clock generation section for more details. */ +#define I2CDIV_HIGH_MSK (0xFF << 8 ) + +/* I2CDIV[LOW] - Serial clock low time. This register controls the clock low time. See the serial clock generation section for more details. */ +#define I2CDIV_LOW_MSK (0xFF << 0 ) + +/* Reset Value for I2CSCON*/ +#define I2CSCON_RVAL 0x0 + +/* I2CSCON[TXDMA] - Enable slave Tx DMA request. */ +#define I2CSCON_TXDMA_BBA (*(volatile unsigned long *) 0x42060538) +#define I2CSCON_TXDMA_MSK (0x1 << 14 ) +#define I2CSCON_TXDMA (0x1 << 14 ) +#define I2CSCON_TXDMA_DIS (0x0 << 14 ) /* DIS. Disable DMA mode. */ +#define I2CSCON_TXDMA_EN (0x1 << 14 ) /* EN. Enable I2C slave DMA requests. */ + +/* I2CSCON[RXDMA] - Enable slave Rx DMA request. */ +#define I2CSCON_RXDMA_BBA (*(volatile unsigned long *) 0x42060534) +#define I2CSCON_RXDMA_MSK (0x1 << 13 ) +#define I2CSCON_RXDMA (0x1 << 13 ) +#define I2CSCON_RXDMA_DIS (0x0 << 13 ) /* DIS. Disable DMA mode. */ +#define I2CSCON_RXDMA_EN (0x1 << 13 ) /* EN. Enable I2C slave DMA requests. */ + +/* I2CSCON[IENREPST] - Repeated start interrupt enable. */ +#define I2CSCON_IENREPST_BBA (*(volatile unsigned long *) 0x42060530) +#define I2CSCON_IENREPST_MSK (0x1 << 12 ) +#define I2CSCON_IENREPST (0x1 << 12 ) +#define I2CSCON_IENREPST_DIS (0x0 << 12 ) /* DIS. Disable an interrupt when the REPSTART status bit asserts. */ +#define I2CSCON_IENREPST_EN (0x1 << 12 ) /* EN. Generate an interrupt when the REPSTART status bit asserts. */ + +/* I2CSCON[IENTX] - Transmit request interrupt enable. */ +#define I2CSCON_IENTX_BBA (*(volatile unsigned long *) 0x42060528) +#define I2CSCON_IENTX_MSK (0x1 << 10 ) +#define I2CSCON_IENTX (0x1 << 10 ) +#define I2CSCON_IENTX_DIS (0x0 << 10 ) /* DIS. Disable transmit request interrupt. */ +#define I2CSCON_IENTX_EN (0x1 << 10 ) /* EN. Enable transmit request interrupt. */ + +/* I2CSCON[IENRX] - Receive request interrupt enable. */ +#define I2CSCON_IENRX_BBA (*(volatile unsigned long *) 0x42060524) +#define I2CSCON_IENRX_MSK (0x1 << 9 ) +#define I2CSCON_IENRX (0x1 << 9 ) +#define I2CSCON_IENRX_DIS (0x0 << 9 ) /* DIS. Disable receive request interrupt. */ +#define I2CSCON_IENRX_EN (0x1 << 9 ) /* EN. Enable receive request interrupt. */ + +/* I2CSCON[IENSTOP] - Stop condition detected interrupt enable. */ +#define I2CSCON_IENSTOP_BBA (*(volatile unsigned long *) 0x42060520) +#define I2CSCON_IENSTOP_MSK (0x1 << 8 ) +#define I2CSCON_IENSTOP (0x1 << 8 ) +#define I2CSCON_IENSTOP_DIS (0x0 << 8 ) /* DIS. Disable stop condition detect interrupt. */ +#define I2CSCON_IENSTOP_EN (0x1 << 8 ) /* EN. Enable stop condition detect interrupt. Enables STOP (I2CSSTA[10]) to generate an interrupt */ + +/* I2CSCON[NACK] - NACK next communication. */ +#define I2CSCON_NACK_BBA (*(volatile unsigned long *) 0x4206051C) +#define I2CSCON_NACK_MSK (0x1 << 7 ) +#define I2CSCON_NACK (0x1 << 7 ) +#define I2CSCON_NACK_DIS (0x0 << 7 ) /* DIS. Disable. */ +#define I2CSCON_NACK_EN (0x1 << 7 ) /* EN. Allow the next communication to be NACK'ed. This can be used for example if during a 24xx I2C serial eeprom style access, an attempt was made to write to a read only or nonexisting location in system memory. That is the indirect address in a 24xx I2C serial eeprom style write pointed to an unwritable memory location. */ + +/* I2CSCON[STRETCH] - Stretch I2CSCL enable. */ +#define I2CSCON_STRETCH_BBA (*(volatile unsigned long *) 0x42060518) +#define I2CSCON_STRETCH_MSK (0x1 << 6 ) +#define I2CSCON_STRETCH (0x1 << 6 ) +#define I2CSCON_STRETCH_DIS (0x0 << 6 ) /* DIS. Disable. */ +#define I2CSCON_STRETCH_EN (0x1 << 6 ) /* EN. Tell the device that, if I2CSCL is 0, hold it at 0. Or if I2CSCL is 1, then when it next goes to 0 hold it at 0. */ + +/* I2CSCON[EARLYTXR] - Early transmit request mode. */ +#define I2CSCON_EARLYTXR_BBA (*(volatile unsigned long *) 0x42060514) +#define I2CSCON_EARLYTXR_MSK (0x1 << 5 ) +#define I2CSCON_EARLYTXR (0x1 << 5 ) +#define I2CSCON_EARLYTXR_DIS (0x0 << 5 ) /* DIS. Disable. */ +#define I2CSCON_EARLYTXR_EN (0x1 << 5 ) /* EN. Enable a transmit request just after the positive edge of the direction bit (READ/WRITE) I2CSCL clock pulse. */ + +/* I2CSCON[GCSB] - General call status bit clear. */ +#define I2CSCON_GCSB_BBA (*(volatile unsigned long *) 0x42060510) +#define I2CSCON_GCSB_MSK (0x1 << 4 ) +#define I2CSCON_GCSB (0x1 << 4 ) +#define I2CSCON_GCSB_CLR (0x1 << 4 ) /* CLR. Clear the General Call status and General Call ID bits. The General Call status and General Call ID bits are not reset by anything other than a write to this bit or a full reset. */ + +/* I2CSCON[HGC] - Hardware general call enable. */ +#define I2CSCON_HGC_BBA (*(volatile unsigned long *) 0x4206050C) +#define I2CSCON_HGC_MSK (0x1 << 3 ) +#define I2CSCON_HGC (0x1 << 3 ) +#define I2CSCON_HGC_DIS (0x0 << 3 ) /* DIS. Disable. */ +#define I2CSCON_HGC_EN (0x1 << 3 ) /* EN. When this bit and the General Call enable bit are set the device after receiving a general call, Address 0x00 and a data byte checks the contents of the I2CALT against the receive shift register. If they match, the device has received a hardware general call. This is used if a device needs urgent attention from a master device without knowing which master it needs to turn to. This is a broadcast message to all master devices in the bus. The device that requires attention embeds its own address into the message. The LSB of the I2CALT register should always be written to a 1. */ + +/* I2CSCON[GC] - General call enable. */ +#define I2CSCON_GC_BBA (*(volatile unsigned long *) 0x42060508) +#define I2CSCON_GC_MSK (0x1 << 2 ) +#define I2CSCON_GC (0x1 << 2 ) +#define I2CSCON_GC_DIS (0x0 << 2 ) /* DIS. Disable. */ +#define I2CSCON_GC_EN (0x1 << 2 ) /* EN. Enable the I2C slave to ACK an I2C general call, Address 0x00 (write). */ + +/* I2CSCON[ADR10] - Enable 10 bit addressing. */ +#define I2CSCON_ADR10_BBA (*(volatile unsigned long *) 0x42060504) +#define I2CSCON_ADR10_MSK (0x1 << 1 ) +#define I2CSCON_ADR10 (0x1 << 1 ) +#define I2CSCON_ADR10_DIS (0x0 << 1 ) /* DIS. If this bit is clear, the slave can support four slave addresses, programmed in Registers I2CID0 to I2CID3. */ +#define I2CSCON_ADR10_EN (0x1 << 1 ) /* EN. Enable 10-bit addressing. One 10-bit address is supported by the slave and is stored in I2CID0 and I2CID1, where I2CID0 contains the first byte of the address and the upper five bits must be programmed to 11110' I2CID2 and I2CID3 can be programmed with 7-bit addresses at the same time. */ + +/* I2CSCON[SLV] - Slave enable. */ +#define I2CSCON_SLV_BBA (*(volatile unsigned long *) 0x42060500) +#define I2CSCON_SLV_MSK (0x1 << 0 ) +#define I2CSCON_SLV (0x1 << 0 ) +#define I2CSCON_SLV_DIS (0x0 << 0 ) /* DIS. Disable the slave and all slave state machine flops are held in reset. */ +#define I2CSCON_SLV_EN (0x1 << 0 ) /* EN. Enable slave. */ + +/* Reset Value for I2CSSTA*/ +#define I2CSSTA_RVAL 0x1 + +/* I2CSSTA[START] - Start and matching address. */ +#define I2CSSTA_START_BBA (*(volatile unsigned long *) 0x420605B8) +#define I2CSSTA_START_MSK (0x1 << 14 ) +#define I2CSSTA_START (0x1 << 14 ) +#define I2CSSTA_START_CLR (0x0 << 14 ) /* CLR. Cleared on receipt of either a stop or start condition. */ +#define I2CSSTA_START_SET (0x1 << 14 ) /* SET. Set if a start is detected on I2CSCL/I2CSDA and one of the following is true: The device address is matched. A general call (GC = 0000_0000) code is received and GC is enabled. A high speed (HS = 0000_1XXX) code is received. A start byte (0000_0001) is received. */ + +/* I2CSSTA[REPSTART] - Repeated start and matching address. (Can drive an interrupt). */ +#define I2CSSTA_REPSTART_BBA (*(volatile unsigned long *) 0x420605B4) +#define I2CSSTA_REPSTART_MSK (0x1 << 13 ) +#define I2CSSTA_REPSTART (0x1 << 13 ) +#define I2CSSTA_REPSTART_CLR (0x0 << 13 ) /* CLR. Cleared when read or on receipt of a stop condition. */ +#define I2CSSTA_REPSTART_SET (0x1 << 13 ) /* SET. Set if START (I2CSSTA[14]) is already asserted and then a repeated start is detected. */ + +/* I2CSSTA[IDMAT] - Device ID matched. */ +#define I2CSSTA_IDMAT_MSK (0x3 << 11 ) + +/* I2CSSTA[STOP] - Stop after start and matching address. (Can drive an interrupt). */ +#define I2CSSTA_STOP_BBA (*(volatile unsigned long *) 0x420605A8) +#define I2CSSTA_STOP_MSK (0x1 << 10 ) +#define I2CSSTA_STOP (0x1 << 10 ) +#define I2CSSTA_STOP_CLR (0x0 << 10 ) /* CLR. Cleared by a read of the status register. */ +#define I2CSSTA_STOP_SET (0x1 << 10 ) /* SET. Set if the slave device received a stop condition after a previous start condition and a matching address. */ + +/* I2CSSTA[GCID] - General call ID. Cleared when the GCSBCLR (I2CSCON[4]) is written to 1. These status bits are not cleared by a general call reset. */ +#define I2CSSTA_GCID_MSK (0x3 << 8 ) + +/* I2CSSTA[GCINT] - General call interrupt. (Always drives an interrupt). */ +#define I2CSSTA_GCINT_BBA (*(volatile unsigned long *) 0x4206059C) +#define I2CSSTA_GCINT_MSK (0x1 << 7 ) +#define I2CSSTA_GCINT (0x1 << 7 ) +#define I2CSSTA_GCINT_CLR (0x0 << 7 ) /* CLR. To clear this bit, write 1 to the I2CSCON[4]. If it was a general call reset, all registers are at their default values. If it was a hardware general call, the Rx FIFO holds the second byte of the general call and this can be compared with the ALT register. */ +#define I2CSSTA_GCINT_SET (0x1 << 7 ) /* SET. Set if the slave device receives a general call of any type. */ + +/* I2CSSTA[BUSY] - Slave busy. */ +#define I2CSSTA_BUSY_BBA (*(volatile unsigned long *) 0x42060598) +#define I2CSSTA_BUSY_MSK (0x1 << 6 ) +#define I2CSSTA_BUSY (0x1 << 6 ) +#define I2CSSTA_BUSY_CLR (0x0 << 6 ) /* CLR. Cleared by hardware on any of the following conditions: The address does not match an ID register, the slave device receives a I2C stop condition or if a repeated start address doesn’t match. */ +#define I2CSSTA_BUSY_SET (0x1 << 6 ) /* SET. Set if the slave device receives an I2C start condition. */ + +/* I2CSSTA[NOACK] - NACK generated by the slave. */ +#define I2CSSTA_NOACK_BBA (*(volatile unsigned long *) 0x42060594) +#define I2CSSTA_NOACK_MSK (0x1 << 5 ) +#define I2CSSTA_NOACK (0x1 << 5 ) +#define I2CSSTA_NOACK_CLR (0x0 << 5 ) /* CLR. Cleared on a read of the I2CSSTA register. */ +#define I2CSSTA_NOACK_SET (0x1 << 5 ) /* SET. Set to indicate that the slave responded to its device address with a NACK. Set under any of the following conditions: If there was no data to transmit and sequence was a slave read, the device address is NACK'ed or if the NACK bit was set in the slave control register and the device was addressed. */ + +/* I2CSSTA[RXOF] - Receive FIFO overflow. */ +#define I2CSSTA_RXOF_BBA (*(volatile unsigned long *) 0x42060590) +#define I2CSSTA_RXOF_MSK (0x1 << 4 ) +#define I2CSSTA_RXOF (0x1 << 4 ) +#define I2CSSTA_RXOF_CLR (0x0 << 4 ) /* CLR. Cleared. */ +#define I2CSSTA_RXOF_SET (0x1 << 4 ) /* SET. Set when a byte is written to the receive FIFO when the FIFO is already full. */ + +/* I2CSSTA[RXREQ] - Receive request. (Can drive an interrupt). */ +#define I2CSSTA_RXREQ_BBA (*(volatile unsigned long *) 0x4206058C) +#define I2CSSTA_RXREQ_MSK (0x1 << 3 ) +#define I2CSSTA_RXREQ (0x1 << 3 ) +#define I2CSSTA_RXREQ_CLR (0x0 << 3 ) /* CLR. Cleared when the receive FIFO is read or flushed. */ +#define I2CSSTA_RXREQ_SET (0x1 << 3 ) /* SET. Set when the receive FIFO is not empty. Set on the falling edge of the I2CSCL clock pulse that clocks in the last data bit of a byte. */ + +/* I2CSSTA[TXREQ] - Transmit request. (Can drive an interrupt). */ +#define I2CSSTA_TXREQ_BBA (*(volatile unsigned long *) 0x42060588) +#define I2CSSTA_TXREQ_MSK (0x1 << 2 ) +#define I2CSSTA_TXREQ (0x1 << 2 ) +#define I2CSSTA_TXREQ_CLR (0x0 << 2 ) /* CLR. This bit is cleared on a read of the I2CSSTA register. */ +#define I2CSSTA_TXREQ_SET (0x1 << 2 ) /* SET. If EARLYTXR = 0, TXREQ is set when the direction bit for a transfer is received high. Thereafter, as long as the transmit FIFO is not full, this bit remains asserted. Initially, it is asserted on the negative edge of the SCL pulse that clocks in the direction bit (if the device address matched also). If EARLYTXR = 1, TXREQ is set when the direction bit for a transfer is received high. Thereafter, as long as the transmit FIFO is not full, this bit will remain asserted. Initially, it is asserted after the positive edge of the SCL pulse that clocks in the direction bit (if the device address matched also). */ + +/* I2CSSTA[TXUR] - Transmit FIFO underflow. */ +#define I2CSSTA_TXUR_BBA (*(volatile unsigned long *) 0x42060584) +#define I2CSSTA_TXUR_MSK (0x1 << 1 ) +#define I2CSSTA_TXUR (0x1 << 1 ) +#define I2CSSTA_TXUR_CLR (0x0 << 1 ) /* CLR. Cleared. */ +#define I2CSSTA_TXUR_SET (0x1 << 1 ) /* SET. Set to 1 if a master requests data from the device and the Tx FIFO is empty for the rising edge of SCL. */ + +/* I2CSSTA[TXFSEREQ] - Tx FIFO status. */ +#define I2CSSTA_TXFSEREQ_BBA (*(volatile unsigned long *) 0x42060580) +#define I2CSSTA_TXFSEREQ_MSK (0x1 << 0 ) +#define I2CSSTA_TXFSEREQ (0x1 << 0 ) +#define I2CSSTA_TXFSEREQ_CLR (0x0 << 0 ) /* CLR. Cleared. */ +#define I2CSSTA_TXFSEREQ_SET (0x1 << 0 ) /* SET. Set whenever the slave Tx FIFO is empty. */ + +/* Reset Value for I2CSRX*/ +#define I2CSRX_RVAL 0x0 + +/* I2CSRX[VALUE] - Receive register. */ +#define I2CSRX_VALUE_MSK (0xFF << 0 ) + +/* Reset Value for I2CSTX*/ +#define I2CSTX_RVAL 0x0 + +/* I2CSTX[VALUE] - Transmit register. */ +#define I2CSTX_VALUE_MSK (0xFF << 0 ) + +/* Reset Value for I2CALT*/ +#define I2CALT_RVAL 0x0 + +/* I2CALT[VALUE] - ALT register.This register is used in conjunction with HGC (I2CSCON[3]) to match a master generating a hardware general call. It is used in the case where a master device cannot be programmed with a slave’s address and, instead, the slave must recognize the master’s address. */ +#define I2CALT_VALUE_MSK (0xFF << 0 ) + +/* Reset Value for I2CID0*/ +#define I2CID0_RVAL 0x0 + +/* I2CID0[VALUE] - Slave ID. */ +#define I2CID0_VALUE_MSK (0xFF << 0 ) + +/* Reset Value for I2CID1*/ +#define I2CID1_RVAL 0x0 + +/* I2CID1[VALUE] - Slave ID. */ +#define I2CID1_VALUE_MSK (0xFF << 0 ) + +/* Reset Value for I2CID2*/ +#define I2CID2_RVAL 0x0 + +/* I2CID2[VALUE] - Slave ID. */ +#define I2CID2_VALUE_MSK (0xFF << 0 ) + +/* Reset Value for I2CID3*/ +#define I2CID3_RVAL 0x0 + +/* I2CID3[VALUE] - Slave ID. */ +#define I2CID3_VALUE_MSK (0xFF << 0 ) + +/* Reset Value for I2CFSTA*/ +#define I2CFSTA_RVAL 0x0 + +/* I2CFSTA[MFLUSH] - Master Transmit FIFO Flush. */ +#define I2CFSTA_MFLUSH_BBA (*(volatile unsigned long *) 0x420609A4) +#define I2CFSTA_MFLUSH_MSK (0x1 << 9 ) +#define I2CFSTA_MFLUSH (0x1 << 9 ) +#define I2CFSTA_MFLUSH_DIS (0x0 << 9 ) /* DIS. For normal FIFO operation. */ +#define I2CFSTA_MFLUSH_EN (0x1 << 9 ) /* EN. FIFO flush enabled, to keep the FIFO empty. */ + +/* I2CFSTA[SFLUSH] - Slave Transmit FIFO Flush. */ +#define I2CFSTA_SFLUSH_BBA (*(volatile unsigned long *) 0x420609A0) +#define I2CFSTA_SFLUSH_MSK (0x1 << 8 ) +#define I2CFSTA_SFLUSH (0x1 << 8 ) +#define I2CFSTA_SFLUSH_DIS (0x0 << 8 ) /* DIS. For normal FIFO operation. */ +#define I2CFSTA_SFLUSH_EN (0x1 << 8 ) /* EN. FIFO flush enabled, to keep the FIFO empty. */ + +/* I2CFSTA[MRXFSTA] - Master Receive FIFO status. */ +#define I2CFSTA_MRXFSTA_MSK (0x3 << 6 ) +#define I2CFSTA_MRXFSTA_EMPTY (0x0 << 6 ) /* EMPTY */ +#define I2CFSTA_MRXFSTA_ONEBYTE (0x1 << 6 ) /* ONEBYTE */ +#define I2CFSTA_MRXFSTA_TWOBYTES (0x2 << 6 ) /* TWOBYTES */ + +/* I2CFSTA[MTXFSTA] - Master Transmit FIFO status. */ +#define I2CFSTA_MTXFSTA_MSK (0x3 << 4 ) +#define I2CFSTA_MTXFSTA_EMPTY (0x0 << 4 ) /* EMPTY */ +#define I2CFSTA_MTXFSTA_ONEBYTE (0x1 << 4 ) /* ONEBYTE */ +#define I2CFSTA_MTXFSTA_TWOBYTES (0x2 << 4 ) /* TWOBYTES */ + +/* I2CFSTA[SRXFSTA] - Slave Receive FIFO status. */ +#define I2CFSTA_SRXFSTA_MSK (0x3 << 2 ) +#define I2CFSTA_SRXFSTA_EMPTY (0x0 << 2 ) /* EMPTY */ +#define I2CFSTA_SRXFSTA_ONEBYTE (0x1 << 2 ) /* ONEBYTE */ +#define I2CFSTA_SRXFSTA_TWOBYTES (0x2 << 2 ) /* TWOBYTES */ + +/* I2CFSTA[STXFSTA] - Slave Transmit FIFO status. */ +#define I2CFSTA_STXFSTA_MSK (0x3 << 0 ) +#define I2CFSTA_STXFSTA_EMPTY (0x0 << 0 ) /* EMPTY */ +#define I2CFSTA_STXFSTA_ONEBYTE (0x1 << 0 ) /* ONEBYTE */ +#define I2CFSTA_STXFSTA_TWOBYTES (0x2 << 0 ) /* TWOBYTES */ +// ------------------------------------------------------------------------------------------------ +// ----- INTERRUPT ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief Interrupts (pADI_INTERRUPT) + */ + +#if (__NO_MMR_STRUCTS__==0) +typedef struct { /*!< pADI_INTERRUPT Structure */ + __IO uint16_t EI0CFG; /*!< External Interrupt Configuration Register 0 */ + __I uint16_t RESERVED0; + __IO uint16_t EI1CFG; /*!< External Interrupt Configuration Register 1 */ + __I uint16_t RESERVED1; + __IO uint16_t EI2CFG; /*!< External Interrupt Configuration Register 2 */ + __I uint16_t RESERVED2[3]; + __IO uint16_t EICLR; /*!< External Interrupts Clear Register */ + __I uint16_t RESERVED3; + __IO uint8_t NMICLR; /*!< NMI Clear Register */ +} ADI_INTERRUPT_TypeDef; +#else // (__NO_MMR_STRUCTS__==0) +#define EI0CFG (*(volatile unsigned short int *) 0x40002420) +#define EI1CFG (*(volatile unsigned short int *) 0x40002424) +#define EI2CFG (*(volatile unsigned short int *) 0x40002428) +#define EICLR (*(volatile unsigned short int *) 0x40002430) +#define NMICLR (*(volatile unsigned char *) 0x40002434) +#endif // (__NO_MMR_STRUCTS__==0) + +/* Reset Value for EI0CFG*/ +#define EI0CFG_RVAL 0x0 + +/* EI0CFG[IRQ3EN] - External interrupt 3 enable bit. */ +#define EI0CFG_IRQ3EN_BBA (*(volatile unsigned long *) 0x4204843C) +#define EI0CFG_IRQ3EN_MSK (0x1 << 15 ) +#define EI0CFG_IRQ3EN (0x1 << 15 ) +#define EI0CFG_IRQ3EN_DIS (0x0 << 15 ) /* DIS. External interrupt 3 disabled. */ +#define EI0CFG_IRQ3EN_EN (0x1 << 15 ) /* EN. External Interrupt 3 enabled. */ + +/* EI0CFG[IRQ3MDE] - External interrupt 3 detection mode. */ +#define EI0CFG_IRQ3MDE_MSK (0x7 << 12 ) +#define EI0CFG_IRQ3MDE_RISE (0x0 << 12 ) /* RISE. Rising edge. */ +#define EI0CFG_IRQ3MDE_FALL (0x1 << 12 ) /* FALL. Falling edge. */ +#define EI0CFG_IRQ3MDE_RISEORFALL (0x2 << 12 ) /* RISEORFALL. Rising or falling edge. */ +#define EI0CFG_IRQ3MDE_HIGHLEVEL (0x3 << 12 ) /* HIGHLEVEL. High level. */ +#define EI0CFG_IRQ3MDE_LOWLEVEL (0x4 << 12 ) /* LOWLEVEL. Low level. */ + +/* EI0CFG[IRQ2EN] - External interrupt 2 enable bit. */ +#define EI0CFG_IRQ2EN_BBA (*(volatile unsigned long *) 0x4204842C) +#define EI0CFG_IRQ2EN_MSK (0x1 << 11 ) +#define EI0CFG_IRQ2EN (0x1 << 11 ) +#define EI0CFG_IRQ2EN_DIS (0x0 << 11 ) /* DIS. External interrupt 2 disabled. */ +#define EI0CFG_IRQ2EN_EN (0x1 << 11 ) /* EN. External Interrupt 2 enabled. */ + +/* EI0CFG[IRQ2MDE] - External interrupt 2 detection mode. */ +#define EI0CFG_IRQ2MDE_MSK (0x7 << 8 ) +#define EI0CFG_IRQ2MDE_RISE (0x0 << 8 ) /* RISE. Rising edge. */ +#define EI0CFG_IRQ2MDE_FALL (0x1 << 8 ) /* FALL. Falling edge. */ +#define EI0CFG_IRQ2MDE_RISEORFALL (0x2 << 8 ) /* RISEORFALL. Rising or falling edge. */ +#define EI0CFG_IRQ2MDE_HIGHLEVEL (0x3 << 8 ) /* HIGHLEVEL. High level. */ +#define EI0CFG_IRQ2MDE_LOWLEVEL (0x4 << 8 ) /* LOWLEVEL. Low level. */ + +/* EI0CFG[IRQ1EN] - External interrupt 1 enable bit. */ +#define EI0CFG_IRQ1EN_BBA (*(volatile unsigned long *) 0x4204841C) +#define EI0CFG_IRQ1EN_MSK (0x1 << 7 ) +#define EI0CFG_IRQ1EN (0x1 << 7 ) +#define EI0CFG_IRQ1EN_DIS (0x0 << 7 ) /* DIS. External interrupt 1 disabled. */ +#define EI0CFG_IRQ1EN_EN (0x1 << 7 ) /* EN. External Interrupt 1 enabled. */ + +/* EI0CFG[IRQ1MDE] - External interrupt 1 detection mode. */ +#define EI0CFG_IRQ1MDE_MSK (0x7 << 4 ) +#define EI0CFG_IRQ1MDE_RISE (0x0 << 4 ) /* RISE. Rising edge. */ +#define EI0CFG_IRQ1MDE_FALL (0x1 << 4 ) /* FALL. Falling edge. */ +#define EI0CFG_IRQ1MDE_RISEORFALL (0x2 << 4 ) /* RISEORFALL. Rising or falling edge. */ +#define EI0CFG_IRQ1MDE_HIGHLEVEL (0x3 << 4 ) /* HIGHLEVEL. High level. */ +#define EI0CFG_IRQ1MDE_LOWLEVEL (0x4 << 4 ) /* LOWLEVEL. Low level. */ + +/* EI0CFG[IRQ0EN] - RF transceiver clock IRQ enable bit. */ +#define EI0CFG_IRQ0EN_BBA (*(volatile unsigned long *) 0x4204840C) +#define EI0CFG_IRQ0EN_MSK (0x1 << 3 ) +#define EI0CFG_IRQ0EN (0x1 << 3 ) +#define EI0CFG_IRQ0EN_DIS (0x0 << 3 ) /* DIS. RF transceiver clock IRQ disabled. */ +#define EI0CFG_IRQ0EN_EN (0x1 << 3 ) /* EN. RF transceiver clock IRQ enabled. */ + +/* EI0CFG[IRQ0MDE] - RF transceiver clock detection mode. */ +#define EI0CFG_IRQ0MDE_MSK (0x7 << 0 ) +#define EI0CFG_IRQ0MDE_RISE (0x0 << 0 ) /* RISE. Rising edge. */ +#define EI0CFG_IRQ0MDE_FALL (0x1 << 0 ) /* FALL. Falling edge. */ +#define EI0CFG_IRQ0MDE_RISEORFALL (0x2 << 0 ) /* RISEORFALL. Rising or falling edge. */ +#define EI0CFG_IRQ0MDE_HIGHLEVEL (0x3 << 0 ) /* HIGHLEVEL. High level. */ +#define EI0CFG_IRQ0MDE_LOWLEVEL (0x4 << 0 ) /* LOWLEVEL. Low level. */ + +/* Reset Value for EI1CFG*/ +#define EI1CFG_RVAL 0x0 + +/* EI1CFG[IRQ7EN] - External interrupt 7 enable bit. */ +#define EI1CFG_IRQ7EN_BBA (*(volatile unsigned long *) 0x420484BC) +#define EI1CFG_IRQ7EN_MSK (0x1 << 15 ) +#define EI1CFG_IRQ7EN (0x1 << 15 ) +#define EI1CFG_IRQ7EN_DIS (0x0 << 15 ) /* DIS. External interrupt 7 disabled. */ +#define EI1CFG_IRQ7EN_EN (0x1 << 15 ) /* EN. External interrupt 7 enabled. */ + +/* EI1CFG[IRQ7MDE] - External interrupt 7 detection mode. */ +#define EI1CFG_IRQ7MDE_MSK (0x7 << 12 ) +#define EI1CFG_IRQ7MDE_RISE (0x0 << 12 ) /* RISE. Rising edge. */ +#define EI1CFG_IRQ7MDE_FALL (0x1 << 12 ) /* FALL. Falling edge. */ +#define EI1CFG_IRQ7MDE_RISEORFALL (0x2 << 12 ) /* RISEORFALL. Rising or falling edge. */ +#define EI1CFG_IRQ7MDE_HIGHLEVEL (0x3 << 12 ) /* HIGHLEVEL. High level. */ +#define EI1CFG_IRQ7MDE_LOWLEVEL (0x4 << 12 ) /* LOWLEVEL. Low level. */ + +/* EI1CFG[IRQ6EN] - External interrupt 6 enable bit. */ +#define EI1CFG_IRQ6EN_BBA (*(volatile unsigned long *) 0x420484AC) +#define EI1CFG_IRQ6EN_MSK (0x1 << 11 ) +#define EI1CFG_IRQ6EN (0x1 << 11 ) +#define EI1CFG_IRQ6EN_DIS (0x0 << 11 ) /* DIS. External interrupt 6 disabled. */ +#define EI1CFG_IRQ6EN_EN (0x1 << 11 ) /* EN. External Interrupt 6 enabled. */ + +/* EI1CFG[IRQ6MDE] - External interrupt 6 detection mode. */ +#define EI1CFG_IRQ6MDE_MSK (0x7 << 8 ) +#define EI1CFG_IRQ6MDE_RISE (0x0 << 8 ) /* RISE. Rising edge. */ +#define EI1CFG_IRQ6MDE_FALL (0x1 << 8 ) /* FALL. Falling edge. */ +#define EI1CFG_IRQ6MDE_RISEORFALL (0x2 << 8 ) /* RISEORFALL. Rising or falling edge. */ +#define EI1CFG_IRQ6MDE_HIGHLEVEL (0x3 << 8 ) /* HIGHLEVEL. High level. */ +#define EI1CFG_IRQ6MDE_LOWLEVEL (0x4 << 8 ) /* LOWLEVEL. Low Level. */ + +/* EI1CFG[IRQ5EN] - External interrupt 5 enable bit. */ +#define EI1CFG_IRQ5EN_BBA (*(volatile unsigned long *) 0x4204849C) +#define EI1CFG_IRQ5EN_MSK (0x1 << 7 ) +#define EI1CFG_IRQ5EN (0x1 << 7 ) +#define EI1CFG_IRQ5EN_DIS (0x0 << 7 ) /* DIS. External interrupt 5 disabled. */ +#define EI1CFG_IRQ5EN_EN (0x1 << 7 ) /* EN. External Interrupt 5 enabled. */ + +/* EI1CFG[IRQ5MDE] - External interrupt 5 detection mode. */ +#define EI1CFG_IRQ5MDE_MSK (0x7 << 4 ) +#define EI1CFG_IRQ5MDE_RISE (0x0 << 4 ) /* RISE. Rising edge. */ +#define EI1CFG_IRQ5MDE_FALL (0x1 << 4 ) /* FALL. Falling edge. */ +#define EI1CFG_IRQ5MDE_RISEORFALL (0x2 << 4 ) /* RISEORFALL. Rising or falling edge. */ +#define EI1CFG_IRQ5MDE_HIGHLEVEL (0x3 << 4 ) /* HIGHLEVEL. High level. */ +#define EI1CFG_IRQ5MDE_LOWLEVEL (0x4 << 4 ) /* LOWLEVEL. Low Level. */ + +/* EI1CFG[IRQ4EN] - External interrupt 4 enable bit. */ +#define EI1CFG_IRQ4EN_BBA (*(volatile unsigned long *) 0x4204848C) +#define EI1CFG_IRQ4EN_MSK (0x1 << 3 ) +#define EI1CFG_IRQ4EN (0x1 << 3 ) +#define EI1CFG_IRQ4EN_DIS (0x0 << 3 ) /* DIS. External interrupt 4 disabled. */ +#define EI1CFG_IRQ4EN_EN (0x1 << 3 ) /* EN. External Interrupt 4 enabled. */ + +/* EI1CFG[IRQ4MDE] - External interrupt 4 detection mode. */ +#define EI1CFG_IRQ4MDE_MSK (0x7 << 0 ) +#define EI1CFG_IRQ4MDE_RISE (0x0 << 0 ) /* RISE. Rising edge. */ +#define EI1CFG_IRQ4MDE_FALL (0x1 << 0 ) /* FALL. Falling edge. */ +#define EI1CFG_IRQ4MDE_RISEORFALL (0x2 << 0 ) /* RISEORFALL. Rising or falling edge. */ +#define EI1CFG_IRQ4MDE_HIGHLEVEL (0x3 << 0 ) /* HIGHLEVEL. High level. */ +#define EI1CFG_IRQ4MDE_LOWLEVEL (0x4 << 0 ) /* LOWLEVEL. Low Level. */ + +/* Reset Value for EI2CFG*/ +#define EI2CFG_RVAL 0x0 + +/* EI2CFG[IRQ8EN] - RF transceiver IRQ enable bit. */ +#define EI2CFG_IRQ8EN_BBA (*(volatile unsigned long *) 0x4204850C) +#define EI2CFG_IRQ8EN_MSK (0x1 << 3 ) +#define EI2CFG_IRQ8EN (0x1 << 3 ) +#define EI2CFG_IRQ8EN_DIS (0x0 << 3 ) /* DIS. RF transceiver IRQ disabled. */ +#define EI2CFG_IRQ8EN_EN (0x1 << 3 ) /* EN. RF transceiver IRQ enabled. */ + +/* EI2CFG[IRQ8MDE] - RF transceiver IRQ detection mode. */ +#define EI2CFG_IRQ8MDE_MSK (0x7 << 0 ) +#define EI2CFG_IRQ8MDE_RISE (0x0 << 0 ) /* RISE. Rising edge. */ +#define EI2CFG_IRQ8MDE_FALL (0x1 << 0 ) /* FALL. Falling edge. */ +#define EI2CFG_IRQ8MDE_RISEORFALL (0x2 << 0 ) /* RISEORFALL. Rising or falling edge. */ +#define EI2CFG_IRQ8MDE_HIGHLEVEL (0x3 << 0 ) /* HIGHLEVEL. High level. */ +#define EI2CFG_IRQ8MDE_LOWLEVEL (0x4 << 0 ) /* LOWLEVEL. Low level. */ + +/* Reset Value for EICLR*/ +#define EICLR_RVAL 0x0 + +/* EICLR[IRQ8] - External interrupt 8 (RF transceiver) clear bit. */ +#define EICLR_IRQ8_BBA (*(volatile unsigned long *) 0x42048620) +#define EICLR_IRQ8_MSK (0x1 << 8 ) +#define EICLR_IRQ8 (0x1 << 8 ) +#define EICLR_IRQ8_CLR (0x1 << 8 ) /* CLR. Clear an internal interrupt flag. */ + +/* EICLR[IRQ7] - External interrupt 7 clear bit. */ +#define EICLR_IRQ7_BBA (*(volatile unsigned long *) 0x4204861C) +#define EICLR_IRQ7_MSK (0x1 << 7 ) +#define EICLR_IRQ7 (0x1 << 7 ) +#define EICLR_IRQ7_CLR (0x1 << 7 ) /* CLR. Clear an internal interrupt flag. */ + +/* EICLR[IRQ6] - External interrupt 6 clear bit. */ +#define EICLR_IRQ6_BBA (*(volatile unsigned long *) 0x42048618) +#define EICLR_IRQ6_MSK (0x1 << 6 ) +#define EICLR_IRQ6 (0x1 << 6 ) +#define EICLR_IRQ6_CLR (0x1 << 6 ) /* CLR. Clear an internal interrupt flag. */ + +/* EICLR[IRQ5] - External interrupt 5 clear bit. */ +#define EICLR_IRQ5_BBA (*(volatile unsigned long *) 0x42048614) +#define EICLR_IRQ5_MSK (0x1 << 5 ) +#define EICLR_IRQ5 (0x1 << 5 ) +#define EICLR_IRQ5_CLR (0x1 << 5 ) /* CLR. Clear an internal interrupt flag. */ + +/* EICLR[IRQ4] - External interrupt 4 clear bit. */ +#define EICLR_IRQ4_BBA (*(volatile unsigned long *) 0x42048610) +#define EICLR_IRQ4_MSK (0x1 << 4 ) +#define EICLR_IRQ4 (0x1 << 4 ) +#define EICLR_IRQ4_CLR (0x1 << 4 ) /* CLR. Clear an internal interrupt flag. */ + +/* EICLR[IRQ3] - External interrupt 3 clear bit. */ +#define EICLR_IRQ3_BBA (*(volatile unsigned long *) 0x4204860C) +#define EICLR_IRQ3_MSK (0x1 << 3 ) +#define EICLR_IRQ3 (0x1 << 3 ) +#define EICLR_IRQ3_CLR (0x1 << 3 ) /* CLR. Clear an internal interrupt flag. */ + +/* EICLR[IRQ2] - External interrupt 2 clear bit. */ +#define EICLR_IRQ2_BBA (*(volatile unsigned long *) 0x42048608) +#define EICLR_IRQ2_MSK (0x1 << 2 ) +#define EICLR_IRQ2 (0x1 << 2 ) +#define EICLR_IRQ2_CLR (0x1 << 2 ) /* CLR. Clear an internal interrupt flag. */ + +/* EICLR[IRQ1] - External interrupt 1 clear bit. */ +#define EICLR_IRQ1_BBA (*(volatile unsigned long *) 0x42048604) +#define EICLR_IRQ1_MSK (0x1 << 1 ) +#define EICLR_IRQ1 (0x1 << 1 ) +#define EICLR_IRQ1_CLR (0x1 << 1 ) /* CLR. Clear an internal interrupt flag. */ + +/* EICLR[IRQ0] - External interrupt 0 clear bit. */ +#define EICLR_IRQ0_BBA (*(volatile unsigned long *) 0x42048600) +#define EICLR_IRQ0_MSK (0x1 << 0 ) +#define EICLR_IRQ0 (0x1 << 0 ) +#define EICLR_IRQ0_CLR (0x1 << 0 ) /* CLR. Clear an internal interrupt flag. */ + +/* Reset Value for NMICLR*/ +#define NMICLR_RVAL 0x0 + +/* NMICLR[CLEAR] - NMI clear bit. */ +#define NMICLR_CLEAR_BBA (*(volatile unsigned long *) 0x42048680) +#define NMICLR_CLEAR_MSK (0x1 << 0 ) +#define NMICLR_CLEAR (0x1 << 0 ) +#define NMICLR_CLEAR_EN (0x1 << 0 ) /* EN. Clear an internal interrupt flag when the NMI interrupt is set. */ +// ------------------------------------------------------------------------------------------------ +// ----- NVIC ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief Nested Vectored Interrupt Controller (pADI_NVIC) + */ + +#if (__NO_MMR_STRUCTS__==0) +#else // (__NO_MMR_STRUCTS__==0) +#define ICTR (*(volatile unsigned long *) 0xE000E004) +#define STCSR (*(volatile unsigned long *) 0xE000E010) +#define STRVR (*(volatile unsigned long *) 0xE000E014) +#define STCVR (*(volatile unsigned long *) 0xE000E018) +#define STCR (*(volatile unsigned long *) 0xE000E01C) +#define ISER0 (*(volatile unsigned long *) 0xE000E100) +#define ISER1 (*(volatile unsigned long *) 0xE000E104) +#define ICER0 (*(volatile unsigned long *) 0xE000E180) +#define ICER1 (*(volatile unsigned long *) 0xE000E184) +#define ISPR0 (*(volatile unsigned long *) 0xE000E200) +#define ISPR1 (*(volatile unsigned long *) 0xE000E204) +#define ICPR0 (*(volatile unsigned long *) 0xE000E280) +#define ICPR1 (*(volatile unsigned long *) 0xE000E284) +#define IABR0 (*(volatile unsigned long *) 0xE000E300) +#define IABR1 (*(volatile unsigned long *) 0xE000E304) +#define IPR0 (*(volatile unsigned long *) 0xE000E400) +#define IPR1 (*(volatile unsigned long *) 0xE000E404) +#define IPR2 (*(volatile unsigned long *) 0xE000E408) +#define IPR3 (*(volatile unsigned long *) 0xE000E40C) +#define IPR4 (*(volatile unsigned long *) 0xE000E410) +#define IPR5 (*(volatile unsigned long *) 0xE000E414) +#define IPR6 (*(volatile unsigned long *) 0xE000E418) +#define IPR7 (*(volatile unsigned long *) 0xE000E41C) +#define IPR8 (*(volatile unsigned long *) 0xE000E420) +#define IPR9 (*(volatile unsigned long *) 0xE000E424) +#define IPR10 (*(volatile unsigned long *) 0xE000E428) +#define CPUID (*(volatile unsigned long *) 0xE000ED00) +#define ICSR (*(volatile unsigned long *) 0xE000ED04) +#define VTOR (*(volatile unsigned long *) 0xE000ED08) +#define AIRCR (*(volatile unsigned long *) 0xE000ED0C) +#define SCR (*(volatile unsigned long *) 0xE000ED10) +#define CCR (*(volatile unsigned long *) 0xE000ED14) +#define SHPR1 (*(volatile unsigned long *) 0xE000ED18) +#define SHPR2 (*(volatile unsigned long *) 0xE000ED1C) +#define SHPR3 (*(volatile unsigned long *) 0xE000ED20) +#define SHCSR (*(volatile unsigned long *) 0xE000ED24) +#define CFSR (*(volatile unsigned long *) 0xE000ED28) +#define HFSR (*(volatile unsigned long *) 0xE000ED2C) +#define MMFAR (*(volatile unsigned long *) 0xE000ED34) +#define BFAR (*(volatile unsigned long *) 0xE000ED38) +#define STIR (*(volatile unsigned long *) 0xE000EF00) +#endif // (__NO_MMR_STRUCTS__==0) + +/* Reset Value for ICTR*/ +#define ICTR_RVAL 0x1 + +/* ICTR[INTLINESNUM] - Total number of interrupt lines in groups of 32 */ +#define ICTR_INTLINESNUM_MSK (0xF << 0 ) + +/* Reset Value for STCSR*/ +#define STCSR_RVAL 0x0 + +/* STCSR[COUNTFLAG] - Returns 1 if timer counted to 0 since last time this register was read */ +#define STCSR_COUNTFLAG_MSK (0x1 << 16 ) +#define STCSR_COUNTFLAG (0x1 << 16 ) +#define STCSR_COUNTFLAG_DIS (0x0 << 16 ) /* DIS */ +#define STCSR_COUNTFLAG_EN (0x1 << 16 ) /* EN */ + +/* STCSR[CLKSOURCE] - clock source used for SysTick */ +#define STCSR_CLKSOURCE_MSK (0x1 << 2 ) +#define STCSR_CLKSOURCE (0x1 << 2 ) +#define STCSR_CLKSOURCE_DIS (0x0 << 2 ) /* DIS */ +#define STCSR_CLKSOURCE_EN (0x1 << 2 ) /* EN */ + +/* STCSR[TICKINT] - If 1, counting down to 0 will cause the SysTick exception to pended. */ +#define STCSR_TICKINT_MSK (0x1 << 1 ) +#define STCSR_TICKINT (0x1 << 1 ) +#define STCSR_TICKINT_DIS (0x0 << 1 ) /* DIS */ +#define STCSR_TICKINT_EN (0x1 << 1 ) /* EN */ + +/* STCSR[ENABLE] - Enable bit */ +#define STCSR_ENABLE_MSK (0x1 << 0 ) +#define STCSR_ENABLE (0x1 << 0 ) +#define STCSR_ENABLE_DIS (0x0 << 0 ) /* DIS */ +#define STCSR_ENABLE_EN (0x1 << 0 ) /* EN */ + +/* Reset Value for STRVR*/ +#define STRVR_RVAL 0x0 + +/* STRVR[RELOAD] - Value to load into the Current Value register when the counter reaches 0 */ +#define STRVR_RELOAD_MSK (0xFFFFFF << 0 ) + +/* Reset Value for STCVR*/ +#define STCVR_RVAL 0x0 + +/* STCVR[CURRENT] - Current counter value */ +#define STCVR_CURRENT_MSK (0xFFFFFFFF << 0 ) + +/* Reset Value for STCR*/ +#define STCR_RVAL 0x0 + +/* STCR[NOREF] - If reads as 1, the Reference clock is not provided */ +#define STCR_NOREF_MSK (0x1 << 31 ) +#define STCR_NOREF (0x1 << 31 ) +#define STCR_NOREF_DIS (0x0 << 31 ) /* DIS */ +#define STCR_NOREF_EN (0x1 << 31 ) /* EN */ + +/* STCR[SKEW] - If reads as 1, the calibration value for 10ms is inexact */ +#define STCR_SKEW_MSK (0x1 << 30 ) +#define STCR_SKEW (0x1 << 30 ) +#define STCR_SKEW_DIS (0x0 << 30 ) /* DIS */ +#define STCR_SKEW_EN (0x1 << 30 ) /* EN */ + +/* STCR[TENMS] - An optional Reload value to be used for 10ms (100Hz) timing */ +#define STCR_TENMS_MSK (0xFFFFFF << 0 ) + +/* Reset Value for ISER0*/ +#define ISER0_RVAL 0x0 + +/* ISER0[DMAI2CMRX] - */ +#define ISER0_DMAI2CMRX_MSK (0x1 << 30 ) +#define ISER0_DMAI2CMRX (0x1 << 30 ) +#define ISER0_DMAI2CMRX_DIS (0x0 << 30 ) /* DIS */ +#define ISER0_DMAI2CMRX_EN (0x1 << 30 ) /* EN */ + +/* ISER0[DMAI2CMTX] - */ +#define ISER0_DMAI2CMTX_MSK (0x1 << 29 ) +#define ISER0_DMAI2CMTX (0x1 << 29 ) +#define ISER0_DMAI2CMTX_DIS (0x0 << 29 ) /* DIS */ +#define ISER0_DMAI2CMTX_EN (0x1 << 29 ) /* EN */ + +/* ISER0[DMAI2CSRX] - */ +#define ISER0_DMAI2CSRX_MSK (0x1 << 28 ) +#define ISER0_DMAI2CSRX (0x1 << 28 ) +#define ISER0_DMAI2CSRX_DIS (0x0 << 28 ) /* DIS */ +#define ISER0_DMAI2CSRX_EN (0x1 << 28 ) /* EN */ + +/* ISER0[DMAI2CSTX] - */ +#define ISER0_DMAI2CSTX_MSK (0x1 << 27 ) +#define ISER0_DMAI2CSTX (0x1 << 27 ) +#define ISER0_DMAI2CSTX_DIS (0x0 << 27 ) /* DIS */ +#define ISER0_DMAI2CSTX_EN (0x1 << 27 ) /* EN */ + +/* ISER0[DMAUARTRX] - */ +#define ISER0_DMAUARTRX_MSK (0x1 << 26 ) +#define ISER0_DMAUARTRX (0x1 << 26 ) +#define ISER0_DMAUARTRX_DIS (0x0 << 26 ) /* DIS */ +#define ISER0_DMAUARTRX_EN (0x1 << 26 ) /* EN */ + +/* ISER0[DMAUARTTX] - */ +#define ISER0_DMAUARTTX_MSK (0x1 << 25 ) +#define ISER0_DMAUARTTX (0x1 << 25 ) +#define ISER0_DMAUARTTX_DIS (0x0 << 25 ) /* DIS */ +#define ISER0_DMAUARTTX_EN (0x1 << 25 ) /* EN */ + +/* ISER0[DMASPI1RX] - */ +#define ISER0_DMASPI1RX_MSK (0x1 << 24 ) +#define ISER0_DMASPI1RX (0x1 << 24 ) +#define ISER0_DMASPI1RX_DIS (0x0 << 24 ) /* DIS */ +#define ISER0_DMASPI1RX_EN (0x1 << 24 ) /* EN */ + +/* ISER0[DMASPI1TX] - */ +#define ISER0_DMASPI1TX_MSK (0x1 << 23 ) +#define ISER0_DMASPI1TX (0x1 << 23 ) +#define ISER0_DMASPI1TX_DIS (0x0 << 23 ) /* DIS */ +#define ISER0_DMASPI1TX_EN (0x1 << 23 ) /* EN */ + +/* ISER0[DMAERROR] - */ +#define ISER0_DMAERROR_MSK (0x1 << 22 ) +#define ISER0_DMAERROR (0x1 << 22 ) +#define ISER0_DMAERROR_DIS (0x0 << 22 ) /* DIS */ +#define ISER0_DMAERROR_EN (0x1 << 22 ) /* EN */ + +/* ISER0[I2CM] - */ +#define ISER0_I2CM_MSK (0x1 << 20 ) +#define ISER0_I2CM (0x1 << 20 ) +#define ISER0_I2CM_DIS (0x0 << 20 ) /* DIS */ +#define ISER0_I2CM_EN (0x1 << 20 ) /* EN */ + +/* ISER0[I2CS] - */ +#define ISER0_I2CS_MSK (0x1 << 19 ) +#define ISER0_I2CS (0x1 << 19 ) +#define ISER0_I2CS_DIS (0x0 << 19 ) /* DIS */ +#define ISER0_I2CS_EN (0x1 << 19 ) /* EN */ + +/* ISER0[SPI1] - */ +#define ISER0_SPI1_MSK (0x1 << 18 ) +#define ISER0_SPI1 (0x1 << 18 ) +#define ISER0_SPI1_DIS (0x0 << 18 ) /* DIS */ +#define ISER0_SPI1_EN (0x1 << 18 ) /* EN */ + +/* ISER0[SPI0] - */ +#define ISER0_SPI0_MSK (0x1 << 17 ) +#define ISER0_SPI0 (0x1 << 17 ) +#define ISER0_SPI0_DIS (0x0 << 17 ) /* DIS */ +#define ISER0_SPI0_EN (0x1 << 17 ) /* EN */ + +/* ISER0[UART] - */ +#define ISER0_UART_MSK (0x1 << 16 ) +#define ISER0_UART (0x1 << 16 ) +#define ISER0_UART_DIS (0x0 << 16 ) /* DIS */ +#define ISER0_UART_EN (0x1 << 16 ) /* EN */ + +/* ISER0[FEE] - */ +#define ISER0_FEE_MSK (0x1 << 15 ) +#define ISER0_FEE (0x1 << 15 ) +#define ISER0_FEE_DIS (0x0 << 15 ) /* DIS */ +#define ISER0_FEE_EN (0x1 << 15 ) /* EN */ + +/* ISER0[ADC] - */ +#define ISER0_ADC_MSK (0x1 << 14 ) +#define ISER0_ADC (0x1 << 14 ) +#define ISER0_ADC_DIS (0x0 << 14 ) /* DIS */ +#define ISER0_ADC_EN (0x1 << 14 ) /* EN */ + +/* ISER0[T1] - */ +#define ISER0_T1_MSK (0x1 << 13 ) +#define ISER0_T1 (0x1 << 13 ) +#define ISER0_T1_DIS (0x0 << 13 ) /* DIS */ +#define ISER0_T1_EN (0x1 << 13 ) /* EN */ + +/* ISER0[T0] - */ +#define ISER0_T0_MSK (0x1 << 12 ) +#define ISER0_T0 (0x1 << 12 ) +#define ISER0_T0_DIS (0x0 << 12 ) /* DIS */ +#define ISER0_T0_EN (0x1 << 12 ) /* EN */ + +/* ISER0[T3] - */ +#define ISER0_T3_MSK (0x1 << 10 ) +#define ISER0_T3 (0x1 << 10 ) +#define ISER0_T3_DIS (0x0 << 10 ) /* DIS */ +#define ISER0_T3_EN (0x1 << 10 ) /* EN */ + +/* ISER0[EXTINT8] - */ +#define ISER0_EXTINT8_MSK (0x1 << 9 ) +#define ISER0_EXTINT8 (0x1 << 9 ) +#define ISER0_EXTINT8_DIS (0x0 << 9 ) /* DIS */ +#define ISER0_EXTINT8_EN (0x1 << 9 ) /* EN */ + +/* ISER0[EXTINT7] - */ +#define ISER0_EXTINT7_MSK (0x1 << 8 ) +#define ISER0_EXTINT7 (0x1 << 8 ) +#define ISER0_EXTINT7_DIS (0x0 << 8 ) /* DIS */ +#define ISER0_EXTINT7_EN (0x1 << 8 ) /* EN */ + +/* ISER0[EXTINT6] - */ +#define ISER0_EXTINT6_MSK (0x1 << 7 ) +#define ISER0_EXTINT6 (0x1 << 7 ) +#define ISER0_EXTINT6_DIS (0x0 << 7 ) /* DIS */ +#define ISER0_EXTINT6_EN (0x1 << 7 ) /* EN */ + +/* ISER0[EXTINT5] - */ +#define ISER0_EXTINT5_MSK (0x1 << 6 ) +#define ISER0_EXTINT5 (0x1 << 6 ) +#define ISER0_EXTINT5_DIS (0x0 << 6 ) /* DIS */ +#define ISER0_EXTINT5_EN (0x1 << 6 ) /* EN */ + +/* ISER0[EXTINT4] - */ +#define ISER0_EXTINT4_MSK (0x1 << 5 ) +#define ISER0_EXTINT4 (0x1 << 5 ) +#define ISER0_EXTINT4_DIS (0x0 << 5 ) /* DIS */ +#define ISER0_EXTINT4_EN (0x1 << 5 ) /* EN */ + +/* ISER0[EXTINT3] - */ +#define ISER0_EXTINT3_MSK (0x1 << 4 ) +#define ISER0_EXTINT3 (0x1 << 4 ) +#define ISER0_EXTINT3_DIS (0x0 << 4 ) /* DIS */ +#define ISER0_EXTINT3_EN (0x1 << 4 ) /* EN */ + +/* ISER0[EXTINT2] - */ +#define ISER0_EXTINT2_MSK (0x1 << 3 ) +#define ISER0_EXTINT2 (0x1 << 3 ) +#define ISER0_EXTINT2_DIS (0x0 << 3 ) /* DIS */ +#define ISER0_EXTINT2_EN (0x1 << 3 ) /* EN */ + +/* ISER0[EXTINT1] - */ +#define ISER0_EXTINT1_MSK (0x1 << 2 ) +#define ISER0_EXTINT1 (0x1 << 2 ) +#define ISER0_EXTINT1_DIS (0x0 << 2 ) /* DIS */ +#define ISER0_EXTINT1_EN (0x1 << 2 ) /* EN */ + +/* ISER0[EXTINT0] - */ +#define ISER0_EXTINT0_MSK (0x1 << 1 ) +#define ISER0_EXTINT0 (0x1 << 1 ) +#define ISER0_EXTINT0_DIS (0x0 << 1 ) /* DIS */ +#define ISER0_EXTINT0_EN (0x1 << 1 ) /* EN */ + +/* ISER0[T2] - */ +#define ISER0_T2_MSK (0x1 << 0 ) +#define ISER0_T2 (0x1 << 0 ) +#define ISER0_T2_DIS (0x0 << 0 ) /* DIS */ +#define ISER0_T2_EN (0x1 << 0 ) /* EN */ + +/* Reset Value for ISER1*/ +#define ISER1_RVAL 0x0 + +/* ISER1[PWM3] - */ +#define ISER1_PWM3_MSK (0x1 << 9 ) +#define ISER1_PWM3 (0x1 << 9 ) +#define ISER1_PWM3_DIS (0x0 << 9 ) /* DIS */ +#define ISER1_PWM3_EN (0x1 << 9 ) /* EN */ + +/* ISER1[PWM2] - */ +#define ISER1_PWM2_MSK (0x1 << 8 ) +#define ISER1_PWM2 (0x1 << 8 ) +#define ISER1_PWM2_DIS (0x0 << 8 ) /* DIS */ +#define ISER1_PWM2_EN (0x1 << 8 ) /* EN */ + +/* ISER1[PWM1] - */ +#define ISER1_PWM1_MSK (0x1 << 7 ) +#define ISER1_PWM1 (0x1 << 7 ) +#define ISER1_PWM1_DIS (0x0 << 7 ) /* DIS */ +#define ISER1_PWM1_EN (0x1 << 7 ) /* EN */ + +/* ISER1[PWM0] - */ +#define ISER1_PWM0_MSK (0x1 << 6 ) +#define ISER1_PWM0 (0x1 << 6 ) +#define ISER1_PWM0_DIS (0x0 << 6 ) /* DIS */ +#define ISER1_PWM0_EN (0x1 << 6 ) /* EN */ + +/* ISER1[PWMTRIP] - */ +#define ISER1_PWMTRIP_MSK (0x1 << 5 ) +#define ISER1_PWMTRIP (0x1 << 5 ) +#define ISER1_PWMTRIP_DIS (0x0 << 5 ) /* DIS */ +#define ISER1_PWMTRIP_EN (0x1 << 5 ) /* EN */ + +/* ISER1[DMASPI0RX] - */ +#define ISER1_DMASPI0RX_MSK (0x1 << 4 ) +#define ISER1_DMASPI0RX (0x1 << 4 ) +#define ISER1_DMASPI0RX_DIS (0x0 << 4 ) /* DIS */ +#define ISER1_DMASPI0RX_EN (0x1 << 4 ) /* EN */ + +/* ISER1[DMASPI0TX] - */ +#define ISER1_DMASPI0TX_MSK (0x1 << 3 ) +#define ISER1_DMASPI0TX (0x1 << 3 ) +#define ISER1_DMASPI0TX_DIS (0x0 << 3 ) /* DIS */ +#define ISER1_DMASPI0TX_EN (0x1 << 3 ) /* EN */ + +/* ISER1[DMAADC] - */ +#define ISER1_DMAADC_MSK (0x1 << 2 ) +#define ISER1_DMAADC (0x1 << 2 ) +#define ISER1_DMAADC_DIS (0x0 << 2 ) /* DIS */ +#define ISER1_DMAADC_EN (0x1 << 2 ) /* EN */ + +/* Reset Value for ICER0*/ +#define ICER0_RVAL 0x0 + +/* ICER0[DMAI2CMRX] - */ +#define ICER0_DMAI2CMRX_MSK (0x1 << 30 ) +#define ICER0_DMAI2CMRX (0x1 << 30 ) +#define ICER0_DMAI2CMRX_DIS (0x0 << 30 ) /* DIS */ +#define ICER0_DMAI2CMRX_EN (0x1 << 30 ) /* EN */ + +/* ICER0[DMAI2CMTX] - */ +#define ICER0_DMAI2CMTX_MSK (0x1 << 29 ) +#define ICER0_DMAI2CMTX (0x1 << 29 ) +#define ICER0_DMAI2CMTX_DIS (0x0 << 29 ) /* DIS */ +#define ICER0_DMAI2CMTX_EN (0x1 << 29 ) /* EN */ + +/* ICER0[DMAI2CSRX] - */ +#define ICER0_DMAI2CSRX_MSK (0x1 << 28 ) +#define ICER0_DMAI2CSRX (0x1 << 28 ) +#define ICER0_DMAI2CSRX_DIS (0x0 << 28 ) /* DIS */ +#define ICER0_DMAI2CSRX_EN (0x1 << 28 ) /* EN */ + +/* ICER0[DMAI2CSTX] - */ +#define ICER0_DMAI2CSTX_MSK (0x1 << 27 ) +#define ICER0_DMAI2CSTX (0x1 << 27 ) +#define ICER0_DMAI2CSTX_DIS (0x0 << 27 ) /* DIS */ +#define ICER0_DMAI2CSTX_EN (0x1 << 27 ) /* EN */ + +/* ICER0[DMAUARTRX] - */ +#define ICER0_DMAUARTRX_MSK (0x1 << 26 ) +#define ICER0_DMAUARTRX (0x1 << 26 ) +#define ICER0_DMAUARTRX_DIS (0x0 << 26 ) /* DIS */ +#define ICER0_DMAUARTRX_EN (0x1 << 26 ) /* EN */ + +/* ICER0[DMAUARTTX] - */ +#define ICER0_DMAUARTTX_MSK (0x1 << 25 ) +#define ICER0_DMAUARTTX (0x1 << 25 ) +#define ICER0_DMAUARTTX_DIS (0x0 << 25 ) /* DIS */ +#define ICER0_DMAUARTTX_EN (0x1 << 25 ) /* EN */ + +/* ICER0[DMASPI1RX] - */ +#define ICER0_DMASPI1RX_MSK (0x1 << 24 ) +#define ICER0_DMASPI1RX (0x1 << 24 ) +#define ICER0_DMASPI1RX_DIS (0x0 << 24 ) /* DIS */ +#define ICER0_DMASPI1RX_EN (0x1 << 24 ) /* EN */ + +/* ICER0[DMASPI1TX] - */ +#define ICER0_DMASPI1TX_MSK (0x1 << 23 ) +#define ICER0_DMASPI1TX (0x1 << 23 ) +#define ICER0_DMASPI1TX_DIS (0x0 << 23 ) /* DIS */ +#define ICER0_DMASPI1TX_EN (0x1 << 23 ) /* EN */ + +/* ICER0[DMAERROR] - */ +#define ICER0_DMAERROR_MSK (0x1 << 22 ) +#define ICER0_DMAERROR (0x1 << 22 ) +#define ICER0_DMAERROR_DIS (0x0 << 22 ) /* DIS */ +#define ICER0_DMAERROR_EN (0x1 << 22 ) /* EN */ + +/* ICER0[I2CM] - */ +#define ICER0_I2CM_MSK (0x1 << 20 ) +#define ICER0_I2CM (0x1 << 20 ) +#define ICER0_I2CM_DIS (0x0 << 20 ) /* DIS */ +#define ICER0_I2CM_EN (0x1 << 20 ) /* EN */ + +/* ICER0[I2CS] - */ +#define ICER0_I2CS_MSK (0x1 << 19 ) +#define ICER0_I2CS (0x1 << 19 ) +#define ICER0_I2CS_DIS (0x0 << 19 ) /* DIS */ +#define ICER0_I2CS_EN (0x1 << 19 ) /* EN */ + +/* ICER0[SPI1] - */ +#define ICER0_SPI1_MSK (0x1 << 18 ) +#define ICER0_SPI1 (0x1 << 18 ) +#define ICER0_SPI1_DIS (0x0 << 18 ) /* DIS */ +#define ICER0_SPI1_EN (0x1 << 18 ) /* EN */ + +/* ICER0[SPI0] - */ +#define ICER0_SPI0_MSK (0x1 << 17 ) +#define ICER0_SPI0 (0x1 << 17 ) +#define ICER0_SPI0_DIS (0x0 << 17 ) /* DIS */ +#define ICER0_SPI0_EN (0x1 << 17 ) /* EN */ + +/* ICER0[UART] - */ +#define ICER0_UART_MSK (0x1 << 16 ) +#define ICER0_UART (0x1 << 16 ) +#define ICER0_UART_DIS (0x0 << 16 ) /* DIS */ +#define ICER0_UART_EN (0x1 << 16 ) /* EN */ + +/* ICER0[FEE] - */ +#define ICER0_FEE_MSK (0x1 << 15 ) +#define ICER0_FEE (0x1 << 15 ) +#define ICER0_FEE_DIS (0x0 << 15 ) /* DIS */ +#define ICER0_FEE_EN (0x1 << 15 ) /* EN */ + +/* ICER0[ADC] - */ +#define ICER0_ADC_MSK (0x1 << 14 ) +#define ICER0_ADC (0x1 << 14 ) +#define ICER0_ADC_DIS (0x0 << 14 ) /* DIS */ +#define ICER0_ADC_EN (0x1 << 14 ) /* EN */ + +/* ICER0[T1] - */ +#define ICER0_T1_MSK (0x1 << 13 ) +#define ICER0_T1 (0x1 << 13 ) +#define ICER0_T1_DIS (0x0 << 13 ) /* DIS */ +#define ICER0_T1_EN (0x1 << 13 ) /* EN */ + +/* ICER0[T0] - */ +#define ICER0_T0_MSK (0x1 << 12 ) +#define ICER0_T0 (0x1 << 12 ) +#define ICER0_T0_DIS (0x0 << 12 ) /* DIS */ +#define ICER0_T0_EN (0x1 << 12 ) /* EN */ + +/* ICER0[T3] - */ +#define ICER0_T3_MSK (0x1 << 10 ) +#define ICER0_T3 (0x1 << 10 ) +#define ICER0_T3_DIS (0x0 << 10 ) /* DIS */ +#define ICER0_T3_EN (0x1 << 10 ) /* EN */ + +/* ICER0[EXTINT8] - */ +#define ICER0_EXTINT8_MSK (0x1 << 9 ) +#define ICER0_EXTINT8 (0x1 << 9 ) +#define ICER0_EXTINT8_DIS (0x0 << 9 ) /* DIS */ +#define ICER0_EXTINT8_EN (0x1 << 9 ) /* EN */ + +/* ICER0[EXTINT7] - */ +#define ICER0_EXTINT7_MSK (0x1 << 8 ) +#define ICER0_EXTINT7 (0x1 << 8 ) +#define ICER0_EXTINT7_DIS (0x0 << 8 ) /* DIS */ +#define ICER0_EXTINT7_EN (0x1 << 8 ) /* EN */ + +/* ICER0[EXTINT6] - */ +#define ICER0_EXTINT6_MSK (0x1 << 7 ) +#define ICER0_EXTINT6 (0x1 << 7 ) +#define ICER0_EXTINT6_DIS (0x0 << 7 ) /* DIS */ +#define ICER0_EXTINT6_EN (0x1 << 7 ) /* EN */ + +/* ICER0[EXTINT5] - */ +#define ICER0_EXTINT5_MSK (0x1 << 6 ) +#define ICER0_EXTINT5 (0x1 << 6 ) +#define ICER0_EXTINT5_DIS (0x0 << 6 ) /* DIS */ +#define ICER0_EXTINT5_EN (0x1 << 6 ) /* EN */ + +/* ICER0[EXTINT4] - */ +#define ICER0_EXTINT4_MSK (0x1 << 5 ) +#define ICER0_EXTINT4 (0x1 << 5 ) +#define ICER0_EXTINT4_DIS (0x0 << 5 ) /* DIS */ +#define ICER0_EXTINT4_EN (0x1 << 5 ) /* EN */ + +/* ICER0[EXTINT3] - */ +#define ICER0_EXTINT3_MSK (0x1 << 4 ) +#define ICER0_EXTINT3 (0x1 << 4 ) +#define ICER0_EXTINT3_DIS (0x0 << 4 ) /* DIS */ +#define ICER0_EXTINT3_EN (0x1 << 4 ) /* EN */ + +/* ICER0[EXTINT2] - */ +#define ICER0_EXTINT2_MSK (0x1 << 3 ) +#define ICER0_EXTINT2 (0x1 << 3 ) +#define ICER0_EXTINT2_DIS (0x0 << 3 ) /* DIS */ +#define ICER0_EXTINT2_EN (0x1 << 3 ) /* EN */ + +/* ICER0[EXTINT1] - */ +#define ICER0_EXTINT1_MSK (0x1 << 2 ) +#define ICER0_EXTINT1 (0x1 << 2 ) +#define ICER0_EXTINT1_DIS (0x0 << 2 ) /* DIS */ +#define ICER0_EXTINT1_EN (0x1 << 2 ) /* EN */ + +/* ICER0[EXTINT0] - */ +#define ICER0_EXTINT0_MSK (0x1 << 1 ) +#define ICER0_EXTINT0 (0x1 << 1 ) +#define ICER0_EXTINT0_DIS (0x0 << 1 ) /* DIS */ +#define ICER0_EXTINT0_EN (0x1 << 1 ) /* EN */ + +/* ICER0[T2] - */ +#define ICER0_T2_MSK (0x1 << 0 ) +#define ICER0_T2 (0x1 << 0 ) +#define ICER0_T2_DIS (0x0 << 0 ) /* DIS */ +#define ICER0_T2_EN (0x1 << 0 ) /* EN */ + +/* Reset Value for ICER1*/ +#define ICER1_RVAL 0x0 + +/* ICER1[PWM3] - */ +#define ICER1_PWM3_MSK (0x1 << 9 ) +#define ICER1_PWM3 (0x1 << 9 ) +#define ICER1_PWM3_DIS (0x0 << 9 ) /* DIS */ +#define ICER1_PWM3_EN (0x1 << 9 ) /* EN */ + +/* ICER1[PWM2] - */ +#define ICER1_PWM2_MSK (0x1 << 8 ) +#define ICER1_PWM2 (0x1 << 8 ) +#define ICER1_PWM2_DIS (0x0 << 8 ) /* DIS */ +#define ICER1_PWM2_EN (0x1 << 8 ) /* EN */ + +/* ICER1[PWM1] - */ +#define ICER1_PWM1_MSK (0x1 << 7 ) +#define ICER1_PWM1 (0x1 << 7 ) +#define ICER1_PWM1_DIS (0x0 << 7 ) /* DIS */ +#define ICER1_PWM1_EN (0x1 << 7 ) /* EN */ + +/* ICER1[PWM0] - */ +#define ICER1_PWM0_MSK (0x1 << 6 ) +#define ICER1_PWM0 (0x1 << 6 ) +#define ICER1_PWM0_DIS (0x0 << 6 ) /* DIS */ +#define ICER1_PWM0_EN (0x1 << 6 ) /* EN */ + +/* ICER1[PWMTRIP] - */ +#define ICER1_PWMTRIP_MSK (0x1 << 5 ) +#define ICER1_PWMTRIP (0x1 << 5 ) +#define ICER1_PWMTRIP_DIS (0x0 << 5 ) /* DIS */ +#define ICER1_PWMTRIP_EN (0x1 << 5 ) /* EN */ + +/* ICER1[DMASPI0RX] - */ +#define ICER1_DMASPI0RX_MSK (0x1 << 4 ) +#define ICER1_DMASPI0RX (0x1 << 4 ) +#define ICER1_DMASPI0RX_DIS (0x0 << 4 ) /* DIS */ +#define ICER1_DMASPI0RX_EN (0x1 << 4 ) /* EN */ + +/* ICER1[DMASPI0TX] - */ +#define ICER1_DMASPI0TX_MSK (0x1 << 3 ) +#define ICER1_DMASPI0TX (0x1 << 3 ) +#define ICER1_DMASPI0TX_DIS (0x0 << 3 ) /* DIS */ +#define ICER1_DMASPI0TX_EN (0x1 << 3 ) /* EN */ + +/* ICER1[DMAADC] - */ +#define ICER1_DMAADC_MSK (0x1 << 2 ) +#define ICER1_DMAADC (0x1 << 2 ) +#define ICER1_DMAADC_DIS (0x0 << 2 ) /* DIS */ +#define ICER1_DMAADC_EN (0x1 << 2 ) /* EN */ + +/* Reset Value for ISPR0*/ +#define ISPR0_RVAL 0x0 + +/* ISPR0[DMAI2CMRX] - */ +#define ISPR0_DMAI2CMRX_MSK (0x1 << 30 ) +#define ISPR0_DMAI2CMRX (0x1 << 30 ) +#define ISPR0_DMAI2CMRX_DIS (0x0 << 30 ) /* DIS */ +#define ISPR0_DMAI2CMRX_EN (0x1 << 30 ) /* EN */ + +/* ISPR0[DMAI2CMTX] - */ +#define ISPR0_DMAI2CMTX_MSK (0x1 << 29 ) +#define ISPR0_DMAI2CMTX (0x1 << 29 ) +#define ISPR0_DMAI2CMTX_DIS (0x0 << 29 ) /* DIS */ +#define ISPR0_DMAI2CMTX_EN (0x1 << 29 ) /* EN */ + +/* ISPR0[DMAI2CSRX] - */ +#define ISPR0_DMAI2CSRX_MSK (0x1 << 28 ) +#define ISPR0_DMAI2CSRX (0x1 << 28 ) +#define ISPR0_DMAI2CSRX_DIS (0x0 << 28 ) /* DIS */ +#define ISPR0_DMAI2CSRX_EN (0x1 << 28 ) /* EN */ + +/* ISPR0[DMAI2CSTX] - */ +#define ISPR0_DMAI2CSTX_MSK (0x1 << 27 ) +#define ISPR0_DMAI2CSTX (0x1 << 27 ) +#define ISPR0_DMAI2CSTX_DIS (0x0 << 27 ) /* DIS */ +#define ISPR0_DMAI2CSTX_EN (0x1 << 27 ) /* EN */ + +/* ISPR0[DMAUARTRX] - */ +#define ISPR0_DMAUARTRX_MSK (0x1 << 26 ) +#define ISPR0_DMAUARTRX (0x1 << 26 ) +#define ISPR0_DMAUARTRX_DIS (0x0 << 26 ) /* DIS */ +#define ISPR0_DMAUARTRX_EN (0x1 << 26 ) /* EN */ + +/* ISPR0[DMAUARTTX] - */ +#define ISPR0_DMAUARTTX_MSK (0x1 << 25 ) +#define ISPR0_DMAUARTTX (0x1 << 25 ) +#define ISPR0_DMAUARTTX_DIS (0x0 << 25 ) /* DIS */ +#define ISPR0_DMAUARTTX_EN (0x1 << 25 ) /* EN */ + +/* ISPR0[DMASPI1RX] - */ +#define ISPR0_DMASPI1RX_MSK (0x1 << 24 ) +#define ISPR0_DMASPI1RX (0x1 << 24 ) +#define ISPR0_DMASPI1RX_DIS (0x0 << 24 ) /* DIS */ +#define ISPR0_DMASPI1RX_EN (0x1 << 24 ) /* EN */ + +/* ISPR0[DMASPI1TX] - */ +#define ISPR0_DMASPI1TX_MSK (0x1 << 23 ) +#define ISPR0_DMASPI1TX (0x1 << 23 ) +#define ISPR0_DMASPI1TX_DIS (0x0 << 23 ) /* DIS */ +#define ISPR0_DMASPI1TX_EN (0x1 << 23 ) /* EN */ + +/* ISPR0[DMAERROR] - */ +#define ISPR0_DMAERROR_MSK (0x1 << 22 ) +#define ISPR0_DMAERROR (0x1 << 22 ) +#define ISPR0_DMAERROR_DIS (0x0 << 22 ) /* DIS */ +#define ISPR0_DMAERROR_EN (0x1 << 22 ) /* EN */ + +/* ISPR0[I2CM] - */ +#define ISPR0_I2CM_MSK (0x1 << 20 ) +#define ISPR0_I2CM (0x1 << 20 ) +#define ISPR0_I2CM_DIS (0x0 << 20 ) /* DIS */ +#define ISPR0_I2CM_EN (0x1 << 20 ) /* EN */ + +/* ISPR0[I2CS] - */ +#define ISPR0_I2CS_MSK (0x1 << 19 ) +#define ISPR0_I2CS (0x1 << 19 ) +#define ISPR0_I2CS_DIS (0x0 << 19 ) /* DIS */ +#define ISPR0_I2CS_EN (0x1 << 19 ) /* EN */ + +/* ISPR0[SPI1] - */ +#define ISPR0_SPI1_MSK (0x1 << 18 ) +#define ISPR0_SPI1 (0x1 << 18 ) +#define ISPR0_SPI1_DIS (0x0 << 18 ) /* DIS */ +#define ISPR0_SPI1_EN (0x1 << 18 ) /* EN */ + +/* ISPR0[SPI0] - */ +#define ISPR0_SPI0_MSK (0x1 << 17 ) +#define ISPR0_SPI0 (0x1 << 17 ) +#define ISPR0_SPI0_DIS (0x0 << 17 ) /* DIS */ +#define ISPR0_SPI0_EN (0x1 << 17 ) /* EN */ + +/* ISPR0[UART] - */ +#define ISPR0_UART_MSK (0x1 << 16 ) +#define ISPR0_UART (0x1 << 16 ) +#define ISPR0_UART_DIS (0x0 << 16 ) /* DIS */ +#define ISPR0_UART_EN (0x1 << 16 ) /* EN */ + +/* ISPR0[FEE] - */ +#define ISPR0_FEE_MSK (0x1 << 15 ) +#define ISPR0_FEE (0x1 << 15 ) +#define ISPR0_FEE_DIS (0x0 << 15 ) /* DIS */ +#define ISPR0_FEE_EN (0x1 << 15 ) /* EN */ + +/* ISPR0[ADC] - */ +#define ISPR0_ADC_MSK (0x1 << 14 ) +#define ISPR0_ADC (0x1 << 14 ) +#define ISPR0_ADC_DIS (0x0 << 14 ) /* DIS */ +#define ISPR0_ADC_EN (0x1 << 14 ) /* EN */ + +/* ISPR0[T1] - */ +#define ISPR0_T1_MSK (0x1 << 13 ) +#define ISPR0_T1 (0x1 << 13 ) +#define ISPR0_T1_DIS (0x0 << 13 ) /* DIS */ +#define ISPR0_T1_EN (0x1 << 13 ) /* EN */ + +/* ISPR0[T0] - */ +#define ISPR0_T0_MSK (0x1 << 12 ) +#define ISPR0_T0 (0x1 << 12 ) +#define ISPR0_T0_DIS (0x0 << 12 ) /* DIS */ +#define ISPR0_T0_EN (0x1 << 12 ) /* EN */ + +/* ISPR0[T3] - */ +#define ISPR0_T3_MSK (0x1 << 10 ) +#define ISPR0_T3 (0x1 << 10 ) +#define ISPR0_T3_DIS (0x0 << 10 ) /* DIS */ +#define ISPR0_T3_EN (0x1 << 10 ) /* EN */ + +/* ISPR0[EXTINT8] - */ +#define ISPR0_EXTINT8_MSK (0x1 << 9 ) +#define ISPR0_EXTINT8 (0x1 << 9 ) +#define ISPR0_EXTINT8_DIS (0x0 << 9 ) /* DIS */ +#define ISPR0_EXTINT8_EN (0x1 << 9 ) /* EN */ + +/* ISPR0[EXTINT7] - */ +#define ISPR0_EXTINT7_MSK (0x1 << 8 ) +#define ISPR0_EXTINT7 (0x1 << 8 ) +#define ISPR0_EXTINT7_DIS (0x0 << 8 ) /* DIS */ +#define ISPR0_EXTINT7_EN (0x1 << 8 ) /* EN */ + +/* ISPR0[EXTINT6] - */ +#define ISPR0_EXTINT6_MSK (0x1 << 7 ) +#define ISPR0_EXTINT6 (0x1 << 7 ) +#define ISPR0_EXTINT6_DIS (0x0 << 7 ) /* DIS */ +#define ISPR0_EXTINT6_EN (0x1 << 7 ) /* EN */ + +/* ISPR0[EXTINT5] - */ +#define ISPR0_EXTINT5_MSK (0x1 << 6 ) +#define ISPR0_EXTINT5 (0x1 << 6 ) +#define ISPR0_EXTINT5_DIS (0x0 << 6 ) /* DIS */ +#define ISPR0_EXTINT5_EN (0x1 << 6 ) /* EN */ + +/* ISPR0[EXTINT4] - */ +#define ISPR0_EXTINT4_MSK (0x1 << 5 ) +#define ISPR0_EXTINT4 (0x1 << 5 ) +#define ISPR0_EXTINT4_DIS (0x0 << 5 ) /* DIS */ +#define ISPR0_EXTINT4_EN (0x1 << 5 ) /* EN */ + +/* ISPR0[EXTINT3] - */ +#define ISPR0_EXTINT3_MSK (0x1 << 4 ) +#define ISPR0_EXTINT3 (0x1 << 4 ) +#define ISPR0_EXTINT3_DIS (0x0 << 4 ) /* DIS */ +#define ISPR0_EXTINT3_EN (0x1 << 4 ) /* EN */ + +/* ISPR0[EXTINT2] - */ +#define ISPR0_EXTINT2_MSK (0x1 << 3 ) +#define ISPR0_EXTINT2 (0x1 << 3 ) +#define ISPR0_EXTINT2_DIS (0x0 << 3 ) /* DIS */ +#define ISPR0_EXTINT2_EN (0x1 << 3 ) /* EN */ + +/* ISPR0[EXTINT1] - */ +#define ISPR0_EXTINT1_MSK (0x1 << 2 ) +#define ISPR0_EXTINT1 (0x1 << 2 ) +#define ISPR0_EXTINT1_DIS (0x0 << 2 ) /* DIS */ +#define ISPR0_EXTINT1_EN (0x1 << 2 ) /* EN */ + +/* ISPR0[EXTINT0] - */ +#define ISPR0_EXTINT0_MSK (0x1 << 1 ) +#define ISPR0_EXTINT0 (0x1 << 1 ) +#define ISPR0_EXTINT0_DIS (0x0 << 1 ) /* DIS */ +#define ISPR0_EXTINT0_EN (0x1 << 1 ) /* EN */ + +/* ISPR0[T2] - */ +#define ISPR0_T2_MSK (0x1 << 0 ) +#define ISPR0_T2 (0x1 << 0 ) +#define ISPR0_T2_DIS (0x0 << 0 ) /* DIS */ +#define ISPR0_T2_EN (0x1 << 0 ) /* EN */ + +/* Reset Value for ISPR1*/ +#define ISPR1_RVAL 0x0 + +/* ISPR1[PWM3] - */ +#define ISPR1_PWM3_MSK (0x1 << 9 ) +#define ISPR1_PWM3 (0x1 << 9 ) +#define ISPR1_PWM3_DIS (0x0 << 9 ) /* DIS */ +#define ISPR1_PWM3_EN (0x1 << 9 ) /* EN */ + +/* ISPR1[PWM2] - */ +#define ISPR1_PWM2_MSK (0x1 << 8 ) +#define ISPR1_PWM2 (0x1 << 8 ) +#define ISPR1_PWM2_DIS (0x0 << 8 ) /* DIS */ +#define ISPR1_PWM2_EN (0x1 << 8 ) /* EN */ + +/* ISPR1[PWM1] - */ +#define ISPR1_PWM1_MSK (0x1 << 7 ) +#define ISPR1_PWM1 (0x1 << 7 ) +#define ISPR1_PWM1_DIS (0x0 << 7 ) /* DIS */ +#define ISPR1_PWM1_EN (0x1 << 7 ) /* EN */ + +/* ISPR1[PWM0] - */ +#define ISPR1_PWM0_MSK (0x1 << 6 ) +#define ISPR1_PWM0 (0x1 << 6 ) +#define ISPR1_PWM0_DIS (0x0 << 6 ) /* DIS */ +#define ISPR1_PWM0_EN (0x1 << 6 ) /* EN */ + +/* ISPR1[PWMTRIP] - */ +#define ISPR1_PWMTRIP_MSK (0x1 << 5 ) +#define ISPR1_PWMTRIP (0x1 << 5 ) +#define ISPR1_PWMTRIP_DIS (0x0 << 5 ) /* DIS */ +#define ISPR1_PWMTRIP_EN (0x1 << 5 ) /* EN */ + +/* ISPR1[DMASPI0RX] - */ +#define ISPR1_DMASPI0RX_MSK (0x1 << 4 ) +#define ISPR1_DMASPI0RX (0x1 << 4 ) +#define ISPR1_DMASPI0RX_DIS (0x0 << 4 ) /* DIS */ +#define ISPR1_DMASPI0RX_EN (0x1 << 4 ) /* EN */ + +/* ISPR1[DMASPI0TX] - */ +#define ISPR1_DMASPI0TX_MSK (0x1 << 3 ) +#define ISPR1_DMASPI0TX (0x1 << 3 ) +#define ISPR1_DMASPI0TX_DIS (0x0 << 3 ) /* DIS */ +#define ISPR1_DMASPI0TX_EN (0x1 << 3 ) /* EN */ + +/* ISPR1[DMAADC] - */ +#define ISPR1_DMAADC_MSK (0x1 << 2 ) +#define ISPR1_DMAADC (0x1 << 2 ) +#define ISPR1_DMAADC_DIS (0x0 << 2 ) /* DIS */ +#define ISPR1_DMAADC_EN (0x1 << 2 ) /* EN */ + +/* Reset Value for ICPR0*/ +#define ICPR0_RVAL 0x0 + +/* ICPR0[DMAI2CMRX] - */ +#define ICPR0_DMAI2CMRX_MSK (0x1 << 30 ) +#define ICPR0_DMAI2CMRX (0x1 << 30 ) +#define ICPR0_DMAI2CMRX_DIS (0x0 << 30 ) /* DIS */ +#define ICPR0_DMAI2CMRX_EN (0x1 << 30 ) /* EN */ + +/* ICPR0[DMAI2CMTX] - */ +#define ICPR0_DMAI2CMTX_MSK (0x1 << 29 ) +#define ICPR0_DMAI2CMTX (0x1 << 29 ) +#define ICPR0_DMAI2CMTX_DIS (0x0 << 29 ) /* DIS */ +#define ICPR0_DMAI2CMTX_EN (0x1 << 29 ) /* EN */ + +/* ICPR0[DMAI2CSRX] - */ +#define ICPR0_DMAI2CSRX_MSK (0x1 << 28 ) +#define ICPR0_DMAI2CSRX (0x1 << 28 ) +#define ICPR0_DMAI2CSRX_DIS (0x0 << 28 ) /* DIS */ +#define ICPR0_DMAI2CSRX_EN (0x1 << 28 ) /* EN */ + +/* ICPR0[DMAI2CSTX] - */ +#define ICPR0_DMAI2CSTX_MSK (0x1 << 27 ) +#define ICPR0_DMAI2CSTX (0x1 << 27 ) +#define ICPR0_DMAI2CSTX_DIS (0x0 << 27 ) /* DIS */ +#define ICPR0_DMAI2CSTX_EN (0x1 << 27 ) /* EN */ + +/* ICPR0[DMAUARTRX] - */ +#define ICPR0_DMAUARTRX_MSK (0x1 << 26 ) +#define ICPR0_DMAUARTRX (0x1 << 26 ) +#define ICPR0_DMAUARTRX_DIS (0x0 << 26 ) /* DIS */ +#define ICPR0_DMAUARTRX_EN (0x1 << 26 ) /* EN */ + +/* ICPR0[DMAUARTTX] - */ +#define ICPR0_DMAUARTTX_MSK (0x1 << 25 ) +#define ICPR0_DMAUARTTX (0x1 << 25 ) +#define ICPR0_DMAUARTTX_DIS (0x0 << 25 ) /* DIS */ +#define ICPR0_DMAUARTTX_EN (0x1 << 25 ) /* EN */ + +/* ICPR0[DMASPI1RX] - */ +#define ICPR0_DMASPI1RX_MSK (0x1 << 24 ) +#define ICPR0_DMASPI1RX (0x1 << 24 ) +#define ICPR0_DMASPI1RX_DIS (0x0 << 24 ) /* DIS */ +#define ICPR0_DMASPI1RX_EN (0x1 << 24 ) /* EN */ + +/* ICPR0[DMASPI1TX] - */ +#define ICPR0_DMASPI1TX_MSK (0x1 << 23 ) +#define ICPR0_DMASPI1TX (0x1 << 23 ) +#define ICPR0_DMASPI1TX_DIS (0x0 << 23 ) /* DIS */ +#define ICPR0_DMASPI1TX_EN (0x1 << 23 ) /* EN */ + +/* ICPR0[DMAERROR] - */ +#define ICPR0_DMAERROR_MSK (0x1 << 22 ) +#define ICPR0_DMAERROR (0x1 << 22 ) +#define ICPR0_DMAERROR_DIS (0x0 << 22 ) /* DIS */ +#define ICPR0_DMAERROR_EN (0x1 << 22 ) /* EN */ + +/* ICPR0[I2CM] - */ +#define ICPR0_I2CM_MSK (0x1 << 20 ) +#define ICPR0_I2CM (0x1 << 20 ) +#define ICPR0_I2CM_DIS (0x0 << 20 ) /* DIS */ +#define ICPR0_I2CM_EN (0x1 << 20 ) /* EN */ + +/* ICPR0[I2CS] - */ +#define ICPR0_I2CS_MSK (0x1 << 19 ) +#define ICPR0_I2CS (0x1 << 19 ) +#define ICPR0_I2CS_DIS (0x0 << 19 ) /* DIS */ +#define ICPR0_I2CS_EN (0x1 << 19 ) /* EN */ + +/* ICPR0[SPI1] - */ +#define ICPR0_SPI1_MSK (0x1 << 18 ) +#define ICPR0_SPI1 (0x1 << 18 ) +#define ICPR0_SPI1_DIS (0x0 << 18 ) /* DIS */ +#define ICPR0_SPI1_EN (0x1 << 18 ) /* EN */ + +/* ICPR0[SPI0] - */ +#define ICPR0_SPI0_MSK (0x1 << 17 ) +#define ICPR0_SPI0 (0x1 << 17 ) +#define ICPR0_SPI0_DIS (0x0 << 17 ) /* DIS */ +#define ICPR0_SPI0_EN (0x1 << 17 ) /* EN */ + +/* ICPR0[UART] - */ +#define ICPR0_UART_MSK (0x1 << 16 ) +#define ICPR0_UART (0x1 << 16 ) +#define ICPR0_UART_DIS (0x0 << 16 ) /* DIS */ +#define ICPR0_UART_EN (0x1 << 16 ) /* EN */ + +/* ICPR0[FEE] - */ +#define ICPR0_FEE_MSK (0x1 << 15 ) +#define ICPR0_FEE (0x1 << 15 ) +#define ICPR0_FEE_DIS (0x0 << 15 ) /* DIS */ +#define ICPR0_FEE_EN (0x1 << 15 ) /* EN */ + +/* ICPR0[ADC] - */ +#define ICPR0_ADC_MSK (0x1 << 14 ) +#define ICPR0_ADC (0x1 << 14 ) +#define ICPR0_ADC_DIS (0x0 << 14 ) /* DIS */ +#define ICPR0_ADC_EN (0x1 << 14 ) /* EN */ + +/* ICPR0[T1] - */ +#define ICPR0_T1_MSK (0x1 << 13 ) +#define ICPR0_T1 (0x1 << 13 ) +#define ICPR0_T1_DIS (0x0 << 13 ) /* DIS */ +#define ICPR0_T1_EN (0x1 << 13 ) /* EN */ + +/* ICPR0[T0] - */ +#define ICPR0_T0_MSK (0x1 << 12 ) +#define ICPR0_T0 (0x1 << 12 ) +#define ICPR0_T0_DIS (0x0 << 12 ) /* DIS */ +#define ICPR0_T0_EN (0x1 << 12 ) /* EN */ + +/* ICPR0[T3] - */ +#define ICPR0_T3_MSK (0x1 << 10 ) +#define ICPR0_T3 (0x1 << 10 ) +#define ICPR0_T3_DIS (0x0 << 10 ) /* DIS */ +#define ICPR0_T3_EN (0x1 << 10 ) /* EN */ + +/* ICPR0[EXTINT8] - */ +#define ICPR0_EXTINT8_MSK (0x1 << 9 ) +#define ICPR0_EXTINT8 (0x1 << 9 ) +#define ICPR0_EXTINT8_DIS (0x0 << 9 ) /* DIS */ +#define ICPR0_EXTINT8_EN (0x1 << 9 ) /* EN */ + +/* ICPR0[EXTINT7] - */ +#define ICPR0_EXTINT7_MSK (0x1 << 8 ) +#define ICPR0_EXTINT7 (0x1 << 8 ) +#define ICPR0_EXTINT7_DIS (0x0 << 8 ) /* DIS */ +#define ICPR0_EXTINT7_EN (0x1 << 8 ) /* EN */ + +/* ICPR0[EXTINT6] - */ +#define ICPR0_EXTINT6_MSK (0x1 << 7 ) +#define ICPR0_EXTINT6 (0x1 << 7 ) +#define ICPR0_EXTINT6_DIS (0x0 << 7 ) /* DIS */ +#define ICPR0_EXTINT6_EN (0x1 << 7 ) /* EN */ + +/* ICPR0[EXTINT5] - */ +#define ICPR0_EXTINT5_MSK (0x1 << 6 ) +#define ICPR0_EXTINT5 (0x1 << 6 ) +#define ICPR0_EXTINT5_DIS (0x0 << 6 ) /* DIS */ +#define ICPR0_EXTINT5_EN (0x1 << 6 ) /* EN */ + +/* ICPR0[EXTINT4] - */ +#define ICPR0_EXTINT4_MSK (0x1 << 5 ) +#define ICPR0_EXTINT4 (0x1 << 5 ) +#define ICPR0_EXTINT4_DIS (0x0 << 5 ) /* DIS */ +#define ICPR0_EXTINT4_EN (0x1 << 5 ) /* EN */ + +/* ICPR0[EXTINT3] - */ +#define ICPR0_EXTINT3_MSK (0x1 << 4 ) +#define ICPR0_EXTINT3 (0x1 << 4 ) +#define ICPR0_EXTINT3_DIS (0x0 << 4 ) /* DIS */ +#define ICPR0_EXTINT3_EN (0x1 << 4 ) /* EN */ + +/* ICPR0[EXTINT2] - */ +#define ICPR0_EXTINT2_MSK (0x1 << 3 ) +#define ICPR0_EXTINT2 (0x1 << 3 ) +#define ICPR0_EXTINT2_DIS (0x0 << 3 ) /* DIS */ +#define ICPR0_EXTINT2_EN (0x1 << 3 ) /* EN */ + +/* ICPR0[EXTINT1] - */ +#define ICPR0_EXTINT1_MSK (0x1 << 2 ) +#define ICPR0_EXTINT1 (0x1 << 2 ) +#define ICPR0_EXTINT1_DIS (0x0 << 2 ) /* DIS */ +#define ICPR0_EXTINT1_EN (0x1 << 2 ) /* EN */ + +/* ICPR0[EXTINT0] - */ +#define ICPR0_EXTINT0_MSK (0x1 << 1 ) +#define ICPR0_EXTINT0 (0x1 << 1 ) +#define ICPR0_EXTINT0_DIS (0x0 << 1 ) /* DIS */ +#define ICPR0_EXTINT0_EN (0x1 << 1 ) /* EN */ + +/* ICPR0[T2] - */ +#define ICPR0_T2_MSK (0x1 << 0 ) +#define ICPR0_T2 (0x1 << 0 ) +#define ICPR0_T2_DIS (0x0 << 0 ) /* DIS */ +#define ICPR0_T2_EN (0x1 << 0 ) /* EN */ + +/* Reset Value for ICPR1*/ +#define ICPR1_RVAL 0x0 + +/* ICPR1[PWM3] - */ +#define ICPR1_PWM3_MSK (0x1 << 9 ) +#define ICPR1_PWM3 (0x1 << 9 ) +#define ICPR1_PWM3_DIS (0x0 << 9 ) /* DIS */ +#define ICPR1_PWM3_EN (0x1 << 9 ) /* EN */ + +/* ICPR1[PWM2] - */ +#define ICPR1_PWM2_MSK (0x1 << 8 ) +#define ICPR1_PWM2 (0x1 << 8 ) +#define ICPR1_PWM2_DIS (0x0 << 8 ) /* DIS */ +#define ICPR1_PWM2_EN (0x1 << 8 ) /* EN */ + +/* ICPR1[PWM1] - */ +#define ICPR1_PWM1_MSK (0x1 << 7 ) +#define ICPR1_PWM1 (0x1 << 7 ) +#define ICPR1_PWM1_DIS (0x0 << 7 ) /* DIS */ +#define ICPR1_PWM1_EN (0x1 << 7 ) /* EN */ + +/* ICPR1[PWM0] - */ +#define ICPR1_PWM0_MSK (0x1 << 6 ) +#define ICPR1_PWM0 (0x1 << 6 ) +#define ICPR1_PWM0_DIS (0x0 << 6 ) /* DIS */ +#define ICPR1_PWM0_EN (0x1 << 6 ) /* EN */ + +/* ICPR1[PWMTRIP] - */ +#define ICPR1_PWMTRIP_MSK (0x1 << 5 ) +#define ICPR1_PWMTRIP (0x1 << 5 ) +#define ICPR1_PWMTRIP_DIS (0x0 << 5 ) /* DIS */ +#define ICPR1_PWMTRIP_EN (0x1 << 5 ) /* EN */ + +/* ICPR1[DMASPI0RX] - */ +#define ICPR1_DMASPI0RX_MSK (0x1 << 4 ) +#define ICPR1_DMASPI0RX (0x1 << 4 ) +#define ICPR1_DMASPI0RX_DIS (0x0 << 4 ) /* DIS */ +#define ICPR1_DMASPI0RX_EN (0x1 << 4 ) /* EN */ + +/* ICPR1[DMASPI0TX] - */ +#define ICPR1_DMASPI0TX_MSK (0x1 << 3 ) +#define ICPR1_DMASPI0TX (0x1 << 3 ) +#define ICPR1_DMASPI0TX_DIS (0x0 << 3 ) /* DIS */ +#define ICPR1_DMASPI0TX_EN (0x1 << 3 ) /* EN */ + +/* ICPR1[DMAADC] - */ +#define ICPR1_DMAADC_MSK (0x1 << 2 ) +#define ICPR1_DMAADC (0x1 << 2 ) +#define ICPR1_DMAADC_DIS (0x0 << 2 ) /* DIS */ +#define ICPR1_DMAADC_EN (0x1 << 2 ) /* EN */ + +/* Reset Value for IABR0*/ +#define IABR0_RVAL 0x0 + +/* IABR0[DMAI2CMRX] - */ +#define IABR0_DMAI2CMRX_MSK (0x1 << 30 ) +#define IABR0_DMAI2CMRX (0x1 << 30 ) +#define IABR0_DMAI2CMRX_DIS (0x0 << 30 ) /* DIS */ +#define IABR0_DMAI2CMRX_EN (0x1 << 30 ) /* EN */ + +/* IABR0[DMAI2CMTX] - */ +#define IABR0_DMAI2CMTX_MSK (0x1 << 29 ) +#define IABR0_DMAI2CMTX (0x1 << 29 ) +#define IABR0_DMAI2CMTX_DIS (0x0 << 29 ) /* DIS */ +#define IABR0_DMAI2CMTX_EN (0x1 << 29 ) /* EN */ + +/* IABR0[DMAI2CSRX] - */ +#define IABR0_DMAI2CSRX_MSK (0x1 << 28 ) +#define IABR0_DMAI2CSRX (0x1 << 28 ) +#define IABR0_DMAI2CSRX_DIS (0x0 << 28 ) /* DIS */ +#define IABR0_DMAI2CSRX_EN (0x1 << 28 ) /* EN */ + +/* IABR0[DMAI2CSTX] - */ +#define IABR0_DMAI2CSTX_MSK (0x1 << 27 ) +#define IABR0_DMAI2CSTX (0x1 << 27 ) +#define IABR0_DMAI2CSTX_DIS (0x0 << 27 ) /* DIS */ +#define IABR0_DMAI2CSTX_EN (0x1 << 27 ) /* EN */ + +/* IABR0[DMAUARTRX] - */ +#define IABR0_DMAUARTRX_MSK (0x1 << 26 ) +#define IABR0_DMAUARTRX (0x1 << 26 ) +#define IABR0_DMAUARTRX_DIS (0x0 << 26 ) /* DIS */ +#define IABR0_DMAUARTRX_EN (0x1 << 26 ) /* EN */ + +/* IABR0[DMAUARTTX] - */ +#define IABR0_DMAUARTTX_MSK (0x1 << 25 ) +#define IABR0_DMAUARTTX (0x1 << 25 ) +#define IABR0_DMAUARTTX_DIS (0x0 << 25 ) /* DIS */ +#define IABR0_DMAUARTTX_EN (0x1 << 25 ) /* EN */ + +/* IABR0[DMASPI1RX] - */ +#define IABR0_DMASPI1RX_MSK (0x1 << 24 ) +#define IABR0_DMASPI1RX (0x1 << 24 ) +#define IABR0_DMASPI1RX_DIS (0x0 << 24 ) /* DIS */ +#define IABR0_DMASPI1RX_EN (0x1 << 24 ) /* EN */ + +/* IABR0[DMASPI1TX] - */ +#define IABR0_DMASPI1TX_MSK (0x1 << 23 ) +#define IABR0_DMASPI1TX (0x1 << 23 ) +#define IABR0_DMASPI1TX_DIS (0x0 << 23 ) /* DIS */ +#define IABR0_DMASPI1TX_EN (0x1 << 23 ) /* EN */ + +/* IABR0[DMAERROR] - */ +#define IABR0_DMAERROR_MSK (0x1 << 22 ) +#define IABR0_DMAERROR (0x1 << 22 ) +#define IABR0_DMAERROR_DIS (0x0 << 22 ) /* DIS */ +#define IABR0_DMAERROR_EN (0x1 << 22 ) /* EN */ + +/* IABR0[I2CM] - */ +#define IABR0_I2CM_MSK (0x1 << 20 ) +#define IABR0_I2CM (0x1 << 20 ) +#define IABR0_I2CM_DIS (0x0 << 20 ) /* DIS */ +#define IABR0_I2CM_EN (0x1 << 20 ) /* EN */ + +/* IABR0[I2CS] - */ +#define IABR0_I2CS_MSK (0x1 << 19 ) +#define IABR0_I2CS (0x1 << 19 ) +#define IABR0_I2CS_DIS (0x0 << 19 ) /* DIS */ +#define IABR0_I2CS_EN (0x1 << 19 ) /* EN */ + +/* IABR0[SPI1] - */ +#define IABR0_SPI1_MSK (0x1 << 18 ) +#define IABR0_SPI1 (0x1 << 18 ) +#define IABR0_SPI1_DIS (0x0 << 18 ) /* DIS */ +#define IABR0_SPI1_EN (0x1 << 18 ) /* EN */ + +/* IABR0[SPI0] - */ +#define IABR0_SPI0_MSK (0x1 << 17 ) +#define IABR0_SPI0 (0x1 << 17 ) +#define IABR0_SPI0_DIS (0x0 << 17 ) /* DIS */ +#define IABR0_SPI0_EN (0x1 << 17 ) /* EN */ + +/* IABR0[UART] - */ +#define IABR0_UART_MSK (0x1 << 16 ) +#define IABR0_UART (0x1 << 16 ) +#define IABR0_UART_DIS (0x0 << 16 ) /* DIS */ +#define IABR0_UART_EN (0x1 << 16 ) /* EN */ + +/* IABR0[FEE] - */ +#define IABR0_FEE_MSK (0x1 << 15 ) +#define IABR0_FEE (0x1 << 15 ) +#define IABR0_FEE_DIS (0x0 << 15 ) /* DIS */ +#define IABR0_FEE_EN (0x1 << 15 ) /* EN */ + +/* IABR0[ADC] - */ +#define IABR0_ADC_MSK (0x1 << 14 ) +#define IABR0_ADC (0x1 << 14 ) +#define IABR0_ADC_DIS (0x0 << 14 ) /* DIS */ +#define IABR0_ADC_EN (0x1 << 14 ) /* EN */ + +/* IABR0[T1] - */ +#define IABR0_T1_MSK (0x1 << 13 ) +#define IABR0_T1 (0x1 << 13 ) +#define IABR0_T1_DIS (0x0 << 13 ) /* DIS */ +#define IABR0_T1_EN (0x1 << 13 ) /* EN */ + +/* IABR0[T0] - */ +#define IABR0_T0_MSK (0x1 << 12 ) +#define IABR0_T0 (0x1 << 12 ) +#define IABR0_T0_DIS (0x0 << 12 ) /* DIS */ +#define IABR0_T0_EN (0x1 << 12 ) /* EN */ + +/* IABR0[T3] - */ +#define IABR0_T3_MSK (0x1 << 10 ) +#define IABR0_T3 (0x1 << 10 ) +#define IABR0_T3_DIS (0x0 << 10 ) /* DIS */ +#define IABR0_T3_EN (0x1 << 10 ) /* EN */ + +/* IABR0[EXTINT8] - */ +#define IABR0_EXTINT8_MSK (0x1 << 9 ) +#define IABR0_EXTINT8 (0x1 << 9 ) +#define IABR0_EXTINT8_DIS (0x0 << 9 ) /* DIS */ +#define IABR0_EXTINT8_EN (0x1 << 9 ) /* EN */ + +/* IABR0[EXTINT7] - */ +#define IABR0_EXTINT7_MSK (0x1 << 8 ) +#define IABR0_EXTINT7 (0x1 << 8 ) +#define IABR0_EXTINT7_DIS (0x0 << 8 ) /* DIS */ +#define IABR0_EXTINT7_EN (0x1 << 8 ) /* EN */ + +/* IABR0[EXTINT6] - */ +#define IABR0_EXTINT6_MSK (0x1 << 7 ) +#define IABR0_EXTINT6 (0x1 << 7 ) +#define IABR0_EXTINT6_DIS (0x0 << 7 ) /* DIS */ +#define IABR0_EXTINT6_EN (0x1 << 7 ) /* EN */ + +/* IABR0[EXTINT5] - */ +#define IABR0_EXTINT5_MSK (0x1 << 6 ) +#define IABR0_EXTINT5 (0x1 << 6 ) +#define IABR0_EXTINT5_DIS (0x0 << 6 ) /* DIS */ +#define IABR0_EXTINT5_EN (0x1 << 6 ) /* EN */ + +/* IABR0[EXTINT4] - */ +#define IABR0_EXTINT4_MSK (0x1 << 5 ) +#define IABR0_EXTINT4 (0x1 << 5 ) +#define IABR0_EXTINT4_DIS (0x0 << 5 ) /* DIS */ +#define IABR0_EXTINT4_EN (0x1 << 5 ) /* EN */ + +/* IABR0[EXTINT3] - */ +#define IABR0_EXTINT3_MSK (0x1 << 4 ) +#define IABR0_EXTINT3 (0x1 << 4 ) +#define IABR0_EXTINT3_DIS (0x0 << 4 ) /* DIS */ +#define IABR0_EXTINT3_EN (0x1 << 4 ) /* EN */ + +/* IABR0[EXTINT2] - */ +#define IABR0_EXTINT2_MSK (0x1 << 3 ) +#define IABR0_EXTINT2 (0x1 << 3 ) +#define IABR0_EXTINT2_DIS (0x0 << 3 ) /* DIS */ +#define IABR0_EXTINT2_EN (0x1 << 3 ) /* EN */ + +/* IABR0[EXTINT1] - */ +#define IABR0_EXTINT1_MSK (0x1 << 2 ) +#define IABR0_EXTINT1 (0x1 << 2 ) +#define IABR0_EXTINT1_DIS (0x0 << 2 ) /* DIS */ +#define IABR0_EXTINT1_EN (0x1 << 2 ) /* EN */ + +/* IABR0[EXTINT0] - */ +#define IABR0_EXTINT0_MSK (0x1 << 1 ) +#define IABR0_EXTINT0 (0x1 << 1 ) +#define IABR0_EXTINT0_DIS (0x0 << 1 ) /* DIS */ +#define IABR0_EXTINT0_EN (0x1 << 1 ) /* EN */ + +/* IABR0[T2] - */ +#define IABR0_T2_MSK (0x1 << 0 ) +#define IABR0_T2 (0x1 << 0 ) +#define IABR0_T2_DIS (0x0 << 0 ) /* DIS */ +#define IABR0_T2_EN (0x1 << 0 ) /* EN */ + +/* Reset Value for IABR1*/ +#define IABR1_RVAL 0x0 + +/* IABR1[PWM3] - */ +#define IABR1_PWM3_MSK (0x1 << 9 ) +#define IABR1_PWM3 (0x1 << 9 ) +#define IABR1_PWM3_DIS (0x0 << 9 ) /* DIS */ +#define IABR1_PWM3_EN (0x1 << 9 ) /* EN */ + +/* IABR1[PWM2] - */ +#define IABR1_PWM2_MSK (0x1 << 8 ) +#define IABR1_PWM2 (0x1 << 8 ) +#define IABR1_PWM2_DIS (0x0 << 8 ) /* DIS */ +#define IABR1_PWM2_EN (0x1 << 8 ) /* EN */ + +/* IABR1[PWM1] - */ +#define IABR1_PWM1_MSK (0x1 << 7 ) +#define IABR1_PWM1 (0x1 << 7 ) +#define IABR1_PWM1_DIS (0x0 << 7 ) /* DIS */ +#define IABR1_PWM1_EN (0x1 << 7 ) /* EN */ + +/* IABR1[PWM0] - */ +#define IABR1_PWM0_MSK (0x1 << 6 ) +#define IABR1_PWM0 (0x1 << 6 ) +#define IABR1_PWM0_DIS (0x0 << 6 ) /* DIS */ +#define IABR1_PWM0_EN (0x1 << 6 ) /* EN */ + +/* IABR1[PWMTRIP] - */ +#define IABR1_PWMTRIP_MSK (0x1 << 5 ) +#define IABR1_PWMTRIP (0x1 << 5 ) +#define IABR1_PWMTRIP_DIS (0x0 << 5 ) /* DIS */ +#define IABR1_PWMTRIP_EN (0x1 << 5 ) /* EN */ + +/* IABR1[DMASPI0RX] - */ +#define IABR1_DMASPI0RX_MSK (0x1 << 4 ) +#define IABR1_DMASPI0RX (0x1 << 4 ) +#define IABR1_DMASPI0RX_DIS (0x0 << 4 ) /* DIS */ +#define IABR1_DMASPI0RX_EN (0x1 << 4 ) /* EN */ + +/* IABR1[DMASPI0TX] - */ +#define IABR1_DMASPI0TX_MSK (0x1 << 3 ) +#define IABR1_DMASPI0TX (0x1 << 3 ) +#define IABR1_DMASPI0TX_DIS (0x0 << 3 ) /* DIS */ +#define IABR1_DMASPI0TX_EN (0x1 << 3 ) /* EN */ + +/* IABR1[DMAADC] - */ +#define IABR1_DMAADC_MSK (0x1 << 2 ) +#define IABR1_DMAADC (0x1 << 2 ) +#define IABR1_DMAADC_DIS (0x0 << 2 ) /* DIS */ +#define IABR1_DMAADC_EN (0x1 << 2 ) /* EN */ + +/* Reset Value for IPR0*/ +#define IPR0_RVAL 0x0 + +/* IPR0[EXTINT2] - */ +#define IPR0_EXTINT2_MSK (0xFF << 24 ) + +/* IPR0[EXTINT1] - */ +#define IPR0_EXTINT1_MSK (0xFF << 16 ) + +/* IPR0[EXTINT0] - Priority of interrupt number 1 */ +#define IPR0_EXTINT0_MSK (0xFF << 8 ) + +/* IPR0[T2] - Priority of interrupt number 0 */ +#define IPR0_T2_MSK (0xFF << 0 ) + +/* Reset Value for IPR1*/ +#define IPR1_RVAL 0x0 + +/* IPR1[EXTINT6] - */ +#define IPR1_EXTINT6_MSK (0xFF << 24 ) + +/* IPR1[EXTINT5] - */ +#define IPR1_EXTINT5_MSK (0xFF << 16 ) + +/* IPR1[EXTINT4] - */ +#define IPR1_EXTINT4_MSK (0xFF << 8 ) + +/* IPR1[EXTINT3] - */ +#define IPR1_EXTINT3_MSK (0xFF << 0 ) + +/* Reset Value for IPR2*/ +#define IPR2_RVAL 0x0 + +/* IPR2[T3] - */ +#define IPR2_T3_MSK (0xFF << 16 ) + +/* IPR2[EXTINT8] - */ +#define IPR2_EXTINT8_MSK (0xFF << 8 ) + +/* IPR2[EXTINT7] - */ +#define IPR2_EXTINT7_MSK (0xFF << 0 ) + +/* Reset Value for IPR3*/ +#define IPR3_RVAL 0x0 + +/* IPR3[FEE] - */ +#define IPR3_FEE_MSK (0xFF << 24 ) + +/* IPR3[ADC] - */ +#define IPR3_ADC_MSK (0xFF << 16 ) + +/* IPR3[T1] - */ +#define IPR3_T1_MSK (0xFF << 8 ) + +/* IPR3[T0] - */ +#define IPR3_T0_MSK (0xFF << 0 ) + +/* Reset Value for IPR4*/ +#define IPR4_RVAL 0x0 + +/* IPR4[I2CS] - */ +#define IPR4_I2CS_MSK (0xFF << 24 ) + +/* IPR4[SPI1] - */ +#define IPR4_SPI1_MSK (0xFF << 16 ) + +/* IPR4[SPI0] - */ +#define IPR4_SPI0_MSK (0xFF << 8 ) + +/* IPR4[UART] - */ +#define IPR4_UART_MSK (0xFF << 0 ) + +/* Reset Value for IPR5*/ +#define IPR5_RVAL 0x0 + +/* IPR5[DMASPI1TX] - */ +#define IPR5_DMASPI1TX_MSK (0xFF << 24 ) + +/* IPR5[DMAERROR] - */ +#define IPR5_DMAERROR_MSK (0xFF << 16 ) + +/* IPR5[I2CM] - I2CM */ +#define IPR5_I2CM_MSK (0xFF << 0 ) + +/* Reset Value for IPR6*/ +#define IPR6_RVAL 0x0 + +/* IPR6[DMAI2CSTX] - */ +#define IPR6_DMAI2CSTX_MSK (0xFF << 24 ) + +/* IPR6[DMAUARTRX] - */ +#define IPR6_DMAUARTRX_MSK (0xFF << 16 ) + +/* IPR6[DMAUARTTX] - */ +#define IPR6_DMAUARTTX_MSK (0xFF << 8 ) + +/* IPR6[DMASPI1RX] - */ +#define IPR6_DMASPI1RX_MSK (0xFF << 0 ) + +/* Reset Value for IPR7*/ +#define IPR7_RVAL 0x0 + +/* IPR7[DMAI2CMRX] - */ +#define IPR7_DMAI2CMRX_MSK (0xFF << 16 ) + +/* IPR7[DMAI2CMTX] - */ +#define IPR7_DMAI2CMTX_MSK (0xFF << 8 ) + +/* IPR7[DMAI2CSRX] - */ +#define IPR7_DMAI2CSRX_MSK (0xFF << 0 ) + +/* Reset Value for IPR8*/ +#define IPR8_RVAL 0x0 + +/* IPR8[DMASPI0TX] - */ +#define IPR8_DMASPI0TX_MSK (0xFF << 24 ) + +/* IPR8[DMAADC] - */ +#define IPR8_DMAADC_MSK (0xFF << 16 ) + +/* Reset Value for IPR9*/ +#define IPR9_RVAL 0x0 + +/* IPR9[PWM1] - */ +#define IPR9_PWM1_MSK (0xFF << 24 ) + +/* IPR9[PWM0] - */ +#define IPR9_PWM0_MSK (0xFF << 16 ) + +/* IPR9[PWMTRIP] - */ +#define IPR9_PWMTRIP_MSK (0xFF << 8 ) + +/* IPR9[DMASPI0RX] - */ +#define IPR9_DMASPI0RX_MSK (0xFF << 0 ) + +/* Reset Value for IPR10*/ +#define IPR10_RVAL 0x0 + +/* IPR10[PWM3] - */ +#define IPR10_PWM3_MSK (0xFF << 8 ) + +/* IPR10[PWM2] - */ +#define IPR10_PWM2_MSK (0xFF << 0 ) + +/* Reset Value for CPUID*/ +#define CPUID_RVAL 0x412FC230 + +/* CPUID[IMPLEMENTER] - Indicates implementor */ +#define CPUID_IMPLEMENTER_MSK (0xFF << 24 ) + +/* CPUID[VARIANT] - Indicates processor revision */ +#define CPUID_VARIANT_MSK (0xF << 20 ) + +/* CPUID[PARTNO] - Indicates part number */ +#define CPUID_PARTNO_MSK (0xFFF << 4 ) + +/* CPUID[REVISION] - Indicates patch release */ +#define CPUID_REVISION_MSK (0xF << 0 ) + +/* Reset Value for ICSR*/ +#define ICSR_RVAL 0x0 + +/* ICSR[NMIPENDSET] - Setting this bit will activate an NMI */ +#define ICSR_NMIPENDSET_MSK (0x1 << 31 ) +#define ICSR_NMIPENDSET (0x1 << 31 ) +#define ICSR_NMIPENDSET_DIS (0x0 << 31 ) /* DIS */ +#define ICSR_NMIPENDSET_EN (0x1 << 31 ) /* EN */ + +/* ICSR[PENDSVSET] - Set a pending PendSV interrupt */ +#define ICSR_PENDSVSET_MSK (0x1 << 28 ) +#define ICSR_PENDSVSET (0x1 << 28 ) +#define ICSR_PENDSVSET_DIS (0x0 << 28 ) /* DIS */ +#define ICSR_PENDSVSET_EN (0x1 << 28 ) /* EN */ + +/* ICSR[PENDSVCLR] - Clear a pending PendSV interrupt */ +#define ICSR_PENDSVCLR_MSK (0x1 << 27 ) +#define ICSR_PENDSVCLR (0x1 << 27 ) +#define ICSR_PENDSVCLR_DIS (0x0 << 27 ) /* DIS */ +#define ICSR_PENDSVCLR_EN (0x1 << 27 ) /* EN */ + +/* ICSR[PENDSTSET] - Set a pending SysTick. Reads back with current state */ +#define ICSR_PENDSTSET_MSK (0x1 << 26 ) +#define ICSR_PENDSTSET (0x1 << 26 ) +#define ICSR_PENDSTSET_DIS (0x0 << 26 ) /* DIS */ +#define ICSR_PENDSTSET_EN (0x1 << 26 ) /* EN */ + +/* ICSR[PENDSTCLR] - Clear a pending SysTick */ +#define ICSR_PENDSTCLR_MSK (0x1 << 25 ) +#define ICSR_PENDSTCLR (0x1 << 25 ) +#define ICSR_PENDSTCLR_DIS (0x0 << 25 ) /* DIS */ +#define ICSR_PENDSTCLR_EN (0x1 << 25 ) /* EN */ + +/* ICSR[ISRPREEMPT] - If set, a pending exception will be serviced on exit from the debug halt state */ +#define ICSR_ISRPREEMPT_MSK (0x1 << 23 ) +#define ICSR_ISRPREEMPT (0x1 << 23 ) +#define ICSR_ISRPREEMPT_DIS (0x0 << 23 ) /* DIS */ +#define ICSR_ISRPREEMPT_EN (0x1 << 23 ) /* EN */ + +/* ICSR[ISRPENDING] - Indicates if an external configurable is pending */ +#define ICSR_ISRPENDING_MSK (0x1 << 22 ) +#define ICSR_ISRPENDING (0x1 << 22 ) +#define ICSR_ISRPENDING_DIS (0x0 << 22 ) /* DIS */ +#define ICSR_ISRPENDING_EN (0x1 << 22 ) /* EN */ + +/* ICSR[VECTPENDING] - Indicates the exception number for the highest priority pending exception */ +#define ICSR_VECTPENDING_MSK (0x1FF << 12 ) + +/* ICSR[RETTOBASE] - */ +#define ICSR_RETTOBASE_MSK (0x1 << 11 ) +#define ICSR_RETTOBASE (0x1 << 11 ) +#define ICSR_RETTOBASE_DIS (0x0 << 11 ) /* DIS */ +#define ICSR_RETTOBASE_EN (0x1 << 11 ) /* EN */ + +/* ICSR[VECTACTIVE] - Thread mode, or exception number */ +#define ICSR_VECTACTIVE_MSK (0x1FF << 0 ) + +/* Reset Value for VTOR*/ +#define VTOR_RVAL 0x0 + +/* VTOR[TBLBASE] - */ +#define VTOR_TBLBASE_MSK (0x1 << 29 ) +#define VTOR_TBLBASE (0x1 << 29 ) +#define VTOR_TBLBASE_DIS (0x0 << 29 ) /* DIS */ +#define VTOR_TBLBASE_EN (0x1 << 29 ) /* EN */ + +/* VTOR[TBLOFF] - */ +#define VTOR_TBLOFF_MSK (0x3FFFFF << 7 ) + +/* Reset Value for AIRCR*/ +#define AIRCR_RVAL 0xFA050000 + +/* AIRCR[VECTKEYSTAT] - Reads as 0xFA05 */ +#define AIRCR_VECTKEYSTAT_MSK (0xFFFF << 16 ) + +/* AIRCR[ENDIANESS] - This bit is static or configured by a hardware input on reset */ +#define AIRCR_ENDIANESS_MSK (0x1 << 15 ) +#define AIRCR_ENDIANESS (0x1 << 15 ) +#define AIRCR_ENDIANESS_DIS (0x0 << 15 ) /* DIS */ +#define AIRCR_ENDIANESS_EN (0x1 << 15 ) /* EN */ + +/* AIRCR[PRIGROUP] - Priority grouping position */ +#define AIRCR_PRIGROUP_MSK (0x7 << 8 ) + +/* AIRCR[SYSRESETREQ] - System Reset Request */ +#define AIRCR_SYSRESETREQ_MSK (0x1 << 2 ) +#define AIRCR_SYSRESETREQ (0x1 << 2 ) +#define AIRCR_SYSRESETREQ_DIS (0x0 << 2 ) /* DIS */ +#define AIRCR_SYSRESETREQ_EN (0x1 << 2 ) /* EN */ + +/* AIRCR[VECTCLRACTIVE] - Clears all active state information for fixed and configurable exceptions */ +#define AIRCR_VECTCLRACTIVE_MSK (0x1 << 1 ) +#define AIRCR_VECTCLRACTIVE (0x1 << 1 ) +#define AIRCR_VECTCLRACTIVE_DIS (0x0 << 1 ) /* DIS */ +#define AIRCR_VECTCLRACTIVE_EN (0x1 << 1 ) /* EN */ + +/* AIRCR[VECTRESET] - Local system reset */ +#define AIRCR_VECTRESET_MSK (0x1 << 0 ) +#define AIRCR_VECTRESET (0x1 << 0 ) +#define AIRCR_VECTRESET_DIS (0x0 << 0 ) /* DIS */ +#define AIRCR_VECTRESET_EN (0x1 << 0 ) /* EN */ + +/* Reset Value for SCR*/ +#define SCR_RVAL 0x0 + +/* SCR[SEVONPEND] - */ +#define SCR_SEVONPEND_MSK (0x1 << 4 ) +#define SCR_SEVONPEND (0x1 << 4 ) +#define SCR_SEVONPEND_DIS (0x0 << 4 ) /* DIS */ +#define SCR_SEVONPEND_EN (0x1 << 4 ) /* EN */ + +/* SCR[SLEEPDEEP] - Sleep deep bit */ +#define SCR_SLEEPDEEP_MSK (0x1 << 2 ) +#define SCR_SLEEPDEEP (0x1 << 2 ) +#define SCR_SLEEPDEEP_DIS (0x0 << 2 ) /* DIS */ +#define SCR_SLEEPDEEP_EN (0x1 << 2 ) /* EN */ + +/* SCR[SLEEPONEXIT] - Sleep on exit when returning from handler mode to thread mode */ +#define SCR_SLEEPONEXIT_MSK (0x1 << 1 ) +#define SCR_SLEEPONEXIT (0x1 << 1 ) +#define SCR_SLEEPONEXIT_DIS (0x0 << 1 ) /* DIS */ +#define SCR_SLEEPONEXIT_EN (0x1 << 1 ) /* EN */ + +/* Reset Value for CCR*/ +#define CCR_RVAL 0x200 + +/* CCR[STKALIGN] - */ +#define CCR_STKALIGN_MSK (0x1 << 9 ) +#define CCR_STKALIGN (0x1 << 9 ) +#define CCR_STKALIGN_DIS (0x0 << 9 ) /* DIS */ +#define CCR_STKALIGN_EN (0x1 << 9 ) /* EN */ + +/* CCR[BFHFNMIGN] - */ +#define CCR_BFHFNMIGN_MSK (0x1 << 8 ) +#define CCR_BFHFNMIGN (0x1 << 8 ) +#define CCR_BFHFNMIGN_DIS (0x0 << 8 ) /* DIS */ +#define CCR_BFHFNMIGN_EN (0x1 << 8 ) /* EN */ + +/* CCR[DIV0TRP] - */ +#define CCR_DIV0TRP_MSK (0x1 << 4 ) +#define CCR_DIV0TRP (0x1 << 4 ) +#define CCR_DIV0TRP_DIS (0x0 << 4 ) /* DIS */ +#define CCR_DIV0TRP_EN (0x1 << 4 ) /* EN */ + +/* CCR[UNALIGNTRP] - */ +#define CCR_UNALIGNTRP_MSK (0x1 << 3 ) +#define CCR_UNALIGNTRP (0x1 << 3 ) +#define CCR_UNALIGNTRP_DIS (0x0 << 3 ) /* DIS */ +#define CCR_UNALIGNTRP_EN (0x1 << 3 ) /* EN */ + +/* CCR[USERSETMPEND] - */ +#define CCR_USERSETMPEND_MSK (0x1 << 1 ) +#define CCR_USERSETMPEND (0x1 << 1 ) +#define CCR_USERSETMPEND_DIS (0x0 << 1 ) /* DIS */ +#define CCR_USERSETMPEND_EN (0x1 << 1 ) /* EN */ + +/* CCR[NONBASETHRDENA] - */ +#define CCR_NONBASETHRDENA_MSK (0x1 << 0 ) +#define CCR_NONBASETHRDENA (0x1 << 0 ) +#define CCR_NONBASETHRDENA_DIS (0x0 << 0 ) /* DIS */ +#define CCR_NONBASETHRDENA_EN (0x1 << 0 ) /* EN */ + +/* Reset Value for SHPR1*/ +#define SHPR1_RVAL 0x0 + +/* SHPR1[PRI7] - Priority of system handler 7 - reserved */ +#define SHPR1_PRI7_MSK (0xFF << 24 ) + +/* SHPR1[PRI6] - Priority of system handler 6 - UsageFault */ +#define SHPR1_PRI6_MSK (0xFF << 16 ) + +/* SHPR1[PRI5] - Priority of system handler 5 - BusFault */ +#define SHPR1_PRI5_MSK (0xFF << 8 ) + +/* SHPR1[PRI4] - Priority of system handler 4 - MemManage */ +#define SHPR1_PRI4_MSK (0xFF << 0 ) + +/* Reset Value for SHPR2*/ +#define SHPR2_RVAL 0x0 + +/* SHPR2[PRI11] - Priority of system handler 11 - SVCall */ +#define SHPR2_PRI11_MSK (0xFF << 24 ) + +/* SHPR2[PRI10] - Priority of system handler 10 - reserved */ +#define SHPR2_PRI10_MSK (0xFF << 16 ) + +/* SHPR2[PRI9] - Priority of system handler 9 - reserved */ +#define SHPR2_PRI9_MSK (0xFF << 8 ) + +/* SHPR2[PRI8] - Priority of system handler 8 - reserved */ +#define SHPR2_PRI8_MSK (0xFF << 0 ) + +/* Reset Value for SHPR3*/ +#define SHPR3_RVAL 0x0 + +/* SHPR3[PRI15] - Priority of system handler 15 - SysTick */ +#define SHPR3_PRI15_MSK (0xFF << 24 ) + +/* SHPR3[PRI14] - Priority of system handler 14 - PendSV */ +#define SHPR3_PRI14_MSK (0xFF << 16 ) + +/* SHPR3[PRI13] - Priority of system handler 13 - reserved */ +#define SHPR3_PRI13_MSK (0xFF << 8 ) + +/* SHPR3[PRI12] - Priority of system handler 12 - DebugMonitor */ +#define SHPR3_PRI12_MSK (0xFF << 0 ) + +/* Reset Value for SHCSR*/ +#define SHCSR_RVAL 0x0 + +/* SHCSR[USGFAULTENA] - Enable for UsageFault */ +#define SHCSR_USGFAULTENA_MSK (0x1 << 18 ) +#define SHCSR_USGFAULTENA (0x1 << 18 ) +#define SHCSR_USGFAULTENA_DIS (0x0 << 18 ) /* DIS */ +#define SHCSR_USGFAULTENA_EN (0x1 << 18 ) /* EN */ + +/* SHCSR[BUSFAULTENA] - Enable for BusFault. */ +#define SHCSR_BUSFAULTENA_MSK (0x1 << 17 ) +#define SHCSR_BUSFAULTENA (0x1 << 17 ) +#define SHCSR_BUSFAULTENA_DIS (0x0 << 17 ) /* DIS */ +#define SHCSR_BUSFAULTENA_EN (0x1 << 17 ) /* EN */ + +/* SHCSR[MEMFAULTENA] - Enable for MemManage fault. */ +#define SHCSR_MEMFAULTENA_MSK (0x1 << 16 ) +#define SHCSR_MEMFAULTENA (0x1 << 16 ) +#define SHCSR_MEMFAULTENA_DIS (0x0 << 16 ) /* DIS */ +#define SHCSR_MEMFAULTENA_EN (0x1 << 16 ) /* EN */ + +/* SHCSR[SVCALLPENDED] - Reads as 1 if SVCall is Pending */ +#define SHCSR_SVCALLPENDED_MSK (0x1 << 15 ) +#define SHCSR_SVCALLPENDED (0x1 << 15 ) +#define SHCSR_SVCALLPENDED_DIS (0x0 << 15 ) /* DIS */ +#define SHCSR_SVCALLPENDED_EN (0x1 << 15 ) /* EN */ + +/* SHCSR[BUSFAULTPENDED] - Reads as 1 if BusFault is Pending */ +#define SHCSR_BUSFAULTPENDED_MSK (0x1 << 14 ) +#define SHCSR_BUSFAULTPENDED (0x1 << 14 ) +#define SHCSR_BUSFAULTPENDED_DIS (0x0 << 14 ) /* DIS */ +#define SHCSR_BUSFAULTPENDED_EN (0x1 << 14 ) /* EN */ + +/* SHCSR[MEMFAULTPENDED] - Reads as 1 if MemManage is Pending */ +#define SHCSR_MEMFAULTPENDED_MSK (0x1 << 13 ) +#define SHCSR_MEMFAULTPENDED (0x1 << 13 ) +#define SHCSR_MEMFAULTPENDED_DIS (0x0 << 13 ) /* DIS */ +#define SHCSR_MEMFAULTPENDED_EN (0x1 << 13 ) /* EN */ + +/* SHCSR[USGFAULTPENDED] - Reads as 1 if UsageFault is Pending */ +#define SHCSR_USGFAULTPENDED_MSK (0x1 << 12 ) +#define SHCSR_USGFAULTPENDED (0x1 << 12 ) +#define SHCSR_USGFAULTPENDED_DIS (0x0 << 12 ) /* DIS */ +#define SHCSR_USGFAULTPENDED_EN (0x1 << 12 ) /* EN */ + +/* SHCSR[SYSTICKACT] - Reads as 1 if SysTick is Active */ +#define SHCSR_SYSTICKACT_MSK (0x1 << 11 ) +#define SHCSR_SYSTICKACT (0x1 << 11 ) +#define SHCSR_SYSTICKACT_DIS (0x0 << 11 ) /* DIS */ +#define SHCSR_SYSTICKACT_EN (0x1 << 11 ) /* EN */ + +/* SHCSR[PENDSVACT] - Reads as 1 if PendSV is Active */ +#define SHCSR_PENDSVACT_MSK (0x1 << 10 ) +#define SHCSR_PENDSVACT (0x1 << 10 ) +#define SHCSR_PENDSVACT_DIS (0x0 << 10 ) /* DIS */ +#define SHCSR_PENDSVACT_EN (0x1 << 10 ) /* EN */ + +/* SHCSR[MONITORACT] - Reads as 1 if the Monitor is Active */ +#define SHCSR_MONITORACT_MSK (0x1 << 8 ) +#define SHCSR_MONITORACT (0x1 << 8 ) +#define SHCSR_MONITORACT_DIS (0x0 << 8 ) /* DIS */ +#define SHCSR_MONITORACT_EN (0x1 << 8 ) /* EN */ + +/* SHCSR[SVCALLACT] - Reads as 1 if SVCall is Active */ +#define SHCSR_SVCALLACT_MSK (0x1 << 7 ) +#define SHCSR_SVCALLACT (0x1 << 7 ) +#define SHCSR_SVCALLACT_DIS (0x0 << 7 ) /* DIS */ +#define SHCSR_SVCALLACT_EN (0x1 << 7 ) /* EN */ + +/* SHCSR[USGFAULTACT] - Reads as 1 if UsageFault is Active. */ +#define SHCSR_USGFAULTACT_MSK (0x1 << 3 ) +#define SHCSR_USGFAULTACT (0x1 << 3 ) +#define SHCSR_USGFAULTACT_DIS (0x0 << 3 ) /* DIS */ +#define SHCSR_USGFAULTACT_EN (0x1 << 3 ) /* EN */ + +/* SHCSR[BUSFAULTACT] - Reads as 1 if BusFault is Active. */ +#define SHCSR_BUSFAULTACT_MSK (0x1 << 1 ) +#define SHCSR_BUSFAULTACT (0x1 << 1 ) +#define SHCSR_BUSFAULTACT_DIS (0x0 << 1 ) /* DIS */ +#define SHCSR_BUSFAULTACT_EN (0x1 << 1 ) /* EN */ + +/* SHCSR[MEMFAULTACT] - Reads as 1 if MemManage is Active */ +#define SHCSR_MEMFAULTACT_MSK (0x1 << 0 ) +#define SHCSR_MEMFAULTACT (0x1 << 0 ) +#define SHCSR_MEMFAULTACT_DIS (0x0 << 0 ) /* DIS */ +#define SHCSR_MEMFAULTACT_EN (0x1 << 0 ) /* EN */ + +/* Reset Value for CFSR*/ +#define CFSR_RVAL 0x0 + +/* CFSR[DIVBYZERO] - Divide by zero error */ +#define CFSR_DIVBYZERO_MSK (0x1 << 25 ) +#define CFSR_DIVBYZERO (0x1 << 25 ) +#define CFSR_DIVBYZERO_DIS (0x0 << 25 ) /* DIS */ +#define CFSR_DIVBYZERO_EN (0x1 << 25 ) /* EN */ + +/* CFSR[UNALIGNED] - Unaligned access error */ +#define CFSR_UNALIGNED_MSK (0x1 << 24 ) +#define CFSR_UNALIGNED (0x1 << 24 ) +#define CFSR_UNALIGNED_DIS (0x0 << 24 ) /* DIS */ +#define CFSR_UNALIGNED_EN (0x1 << 24 ) /* EN */ + +/* CFSR[NOCP] - Coprocessor access error */ +#define CFSR_NOCP_MSK (0x1 << 19 ) +#define CFSR_NOCP (0x1 << 19 ) +#define CFSR_NOCP_DIS (0x0 << 19 ) /* DIS */ +#define CFSR_NOCP_EN (0x1 << 19 ) /* EN */ + +/* CFSR[INVPC] - Integrity check error on EXC_RETURN */ +#define CFSR_INVPC_MSK (0x1 << 18 ) +#define CFSR_INVPC (0x1 << 18 ) +#define CFSR_INVPC_DIS (0x0 << 18 ) /* DIS */ +#define CFSR_INVPC_EN (0x1 << 18 ) /* EN */ + +/* CFSR[INVSTATE] - Invalid EPSR.T bit or illegal EPSR.IT bits for executing */ +#define CFSR_INVSTATE_MSK (0x1 << 17 ) +#define CFSR_INVSTATE (0x1 << 17 ) +#define CFSR_INVSTATE_DIS (0x0 << 17 ) /* DIS */ +#define CFSR_INVSTATE_EN (0x1 << 17 ) /* EN */ + +/* CFSR[UNDEFINSTR] - Undefined instruction executed */ +#define CFSR_UNDEFINSTR_MSK (0x1 << 16 ) +#define CFSR_UNDEFINSTR (0x1 << 16 ) +#define CFSR_UNDEFINSTR_DIS (0x0 << 16 ) /* DIS */ +#define CFSR_UNDEFINSTR_EN (0x1 << 16 ) /* EN */ + +/* CFSR[BFARVALID] - This bit is set if the BFAR register has valid contents */ +#define CFSR_BFARVALID_MSK (0x1 << 15 ) +#define CFSR_BFARVALID (0x1 << 15 ) +#define CFSR_BFARVALID_DIS (0x0 << 15 ) /* DIS */ +#define CFSR_BFARVALID_EN (0x1 << 15 ) /* EN */ + +/* CFSR[STKERR] - This bit indicates a derived bus fault has occurred on exception entry */ +#define CFSR_STKERR_MSK (0x1 << 12 ) +#define CFSR_STKERR (0x1 << 12 ) +#define CFSR_STKERR_DIS (0x0 << 12 ) /* DIS */ +#define CFSR_STKERR_EN (0x1 << 12 ) /* EN */ + +/* CFSR[UNSTKERR] - This bit indicates a derived bus fault has occurred on exception return */ +#define CFSR_UNSTKERR_MSK (0x1 << 11 ) +#define CFSR_UNSTKERR (0x1 << 11 ) +#define CFSR_UNSTKERR_DIS (0x0 << 11 ) /* DIS */ +#define CFSR_UNSTKERR_EN (0x1 << 11 ) /* EN */ + +/* CFSR[IMPRECISERR] - Imprecise data access error */ +#define CFSR_IMPRECISERR_MSK (0x1 << 10 ) +#define CFSR_IMPRECISERR (0x1 << 10 ) +#define CFSR_IMPRECISERR_DIS (0x0 << 10 ) /* DIS */ +#define CFSR_IMPRECISERR_EN (0x1 << 10 ) /* EN */ + +/* CFSR[PRECISERR] - Precise data access error. The BFAR is written with the faulting address */ +#define CFSR_PRECISERR_MSK (0x1 << 9 ) +#define CFSR_PRECISERR (0x1 << 9 ) +#define CFSR_PRECISERR_DIS (0x0 << 9 ) /* DIS */ +#define CFSR_PRECISERR_EN (0x1 << 9 ) /* EN */ + +/* CFSR[IBUSERR] - This bit indicates a bus fault on an instruction prefetch */ +#define CFSR_IBUSERR_MSK (0x1 << 8 ) +#define CFSR_IBUSERR (0x1 << 8 ) +#define CFSR_IBUSERR_DIS (0x0 << 8 ) /* DIS */ +#define CFSR_IBUSERR_EN (0x1 << 8 ) /* EN */ + +/* CFSR[MMARVALID] - This bit is set if the MMAR register has valid contents. */ +#define CFSR_MMARVALID_MSK (0x1 << 7 ) +#define CFSR_MMARVALID (0x1 << 7 ) +#define CFSR_MMARVALID_DIS (0x0 << 7 ) /* DIS */ +#define CFSR_MMARVALID_EN (0x1 << 7 ) /* EN */ + +/* CFSR[MSTKERR] - A derived MemManage fault has occurred on exception entry */ +#define CFSR_MSTKERR_MSK (0x1 << 4 ) +#define CFSR_MSTKERR (0x1 << 4 ) +#define CFSR_MSTKERR_DIS (0x0 << 4 ) /* DIS */ +#define CFSR_MSTKERR_EN (0x1 << 4 ) /* EN */ + +/* CFSR[MUNSTKERR] - A derived MemManage fault has occurred on exception return */ +#define CFSR_MUNSTKERR_MSK (0x1 << 3 ) +#define CFSR_MUNSTKERR (0x1 << 3 ) +#define CFSR_MUNSTKERR_DIS (0x0 << 3 ) /* DIS */ +#define CFSR_MUNSTKERR_EN (0x1 << 3 ) /* EN */ + +/* CFSR[DACCVIOL] - Data access violation. The MMAR is set to the data address which the load store tried to access. */ +#define CFSR_DACCVIOL_MSK (0x1 << 1 ) +#define CFSR_DACCVIOL (0x1 << 1 ) +#define CFSR_DACCVIOL_DIS (0x0 << 1 ) /* DIS */ +#define CFSR_DACCVIOL_EN (0x1 << 1 ) /* EN */ + +/* CFSR[IACCVIOL] - violation on an instruction fetch. */ +#define CFSR_IACCVIOL_MSK (0x1 << 0 ) +#define CFSR_IACCVIOL (0x1 << 0 ) +#define CFSR_IACCVIOL_DIS (0x0 << 0 ) /* DIS */ +#define CFSR_IACCVIOL_EN (0x1 << 0 ) /* EN */ + +/* Reset Value for HFSR*/ +#define HFSR_RVAL 0x0 + +/* HFSR[DEBUGEVT] - Debug event, and the Debug Fault Status Register has been updated. */ +#define HFSR_DEBUGEVT_MSK (0x1 << 31 ) +#define HFSR_DEBUGEVT (0x1 << 31 ) +#define HFSR_DEBUGEVT_DIS (0x0 << 31 ) /* DIS */ +#define HFSR_DEBUGEVT_EN (0x1 << 31 ) /* EN */ + +/* HFSR[FORCED] - Configurable fault cannot be activated due to priority or it was disabled. Priority escalated to a HardFault. */ +#define HFSR_FORCED_MSK (0x1 << 30 ) +#define HFSR_FORCED (0x1 << 30 ) +#define HFSR_FORCED_DIS (0x0 << 30 ) /* DIS */ +#define HFSR_FORCED_EN (0x1 << 30 ) /* EN */ + +/* HFSR[VECTTBL] - Fault was due to vector table read on exception processing */ +#define HFSR_VECTTBL_MSK (0x1 << 1 ) +#define HFSR_VECTTBL (0x1 << 1 ) +#define HFSR_VECTTBL_DIS (0x0 << 1 ) /* DIS */ +#define HFSR_VECTTBL_EN (0x1 << 1 ) /* EN */ + +/* Reset Value for MMFAR*/ +#define MMFAR_RVAL 0x0 + +/* MMFAR[ADDRESS] - Data address MPU faulted. */ +#define MMFAR_ADDRESS_MSK (0xFFFFFFFF << 0 ) + +/* Reset Value for BFAR*/ +#define BFAR_RVAL 0x0 + +/* BFAR[ADDRESS] - Updated on precise data access faults */ +#define BFAR_ADDRESS_MSK (0xFFFFFFFF << 0 ) + +/* Reset Value for STIR*/ +#define STIR_RVAL 0x0 + +/* STIR[INTID] - The value written in this field is the interrupt to be triggered. */ +#define STIR_INTID_MSK (0x3FF << 0 ) +// ------------------------------------------------------------------------------------------------ +// ----- PWRCTL ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief Power Management Unit (pADI_PWRCTL) + */ + +#if (__NO_MMR_STRUCTS__==0) +typedef struct { /*!< pADI_PWRCTL Structure */ + __IO uint16_t PWRMOD; /*!< Power Modes Register */ + __I uint16_t RESERVED0; + __IO uint16_t PWRKEY; /*!< Key Protection for the PWRMOD Register. */ + __I uint16_t RESERVED1; + __IO uint8_t PSMCON; /*!< Power Supply Monitor Control and Status */ + __I uint8_t RESERVED2[111]; + __IO uint8_t SRAMRET; /*!< SRAM Retention Register */ + __I uint8_t RESERVED3[3]; + __IO uint8_t SHUTDOWN; /*!< Shutdown Acknowledge Register */ +} ADI_PWRCTL_TypeDef; +#else // (__NO_MMR_STRUCTS__==0) +#define PWRMOD (*(volatile unsigned short int *) 0x40002400) +#define PWRKEY (*(volatile unsigned short int *) 0x40002404) +#define PSMCON (*(volatile unsigned char *) 0x40002408) +#define SRAMRET (*(volatile unsigned char *) 0x40002478) +#define SHUTDOWN (*(volatile unsigned char *) 0x4000247C) +#endif // (__NO_MMR_STRUCTS__==0) + +/* Reset Value for PWRMOD*/ +#define PWRMOD_RVAL 0x100 + +/* PWRMOD[WICENACK] - WIC Acknowledge, for cortex M3 deep sleep mode */ +#define PWRMOD_WICENACK_BBA (*(volatile unsigned long *) 0x4204800C) +#define PWRMOD_WICENACK_MSK (0x1 << 3 ) +#define PWRMOD_WICENACK (0x1 << 3 ) +#define PWRMOD_WICENACK_CLR (0x0 << 3 ) /* CLR. Cleared automatically by hardware when the cortex M3 processor is not ready to enter deep sleep mode including if serial wire activity is detected. */ +#define PWRMOD_WICENACK_SET (0x1 << 3 ) /* SET. Set automatically by the cortex M3 processor when ready to enter sleep deep mode. */ + +/* PWRMOD[MOD] - Low Power Mode */ +#define PWRMOD_MOD_MSK (0x7 << 0 ) +#define PWRMOD_MOD_FLEXI (0x0 << 0 ) /* FLEXI. */ +#define PWRMOD_MOD_HIBERNATE (0x5 << 0 ) /* HIBERNATE. */ +#define PWRMOD_MOD_SHUTDOWN (0x6 << 0 ) /* SHUTDOWN. */ + +/* Reset Value for PWRKEY*/ +#define PWRKEY_RVAL 0x0 + +/* PWRKEY[VALUE] - */ +#define PWRKEY_VALUE_MSK (0xFFFF << 0 ) +#define PWRKEY_VALUE_KEY1 (0x4859 << 0 ) /* KEY1 */ +#define PWRKEY_VALUE_KEY2 (0xF27B << 0 ) /* KEY2 */ + +/* Reset Value for PSMCON*/ +#define PSMCON_RVAL 0x3 + +/* PSMCON[PD] - Power Supply Monitor power down bit. */ +#define PSMCON_PD_BBA (*(volatile unsigned long *) 0x42048104) +#define PSMCON_PD_MSK (0x1 << 1 ) +#define PSMCON_PD (0x1 << 1 ) +#define PSMCON_PD_DIS (0x0 << 1 ) /* DIS. Power up the PSM. */ +#define PSMCON_PD_EN (0x1 << 1 ) /* EN. Power down the PSM. */ + +/* Reset Value for SRAMRET*/ +#define SRAMRET_RVAL 0x1 + +/* SRAMRET[RETAIN] - SRAM retention enable bit */ +#define SRAMRET_RETAIN_BBA (*(volatile unsigned long *) 0x42048F00) +#define SRAMRET_RETAIN_MSK (0x1 << 0 ) +#define SRAMRET_RETAIN (0x1 << 0 ) +#define SRAMRET_RETAIN_DIS (0x0 << 0 ) /* DIS. To retain contents of the bottom 8 kB of SRAM only */ +#define SRAMRET_RETAIN_EN (0x1 << 0 ) /* EN. To retain contents of the entire 16 kB of SRAM */ + +/* Reset Value for SHUTDOWN*/ +#define SHUTDOWN_RVAL 0x0 + +/* SHUTDOWN[EINT8] - External Interrupt 8 detected during SHUTDOWN mode */ +#define SHUTDOWN_EINT8_BBA (*(volatile unsigned long *) 0x42048F88) +#define SHUTDOWN_EINT8_MSK (0x1 << 2 ) +#define SHUTDOWN_EINT8 (0x1 << 2 ) +#define SHUTDOWN_EINT8_CLR (0x0 << 2 ) /* CLR. Cleared automatically by hardware when clearing IRQ8 in EICLR. */ +#define SHUTDOWN_EINT8_SET (0x1 << 2 ) /* SET Indicates the interrupt was detected */ + +/* SHUTDOWN[EINT1] - External Interrupt 1 detected during SHUTDOWN mode */ +#define SHUTDOWN_EINT1_BBA (*(volatile unsigned long *) 0x42048F84) +#define SHUTDOWN_EINT1_MSK (0x1 << 1 ) +#define SHUTDOWN_EINT1 (0x1 << 1 ) +#define SHUTDOWN_EINT1_CLR (0x0 << 1 ) /* CLR. Cleared automatically by hardware when clearing IRQ1 in EICLR. */ +#define SHUTDOWN_EINT1_SET (0x1 << 1 ) /* SET Indicates the interrupt was detected */ + +/* SHUTDOWN[EINT0] - External Interrupt 0 detected during SHUTDOWN mode */ +#define SHUTDOWN_EINT0_BBA (*(volatile unsigned long *) 0x42048F80) +#define SHUTDOWN_EINT0_MSK (0x1 << 0 ) +#define SHUTDOWN_EINT0 (0x1 << 0 ) +#define SHUTDOWN_EINT0_CLR (0x0 << 0 ) /* CLR. Cleared automatically by hardware when clearing IRQ0 in EICLR. */ +#define SHUTDOWN_EINT0_SET (0x1 << 0 ) /* SET Indicates the interrupt was detected */ +// ------------------------------------------------------------------------------------------------ +// ----- PWM ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief Pulse Width Modulation (pADI_PWM) + */ + +#if (__NO_MMR_STRUCTS__==0) +typedef struct { /*!< pADI_PWM Structure */ + __IO uint16_t PWMCON0; /*!< PWM Control Register */ + __I uint16_t RESERVED0; + __IO uint8_t PWMCON1; /*!< Trip Control Register */ + __I uint8_t RESERVED1[3]; + __IO uint16_t PWMCLRI; /*!< PWM Interrupt Clear */ + __I uint16_t RESERVED2[3]; + __IO uint16_t PWM0COM0; /*!< Compare Register 0 for Pair 0 */ + __I uint16_t RESERVED3; + __IO uint16_t PWM0COM1; /*!< Compare Register 1 for Pair 0 */ + __I uint16_t RESERVED4; + __IO uint16_t PWM0COM2; /*!< Compare Register 2 for Pair 0 */ + __I uint16_t RESERVED5; + __IO uint16_t PWM0LEN; /*!< Period Value Register for Pair 0 */ + __I uint16_t RESERVED6; + __IO uint16_t PWM1COM0; /*!< Compare Register 0 for Pair 1 */ + __I uint16_t RESERVED7; + __IO uint16_t PWM1COM1; /*!< Compare Register 1 for Pair 1 */ + __I uint16_t RESERVED8; + __IO uint16_t PWM1COM2; /*!< Compare Register 2 for Pair 1 */ + __I uint16_t RESERVED9; + __IO uint16_t PWM1LEN; /*!< Period Value Register for Pair 1 */ + __I uint16_t RESERVED10; + __IO uint16_t PWM2COM0; /*!< Compare Register 0 for Pair 2 */ + __I uint16_t RESERVED11; + __IO uint16_t PWM2COM1; /*!< Compare Register 1 for Pair 2 */ + __I uint16_t RESERVED12; + __IO uint16_t PWM2COM2; /*!< Compare Register 2 for Pair 2 */ + __I uint16_t RESERVED13; + __IO uint16_t PWM2LEN; /*!< Period Value Register for Pair 2 */ + __I uint16_t RESERVED14; + __IO uint16_t PWM3COM0; /*!< Compare Register 0 for Pair 3 */ + __I uint16_t RESERVED15; + __IO uint16_t PWM3COM1; /*!< Compare Register 1 for Pair 3 */ + __I uint16_t RESERVED16; + __IO uint16_t PWM3COM2; /*!< Compare Register 2 for Pair 3 */ + __I uint16_t RESERVED17; + __IO uint16_t PWM3LEN; /*!< Period Value Register for Pair 3 */ +} ADI_PWM_TypeDef; +#else // (__NO_MMR_STRUCTS__==0) +#define PWMCON0 (*(volatile unsigned short int *) 0x40001000) +#define PWMCON1 (*(volatile unsigned char *) 0x40001004) +#define PWMCLRI (*(volatile unsigned short int *) 0x40001008) +#define PWM0COM0 (*(volatile unsigned short int *) 0x40001010) +#define PWM0COM1 (*(volatile unsigned short int *) 0x40001014) +#define PWM0COM2 (*(volatile unsigned short int *) 0x40001018) +#define PWM0LEN (*(volatile unsigned short int *) 0x4000101C) +#define PWM1COM0 (*(volatile unsigned short int *) 0x40001020) +#define PWM1COM1 (*(volatile unsigned short int *) 0x40001024) +#define PWM1COM2 (*(volatile unsigned short int *) 0x40001028) +#define PWM1LEN (*(volatile unsigned short int *) 0x4000102C) +#define PWM2COM0 (*(volatile unsigned short int *) 0x40001030) +#define PWM2COM1 (*(volatile unsigned short int *) 0x40001034) +#define PWM2COM2 (*(volatile unsigned short int *) 0x40001038) +#define PWM2LEN (*(volatile unsigned short int *) 0x4000103C) +#define PWM3COM0 (*(volatile unsigned short int *) 0x40001040) +#define PWM3COM1 (*(volatile unsigned short int *) 0x40001044) +#define PWM3COM2 (*(volatile unsigned short int *) 0x40001048) +#define PWM3LEN (*(volatile unsigned short int *) 0x4000104C) +#endif // (__NO_MMR_STRUCTS__==0) + +/* Reset Value for PWMCON0*/ +#define PWMCON0_RVAL 0x12 + +/* PWMCON0[SYNC] - PWM Synchronization. */ +#define PWMCON0_SYNC_BBA (*(volatile unsigned long *) 0x4202003C) +#define PWMCON0_SYNC_MSK (0x1 << 15 ) +#define PWMCON0_SYNC (0x1 << 15 ) +#define PWMCON0_SYNC_DIS (0x0 << 15 ) /* DIS. Ignore transitions on the PWMSYNC pin. */ +#define PWMCON0_SYNC_EN (0x1 << 15 ) /* EN. All PWM counters are reset on the next clock edge after the detection of a falling edge on the PWMSYNC pin. */ + +/* PWMCON0[PWM7INV] - Inversion of PWM output. Available in standard mode only. */ +#define PWMCON0_PWM7INV_BBA (*(volatile unsigned long *) 0x42020038) +#define PWMCON0_PWM7INV_MSK (0x1 << 14 ) +#define PWMCON0_PWM7INV (0x1 << 14 ) +#define PWMCON0_PWM7INV_DIS (0x0 << 14 ) /* DIS. PWM7 is normal. */ +#define PWMCON0_PWM7INV_EN (0x1 << 14 ) /* EN. Invert PWM7. */ + +/* PWMCON0[PWM5INV] - Inversion of PWM output. Available in standard mode only. */ +#define PWMCON0_PWM5INV_BBA (*(volatile unsigned long *) 0x42020034) +#define PWMCON0_PWM5INV_MSK (0x1 << 13 ) +#define PWMCON0_PWM5INV (0x1 << 13 ) +#define PWMCON0_PWM5INV_DIS (0x0 << 13 ) /* DIS. PWM5 is normal. */ +#define PWMCON0_PWM5INV_EN (0x1 << 13 ) /* EN. Invert PWM5. */ + +/* PWMCON0[PWM3INV] - Inversion of PWM output. Available in standard mode only. */ +#define PWMCON0_PWM3INV_BBA (*(volatile unsigned long *) 0x42020030) +#define PWMCON0_PWM3INV_MSK (0x1 << 12 ) +#define PWMCON0_PWM3INV (0x1 << 12 ) +#define PWMCON0_PWM3INV_DIS (0x0 << 12 ) /* DIS. PWM3 is normal. */ +#define PWMCON0_PWM3INV_EN (0x1 << 12 ) /* EN. Invert PWM3. */ + +/* PWMCON0[PWM1INV] - Inversion of PWM output. Available in standard mode only. */ +#define PWMCON0_PWM1INV_BBA (*(volatile unsigned long *) 0x4202002C) +#define PWMCON0_PWM1INV_MSK (0x1 << 11 ) +#define PWMCON0_PWM1INV (0x1 << 11 ) +#define PWMCON0_PWM1INV_DIS (0x0 << 11 ) /* DIS. PWM1 is normal. */ +#define PWMCON0_PWM1INV_EN (0x1 << 11 ) /* EN. Invert PWM1. */ + +/* PWMCON0[PWMIEN] - Enable PWM interrupts. */ +#define PWMCON0_PWMIEN_BBA (*(volatile unsigned long *) 0x42020028) +#define PWMCON0_PWMIEN_MSK (0x1 << 10 ) +#define PWMCON0_PWMIEN (0x1 << 10 ) +#define PWMCON0_PWMIEN_DIS (0x0 << 10 ) /* DIS. Disable PWM interrupts. */ +#define PWMCON0_PWMIEN_EN (0x1 << 10 ) /* EN. Enable PWM interrupts. */ + +/* PWMCON0[ENA] - Enable PWM outputs. Available in H-Bridge mode only. */ +#define PWMCON0_ENA_BBA (*(volatile unsigned long *) 0x42020024) +#define PWMCON0_ENA_MSK (0x1 << 9 ) +#define PWMCON0_ENA (0x1 << 9 ) +#define PWMCON0_ENA_DIS (0x0 << 9 ) /* DIS. Disable PWM outputs. */ +#define PWMCON0_ENA_EN (0x1 << 9 ) /* EN. Enable PWM outputs. */ + +/* PWMCON0[PWMCP] - PWM Clock Prescaler. Sets UCLK divider. */ +#define PWMCON0_PWMCP_MSK (0x7 << 6 ) +#define PWMCON0_PWMCP_UCLKDIV2 (0x0 << 6 ) /* UCLK/2. */ +#define PWMCON0_PWMCP_UCLKDIV4 (0x1 << 6 ) /* UCLK/4. */ +#define PWMCON0_PWMCP_UCLKDIV8 (0x2 << 6 ) /* UCLK/8. */ +#define PWMCON0_PWMCP_UCLKDIV16 (0x3 << 6 ) /* UCLK/16. */ +#define PWMCON0_PWMCP_UCLKDIV32 (0x4 << 6 ) /* UCLK/32. */ +#define PWMCON0_PWMCP_UCLKDIV64 (0x5 << 6 ) /* UCLK/64. */ +#define PWMCON0_PWMCP_UCLKDIV128 (0x6 << 6 ) /* UCLK/128. */ +#define PWMCON0_PWMCP_UCLKDIV256 (0x7 << 6 ) /* UCLK/256. */ + +/* PWMCON0[POINV] - Invert all PWM outputs. Available in H-Bridge mode only. */ +#define PWMCON0_POINV_BBA (*(volatile unsigned long *) 0x42020014) +#define PWMCON0_POINV_MSK (0x1 << 5 ) +#define PWMCON0_POINV (0x1 << 5 ) +#define PWMCON0_POINV_DIS (0x0 << 5 ) /* DIS. PWM outputs as normal. */ +#define PWMCON0_POINV_EN (0x1 << 5 ) /* EN. Invert all PWM outputs. */ + +/* PWMCON0[HOFF] - High Side Off. Available in H-Bridge mode only. */ +#define PWMCON0_HOFF_BBA (*(volatile unsigned long *) 0x42020010) +#define PWMCON0_HOFF_MSK (0x1 << 4 ) +#define PWMCON0_HOFF (0x1 << 4 ) +#define PWMCON0_HOFF_DIS (0x0 << 4 ) /* DIS. PWM outputs as normal. */ +#define PWMCON0_HOFF_EN (0x1 << 4 ) /* EN. Force PWM0 and PWM2 outputs high and PWM1 and PWM3 low. */ + +/* PWMCON0[LCOMP] - Load Compare Registers. */ +#define PWMCON0_LCOMP_BBA (*(volatile unsigned long *) 0x4202000C) +#define PWMCON0_LCOMP_MSK (0x1 << 3 ) +#define PWMCON0_LCOMP (0x1 << 3 ) +#define PWMCON0_LCOMP_DIS (0x0 << 3 ) /* DIS. Use the values previously stored in the internal compare registers. */ +#define PWMCON0_LCOMP_EN (0x1 << 3 ) /* EN. Load the internal compare registers with the values in PWMxCOMx on the next transition of the PWM timer from 0x00 to 0x01. */ + +/* PWMCON0[DIR] - Direction Control. Available in H-Bridge mode only. */ +#define PWMCON0_DIR_BBA (*(volatile unsigned long *) 0x42020008) +#define PWMCON0_DIR_MSK (0x1 << 2 ) +#define PWMCON0_DIR (0x1 << 2 ) +#define PWMCON0_DIR_DIS (0x0 << 2 ) /* DIS. Enable PWM2 and PWM3 as the output signals while PWM0 and PWM1 are held low. */ +#define PWMCON0_DIR_EN (0x1 << 2 ) /* EN. Enable PWM0 and PWM1 as the output signals while PWM2 and PWM3 are held low. */ + +/* PWMCON0[HMODE] - Enable H-Bridge Mode. */ +#define PWMCON0_HMODE_BBA (*(volatile unsigned long *) 0x42020004) +#define PWMCON0_HMODE_MSK (0x1 << 1 ) +#define PWMCON0_HMODE (0x1 << 1 ) +#define PWMCON0_HMODE_DIS (0x0 << 1 ) /* DIS. The PWM operates in standard mode. */ +#define PWMCON0_HMODE_EN (0x1 << 1 ) /* EN. The PWM is configured in H-Bridge mode. */ + +/* PWMCON0[PWMEN] - Enable all PWM outputs. */ +#define PWMCON0_PWMEN_BBA (*(volatile unsigned long *) 0x42020000) +#define PWMCON0_PWMEN_MSK (0x1 << 0 ) +#define PWMCON0_PWMEN (0x1 << 0 ) +#define PWMCON0_PWMEN_DIS (0x0 << 0 ) /* DIS. Disables all PWM outputs. */ +#define PWMCON0_PWMEN_EN (0x1 << 0 ) /* EN. Enables all PWM outputs. */ + +/* Reset Value for PWMCON1*/ +#define PWMCON1_RVAL 0x0 + +/* PWMCON1[TRIPEN] - Enable PWM trip functionality. */ +#define PWMCON1_TRIPEN_BBA (*(volatile unsigned long *) 0x42020098) +#define PWMCON1_TRIPEN_MSK (0x1 << 6 ) +#define PWMCON1_TRIPEN (0x1 << 6 ) +#define PWMCON1_TRIPEN_DIS (0x0 << 6 ) /* DIS. Disable PWM trip functionality. */ +#define PWMCON1_TRIPEN_EN (0x1 << 6 ) /* EN. Enable PWM trip functionality. */ + +/* Reset Value for PWMCLRI*/ +#define PWMCLRI_RVAL 0x0 + +/* PWMCLRI[TRIP] - Clear the latched trip interrupt. This bit always reads 0. */ +#define PWMCLRI_TRIP_BBA (*(volatile unsigned long *) 0x42020110) +#define PWMCLRI_TRIP_MSK (0x1 << 4 ) +#define PWMCLRI_TRIP (0x1 << 4 ) +#define PWMCLRI_TRIP_EN (0x1 << 4 ) /* EN. Clear the latched PWMTRIP interrupt. */ + +/* PWMCLRI[IRQPWM3] - Clear the latched PWM3 interrupt. This bit always reads 0. */ +#define PWMCLRI_IRQPWM3_BBA (*(volatile unsigned long *) 0x4202010C) +#define PWMCLRI_IRQPWM3_MSK (0x1 << 3 ) +#define PWMCLRI_IRQPWM3 (0x1 << 3 ) +#define PWMCLRI_IRQPWM3_EN (0x1 << 3 ) /* EN. Clear the latched IRQPWM3 interrupt. */ + +/* PWMCLRI[IRQPWM2] - Clear the latched PWM2 interrupt. This bit always reads 0. */ +#define PWMCLRI_IRQPWM2_BBA (*(volatile unsigned long *) 0x42020108) +#define PWMCLRI_IRQPWM2_MSK (0x1 << 2 ) +#define PWMCLRI_IRQPWM2 (0x1 << 2 ) +#define PWMCLRI_IRQPWM2_EN (0x1 << 2 ) /* EN. Clear the latched IRQPWM2 interrupt. */ + +/* PWMCLRI[IRQPWM1] - Clear the latched PWM1 interrupt. This bit always reads 0. */ +#define PWMCLRI_IRQPWM1_BBA (*(volatile unsigned long *) 0x42020104) +#define PWMCLRI_IRQPWM1_MSK (0x1 << 1 ) +#define PWMCLRI_IRQPWM1 (0x1 << 1 ) +#define PWMCLRI_IRQPWM1_EN (0x1 << 1 ) /* EN. Clear the latched IRQPWM1 interrupt. */ + +/* PWMCLRI[IRQPWM0] - Clear the latched PWM0 interrupt. This bit always reads 0. */ +#define PWMCLRI_IRQPWM0_BBA (*(volatile unsigned long *) 0x42020100) +#define PWMCLRI_IRQPWM0_MSK (0x1 << 0 ) +#define PWMCLRI_IRQPWM0 (0x1 << 0 ) +#define PWMCLRI_IRQPWM0_EN (0x1 << 0 ) /* EN. Clear the latched IRQPWM0 interrupt. */ + +/* Reset Value for PWM0COM0*/ +#define PWM0COM0_RVAL 0x0 + +/* PWM0COM0[VALUE] - */ +#define PWM0COM0_VALUE_MSK (0xFFFF << 0 ) + +/* Reset Value for PWM0COM1*/ +#define PWM0COM1_RVAL 0x0 + +/* PWM0COM1[VALUE] - */ +#define PWM0COM1_VALUE_MSK (0xFFFF << 0 ) + +/* Reset Value for PWM0COM2*/ +#define PWM0COM2_RVAL 0x0 + +/* PWM0COM2[VALUE] - */ +#define PWM0COM2_VALUE_MSK (0xFFFF << 0 ) + +/* Reset Value for PWM0LEN*/ +#define PWM0LEN_RVAL 0x0 + +/* PWM0LEN[VALUE] - */ +#define PWM0LEN_VALUE_MSK (0xFFFF << 0 ) + +/* Reset Value for PWM1COM0*/ +#define PWM1COM0_RVAL 0x0 + +/* PWM1COM0[VALUE] - */ +#define PWM1COM0_VALUE_MSK (0xFFFF << 0 ) + +/* Reset Value for PWM1COM1*/ +#define PWM1COM1_RVAL 0x0 + +/* PWM1COM1[VALUE] - */ +#define PWM1COM1_VALUE_MSK (0xFFFF << 0 ) + +/* Reset Value for PWM1COM2*/ +#define PWM1COM2_RVAL 0x0 + +/* PWM1COM2[VALUE] - */ +#define PWM1COM2_VALUE_MSK (0xFFFF << 0 ) + +/* Reset Value for PWM1LEN*/ +#define PWM1LEN_RVAL 0x0 + +/* PWM1LEN[VALUE] - */ +#define PWM1LEN_VALUE_MSK (0xFFFF << 0 ) + +/* Reset Value for PWM2COM0*/ +#define PWM2COM0_RVAL 0x0 + +/* PWM2COM0[VALUE] - */ +#define PWM2COM0_VALUE_MSK (0xFFFF << 0 ) + +/* Reset Value for PWM2COM1*/ +#define PWM2COM1_RVAL 0x0 + +/* PWM2COM1[VALUE] - */ +#define PWM2COM1_VALUE_MSK (0xFFFF << 0 ) + +/* Reset Value for PWM2COM2*/ +#define PWM2COM2_RVAL 0x0 + +/* PWM2COM2[VALUE] - */ +#define PWM2COM2_VALUE_MSK (0xFFFF << 0 ) + +/* Reset Value for PWM2LEN*/ +#define PWM2LEN_RVAL 0x0 + +/* PWM2LEN[VALUE] - */ +#define PWM2LEN_VALUE_MSK (0xFFFF << 0 ) + +/* Reset Value for PWM3COM0*/ +#define PWM3COM0_RVAL 0x0 + +/* PWM3COM0[VALUE] - */ +#define PWM3COM0_VALUE_MSK (0xFFFF << 0 ) + +/* Reset Value for PWM3COM1*/ +#define PWM3COM1_RVAL 0x0 + +/* PWM3COM1[VALUE] - */ +#define PWM3COM1_VALUE_MSK (0xFFFF << 0 ) + +/* Reset Value for PWM3COM2*/ +#define PWM3COM2_RVAL 0x0 + +/* PWM3COM2[VALUE] - */ +#define PWM3COM2_VALUE_MSK (0xFFFF << 0 ) + +/* Reset Value for PWM3LEN*/ +#define PWM3LEN_RVAL 0x0 + +/* PWM3LEN[VALUE] - */ +#define PWM3LEN_VALUE_MSK (0xFFFF << 0 ) +// ------------------------------------------------------------------------------------------------ +// ----- RESET ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief Reset (pADI_RESET) + */ + +#if (__NO_MMR_STRUCTS__==0) +typedef struct { /*!< pADI_RESET Structure */ + + union { + __IO uint8_t RSTSTA; /*!< Reset Status */ + __IO uint8_t RSTCLR; /*!< Reset Status Clear */ + } ; +} ADI_RESET_TypeDef; +#else // (__NO_MMR_STRUCTS__==0) +#define RSTSTA (*(volatile unsigned char *) 0x40002440) +#define RSTCLR (*(volatile unsigned char *) 0x40002440) +#endif // (__NO_MMR_STRUCTS__==0) + +/* Reset Value for RSTSTA*/ +#define RSTSTA_RVAL 0x3 + +/* RSTSTA[SWRST] - Software reset status bit */ +#define RSTSTA_SWRST_BBA (*(volatile unsigned long *) 0x42048810) +#define RSTSTA_SWRST_MSK (0x1 << 4 ) +#define RSTSTA_SWRST (0x1 << 4 ) +#define RSTSTA_SWRST_CLR (0x0 << 4 ) /* CLR. Indicates that no software reset has occurred. */ +#define RSTSTA_SWRST_SET (0x1 << 4 ) /* SET. Indicates that a software reset has occurred. */ + +/* RSTSTA[WDRST] - Watchdog reset status bit */ +#define RSTSTA_WDRST_BBA (*(volatile unsigned long *) 0x4204880C) +#define RSTSTA_WDRST_MSK (0x1 << 3 ) +#define RSTSTA_WDRST (0x1 << 3 ) +#define RSTSTA_WDRST_CLR (0x0 << 3 ) /* CLR. Indicates that no watchdog reset has occurred. */ +#define RSTSTA_WDRST_SET (0x1 << 3 ) /* SET. Indicates that a Watchdog Reset has occurred. */ + +/* RSTSTA[EXTRST] - External reset status bit */ +#define RSTSTA_EXTRST_BBA (*(volatile unsigned long *) 0x42048808) +#define RSTSTA_EXTRST_MSK (0x1 << 2 ) +#define RSTSTA_EXTRST (0x1 << 2 ) +#define RSTSTA_EXTRST_CLR (0x0 << 2 ) /* CLR. Indicates that no external reset has occurred. */ +#define RSTSTA_EXTRST_SET (0x1 << 2 ) /* SET. Indicates an external reset has occurred. */ + +/* RSTSTA[PORHV] - Power-on reset status bit HV */ +#define RSTSTA_PORHV_BBA (*(volatile unsigned long *) 0x42048804) +#define RSTSTA_PORHV_MSK (0x1 << 1 ) +#define RSTSTA_PORHV (0x1 << 1 ) +#define RSTSTA_PORHV_CLR (0x0 << 1 ) /* CLR. Indicates a POR or wake up from SHUTDOWN has not occurred. */ +#define RSTSTA_PORHV_SET (0x1 << 1 ) /* SET. This bit indicates that the AVDD supply has dropped below the POR trip point, causing a Power On Reset. It is also set when waking up from SHUTDOWN mode. */ + +/* RSTSTA[PORLV] - Power-on reset status bit LV */ +#define RSTSTA_PORLV_BBA (*(volatile unsigned long *) 0x42048800) +#define RSTSTA_PORLV_MSK (0x1 << 0 ) +#define RSTSTA_PORLV (0x1 << 0 ) +#define RSTSTA_PORLV_CLR (0x0 << 0 ) /* CLR. Indicates a POR or wake up from SHUTDOWN has not occurred. */ +#define RSTSTA_PORLV_SET (0x1 << 0 ) /* SET. This bit indicates that the AVDD supply has dropped below the POR trip point, causing a Power On Reset. It is also set when waking up from SHUTDOWN mode. */ + +/* Reset Value for RSTCLR*/ +#define RSTCLR_RVAL 0x3 + +/* RSTCLR[SWRST] - Software reset clear status bit */ +#define RSTCLR_SWRST_BBA (*(volatile unsigned long *) 0x42048810) +#define RSTCLR_SWRST_MSK (0x1 << 4 ) +#define RSTCLR_SWRST (0x1 << 4 ) +#define RSTCLR_SWRST_DIS (0x0 << 4 ) /* DIS. Has no effect. */ +#define RSTCLR_SWRST_EN (0x1 << 4 ) /* EN. Clears the SWRST status bit in RSTSTA. */ + +/* RSTCLR[WDRST] - Watchdog reset clear status bit */ +#define RSTCLR_WDRST_BBA (*(volatile unsigned long *) 0x4204880C) +#define RSTCLR_WDRST_MSK (0x1 << 3 ) +#define RSTCLR_WDRST (0x1 << 3 ) +#define RSTCLR_WDRST_DIS (0x0 << 3 ) /* DIS. Has no effect. */ +#define RSTCLR_WDRST_EN (0x1 << 3 ) /* EN. Clears the WDRST status bit in RSTSTA. */ + +/* RSTCLR[EXTRST] - External reset clear status bit */ +#define RSTCLR_EXTRST_BBA (*(volatile unsigned long *) 0x42048808) +#define RSTCLR_EXTRST_MSK (0x1 << 2 ) +#define RSTCLR_EXTRST (0x1 << 2 ) +#define RSTCLR_EXTRST_DIS (0x0 << 2 ) /* DIS. Has no effect. */ +#define RSTCLR_EXTRST_EN (0x1 << 2 ) /* EN. Clears the EXTRST status bit in RSTSTA. */ + +/* RSTCLR[PORHV] - Power on reset clear status bit */ +#define RSTCLR_PORHV_BBA (*(volatile unsigned long *) 0x42048804) +#define RSTCLR_PORHV_MSK (0x1 << 1 ) +#define RSTCLR_PORHV (0x1 << 1 ) +#define RSTCLR_PORHV_DIS (0x0 << 1 ) /* DIS. Has no effect. */ +#define RSTCLR_PORHV_EN (0x1 << 1 ) /* EN. Clears PORLV status bit in RSTSTA. */ + +/* RSTCLR[PORLV] - Power-on reset clear status bit LV */ +#define RSTCLR_PORLV_BBA (*(volatile unsigned long *) 0x42048800) +#define RSTCLR_PORLV_MSK (0x1 << 0 ) +#define RSTCLR_PORLV (0x1 << 0 ) +#define RSTCLR_PORLV_DIS (0x0 << 0 ) /* DIS. Has no effect. */ +#define RSTCLR_PORLV_EN (0x1 << 0 ) /* EN. Clears the PORLV status bit in RSTSTA. */ +// ------------------------------------------------------------------------------------------------ +// ----- SPI0 ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief Serial Peripheral Interface (pADI_SPI0) + */ + +#if (__NO_MMR_STRUCTS__==0) +typedef struct { /*!< pADI_SPI0 Structure */ + __IO uint16_t SPISTA; /*!< SPI0 Status Register */ + __I uint16_t RESERVED0; + __IO uint8_t SPIRX; /*!< SPI0 Receive Register */ + __I uint8_t RESERVED1[3]; + __IO uint8_t SPITX; /*!< SPI0 Transmit Register */ + __I uint8_t RESERVED2[3]; + __IO uint16_t SPIDIV; /*!< SPI0 Bit Rate Selection Register */ + __I uint16_t RESERVED3; + __IO uint16_t SPICON; /*!< SPI0 Configuration Register */ + __I uint16_t RESERVED4; + __IO uint16_t SPIDMA; /*!< SPI0 DMA Enable Register */ + __I uint16_t RESERVED5; + __IO uint16_t SPICNT; /*!< SPI0 DMA Master Received Byte Count Register */ +} ADI_SPI_TypeDef; +#else // (__NO_MMR_STRUCTS__==0) +#define SPI0STA (*(volatile unsigned short int *) 0x40004000) +#define SPI0RX (*(volatile unsigned char *) 0x40004004) +#define SPI0TX (*(volatile unsigned char *) 0x40004008) +#define SPI0DIV (*(volatile unsigned short int *) 0x4000400C) +#define SPI0CON (*(volatile unsigned short int *) 0x40004010) +#define SPI0DMA (*(volatile unsigned short int *) 0x40004014) +#define SPI0CNT (*(volatile unsigned short int *) 0x40004018) +#endif // (__NO_MMR_STRUCTS__==0) + +/* Reset Value for SPI0STA*/ +#define SPI0STA_RVAL 0x0 + +/* SPI0STA[CSERR] - CS error status bit. This bit generates an interrupt when detecting an abrupt CS desassertion before the full byte of data is transmitted completely. */ +#define SPI0STA_CSERR_BBA (*(volatile unsigned long *) 0x42080030) +#define SPI0STA_CSERR_MSK (0x1 << 12 ) +#define SPI0STA_CSERR (0x1 << 12 ) +#define SPI0STA_CSERR_CLR (0x0 << 12 ) /* CLR: Cleared when no CS error is detected. Cleared to 0 on a read of SPI0STA register. */ +#define SPI0STA_CSERR_SET (0x1 << 12 ) /* SET: Set when the CS line is deasserted abruptly. */ + +/* SPI0STA[RXS] - Rx FIFO excess bytes present. */ +#define SPI0STA_RXS_BBA (*(volatile unsigned long *) 0x4208002C) +#define SPI0STA_RXS_MSK (0x1 << 11 ) +#define SPI0STA_RXS (0x1 << 11 ) +#define SPI0STA_RXS_CLR (0x0 << 11 ) /* CLR. When the number of bytes in the FIFO is equal or less than the number in SPI0CON[15:14]. This bit is not cleared on a read of SPI0STA register. */ +#define SPI0STA_RXS_SET (0x1 << 11 ) /* SET. When there are more bytes in the Rx FIFO than configured in MOD (SPI0CON[15:14]). For example if MOD = TX1RX1, RXS is set when there are 2 or more bytes in the Rx FIFO. This bit does not dependent on SPI0CON[6] and does not cause an interrupt. */ + +/* SPI0STA[RXFSTA] - Rx FIFO status bits, indicates how many valid bytes are in the Rx FIFO. */ +#define SPI0STA_RXFSTA_MSK (0x7 << 8 ) +#define SPI0STA_RXFSTA_EMPTY (0x0 << 8 ) /* EMPTY. When Rx FIFO is empty. */ +#define SPI0STA_RXFSTA_ONEBYTE (0x1 << 8 ) /* ONEBYTE. When 1 valid byte is in the FIFO. */ +#define SPI0STA_RXFSTA_TWOBYTES (0x2 << 8 ) /* TWOBYTES. When 2 valid bytes are in the FIFO. */ +#define SPI0STA_RXFSTA_THREEBYTES (0x3 << 8 ) /* THREEBYTES. When 3 valid bytes are in the FIFO. */ +#define SPI0STA_RXFSTA_FOURBYTES (0x4 << 8 ) /* FOURBYTES. When 4 valid bytes are in the FIFO. */ + +/* SPI0STA[RXOF] - Rx FIFO overflow status bit. This bit generates an interrupt. */ +#define SPI0STA_RXOF_BBA (*(volatile unsigned long *) 0x4208001C) +#define SPI0STA_RXOF_MSK (0x1 << 7 ) +#define SPI0STA_RXOF (0x1 << 7 ) +#define SPI0STA_RXOF_CLR (0x0 << 7 ) /* CLR. Cleared to 0 on a read of SPI0STA register. */ +#define SPI0STA_RXOF_SET (0x1 << 7 ) /* SET. Set when the Rx FIFO is already full when new data is loaded to the FIFO. This bit generates an interrupt except when RFLUSH is set. (SPI0CON[12]). */ + +/* SPI0STA[RX] - Rx interrupt status bit. This bit generates an interrupt, except when DMA transfer is enabled. */ +#define SPI0STA_RX_BBA (*(volatile unsigned long *) 0x42080018) +#define SPI0STA_RX_MSK (0x1 << 6 ) +#define SPI0STA_RX (0x1 << 6 ) +#define SPI0STA_RX_CLR (0x0 << 6 ) /* CLR. Cleared to 0 on a read of SPI0STA register. */ +#define SPI0STA_RX_SET (0x1 << 6 ) /* SET. Set when a receive interrupt occurs. This bit is set when TIM (SPI0CON[6]) is cleared and the required number of bytes have been received. */ + +/* SPI0STA[TX] - Tx interrupt status bit. This bit generates an interrupt, except when DMA transfer is enabled. */ +#define SPI0STA_TX_BBA (*(volatile unsigned long *) 0x42080014) +#define SPI0STA_TX_MSK (0x1 << 5 ) +#define SPI0STA_TX (0x1 << 5 ) +#define SPI0STA_TX_CLR (0x0 << 5 ) /* CLR. Cleared to 0 on a read of SPI0STA register. */ +#define SPI0STA_TX_SET (0x1 << 5 ) /* SET. Set when a transmit interrupt occurs. This bit is set when TIM (SPI0CON[6]) set and the required number of bytes have been transmitted. */ + +/* SPI0STA[TXUR] - Tx FIFO Underrun. This bit generates an interrupt. */ +#define SPI0STA_TXUR_BBA (*(volatile unsigned long *) 0x42080010) +#define SPI0STA_TXUR_MSK (0x1 << 4 ) +#define SPI0STA_TXUR (0x1 << 4 ) +#define SPI0STA_TXUR_CLR (0x0 << 4 ) /* CLR. Cleared to 0 on a read of SPI0STA register. */ +#define SPI0STA_TXUR_SET (0x1 << 4 ) /* SET. Set when a transmit is initiated without any valid data in the Tx FIFO. This bit generates an interrupt except when TFLUSH is set in SPI0CON. */ + +/* SPI0STA[TXFSTA] - Tx FIFO status bits, indicates how many valid bytes are in the Tx FIFO. */ +#define SPI0STA_TXFSTA_MSK (0x7 << 1 ) +#define SPI0STA_TXFSTA_EMPTY (0x0 << 1 ) /* EMPTY. Tx FIFO is empty. */ +#define SPI0STA_TXFSTA_ONEBYTE (0x1 << 1 ) /* ONEBYTE. 1 valid byte is in the FIFO. */ +#define SPI0STA_TXFSTA_TWOBYTES (0x2 << 1 ) /* TWOBYTES. 2 valid bytes are in the FIFO. */ +#define SPI0STA_TXFSTA_THREEBYTES (0x3 << 1 ) /* THREEBYTES. 3 valid bytes are in the FIFO. */ +#define SPI0STA_TXFSTA_FOURBYTES (0x4 << 1 ) /* FOURBYTES . 4 valid bytes are in the FIFO. */ + +/* SPI0STA[IRQ] - Interrupt status bit. */ +#define SPI0STA_IRQ_BBA (*(volatile unsigned long *) 0x42080000) +#define SPI0STA_IRQ_MSK (0x1 << 0 ) +#define SPI0STA_IRQ (0x1 << 0 ) +#define SPI0STA_IRQ_CLR (0x0 << 0 ) /* CLR. Cleared to 0 on a read of SPI0STA register. */ +#define SPI0STA_IRQ_SET (0x1 << 0 ) /* SET. Set to 1 when an SPI0 based interrupt occurs. */ + +/* Reset Value for SPI0RX*/ +#define SPI0RX_RVAL 0x0 + +/* SPI0RX[VALUE] - 8-bit receive register. A read of the RX FIFO returns the next byte to be read from the FIFO. A read of the FIFO when it is empty returns zero. */ +#define SPI0RX_VALUE_MSK (0xFF << 0 ) + +/* Reset Value for SPI0TX*/ +#define SPI0TX_RVAL 0x0 + +/* SPI0TX[VALUE] - 8-bit transmit register. A write to the Tx FIFO address space writes data to the next available location in the Tx FIFO. If the FIFO is full, the oldest byte of data in the FIFO is overwritten. A read from this address location return zero. */ +#define SPI0TX_VALUE_MSK (0xFF << 0 ) + +/* Reset Value for SPI0DIV*/ +#define SPI0DIV_RVAL 0x0 + +/* SPI0DIV[BCRST] - Configures the behavior of SPI communication after an abrupt deassertion of CS. This bit should be set in slave and master mode. */ +#define SPI0DIV_BCRST_BBA (*(volatile unsigned long *) 0x4208019C) +#define SPI0DIV_BCRST_MSK (0x1 << 7 ) +#define SPI0DIV_BCRST (0x1 << 7 ) +#define SPI0DIV_BCRST_DIS (0x0 << 7 ) /* DIS. Resumes communication from where it stopped when the CS is deasserted. The rest of the bits are then received/ transmitted when CS returns low. User code should ignore the CSERR interrupt. */ +#define SPI0DIV_BCRST_EN (0x1 << 7 ) /* EN. Enabled for a clean restart of SPI transfer after a CSERR condition. User code must also clear the SPI enable bit in SPI0CON during the CSERR interrupt. */ + +/* SPI0DIV[DIV] - Factor used to divide UCLK in the generation of the master mode serial clock. */ +#define SPI0DIV_DIV_MSK (0x3F << 0 ) + +/* Reset Value for SPI0CON*/ +#define SPI0CON_RVAL 0x0 + +/* SPI0CON[MOD] - IRQ mode bits. When TIM is set these bits configure when the Tx/Rx interrupts occur in a transfer. For a DMA Rx transfer, these bits should be 00. */ +#define SPI0CON_MOD_MSK (0x3 << 14 ) +#define SPI0CON_MOD_TX1RX1 (0x0 << 14 ) /* TX1RX1. Tx/Rx interrupt occurs when 1 byte has been transmitted/received from/into the FIFO. */ +#define SPI0CON_MOD_TX2RX2 (0x1 << 14 ) /* TX2RX2. Tx/Rx interrupt occurs when 2 bytes have been transmitted/received from/into the FIFO. */ +#define SPI0CON_MOD_TX3RX3 (0x2 << 14 ) /* TX3RX3. Tx/Rx interrupt occurs when 3 bytes have been transmitted/received from/into the FIFO. */ +#define SPI0CON_MOD_TX4RX4 (0x3 << 14 ) /* TX4RX4. Tx/Rx interrupt occurs when 4 bytes have been transmitted/received from/into the FIFO. */ + +/* SPI0CON[TFLUSH] - Tx FIFO flush enable bit. */ +#define SPI0CON_TFLUSH_BBA (*(volatile unsigned long *) 0x42080234) +#define SPI0CON_TFLUSH_MSK (0x1 << 13 ) +#define SPI0CON_TFLUSH (0x1 << 13 ) +#define SPI0CON_TFLUSH_DIS (0x0 << 13 ) /* DIS. Disable Tx FIFO flushing. */ +#define SPI0CON_TFLUSH_EN (0x1 << 13 ) /* EN. Flush the Tx FIFO. This bit does not clear itself and should be toggled if a single flush is required. If this bit is left high, then either the last transmitted value or 0x00 is transmitted depending on the ZEN bit (SPI0CON[7]). Any writes to the Tx FIFO are ignored while this bit is set. */ + +/* SPI0CON[RFLUSH] - Rx FIFO flush enable bit. */ +#define SPI0CON_RFLUSH_BBA (*(volatile unsigned long *) 0x42080230) +#define SPI0CON_RFLUSH_MSK (0x1 << 12 ) +#define SPI0CON_RFLUSH (0x1 << 12 ) +#define SPI0CON_RFLUSH_DIS (0x0 << 12 ) /* DIS. Disable Rx FIFO flushing. */ +#define SPI0CON_RFLUSH_EN (0x1 << 12 ) /* EN. If this bit is set, all incoming data is ignored and no interrupts are generated. If set and TIM = 0 (SPI0CON[6]), a read of the Rx FIFO initiates a transfer. */ + +/* SPI0CON[CON] - Continuous transfer enable bit. */ +#define SPI0CON_CON_BBA (*(volatile unsigned long *) 0x4208022C) +#define SPI0CON_CON_MSK (0x1 << 11 ) +#define SPI0CON_CON (0x1 << 11 ) +#define SPI0CON_CON_DIS (0x0 << 11 ) /* DIS. Disable continuous transfer. Each transfer consists of a single 8-bit serial transfer. If valid data exists in the SPIxTX register, then a new transfer is initiated after a stall period of one serial clock cycle. The CS line is deactivated for this one serial clock cycle. */ +#define SPI0CON_CON_EN (0x1 << 11 ) /* EN. Enable continuous transfer. In master mode, the transfer continues until no valid data is available in the Tx register. CS is asserted and remains asserted for the duration of each 8-bit serial transfer until Tx is empty. */ + +/* SPI0CON[LOOPBACK] - Loopback enable bit. */ +#define SPI0CON_LOOPBACK_BBA (*(volatile unsigned long *) 0x42080228) +#define SPI0CON_LOOPBACK_MSK (0x1 << 10 ) +#define SPI0CON_LOOPBACK (0x1 << 10 ) +#define SPI0CON_LOOPBACK_DIS (0x0 << 10 ) /* DIS. Normal mode. */ +#define SPI0CON_LOOPBACK_EN (0x1 << 10 ) /* EN. Connect MISO to MOSI, thus, data transmitted from Tx register is looped back to the Rx register. SPI must be configured in master mode. */ + +/* SPI0CON[SOEN] - Slave output enable bit. */ +#define SPI0CON_SOEN_BBA (*(volatile unsigned long *) 0x42080224) +#define SPI0CON_SOEN_MSK (0x1 << 9 ) +#define SPI0CON_SOEN (0x1 << 9 ) +#define SPI0CON_SOEN_DIS (0x0 << 9 ) /* DIS. Disable the output driver on the MISO pin. The MISO pin is open-circuit when this bit is clear. */ +#define SPI0CON_SOEN_EN (0x1 << 9 ) /* EN. MISO operates as normal. */ + +/* SPI0CON[RXOF] - RX overflow overwrite enable bit. */ +#define SPI0CON_RXOF_BBA (*(volatile unsigned long *) 0x42080220) +#define SPI0CON_RXOF_MSK (0x1 << 8 ) +#define SPI0CON_RXOF (0x1 << 8 ) +#define SPI0CON_RXOF_DIS (0x0 << 8 ) /* DIS. The new serial byte received is discarded when there is no space left in the FIFO */ +#define SPI0CON_RXOF_EN (0x1 << 8 ) /* EN. The valid data in the Rx register is overwritten by the new serial byte received when there is no space left in the FIFO. */ + +/* SPI0CON[ZEN] - Transmit underrun: Transmit 0s when the Tx FIFO is empty */ +#define SPI0CON_ZEN_BBA (*(volatile unsigned long *) 0x4208021C) +#define SPI0CON_ZEN_MSK (0x1 << 7 ) +#define SPI0CON_ZEN (0x1 << 7 ) +#define SPI0CON_ZEN_DIS (0x0 << 7 ) /* DIS. The last byte from the previous transmission is shifted out when a transfer is initiated with no valid data in the FIFO. */ +#define SPI0CON_ZEN_EN (0x1 << 7 ) /* EN. Transmit 0x00 when a transfer is initiated with no valid data in the FIFO. */ + +/* SPI0CON[TIM] - Transfer and interrupt mode bit. */ +#define SPI0CON_TIM_BBA (*(volatile unsigned long *) 0x42080218) +#define SPI0CON_TIM_MSK (0x1 << 6 ) +#define SPI0CON_TIM (0x1 << 6 ) +#define SPI0CON_TIM_TXWR (0x1 << 6 ) /* TXWR. Initiate transfer with a write to the SPIxTX register. Interrupt only occurs when Tx is empty. */ +#define SPI0CON_TIM_RXRD (0x0 << 6 ) /* RXRD. Initiate transfer with a read of the SPIxRX register. The read must be done while the SPI interface is idle. Interrupt only occurs when Rx is full. */ + +/* SPI0CON[LSB] - LSB first transfer enable bit. */ +#define SPI0CON_LSB_BBA (*(volatile unsigned long *) 0x42080214) +#define SPI0CON_LSB_MSK (0x1 << 5 ) +#define SPI0CON_LSB (0x1 << 5 ) +#define SPI0CON_LSB_DIS (0x0 << 5 ) /* DIS. MSB is transmitted first. */ +#define SPI0CON_LSB_EN (0x1 << 5 ) /* EN. LSB is transmitted first. */ + +/* SPI0CON[WOM] - Wired OR enable bit. */ +#define SPI0CON_WOM_BBA (*(volatile unsigned long *) 0x42080210) +#define SPI0CON_WOM_MSK (0x1 << 4 ) +#define SPI0CON_WOM (0x1 << 4 ) +#define SPI0CON_WOM_DIS (0x0 << 4 ) /* DIS. Normal driver output operation. */ +#define SPI0CON_WOM_EN (0x1 << 4 ) /* EN. Enable open circuit data output for multimaster/multislave configuration. */ + +/* SPI0CON[CPOL] - Serial clock polarity mode bit. */ +#define SPI0CON_CPOL_BBA (*(volatile unsigned long *) 0x4208020C) +#define SPI0CON_CPOL_MSK (0x1 << 3 ) +#define SPI0CON_CPOL (0x1 << 3 ) +#define SPI0CON_CPOL_LOW (0x0 << 3 ) /* LOW. Serial clock idles low. */ +#define SPI0CON_CPOL_HIGH (0x1 << 3 ) /* HIGH. Serial clock idles high. */ + +/* SPI0CON[CPHA] - Serial clock phase mode bit. */ +#define SPI0CON_CPHA_BBA (*(volatile unsigned long *) 0x42080208) +#define SPI0CON_CPHA_MSK (0x1 << 2 ) +#define SPI0CON_CPHA (0x1 << 2 ) +#define SPI0CON_CPHA_SAMPLELEADING (0x0 << 2 ) /* SAMPLELEADING. Serial clock pulses at the middle of the first data bit transfer. */ +#define SPI0CON_CPHA_SAMPLETRAILING (0x1 << 2 ) /* SAMPLETRAILING. Serial clock pulses at the start of the first data bit. */ + +/* SPI0CON[MASEN] - Master mode enable bit. */ +#define SPI0CON_MASEN_BBA (*(volatile unsigned long *) 0x42080204) +#define SPI0CON_MASEN_MSK (0x1 << 1 ) +#define SPI0CON_MASEN (0x1 << 1 ) +#define SPI0CON_MASEN_DIS (0x0 << 1 ) /* DIS. Configure in slave mode. */ +#define SPI0CON_MASEN_EN (0x1 << 1 ) /* EN. Configure in master mode. */ + +/* SPI0CON[ENABLE] - SPI enable bit. */ +#define SPI0CON_ENABLE_BBA (*(volatile unsigned long *) 0x42080200) +#define SPI0CON_ENABLE_MSK (0x1 << 0 ) +#define SPI0CON_ENABLE (0x1 << 0 ) +#define SPI0CON_ENABLE_DIS (0x0 << 0 ) /* DIS. Disable the SPI. Clearing this bit will also reset all the FIFO related logic to enable a clean start. */ +#define SPI0CON_ENABLE_EN (0x1 << 0 ) /* EN. Enable the SPI. */ + +/* Reset Value for SPI0DMA*/ +#define SPI0DMA_RVAL 0x0 + +/* SPI0DMA[IENRXDMA] - Receive DMA request enable bit. */ +#define SPI0DMA_IENRXDMA_BBA (*(volatile unsigned long *) 0x42080288) +#define SPI0DMA_IENRXDMA_MSK (0x1 << 2 ) +#define SPI0DMA_IENRXDMA (0x1 << 2 ) +#define SPI0DMA_IENRXDMA_DIS (0x0 << 2 ) /* DIS. Disable Rx DMA requests. */ +#define SPI0DMA_IENRXDMA_EN (0x1 << 2 ) /* EN. Enable Rx DMA requests. */ + +/* SPI0DMA[IENTXDMA] - Transmit DMA request enable bit. */ +#define SPI0DMA_IENTXDMA_BBA (*(volatile unsigned long *) 0x42080284) +#define SPI0DMA_IENTXDMA_MSK (0x1 << 1 ) +#define SPI0DMA_IENTXDMA (0x1 << 1 ) +#define SPI0DMA_IENTXDMA_DIS (0x0 << 1 ) /* DIS. Disable Tx DMA requests. */ +#define SPI0DMA_IENTXDMA_EN (0x1 << 1 ) /* EN. Enable Tx DMA requests. */ + +/* SPI0DMA[ENABLE] - DMA data transfer enable bit. */ +#define SPI0DMA_ENABLE_BBA (*(volatile unsigned long *) 0x42080280) +#define SPI0DMA_ENABLE_MSK (0x1 << 0 ) +#define SPI0DMA_ENABLE (0x1 << 0 ) +#define SPI0DMA_ENABLE_DIS (0x0 << 0 ) /* DIS. Disable DMA transfer. This bit needs to be cleared to prevent extra DMA request to the µDMA controller. */ +#define SPI0DMA_ENABLE_EN (0x1 << 0 ) /* EN. Enable a DMA transfer. Starts the transfer of a master configured to initiate transfer on transmit. */ + +/* Reset Value for SPI0CNT*/ +#define SPI0CNT_RVAL 0x0 + +/* SPI0CNT[VALUE] - Number of bytes requested by the SPI master during DMA transfer, when configured to initiate a transfer on a read of SPI0RX. This register is only used in DMA, master, Rx mode. */ +#define SPI0CNT_VALUE_MSK (0xFF << 0 ) +#if (__NO_MMR_STRUCTS__==1) + +#define SPI1STA (*(volatile unsigned short int *) 0x40004400) +#define SPI1RX (*(volatile unsigned char *) 0x40004404) +#define SPI1TX (*(volatile unsigned char *) 0x40004408) +#define SPI1DIV (*(volatile unsigned short int *) 0x4000440C) +#define SPI1CON (*(volatile unsigned short int *) 0x40004410) +#define SPI1DMA (*(volatile unsigned short int *) 0x40004414) +#define SPI1CNT (*(volatile unsigned short int *) 0x40004418) +#endif // (__NO_MMR_STRUCTS__==1) + +/* Reset Value for SPI1STA*/ +#define SPI1STA_RVAL 0x0 + +/* SPI1STA[CSERR] - CS error status bit. This bit generates an interrupt when detecting an abrupt CS desassertion before the full byte of data is transmitted completely. */ +#define SPI1STA_CSERR_BBA (*(volatile unsigned long *) 0x42088030) +#define SPI1STA_CSERR_MSK (0x1 << 12 ) +#define SPI1STA_CSERR (0x1 << 12 ) +#define SPI1STA_CSERR_CLR (0x0 << 12 ) /* CLR: Cleared when no CS error is detected. Cleared to 0 on a read of SPI1STA register. */ +#define SPI1STA_CSERR_SET (0x1 << 12 ) /* SET. Set when the CS line is deasserted abruptly. */ + +/* SPI1STA[RXS] - Rx FIFO excess bytes present. */ +#define SPI1STA_RXS_BBA (*(volatile unsigned long *) 0x4208802C) +#define SPI1STA_RXS_MSK (0x1 << 11 ) +#define SPI1STA_RXS (0x1 << 11 ) +#define SPI1STA_RXS_CLR (0x0 << 11 ) /* CLR. When the number of bytes in the FIFO is equal or less than the number in SPI0CON[15:14]. This bit is not cleared on a read of SPI0STA register. */ +#define SPI1STA_RXS_SET (0x1 << 11 ) /* SET. When there are more bytes in the Rx FIFO than configured in MOD (SPI1CON[15:14]). For example if MOD = TX1RX1, RXS is set when there are 2 or more bytes in the Rx FIFO. This bit does not dependent on SPI1CON[6] and does not cause an interrupt. */ + +/* SPI1STA[RXFSTA] - Rx FIFO status bits, indicates how many valid bytes are in the Rx FIFO. */ +#define SPI1STA_RXFSTA_MSK (0x7 << 8 ) +#define SPI1STA_RXFSTA_EMPTY (0x0 << 8 ) /* EMPTY. When Rx FIFO is empty. */ +#define SPI1STA_RXFSTA_ONEBYTE (0x1 << 8 ) /* ONEBYTE. When 1 valid byte is in the FIFO. */ +#define SPI1STA_RXFSTA_TWOBYTES (0x2 << 8 ) /* TWOBYTES. When 2 valid bytes are in the FIFO. */ +#define SPI1STA_RXFSTA_THREEBYTES (0x3 << 8 ) /* THREEBYTES. When 3 valid bytes are in the FIFO. */ +#define SPI1STA_RXFSTA_FOURBYTES (0x4 << 8 ) /* FOURBYTES. When 4 valid bytes are in the FIFO. */ + +/* SPI1STA[RXOF] - Rx FIFO overflow status bit. This bit generates an interrupt. */ +#define SPI1STA_RXOF_BBA (*(volatile unsigned long *) 0x4208801C) +#define SPI1STA_RXOF_MSK (0x1 << 7 ) +#define SPI1STA_RXOF (0x1 << 7 ) +#define SPI1STA_RXOF_CLR (0x0 << 7 ) /* CLR.Cleared to 0 on a read of SPI1STA register. */ +#define SPI1STA_RXOF_SET (0x1 << 7 ) /* SET. Set when the Rx FIFO is already full when new data is loaded to the FIFO. This bit generates an interrupt except when RFLUSH is set. (SPI1CON[12]). */ + +/* SPI1STA[RX] - Rx interrupt status bit. This bit generates an interrupt, except when DMA transfer is enabled. */ +#define SPI1STA_RX_BBA (*(volatile unsigned long *) 0x42088018) +#define SPI1STA_RX_MSK (0x1 << 6 ) +#define SPI1STA_RX (0x1 << 6 ) +#define SPI1STA_RX_CLR (0x0 << 6 ) /* CLR. Cleared to 0 on a read of SPI1STA register. */ +#define SPI1STA_RX_SET (0x1 << 6 ) /* SET. Set when a receive interrupt occurs. This bit is set when TIM (SPI1CON[6]) is cleared and the required number of bytes have been received. */ + +/* SPI1STA[TX] - Tx interrupt status bit. This bit generates an interrupt, except when DMA transfer is enabled. */ +#define SPI1STA_TX_BBA (*(volatile unsigned long *) 0x42088014) +#define SPI1STA_TX_MSK (0x1 << 5 ) +#define SPI1STA_TX (0x1 << 5 ) +#define SPI1STA_TX_CLR (0x0 << 5 ) /* CLR. Cleared to 0 on a read of SPI1STA register. */ +#define SPI1STA_TX_SET (0x1 << 5 ) /* SET. Set when a transmit interrupt occurs. This bit is set when TIM (SPI1CON[6]) is set and the required number of bytes have been transmitted. */ + +/* SPI1STA[TXUR] - Tx FIFO Underrun. This bit generates an interrupt. */ +#define SPI1STA_TXUR_BBA (*(volatile unsigned long *) 0x42088010) +#define SPI1STA_TXUR_MSK (0x1 << 4 ) +#define SPI1STA_TXUR (0x1 << 4 ) +#define SPI1STA_TXUR_CLR (0x0 << 4 ) /* CLR. Cleared to 0 on a read of SPI1STA register. */ +#define SPI1STA_TXUR_SET (0x1 << 4 ) /* SET. Set when a transmit is initiated without any valid data in the Tx FIFO. This bit generates an interrupt except when TFLUSH is set in SPI1CON. */ + +/* SPI1STA[TXFSTA] - Tx FIFO status bits, indicates how many valid bytes are in the Tx FIFO. */ +#define SPI1STA_TXFSTA_MSK (0x7 << 1 ) +#define SPI1STA_TXFSTA_EMPTY (0x0 << 1 ) /* EMPTY. When Tx FIFO is empty. */ +#define SPI1STA_TXFSTA_ONEBYTE (0x1 << 1 ) /* ONEBYTE. 1 valid byte is in the FIFO. */ +#define SPI1STA_TXFSTA_TWOBYTES (0x2 << 1 ) /* TWOBYTES. 2 valid bytes are in the FIFO. */ +#define SPI1STA_TXFSTA_THREEBYTES (0x3 << 1 ) /* THREEBYTES. 3 valid bytes are in the FIFO. */ +#define SPI1STA_TXFSTA_FOURBYTES (0x4 << 1 ) /* FOURBYTES. 4 valid bytes are in the FIFO. */ + +/* SPI1STA[IRQ] - Interrupt status bit. */ +#define SPI1STA_IRQ_BBA (*(volatile unsigned long *) 0x42088000) +#define SPI1STA_IRQ_MSK (0x1 << 0 ) +#define SPI1STA_IRQ (0x1 << 0 ) +#define SPI1STA_IRQ_CLR (0x0 << 0 ) /* CLR. Cleared to 0 on a read of SPI1STA register. */ +#define SPI1STA_IRQ_SET (0x1 << 0 ) /* SET. Set to 1 when an SPI1 based interrupt occurs. */ + +/* Reset Value for SPI1RX*/ +#define SPI1RX_RVAL 0x0 + +/* SPI1RX[VALUE] - 8-bit receive register. A read of the RX FIFO returns the next byte to be read from the FIFO. A read of the FIFO when it is empty returns zero. */ +#define SPI1RX_VALUE_MSK (0xFF << 0 ) + +/* Reset Value for SPI1TX*/ +#define SPI1TX_RVAL 0x0 + +/* SPI1TX[VALUE] - 8-bit transmit register. A write to the Tx FIFO address space writes data to the next available location in the Tx FIFO. If the FIFO is full, the oldest byte of data in the FIFO is overwritten. A read from this address location return zero. */ +#define SPI1TX_VALUE_MSK (0xFF << 0 ) + +/* Reset Value for SPI1DIV*/ +#define SPI1DIV_RVAL 0x0 + +/* SPI1DIV[BCRST] - Configures the behavior of SPI communication after an abrupt deassertion of CS. This bit should be set in slave and master mode. */ +#define SPI1DIV_BCRST_BBA (*(volatile unsigned long *) 0x4208819C) +#define SPI1DIV_BCRST_MSK (0x1 << 7 ) +#define SPI1DIV_BCRST (0x1 << 7 ) +#define SPI1DIV_BCRST_DIS (0x0 << 7 ) /* DIS. Resumes communication from where it stopped when the CS is deasserted. The rest of the bits are then received/ transmitted when CS returns low. User code should ignore the CSERR interrupt. */ +#define SPI1DIV_BCRST_EN (0x1 << 7 ) /* EN. Enabled for a clean restart of SPI transfer after a CSERR condition. User code must also clear the SPI enable bit in SPI1CON during the CSERR interrupt. */ + +/* SPI1DIV[DIV] - Factor used to divide UCLK in the generation of the master mode serial clock. */ +#define SPI1DIV_DIV_MSK (0x3F << 0 ) + +/* Reset Value for SPI1CON*/ +#define SPI1CON_RVAL 0x0 + +/* SPI1CON[MOD] - IRQ mode bits. When TIM is set these bits configure when the Tx/Rx interrupts occur in a transfer. For a DMA Rx transfer, these bits should be 00. */ +#define SPI1CON_MOD_MSK (0x3 << 14 ) +#define SPI1CON_MOD_TX1RX1 (0x0 << 14 ) /* TX1RX1. Tx/Rx interrupt occurs when 1 byte has been transmitted/received from/into the FIFO. */ +#define SPI1CON_MOD_TX2RX2 (0x1 << 14 ) /* TX2RX2. Tx/Rx interrupt occurs when 2 bytes have been transmitted/received from/into the FIFO. */ +#define SPI1CON_MOD_TX3RX3 (0x2 << 14 ) /* TX3RX3. Tx/Rx interrupt occurs when 3 bytes have been transmitted/received from/into the FIFO. */ +#define SPI1CON_MOD_TX4RX4 (0x3 << 14 ) /* TX4RX4. Tx/Rx interrupt occurs when 4 bytes have been transmitted/received from/into the FIFO. */ + +/* SPI1CON[TFLUSH] - Tx FIFO flush enable bit. */ +#define SPI1CON_TFLUSH_BBA (*(volatile unsigned long *) 0x42088234) +#define SPI1CON_TFLUSH_MSK (0x1 << 13 ) +#define SPI1CON_TFLUSH (0x1 << 13 ) +#define SPI1CON_TFLUSH_DIS (0x0 << 13 ) /* DIS. Disable Tx FIFO flushing. */ +#define SPI1CON_TFLUSH_EN (0x1 << 13 ) /* EN. Flush the Tx FIFO. This bit does not clear itself and should be toggled if a single flush is required. If this bit is left high, then either the last transmitted value or 0x00 is transmitted depending on the ZEN bit (SPI1CON[7]). Any writes to the Tx FIFO are ignored while this bit is set. */ + +/* SPI1CON[RFLUSH] - Rx FIFO flush enable bit. */ +#define SPI1CON_RFLUSH_BBA (*(volatile unsigned long *) 0x42088230) +#define SPI1CON_RFLUSH_MSK (0x1 << 12 ) +#define SPI1CON_RFLUSH (0x1 << 12 ) +#define SPI1CON_RFLUSH_DIS (0x0 << 12 ) /* DIS. Disable Rx FIFO flushing. */ +#define SPI1CON_RFLUSH_EN (0x1 << 12 ) /* EN. If this bit is set, all incoming data is ignored and no interrupts are generated. If set and TIM = 0 (SPI1CON[6]), a read of the Rx FIFO initiates a transfer. */ + +/* SPI1CON[CON] - Continuous transfer enable bit. */ +#define SPI1CON_CON_BBA (*(volatile unsigned long *) 0x4208822C) +#define SPI1CON_CON_MSK (0x1 << 11 ) +#define SPI1CON_CON (0x1 << 11 ) +#define SPI1CON_CON_DIS (0x0 << 11 ) /* DIS. Disable continuous transfer. Each transfer consists of a single 8-bit serial transfer. If valid data exists in the SPIxTX register, then a new transfer is initiated after a stall period of one serial clock cycle. The CS line is deactivated for this one serial clock cycle. */ +#define SPI1CON_CON_EN (0x1 << 11 ) /* EN. Enable continuous transfer. In master mode, the transfer continues until no valid data is available in the Tx register. CS is asserted and remains asserted for the duration of each 8-bit serial transfer until Tx is empty. */ + +/* SPI1CON[LOOPBACK] - Loopback enable bit. */ +#define SPI1CON_LOOPBACK_BBA (*(volatile unsigned long *) 0x42088228) +#define SPI1CON_LOOPBACK_MSK (0x1 << 10 ) +#define SPI1CON_LOOPBACK (0x1 << 10 ) +#define SPI1CON_LOOPBACK_DIS (0x0 << 10 ) /* DIS. Normal mode. */ +#define SPI1CON_LOOPBACK_EN (0x1 << 10 ) /* EN. Connect MISO to MOSI, thus, data transmitted from Tx register is looped back to the Rx register. SPI must be configured in master mode. */ + +/* SPI1CON[SOEN] - Slave output enable bit. */ +#define SPI1CON_SOEN_BBA (*(volatile unsigned long *) 0x42088224) +#define SPI1CON_SOEN_MSK (0x1 << 9 ) +#define SPI1CON_SOEN (0x1 << 9 ) +#define SPI1CON_SOEN_DIS (0x0 << 9 ) /* DIS. Disable the output driver on the MISO pin. The MISO pin is open-circuit when this bit is clear. */ +#define SPI1CON_SOEN_EN (0x1 << 9 ) /* EN. MISO operates as normal. */ + +/* SPI1CON[RXOF] - RX overflow overwrite enable bit. */ +#define SPI1CON_RXOF_BBA (*(volatile unsigned long *) 0x42088220) +#define SPI1CON_RXOF_MSK (0x1 << 8 ) +#define SPI1CON_RXOF (0x1 << 8 ) +#define SPI1CON_RXOF_DIS (0x0 << 8 ) /* DIS. The new serial byte received is discarded when there is no space left in the FIFO */ +#define SPI1CON_RXOF_EN (0x1 << 8 ) /* EN. The valid data in the Rx register is overwritten by the new serial byte received when there is no space left in the FIFO. */ + +/* SPI1CON[ZEN] - TX underrun: Transmit 0s when Tx FIFO is empty. */ +#define SPI1CON_ZEN_BBA (*(volatile unsigned long *) 0x4208821C) +#define SPI1CON_ZEN_MSK (0x1 << 7 ) +#define SPI1CON_ZEN (0x1 << 7 ) +#define SPI1CON_ZEN_DIS (0x0 << 7 ) /* DIS. The last byte from the previous transmission is shifted out when a transfer is initiated with no valid data in the FIFO. */ +#define SPI1CON_ZEN_EN (0x1 << 7 ) /* EN. Transmit 0x00 when a transfer is initiated with no valid data in the FIFO. */ + +/* SPI1CON[TIM] - Transfer and interrupt mode bit. */ +#define SPI1CON_TIM_BBA (*(volatile unsigned long *) 0x42088218) +#define SPI1CON_TIM_MSK (0x1 << 6 ) +#define SPI1CON_TIM (0x1 << 6 ) +#define SPI1CON_TIM_TXWR (0x1 << 6 ) /* TXWR. Initiate transfer with a write to the SPIxTX register. Interrupt only occurs when Tx is empty. */ +#define SPI1CON_TIM_RXRD (0x0 << 6 ) /* RXRD. Initiate transfer with a read of the SPIxRX register. The read must be done while the SPI interface is idle. Interrupt only occurs when Rx is full. */ + +/* SPI1CON[LSB] - LSB first transfer enable bit. */ +#define SPI1CON_LSB_BBA (*(volatile unsigned long *) 0x42088214) +#define SPI1CON_LSB_MSK (0x1 << 5 ) +#define SPI1CON_LSB (0x1 << 5 ) +#define SPI1CON_LSB_DIS (0x0 << 5 ) /* DIS. MSB is transmitted first. */ +#define SPI1CON_LSB_EN (0x1 << 5 ) /* EN. LSB is transmitted first. */ + +/* SPI1CON[WOM] - Wired OR enable bit. */ +#define SPI1CON_WOM_BBA (*(volatile unsigned long *) 0x42088210) +#define SPI1CON_WOM_MSK (0x1 << 4 ) +#define SPI1CON_WOM (0x1 << 4 ) +#define SPI1CON_WOM_DIS (0x0 << 4 ) /* DIS. Normal driver output operation. */ +#define SPI1CON_WOM_EN (0x1 << 4 ) /* EN. Enable open circuit data output for multimaster/multislave configuration. */ + +/* SPI1CON[CPOL] - Serial clock polarity mode bit. */ +#define SPI1CON_CPOL_BBA (*(volatile unsigned long *) 0x4208820C) +#define SPI1CON_CPOL_MSK (0x1 << 3 ) +#define SPI1CON_CPOL (0x1 << 3 ) +#define SPI1CON_CPOL_LOW (0x0 << 3 ) /* LOW. Serial clock idles low. */ +#define SPI1CON_CPOL_HIGH (0x1 << 3 ) /* HIGH. Serial clock idles high. */ + +/* SPI1CON[CPHA] - Serial clock phase mode bit. */ +#define SPI1CON_CPHA_BBA (*(volatile unsigned long *) 0x42088208) +#define SPI1CON_CPHA_MSK (0x1 << 2 ) +#define SPI1CON_CPHA (0x1 << 2 ) +#define SPI1CON_CPHA_SAMPLELEADING (0x0 << 2 ) /* SAMPLELEADING. Serial clock pulses at the middle of the first data bit transfer. */ +#define SPI1CON_CPHA_SAMPLETRAILING (0x1 << 2 ) /* SAMPLETRAILING. Serial clock pulses at the start of the first data bit. */ + +/* SPI1CON[MASEN] - Master mode enable bit. */ +#define SPI1CON_MASEN_BBA (*(volatile unsigned long *) 0x42088204) +#define SPI1CON_MASEN_MSK (0x1 << 1 ) +#define SPI1CON_MASEN (0x1 << 1 ) +#define SPI1CON_MASEN_DIS (0x0 << 1 ) /* DIS. Configure in slave mode. */ +#define SPI1CON_MASEN_EN (0x1 << 1 ) /* EN. Configure in master mode. */ + +/* SPI1CON[ENABLE] - SPI enable bit. */ +#define SPI1CON_ENABLE_BBA (*(volatile unsigned long *) 0x42088200) +#define SPI1CON_ENABLE_MSK (0x1 << 0 ) +#define SPI1CON_ENABLE (0x1 << 0 ) +#define SPI1CON_ENABLE_DIS (0x0 << 0 ) /* DIS. Disable the SPI. Clearing this bit will also reset all the FIFO related logic to enable a clean start. */ +#define SPI1CON_ENABLE_EN (0x1 << 0 ) /* EN. Enable the SPI. */ + +/* Reset Value for SPI1DMA*/ +#define SPI1DMA_RVAL 0x0 + +/* SPI1DMA[IENRXDMA] - Receive DMA request enable bit. */ +#define SPI1DMA_IENRXDMA_BBA (*(volatile unsigned long *) 0x42088288) +#define SPI1DMA_IENRXDMA_MSK (0x1 << 2 ) +#define SPI1DMA_IENRXDMA (0x1 << 2 ) +#define SPI1DMA_IENRXDMA_DIS (0x0 << 2 ) /* DIS. Disable Rx DMA requests. */ +#define SPI1DMA_IENRXDMA_EN (0x1 << 2 ) /* EN. Enable Rx DMA requests. */ + +/* SPI1DMA[IENTXDMA] - Transmit DMA request enable bit. */ +#define SPI1DMA_IENTXDMA_BBA (*(volatile unsigned long *) 0x42088284) +#define SPI1DMA_IENTXDMA_MSK (0x1 << 1 ) +#define SPI1DMA_IENTXDMA (0x1 << 1 ) +#define SPI1DMA_IENTXDMA_DIS (0x0 << 1 ) /* DIS. Disable Tx DMA requests. */ +#define SPI1DMA_IENTXDMA_EN (0x1 << 1 ) /* EN. Enable Tx DMA requests. */ + +/* SPI1DMA[ENABLE] - DMA data transfer enable bit. */ +#define SPI1DMA_ENABLE_BBA (*(volatile unsigned long *) 0x42088280) +#define SPI1DMA_ENABLE_MSK (0x1 << 0 ) +#define SPI1DMA_ENABLE (0x1 << 0 ) +#define SPI1DMA_ENABLE_DIS (0x0 << 0 ) /* DIS. Disable DMA transfer. This bit needs to be cleared to prevent extra DMA request to the µDMA controller. */ +#define SPI1DMA_ENABLE_EN (0x1 << 0 ) /* EN. Enable a DMA transfer. Starts the transfer of a master configured to initiate transfer on transmit. */ + +/* Reset Value for SPI1CNT*/ +#define SPI1CNT_RVAL 0x0 + +/* SPI1CNT[VALUE] - Number of bytes requested by the SPI master during DMA transfer, when configured to initiate a transfer on a read of SPI0RX. This register is only used in DMA, master, Rx mode.. */ +#define SPI1CNT_VALUE_MSK (0xFF << 0 ) +// ------------------------------------------------------------------------------------------------ +// ----- T0 ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief Timer 0 (pADI_TM0) + */ + +#if (__NO_MMR_STRUCTS__==0) +typedef struct { /*!< pADI_TM0 Structure */ + __IO uint16_t LD; /*!< 16-bit Load Value */ + __I uint16_t RESERVED0; + __IO uint16_t VAL; /*!< 16-bit Timer Value */ + __I uint16_t RESERVED1; + __IO uint16_t CON; /*!< Control Register */ + __I uint16_t RESERVED2; + __IO uint16_t CLRI; /*!< Clear Interrupt Register */ + __I uint16_t RESERVED3; + __IO uint16_t CAP; /*!< Capture Register */ + __I uint16_t RESERVED4[5]; + __IO uint16_t STA; /*!< Status Register */ +} ADI_TIMER_TypeDef; +#else // (__NO_MMR_STRUCTS__==0) +#define T0LD (*(volatile unsigned short int *) 0x40000000) +#define T0VAL (*(volatile unsigned short int *) 0x40000004) +#define T0CON (*(volatile unsigned short int *) 0x40000008) +#define T0CLRI (*(volatile unsigned short int *) 0x4000000C) +#define T0CAP (*(volatile unsigned short int *) 0x40000010) +#define T0STA (*(volatile unsigned short int *) 0x4000001C) +#endif // (__NO_MMR_STRUCTS__==0) + +/* Reset Value for T0LD*/ +#define T0LD_RVAL 0x0 + +/* T0LD[VALUE] - Load value. */ +#define T0LD_VALUE_MSK (0xFFFF << 0 ) + +/* Reset Value for T0VAL*/ +#define T0VAL_RVAL 0x0 + +/* T0VAL[VALUE] - Current counter value. */ +#define T0VAL_VALUE_MSK (0xFFFF << 0 ) + +/* Reset Value for T0CON*/ +#define T0CON_RVAL 0xA + +/* T0CON[EVENTEN] - Enable event bit. */ +#define T0CON_EVENTEN_BBA (*(volatile unsigned long *) 0x42000130) +#define T0CON_EVENTEN_MSK (0x1 << 12 ) +#define T0CON_EVENTEN (0x1 << 12 ) +#define T0CON_EVENTEN_DIS (0x0 << 12 ) /* DIS. Cleared by user. */ +#define T0CON_EVENTEN_EN (0x1 << 12 ) /* EN. Enable time capture of an event. */ + +/* T0CON[EVENT] - Event select bits. Settings not described are reserved and should not be used. */ +#define T0CON_EVENT_MSK (0xF << 8 ) +#define T0CON_EVENT_T2 (0x0 << 8 ) /* T2. Wakeup Timer. */ +#define T0CON_EVENT_EXT0 (0x1 << 8 ) /* EXT0. External interrupt 0. */ +#define T0CON_EVENT_EXT1 (0x2 << 8 ) /* EXT1. External interrupt 1. */ +#define T0CON_EVENT_EXT2 (0x3 << 8 ) /* EXT2. External interrupt 2. */ +#define T0CON_EVENT_EXT3 (0x4 << 8 ) /* EXT3. External interrupt 3. */ +#define T0CON_EVENT_EXT4 (0x5 << 8 ) /* EXT4. External interrupt 4. */ +#define T0CON_EVENT_EXT5 (0x6 << 8 ) /* EXT5. External interrupt 5. */ +#define T0CON_EVENT_EXT6 (0x7 << 8 ) /* EXT6. External interrupt 6. */ +#define T0CON_EVENT_EXT7 (0x8 << 8 ) /* EXT7. External interrupt 7. */ +#define T0CON_EVENT_EXT8 (0x9 << 8 ) /* EXT8. External interrupt 8. */ +#define T0CON_EVENT_T3 (0xA << 8 ) /* T3. Watchdog timer. */ +#define T0CON_EVENT_T1 (0xC << 8 ) /* T1. Timer 1. */ +#define T0CON_EVENT_ADC (0xD << 8 ) /* ADC. Analog to Digital Converter. */ +#define T0CON_EVENT_FEE (0xE << 8 ) /* FEE. Flash Controller. */ +#define T0CON_EVENT_COM (0xF << 8 ) /* COM. UART Peripheral. */ + +/* T0CON[RLD] - Reload control bit for periodic mode. */ +#define T0CON_RLD_BBA (*(volatile unsigned long *) 0x4200011C) +#define T0CON_RLD_MSK (0x1 << 7 ) +#define T0CON_RLD (0x1 << 7 ) +#define T0CON_RLD_DIS (0x0 << 7 ) /* DIS. Reload on a time out. */ +#define T0CON_RLD_EN (0x1 << 7 ) /* EN. Reload the counter on a write to T0CLRI. */ + +/* T0CON[CLK] - Clock select. */ +#define T0CON_CLK_MSK (0x3 << 5 ) +#define T0CON_CLK_UCLK (0x0 << 5 ) /* UCLK. Undivided system clock. */ +#define T0CON_CLK_PCLK (0x1 << 5 ) /* PCLK. Peripheral clock. */ +#define T0CON_CLK_LFOSC (0x2 << 5 ) /* LFOSC. 32 kHz internal oscillator. */ +#define T0CON_CLK_LFXTAL (0x3 << 5 ) /* LFXTAL. 32 kHz external crystal. */ + +/* T0CON[ENABLE] - Timer enable bit. */ +#define T0CON_ENABLE_BBA (*(volatile unsigned long *) 0x42000110) +#define T0CON_ENABLE_MSK (0x1 << 4 ) +#define T0CON_ENABLE (0x1 << 4 ) +#define T0CON_ENABLE_DIS (0x0 << 4 ) /* DIS. Disable the timer. Clearing this bit resets the timer, including the T0VAL register. */ +#define T0CON_ENABLE_EN (0x1 << 4 ) /* EN. Enable the timer. The timer starts counting from its initial value, 0 if count-up mode or 0xFFFF if count-down mode. */ + +/* T0CON[MOD] - Timer mode. */ +#define T0CON_MOD_BBA (*(volatile unsigned long *) 0x4200010C) +#define T0CON_MOD_MSK (0x1 << 3 ) +#define T0CON_MOD (0x1 << 3 ) +#define T0CON_MOD_FREERUN (0x0 << 3 ) /* FREERUN. Operate in free running mode. */ +#define T0CON_MOD_PERIODIC (0x1 << 3 ) /* PERIODIC. Operate in periodic mode. */ + +/* T0CON[UP] - Count down/up. */ +#define T0CON_UP_BBA (*(volatile unsigned long *) 0x42000108) +#define T0CON_UP_MSK (0x1 << 2 ) +#define T0CON_UP (0x1 << 2 ) +#define T0CON_UP_DIS (0x0 << 2 ) /* DIS. Timer to count down. */ +#define T0CON_UP_EN (0x1 << 2 ) /* EN. Timer to count up. */ + +/* T0CON[PRE] - Prescaler. */ +#define T0CON_PRE_MSK (0x3 << 0 ) +#define T0CON_PRE_DIV1 (0x0 << 0 ) /* DIV1. Source clock/1.If the selected clock source is UCLK or PCLK this setting results in a prescaler of 4. */ +#define T0CON_PRE_DIV16 (0x1 << 0 ) /* DIV16. Source clock/16. */ +#define T0CON_PRE_DIV256 (0x2 << 0 ) /* DIV256. Source clock/256. */ +#define T0CON_PRE_DIV32768 (0x3 << 0 ) /* DIV32768. Source clock/32768. */ + +/* Reset Value for T0CLRI*/ +#define T0CLRI_RVAL 0x0 + +/* T0CLRI[CAP] - Clear captured event interrupt. */ +#define T0CLRI_CAP_BBA (*(volatile unsigned long *) 0x42000184) +#define T0CLRI_CAP_MSK (0x1 << 1 ) +#define T0CLRI_CAP (0x1 << 1 ) +#define T0CLRI_CAP_CLR (0x1 << 1 ) /* CLR. Clear a captured event interrupt. This bit always reads 0. */ + +/* T0CLRI[TMOUT] - Clear timeout interrupt. */ +#define T0CLRI_TMOUT_BBA (*(volatile unsigned long *) 0x42000180) +#define T0CLRI_TMOUT_MSK (0x1 << 0 ) +#define T0CLRI_TMOUT (0x1 << 0 ) +#define T0CLRI_TMOUT_CLR (0x1 << 0 ) /* CLR. Clear a timeout interrupt. This bit always reads 0. */ + +/* Reset Value for T0CAP*/ +#define T0CAP_RVAL 0x0 + +/* T0CAP[VALUE] - Capture value. */ +#define T0CAP_VALUE_MSK (0xFFFF << 0 ) + +/* Reset Value for T0STA*/ +#define T0STA_RVAL 0x0 + +/* T0STA[CLRI] - T0CLRI write sync in progress.. */ +#define T0STA_CLRI_BBA (*(volatile unsigned long *) 0x4200039C) +#define T0STA_CLRI_MSK (0x1 << 7 ) +#define T0STA_CLRI (0x1 << 7 ) +#define T0STA_CLRI_CLR (0x0 << 7 ) /* CLR. Cleared when the interrupt is cleared in the timer clock domain. */ +#define T0STA_CLRI_SET (0x1 << 7 ) /* SET. Set automatically when the T0CLRI value is being updated in the timer clock domain, indicating that the timer’s configuration is not yet valid. */ + +/* T0STA[CON] - T0CON write sync in progress. */ +#define T0STA_CON_BBA (*(volatile unsigned long *) 0x42000398) +#define T0STA_CON_MSK (0x1 << 6 ) +#define T0STA_CON (0x1 << 6 ) +#define T0STA_CON_CLR (0x0 << 6 ) /* CLR. Timer ready to receive commands to T0CON. The previous change of T0CON has been synchronized in the timer clock domain. */ +#define T0STA_CON_SET (0x1 << 6 ) /* SET. Timer not ready to receive commands to T0CON. Previous change of the T0CON value has not been synchronized in the timer clock domain. */ + +/* T0STA[CAP] - Capture event pending. */ +#define T0STA_CAP_BBA (*(volatile unsigned long *) 0x42000384) +#define T0STA_CAP_MSK (0x1 << 1 ) +#define T0STA_CAP (0x1 << 1 ) +#define T0STA_CAP_CLR (0x0 << 1 ) /* CLR. No capture event is pending. */ +#define T0STA_CAP_SET (0x1 << 1 ) /* SET. Capture event is pending. */ + +/* T0STA[TMOUT] - Time out event occurred. */ +#define T0STA_TMOUT_BBA (*(volatile unsigned long *) 0x42000380) +#define T0STA_TMOUT_MSK (0x1 << 0 ) +#define T0STA_TMOUT (0x1 << 0 ) +#define T0STA_TMOUT_CLR (0x0 << 0 ) /* CLR. No timeout event has occurred. */ +#define T0STA_TMOUT_SET (0x1 << 0 ) /* SET. Timeout event has occurred. For count-up mode, this is when the counter reaches full scale. For count-down mode, this is when the counter reaches 0. */ +#if (__NO_MMR_STRUCTS__==1) + +#define T1LD (*(volatile unsigned short int *) 0x40000400) +#define T1VAL (*(volatile unsigned short int *) 0x40000404) +#define T1CON (*(volatile unsigned short int *) 0x40000408) +#define T1CLRI (*(volatile unsigned short int *) 0x4000040C) +#define T1CAP (*(volatile unsigned short int *) 0x40000410) +#define T1STA (*(volatile unsigned short int *) 0x4000041C) +#endif // (__NO_MMR_STRUCTS__==1) + +/* Reset Value for T1LD*/ +#define T1LD_RVAL 0x0 + +/* T1LD[VALUE] - Load value. */ +#define T1LD_VALUE_MSK (0xFFFF << 0 ) + +/* Reset Value for T1VAL*/ +#define T1VAL_RVAL 0x0 + +/* T1VAL[VALUE] - Current counter value. */ +#define T1VAL_VALUE_MSK (0xFFFF << 0 ) + +/* Reset Value for T1CON*/ +#define T1CON_RVAL 0xA + +/* T1CON[EVENTEN] - Enable event bit. */ +#define T1CON_EVENTEN_BBA (*(volatile unsigned long *) 0x42008130) +#define T1CON_EVENTEN_MSK (0x1 << 12 ) +#define T1CON_EVENTEN (0x1 << 12 ) +#define T1CON_EVENTEN_DIS (0x0 << 12 ) /* DIS. Cleared by user. */ +#define T1CON_EVENTEN_EN (0x1 << 12 ) /* EN. Enable time capture of an event. */ + +/* T1CON[EVENT] - Event select bits. Settings not described are reserved and should not be used. */ +#define T1CON_EVENT_MSK (0xF << 8 ) +#define T1CON_EVENT_T0 (0x0 << 8 ) /* T0. Timer 0. */ +#define T1CON_EVENT_SPI0 (0x1 << 8 ) /* SPI0. SPI0 Peripheral. */ +#define T1CON_EVENT_SPI1 (0x2 << 8 ) /* SPI1. SPI1 Peripheral. */ +#define T1CON_EVENT_I2CS (0x3 << 8 ) /* I2CS. I2C slave peripheral. */ +#define T1CON_EVENT_I2CM (0x4 << 8 ) /* I2CM. I2C master peripheral. */ +#define T1CON_EVENT_DMAERR (0x6 << 8 ) /* DMAERR. DMA error */ +#define T1CON_EVENT_DMADONE (0x7 << 8 ) /* DMADONE. Completion of transfer on any of the DMA channel. */ +#define T1CON_EVENT_EXT1 (0x8 << 8 ) /* EXT1. External interrupt 1. */ +#define T1CON_EVENT_EXT2 (0x9 << 8 ) /* EXT2. External interrupt 2. */ +#define T1CON_EVENT_EXT3 (0xA << 8 ) /* EXT3. External interrupt 3. */ +#define T1CON_EVENT_PWMTRIP (0xB << 8 ) /* PWMTRIP. */ +#define T1CON_EVENT_PWM0 (0xC << 8 ) /* PWM0. PWM pair 0. */ +#define T1CON_EVENT_PWM1 (0xD << 8 ) /* PWM1. PWM pair 1. */ +#define T1CON_EVENT_PWM2 (0xE << 8 ) /* PWM2. PWM pair 2. */ +#define T1CON_EVENT_PWM3 (0xF << 8 ) /* PWM3. PWM pair 3. */ + +/* T1CON[RLD] - Reload control bit for periodic mode. */ +#define T1CON_RLD_BBA (*(volatile unsigned long *) 0x4200811C) +#define T1CON_RLD_MSK (0x1 << 7 ) +#define T1CON_RLD (0x1 << 7 ) +#define T1CON_RLD_DIS (0x0 << 7 ) /* DIS. Reload on a time out. */ +#define T1CON_RLD_EN (0x1 << 7 ) /* EN. Reload the counter on a write to T1CLRI. */ + +/* T1CON[CLK] - Clock select. */ +#define T1CON_CLK_MSK (0x3 << 5 ) +#define T1CON_CLK_UCLK (0x0 << 5 ) /* UCLK. Undivided system clock. */ +#define T1CON_CLK_PCLK (0x1 << 5 ) /* PCLK. Peripheral clock. */ +#define T1CON_CLK_LFOSC (0x2 << 5 ) /* LFOSC. 32 kHz internal oscillator. */ +#define T1CON_CLK_LFXTAL (0x3 << 5 ) /* LFXTAL. 32 kHz external crystal. */ + +/* T1CON[ENABLE] - Timer enable bit. */ +#define T1CON_ENABLE_BBA (*(volatile unsigned long *) 0x42008110) +#define T1CON_ENABLE_MSK (0x1 << 4 ) +#define T1CON_ENABLE (0x1 << 4 ) +#define T1CON_ENABLE_DIS (0x0 << 4 ) /* DIS. Disable the timer. Clearing this bit resets the timer, including the T1VAL register. */ +#define T1CON_ENABLE_EN (0x1 << 4 ) /* EN. Enable the timer. The timer starts counting from its initial value, 0 if count-up mode or 0xFFFF if count-down mode. */ + +/* T1CON[MOD] - Timer mode. */ +#define T1CON_MOD_BBA (*(volatile unsigned long *) 0x4200810C) +#define T1CON_MOD_MSK (0x1 << 3 ) +#define T1CON_MOD (0x1 << 3 ) +#define T1CON_MOD_FREERUN (0x0 << 3 ) /* FREERUN. Operate in free running mode. */ +#define T1CON_MOD_PERIODIC (0x1 << 3 ) /* PERIODIC. Operate in periodic mode. */ + +/* T1CON[UP] - Count down/up. */ +#define T1CON_UP_BBA (*(volatile unsigned long *) 0x42008108) +#define T1CON_UP_MSK (0x1 << 2 ) +#define T1CON_UP (0x1 << 2 ) +#define T1CON_UP_DIS (0x0 << 2 ) /* DIS. Timer to count down. */ +#define T1CON_UP_EN (0x1 << 2 ) /* EN. Timer to count up. */ + +/* T1CON[PRE] - Prescaler. */ +#define T1CON_PRE_MSK (0x3 << 0 ) +#define T1CON_PRE_DIV1 (0x0 << 0 ) /* DIV1. Source clock/1.If the selected clock source is UCLK or PCLK this setting results in a prescaler of 4. */ +#define T1CON_PRE_DIV16 (0x1 << 0 ) /* DIV16. Source clock/16. */ +#define T1CON_PRE_DIV256 (0x2 << 0 ) /* DIV256. Source clock/256. */ +#define T1CON_PRE_DIV32768 (0x3 << 0 ) /* DIV32768. Source clock/32768. */ + +/* Reset Value for T1CLRI*/ +#define T1CLRI_RVAL 0x0 + +/* T1CLRI[CAP] - Clear captured event interrupt. */ +#define T1CLRI_CAP_BBA (*(volatile unsigned long *) 0x42008184) +#define T1CLRI_CAP_MSK (0x1 << 1 ) +#define T1CLRI_CAP (0x1 << 1 ) +#define T1CLRI_CAP_CLR (0x1 << 1 ) /* CLR. Clear a captured event interrupt. This bit always reads 0. */ + +/* T1CLRI[TMOUT] - Clear timeout interrupt. */ +#define T1CLRI_TMOUT_BBA (*(volatile unsigned long *) 0x42008180) +#define T1CLRI_TMOUT_MSK (0x1 << 0 ) +#define T1CLRI_TMOUT (0x1 << 0 ) +#define T1CLRI_TMOUT_CLR (0x1 << 0 ) /* CLR. Clear a timeout interrupt. This bit always reads 0. */ + +/* Reset Value for T1CAP*/ +#define T1CAP_RVAL 0x0 + +/* T1CAP[VALUE] - Capture value. */ +#define T1CAP_VALUE_MSK (0xFFFF << 0 ) + +/* Reset Value for T1STA*/ +#define T1STA_RVAL 0x0 + +/* T1STA[CLRI] - T1CLRI write sync in progress. */ +#define T1STA_CLRI_BBA (*(volatile unsigned long *) 0x4200839C) +#define T1STA_CLRI_MSK (0x1 << 7 ) +#define T1STA_CLRI (0x1 << 7 ) +#define T1STA_CLRI_CLR (0x0 << 7 ) /* CLR. Cleared when the interrupt is cleared in the timer clock domain. */ +#define T1STA_CLRI_SET (0x1 << 7 ) /* SET. Set automatically when the T1CLRI value is being updated in the timer clock domain, indicating that the timer’s configuration is not yet valid. */ + +/* T1STA[CON] - T1CON write sync in progress. */ +#define T1STA_CON_BBA (*(volatile unsigned long *) 0x42008398) +#define T1STA_CON_MSK (0x1 << 6 ) +#define T1STA_CON (0x1 << 6 ) +#define T1STA_CON_CLR (0x0 << 6 ) /* CLR. Timer ready to receive commands to T1CON. The previous change of T1CON has been synchronized in the timer clock domain. */ +#define T1STA_CON_SET (0x1 << 6 ) /* SET. Timer not ready to receive commands to T1CON. Previous change of the T1CON value has not been synchronized in the timer clock domain. */ + +/* T1STA[CAP] - Capture event pending. */ +#define T1STA_CAP_BBA (*(volatile unsigned long *) 0x42008384) +#define T1STA_CAP_MSK (0x1 << 1 ) +#define T1STA_CAP (0x1 << 1 ) +#define T1STA_CAP_CLR (0x0 << 1 ) /* CLR. No capture event is pending. */ +#define T1STA_CAP_SET (0x1 << 1 ) /* SET. Capture event is pending. */ + +/* T1STA[TMOUT] - Time out event occurred. */ +#define T1STA_TMOUT_BBA (*(volatile unsigned long *) 0x42008380) +#define T1STA_TMOUT_MSK (0x1 << 0 ) +#define T1STA_TMOUT (0x1 << 0 ) +#define T1STA_TMOUT_CLR (0x0 << 0 ) /* CLR. No timeout event has occurred. */ +#define T1STA_TMOUT_SET (0x1 << 0 ) /* SET. Timeout event has occurred. For count-up mode, this is when the counter reaches full scale. For count-down mode, this is when the counter reaches 0. */ +// ------------------------------------------------------------------------------------------------ +// ----- UART ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief UART (pADI_UART) + */ + +#if (__NO_MMR_STRUCTS__==0) +typedef struct { /*!< pADI_UART Structure */ + + union { + __IO uint8_t COMTX; /*!< Transmit Holding Register */ + __IO uint8_t COMRX; /*!< Receive Buffer Register */ + } ; + __I uint8_t RESERVED0[3]; + __IO uint8_t COMIEN; /*!< Interrupt Enable Register */ + __I uint8_t RESERVED1[3]; + __IO uint8_t COMIIR; /*!< Interrupt Identification Register */ + __I uint8_t RESERVED2[3]; + __IO uint8_t COMLCR; /*!< Line Control Register */ + __I uint8_t RESERVED3[3]; + __IO uint8_t COMMCR; /*!< Module Control Register */ + __I uint8_t RESERVED4[3]; + __IO uint8_t COMLSR; /*!< Line Status Register */ + __I uint8_t RESERVED5[3]; + __IO uint8_t COMMSR; /*!< Modem Status Register */ + __I uint8_t RESERVED6[11]; + __IO uint16_t COMFBR; /*!< Fractional Baud Rate Register. */ + __I uint16_t RESERVED7; + __IO uint16_t COMDIV; /*!< Baud Rate Divider Register */ +} ADI_UART_TypeDef; +#else // (__NO_MMR_STRUCTS__==0) +#define COMTX (*(volatile unsigned char *) 0x40005000) +#define COMRX (*(volatile unsigned char *) 0x40005000) +#define COMIEN (*(volatile unsigned char *) 0x40005004) +#define COMIIR (*(volatile unsigned char *) 0x40005008) +#define COMLCR (*(volatile unsigned char *) 0x4000500C) +#define COMMCR (*(volatile unsigned char *) 0x40005010) +#define COMLSR (*(volatile unsigned char *) 0x40005014) +#define COMMSR (*(volatile unsigned char *) 0x40005018) +#define COMFBR (*(volatile unsigned short int *) 0x40005024) +#define COMDIV (*(volatile unsigned short int *) 0x40005028) +#endif // (__NO_MMR_STRUCTS__==0) + +/* Reset Value for COMTX*/ +#define COMTX_RVAL 0x0 + +/* COMTX[VALUE] - Transmit Holding Register */ +#define COMTX_VALUE_MSK (0xFF << 0 ) + +/* Reset Value for COMRX*/ +#define COMRX_RVAL 0x0 + +/* COMRX[VALUE] - Receive Buffer Register */ +#define COMRX_VALUE_MSK (0xFF << 0 ) + +/* Reset Value for COMIEN*/ +#define COMIEN_RVAL 0x0 + +/* COMIEN[EDMAR] - DMA requests in transmit mode */ +#define COMIEN_EDMAR_BBA (*(volatile unsigned long *) 0x420A0094) +#define COMIEN_EDMAR_MSK (0x1 << 5 ) +#define COMIEN_EDMAR (0x1 << 5 ) +#define COMIEN_EDMAR_DIS (0x0 << 5 ) /* DIS. Disable. */ +#define COMIEN_EDMAR_EN (0x1 << 5 ) /* EN. Enable. */ + +/* COMIEN[EDMAT] - DMA requests in receive mode */ +#define COMIEN_EDMAT_BBA (*(volatile unsigned long *) 0x420A0090) +#define COMIEN_EDMAT_MSK (0x1 << 4 ) +#define COMIEN_EDMAT (0x1 << 4 ) +#define COMIEN_EDMAT_DIS (0x0 << 4 ) /* DIS. Disable. */ +#define COMIEN_EDMAT_EN (0x1 << 4 ) /* EN. Enable. */ + +/* COMIEN[EDSSI] - Modem status interrupt */ +#define COMIEN_EDSSI_BBA (*(volatile unsigned long *) 0x420A008C) +#define COMIEN_EDSSI_MSK (0x1 << 3 ) +#define COMIEN_EDSSI (0x1 << 3 ) +#define COMIEN_EDSSI_DIS (0x0 << 3 ) /* DIS. Disable. */ +#define COMIEN_EDSSI_EN (0x1 << 3 ) /* EN. Enable. */ + +/* COMIEN[ELSI] - Rx status interrupt */ +#define COMIEN_ELSI_BBA (*(volatile unsigned long *) 0x420A0088) +#define COMIEN_ELSI_MSK (0x1 << 2 ) +#define COMIEN_ELSI (0x1 << 2 ) +#define COMIEN_ELSI_DIS (0x0 << 2 ) /* DIS. Disable. */ +#define COMIEN_ELSI_EN (0x1 << 2 ) /* EN. Enable. */ + +/* COMIEN[ETBEI] - Transmit buffer empty interrupt */ +#define COMIEN_ETBEI_BBA (*(volatile unsigned long *) 0x420A0084) +#define COMIEN_ETBEI_MSK (0x1 << 1 ) +#define COMIEN_ETBEI (0x1 << 1 ) +#define COMIEN_ETBEI_DIS (0x0 << 1 ) /* DIS. Disable. */ +#define COMIEN_ETBEI_EN (0x1 << 1 ) /* EN. Enable the transmit interrupt. An interrupt is generated when the COMTX register is empty. Note that if the COMTX is already empty when enabling this bit, an interrupt is generated immediately. */ + +/* COMIEN[ERBFI] - Receive buffer full interrupt */ +#define COMIEN_ERBFI_BBA (*(volatile unsigned long *) 0x420A0080) +#define COMIEN_ERBFI_MSK (0x1 << 0 ) +#define COMIEN_ERBFI (0x1 << 0 ) +#define COMIEN_ERBFI_DIS (0x0 << 0 ) /* DIS. Disable. */ +#define COMIEN_ERBFI_EN (0x1 << 0 ) /* EN. Enable the receive interrupt. An interrupt is generated when the COMRX register is loaded with the received data. Note that if the COMRX is already full when enabling this bit, an interrupt is generated immediately. */ + +/* Reset Value for COMIIR*/ +#define COMIIR_RVAL 0x1 + +/* COMIIR[STA] - Status bits. */ +#define COMIIR_STA_MSK (0x3 << 1 ) +#define COMIIR_STA_MODEMSTATUS (0x0 << 1 ) /* MODEMSTATUS. Modem status interrupt. */ +#define COMIIR_STA_TXBUFEMPTY (0x1 << 1 ) /* TXBUFEMPTY. Transmit buffer empty interrupt. */ +#define COMIIR_STA_RXBUFFULL (0x2 << 1 ) /* RXBUFFULL. Receive buffer full interrupt. Read COMRX register to clear. */ +#define COMIIR_STA_RXLINESTATUS (0x3 << 1 ) /* RXLINESTATUS. Receive line status interrupt. Read COMLSR register to clear. */ + +/* COMIIR[NINT] - Interrupt flag. */ +#define COMIIR_NINT_BBA (*(volatile unsigned long *) 0x420A0100) +#define COMIIR_NINT_MSK (0x1 << 0 ) +#define COMIIR_NINT (0x1 << 0 ) +#define COMIIR_NINT_CLR (0x0 << 0 ) /* CLR. Indicates any of the following: receive buffer full, transmit buffer empty, line status, or modem status interrupt occurred. */ +#define COMIIR_NINT_SET (0x1 << 0 ) /* SET. There is no interrupt (default). */ + +/* Reset Value for COMLCR*/ +#define COMLCR_RVAL 0x0 + +/* COMLCR[BRK] - Set Break. */ +#define COMLCR_BRK_BBA (*(volatile unsigned long *) 0x420A0198) +#define COMLCR_BRK_MSK (0x1 << 6 ) +#define COMLCR_BRK (0x1 << 6 ) +#define COMLCR_BRK_DIS (0x0 << 6 ) /* DIS to operate in normal mode. */ +#define COMLCR_BRK_EN (0x1 << 6 ) /* EN to force TxD to 0. */ + +/* COMLCR[SP] - Stick Parity. */ +#define COMLCR_SP_BBA (*(volatile unsigned long *) 0x420A0194) +#define COMLCR_SP_MSK (0x1 << 5 ) +#define COMLCR_SP (0x1 << 5 ) +#define COMLCR_SP_DIS (0x0 << 5 ) /* DIS. Parity is not forced based on EPS and PEN values. */ +#define COMLCR_SP_EN (0x1 << 5 ) /* EN. Force parity to defined values based on EPS and PEN values. EPS = 1 and PEN = 1, parity forced to 1 EPS = 0 and PEN = 1, parity forced to 0 EPS = X and PEN = 0, no parity transmitted. */ + +/* COMLCR[EPS] - Even Parity Select Bit. */ +#define COMLCR_EPS_BBA (*(volatile unsigned long *) 0x420A0190) +#define COMLCR_EPS_MSK (0x1 << 4 ) +#define COMLCR_EPS (0x1 << 4 ) +#define COMLCR_EPS_DIS (0x0 << 4 ) /* DIS. Odd parity. */ +#define COMLCR_EPS_EN (0x1 << 4 ) /* EN. Even parity. */ + +/* COMLCR[PEN] - Parity Enable Bit. */ +#define COMLCR_PEN_BBA (*(volatile unsigned long *) 0x420A018C) +#define COMLCR_PEN_MSK (0x1 << 3 ) +#define COMLCR_PEN (0x1 << 3 ) +#define COMLCR_PEN_DIS (0x0 << 3 ) /* DIS. No parity transmission or checking. */ +#define COMLCR_PEN_EN (0x1 << 3 ) /* EN. Transmit and check the parity bit. */ + +/* COMLCR[STOP] - Stop Bit. */ +#define COMLCR_STOP_BBA (*(volatile unsigned long *) 0x420A0188) +#define COMLCR_STOP_MSK (0x1 << 2 ) +#define COMLCR_STOP (0x1 << 2 ) +#define COMLCR_STOP_DIS (0x0 << 2 ) /* DIS. Generate one stop bit in the transmitted data. */ +#define COMLCR_STOP_EN (0x1 << 2 ) /* EN. Transmit 1.5 stop bits if the word length is 5 bits, or 2 stop bits if the word length is 6, 7, or 8 bits. The receiver checks the first stop bit only, regardless of the number of stop bits selected. */ + +/* COMLCR[WLS] - Word Length Select Bits. */ +#define COMLCR_WLS_MSK (0x3 << 0 ) +#define COMLCR_WLS_5BITS (0x0 << 0 ) /* 5BITS. 5 bits. */ +#define COMLCR_WLS_6BITS (0x1 << 0 ) /* 6BITS. 6 bits. */ +#define COMLCR_WLS_7BITS (0x2 << 0 ) /* 7BITS. 7 bits. */ +#define COMLCR_WLS_8BITS (0x3 << 0 ) /* 8BITS. 8 bits. */ + +/* Reset Value for COMMCR*/ +#define COMMCR_RVAL 0x0 + +/* COMMCR[LOOPBACK] - Loop Back. */ +#define COMMCR_LOOPBACK_BBA (*(volatile unsigned long *) 0x420A0210) +#define COMMCR_LOOPBACK_MSK (0x1 << 4 ) +#define COMMCR_LOOPBACK (0x1 << 4 ) +#define COMMCR_LOOPBACK_DIS (0x0 << 4 ) /* DIS. Normal mode. */ +#define COMMCR_LOOPBACK_EN (0x1 << 4 ) /* EN. Enable loopback mode. */ + +/* COMMCR[RTS] - Request To Send output control bit. */ +#define COMMCR_RTS_BBA (*(volatile unsigned long *) 0x420A0204) +#define COMMCR_RTS_MSK (0x1 << 1 ) +#define COMMCR_RTS (0x1 << 1 ) +#define COMMCR_RTS_DIS (0x0 << 1 ) /* DIS. Force the RTS output to 1. */ +#define COMMCR_RTS_EN (0x1 << 1 ) /* EN. Force the RTS output to 0. */ + +/* Reset Value for COMLSR*/ +#define COMLSR_RVAL 0x60 + +/* COMLSR[TEMT] - COMTX and Shift Register Empty Status Bit. */ +#define COMLSR_TEMT_BBA (*(volatile unsigned long *) 0x420A0298) +#define COMLSR_TEMT_MSK (0x1 << 6 ) +#define COMLSR_TEMT (0x1 << 6 ) +#define COMLSR_TEMT_CLR (0x0 << 6 ) /* CLR. Cleared when writing to COMTX. */ +#define COMLSR_TEMT_SET (0x1 << 6 ) /* SET. If COMTX and the shift register are empty, this bit indicates that the data has been transmitted, that is, it is no longer present in the shift register (default). */ + +/* COMLSR[THRE] - COMTX Empty Status Bit. */ +#define COMLSR_THRE_BBA (*(volatile unsigned long *) 0x420A0294) +#define COMLSR_THRE_MSK (0x1 << 5 ) +#define COMLSR_THRE (0x1 << 5 ) +#define COMLSR_THRE_CLR (0x0 << 5 ) /* CLR. Cleared when writing to COMTX. */ +#define COMLSR_THRE_SET (0x1 << 5 ) /* SET. If COMTX is empty, COMTX can be written as soon as this bit is set. The previous data may not have been transmitted yet and can still be present in the shift register (default). */ + +/* COMLSR[BI] - Break Indicator. */ +#define COMLSR_BI_BBA (*(volatile unsigned long *) 0x420A0290) +#define COMLSR_BI_MSK (0x1 << 4 ) +#define COMLSR_BI (0x1 << 4 ) +#define COMLSR_BI_CLR (0x0 << 4 ) /* CLR. Cleared automatically. */ +#define COMLSR_BI_SET (0x1 << 4 ) /* SET. Set when UART RXD is held low for more than the maximum word length. */ + +/* COMLSR[FE] - Framing Error. */ +#define COMLSR_FE_BBA (*(volatile unsigned long *) 0x420A028C) +#define COMLSR_FE_MSK (0x1 << 3 ) +#define COMLSR_FE (0x1 << 3 ) +#define COMLSR_FE_CLR (0x0 << 3 ) /* CLR. Cleared automatically. */ +#define COMLSR_FE_SET (0x1 << 3 ) /* SET. Set when the stop bit is invalid. */ + +/* COMLSR[PE] - Parity Error. */ +#define COMLSR_PE_BBA (*(volatile unsigned long *) 0x420A0288) +#define COMLSR_PE_MSK (0x1 << 2 ) +#define COMLSR_PE (0x1 << 2 ) +#define COMLSR_PE_CLR (0x0 << 2 ) /* CLR. Cleared automatically. */ +#define COMLSR_PE_SET (0x1 << 2 ) /* SET. Set when a parity error occurs. */ + +/* COMLSR[OE] - Overrun Error. */ +#define COMLSR_OE_BBA (*(volatile unsigned long *) 0x420A0284) +#define COMLSR_OE_MSK (0x1 << 1 ) +#define COMLSR_OE (0x1 << 1 ) +#define COMLSR_OE_CLR (0x0 << 1 ) /* CLR. Cleared automatically. */ +#define COMLSR_OE_SET (0x1 << 1 ) /* SET. Set automatically if data is overwritten before being read. */ + +/* COMLSR[DR] - Data Ready. */ +#define COMLSR_DR_BBA (*(volatile unsigned long *) 0x420A0280) +#define COMLSR_DR_MSK (0x1 << 0 ) +#define COMLSR_DR (0x1 << 0 ) +#define COMLSR_DR_CLR (0x0 << 0 ) /* CLR. Cleared by reading COMRX. */ +#define COMLSR_DR_SET (0x1 << 0 ) /* SET. Set automatically when COMRX is full. */ + +/* Reset Value for COMMSR*/ +#define COMMSR_RVAL 0x0 + +/* COMMSR[CTS] - Clear To Send signal status bit. */ +#define COMMSR_CTS_BBA (*(volatile unsigned long *) 0x420A0310) +#define COMMSR_CTS_MSK (0x1 << 4 ) +#define COMMSR_CTS (0x1 << 4 ) +#define COMMSR_CTS_CLR (0x0 << 4 ) /* CLR. Cleared to 0 when CTS input is logic high. */ +#define COMMSR_CTS_SET (0x1 << 4 ) /* SET. Set to 1 when CTS input is logic low. */ + +/* COMMSR[DCTS] - Delta CTS */ +#define COMMSR_DCTS_BBA (*(volatile unsigned long *) 0x420A0300) +#define COMMSR_DCTS_MSK (0x1 << 0 ) +#define COMMSR_DCTS (0x1 << 0 ) +#define COMMSR_DCTS_DIS (0x0 << 0 ) /* DIS. Cleared automatically by reading COMMSR. */ +#define COMMSR_DCTS_EN (0x1 << 0 ) /* EN. Set automatically if CTS changed state since COMMSR last read. */ + +/* Reset Value for COMFBR*/ +#define COMFBR_RVAL 0x0 + +/* COMFBR[ENABLE] - Fractional baud rate generator enable bit. Used for more accurate baud rate generation. */ +#define COMFBR_ENABLE_BBA (*(volatile unsigned long *) 0x420A04BC) +#define COMFBR_ENABLE_MSK (0x1 << 15 ) +#define COMFBR_ENABLE (0x1 << 15 ) +#define COMFBR_ENABLE_DIS (0x0 << 15 ) /* DIS. Disable. */ +#define COMFBR_ENABLE_EN (0x1 << 15 ) /* EN. Enable. */ + +/* COMFBR[DIVM] - Fractional baud rate M divide bits (1 to 3). These bits should not be set to 0. */ +#define COMFBR_DIVM_MSK (0x3 << 11 ) + +/* COMFBR[DIVN] - Fractional baud rate N divide bits (0 to 2047). */ +#define COMFBR_DIVN_MSK (0x7FF << 0 ) + +/* Reset Value for COMDIV*/ +#define COMDIV_RVAL 0x1 + +/* COMDIV[VALUE] - Sets the baud rate. The COMDIV register should not be 0. */ +#define COMDIV_VALUE_MSK (0xFFFF << 0 ) +// ------------------------------------------------------------------------------------------------ +// ----- WUT ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief WakeUp Timer (pADI_WUT) + */ + +#if (__NO_MMR_STRUCTS__==0) +typedef struct { /*!< pADI_WUT Structure */ + __IO uint16_t T2VAL0; /*!< Current Wake-Up Timer Value LSB */ + __I uint16_t RESERVED0; + __IO uint16_t T2VAL1; /*!< Current Wake-Up Timer Value MSB */ + __I uint16_t RESERVED1; + __IO uint16_t T2CON; /*!< Control Register */ + __I uint16_t RESERVED2; + __IO uint16_t T2INC; /*!< 12-bit Interval Register for Wake-Up Field A */ + __I uint16_t RESERVED3; + __IO uint16_t T2WUFB0; /*!< Wake-Up Field B LSB */ + __I uint16_t RESERVED4; + __IO uint16_t T2WUFB1; /*!< Wake-Up Field B MSB */ + __I uint16_t RESERVED5; + __IO uint16_t T2WUFC0; /*!< Wake-Up Field C LSB */ + __I uint16_t RESERVED6; + __IO uint16_t T2WUFC1; /*!< Wake-Up Field C MSB */ + __I uint16_t RESERVED7; + __IO uint16_t T2WUFD0; /*!< Wake-UpField D LSB */ + __I uint16_t RESERVED8; + __IO uint16_t T2WUFD1; /*!< Wake-Up Field D MSB */ + __I uint16_t RESERVED9; + __IO uint16_t T2IEN; /*!< Interrupt Enable */ + __I uint16_t RESERVED10; + __IO uint16_t T2STA; /*!< Status */ + __I uint16_t RESERVED11; + __IO uint16_t T2CLRI; /*!< Clear Interrupts */ + __I uint16_t RESERVED12[5]; + __IO uint16_t T2WUFA0; /*!< Wake-Up Field A LSB */ + __I uint16_t RESERVED13; + __IO uint16_t T2WUFA1; /*!< Wake-Up Field A MSB */ +} ADI_WUT_TypeDef; +#else // (__NO_MMR_STRUCTS__==0) +#define T2VAL0 (*(volatile unsigned short int *) 0x40002500) +#define T2VAL1 (*(volatile unsigned short int *) 0x40002504) +#define T2CON (*(volatile unsigned short int *) 0x40002508) +#define T2INC (*(volatile unsigned short int *) 0x4000250C) +#define T2WUFB0 (*(volatile unsigned short int *) 0x40002510) +#define T2WUFB1 (*(volatile unsigned short int *) 0x40002514) +#define T2WUFC0 (*(volatile unsigned short int *) 0x40002518) +#define T2WUFC1 (*(volatile unsigned short int *) 0x4000251C) +#define T2WUFD0 (*(volatile unsigned short int *) 0x40002520) +#define T2WUFD1 (*(volatile unsigned short int *) 0x40002524) +#define T2IEN (*(volatile unsigned short int *) 0x40002528) +#define T2STA (*(volatile unsigned short int *) 0x4000252C) +#define T2CLRI (*(volatile unsigned short int *) 0x40002530) +#define T2WUFA0 (*(volatile unsigned short int *) 0x4000253C) +#define T2WUFA1 (*(volatile unsigned short int *) 0x40002540) +#endif // (__NO_MMR_STRUCTS__==0) + +/* Reset Value for T2VAL0*/ +#define T2VAL0_RVAL 0x0 + +/* T2VAL0[VALUE] - Current Wake-Up timer value (bits 15 to 0). */ +#define T2VAL0_VALUE_MSK (0xFFFF << 0 ) + +/* Reset Value for T2VAL1*/ +#define T2VAL1_RVAL 0x0 + +/* T2VAL1[VALUE] - Current Wake-Up timer value (bits 31 to 16). */ +#define T2VAL1_VALUE_MSK (0xFFFF << 0 ) + +/* Reset Value for T2CON*/ +#define T2CON_RVAL 0x40 + +/* T2CON[STOPINC] - Allows the user to update the interval register safely. */ +#define T2CON_STOPINC_BBA (*(volatile unsigned long *) 0x4204A12C) +#define T2CON_STOPINC_MSK (0x1 << 11 ) +#define T2CON_STOPINC (0x1 << 11 ) +#define T2CON_STOPINC_DIS (0x0 << 11 ) /* DIS. Allows the wake-up field A to be updated by hardware. */ +#define T2CON_STOPINC_EN (0x1 << 11 ) /* EN. Prevents wake-up field A being automatically updated by hardware.This allows user software to update the T2INC register value. */ + +/* T2CON[CLK] - Clock select. */ +#define T2CON_CLK_MSK (0x3 << 9 ) +#define T2CON_CLK_PCLK (0x0 << 9 ) /* PCLK. Peripheral clock. */ +#define T2CON_CLK_LFXTAL (0x1 << 9 ) /* LFXTAL. 32 kHz external crystal. */ +#define T2CON_CLK_LFOSC (0x2 << 9 ) /* LFOSC. 32 kHz internal oscillator. */ +#define T2CON_CLK_EXTCLK (0x3 << 9 ) /* EXTCLK. External clock applied on P0.5. */ + +/* T2CON[WUEN] - Wake-up enable bits for time field values. */ +#define T2CON_WUEN_BBA (*(volatile unsigned long *) 0x4204A120) +#define T2CON_WUEN_MSK (0x1 << 8 ) +#define T2CON_WUEN (0x1 << 8 ) +#define T2CON_WUEN_DIS (0x0 << 8 ) /* DIS. Disable asynchronous Wake-Up timer. Interrupt conditions will not wake-up the part from sleep mode. */ +#define T2CON_WUEN_EN (0x1 << 8 ) /* EN. Enable asynchronous Wake-Up timer even when the core clock is off. Once the timer value equals any of the interrupt enabled compare field, a wake-up signal is generated. */ + +/* T2CON[ENABLE] - Timer enable bit. */ +#define T2CON_ENABLE_BBA (*(volatile unsigned long *) 0x4204A11C) +#define T2CON_ENABLE_MSK (0x1 << 7 ) +#define T2CON_ENABLE (0x1 << 7 ) +#define T2CON_ENABLE_DIS (0x0 << 7 ) /* DIS. Disable the timer. */ +#define T2CON_ENABLE_EN (0x1 << 7 ) /* EN. Enable the timer. When enabled wait for T2STA[8] to clear before continuing. */ + +/* T2CON[MOD] - Timer free run enable. */ +#define T2CON_MOD_BBA (*(volatile unsigned long *) 0x4204A118) +#define T2CON_MOD_MSK (0x1 << 6 ) +#define T2CON_MOD (0x1 << 6 ) +#define T2CON_MOD_PERIODIC (0x0 << 6 ) /* PERIODIC. Operate in periodic mode. Counts up to the value in T2WUFD */ +#define T2CON_MOD_FREERUN (0x1 << 6 ) /* FREERUN. Operate in free running mode (default). Counts from 0 to FFFF FFFF and starts again at 0. */ + +/* T2CON[FREEZE] - Freeze enable bit. */ +#define T2CON_FREEZE_BBA (*(volatile unsigned long *) 0x4204A10C) +#define T2CON_FREEZE_MSK (0x1 << 3 ) +#define T2CON_FREEZE (0x1 << 3 ) +#define T2CON_FREEZE_DIS (0x0 << 3 ) /* DIS. Disable this feature. */ +#define T2CON_FREEZE_EN (0x1 << 3 ) /* EN. Enable the freeze of the high 16 bits after the lower bits have been read from T2VAL0. This ensures that the software reads an atomic shot of the timer. The entire T2VAL register unfreezes after the high bits (T2VAL1) have been read. */ + +/* T2CON[PRE] - Prescaler. */ +#define T2CON_PRE_MSK (0x3 << 0 ) +#define T2CON_PRE_DIV1 (0x0 << 0 ) /* DIV1. Source clock/1. If the selected clock source is PCLK this setting results in a prescaler of 4. */ +#define T2CON_PRE_DIV16 (0x1 << 0 ) /* DIV16. Source clock/16. */ +#define T2CON_PRE_DIV256 (0x2 << 0 ) /* DIV256. Source clock/256. */ +#define T2CON_PRE_DIV32768 (0x3 << 0 ) /* DIV32768. Source clock/32768. */ + +/* Reset Value for T2INC*/ +#define T2INC_RVAL 0xC8 + +/* T2INC[VALUE] - Wake-up interval */ +#define T2INC_VALUE_MSK (0xFFF << 0 ) + +/* Reset Value for T2WUFB0*/ +#define T2WUFB0_RVAL 0x1FFF + +/* T2WUFB0[VALUE] - Lower 16 bits of Wake-Up Field B */ +#define T2WUFB0_VALUE_MSK (0xFFFF << 0 ) + +/* Reset Value for T2WUFB1*/ +#define T2WUFB1_RVAL 0x0 + +/* T2WUFB1[VALUE] - Upper 16 bits of Wake-Up Field B */ +#define T2WUFB1_VALUE_MSK (0xFFFF << 0 ) + +/* Reset Value for T2WUFC0*/ +#define T2WUFC0_RVAL 0x2FFF + +/* T2WUFC0[VALUE] - Lower 16 bits of Wake-Up Field C */ +#define T2WUFC0_VALUE_MSK (0xFFFF << 0 ) + +/* Reset Value for T2WUFC1*/ +#define T2WUFC1_RVAL 0x0 + +/* T2WUFC1[VALUE] - Upper 16 bits of Wake-Up Field C */ +#define T2WUFC1_VALUE_MSK (0xFFFF << 0 ) + +/* Reset Value for T2WUFD0*/ +#define T2WUFD0_RVAL 0x3FFF + +/* T2WUFD0[VALUE] - Lower 16 bits of Wake-Up Field D */ +#define T2WUFD0_VALUE_MSK (0xFFFF << 0 ) + +/* Reset Value for T2WUFD1*/ +#define T2WUFD1_RVAL 0x0 + +/* T2WUFD1[VALUE] - Upper 16 bits of Wake-Up Field D */ +#define T2WUFD1_VALUE_MSK (0xFFFF << 0 ) + +/* Reset Value for T2IEN*/ +#define T2IEN_RVAL 0x0 + +/* T2IEN[ROLL] - Interrupt enable bit when the counter rolls over. Only occurs in free running mode. */ +#define T2IEN_ROLL_BBA (*(volatile unsigned long *) 0x4204A510) +#define T2IEN_ROLL_MSK (0x1 << 4 ) +#define T2IEN_ROLL (0x1 << 4 ) +#define T2IEN_ROLL_DIS (0x0 << 4 ) /* DIS. Disable the roll over interrupt. */ +#define T2IEN_ROLL_EN (0x1 << 4 ) /* EN. Generate an interrupt when Timer2 rolls over. */ + +/* T2IEN[WUFD] - T2WUFD interrupt enable */ +#define T2IEN_WUFD_BBA (*(volatile unsigned long *) 0x4204A50C) +#define T2IEN_WUFD_MSK (0x1 << 3 ) +#define T2IEN_WUFD (0x1 << 3 ) +#define T2IEN_WUFD_DIS (0x0 << 3 ) /* DIS. Disable T2WUFD interrupt. */ +#define T2IEN_WUFD_EN (0x1 << 3 ) /* EN. Generate an interrupt when T2VAL reaches T2WUFD. */ + +/* T2IEN[WUFC] - T2WUFC interrupt enable */ +#define T2IEN_WUFC_BBA (*(volatile unsigned long *) 0x4204A508) +#define T2IEN_WUFC_MSK (0x1 << 2 ) +#define T2IEN_WUFC (0x1 << 2 ) +#define T2IEN_WUFC_DIS (0x0 << 2 ) /* DIS. Disable T2WUFC interrupt. */ +#define T2IEN_WUFC_EN (0x1 << 2 ) /* EN. Generate an interrupt when T2VAL reaches T2WUFC. */ + +/* T2IEN[WUFB] - T2WUFB interrupt enable */ +#define T2IEN_WUFB_BBA (*(volatile unsigned long *) 0x4204A504) +#define T2IEN_WUFB_MSK (0x1 << 1 ) +#define T2IEN_WUFB (0x1 << 1 ) +#define T2IEN_WUFB_DIS (0x0 << 1 ) /* DIS. Disable T2WUFB interrupt. */ +#define T2IEN_WUFB_EN (0x1 << 1 ) /* EN. Generate an interrupt when T2VAL reaches T2WUFB. */ + +/* T2IEN[WUFA] - T2WUFA interrupt enable */ +#define T2IEN_WUFA_BBA (*(volatile unsigned long *) 0x4204A500) +#define T2IEN_WUFA_MSK (0x1 << 0 ) +#define T2IEN_WUFA (0x1 << 0 ) +#define T2IEN_WUFA_DIS (0x0 << 0 ) /* DIS. Disable T2WUFA interrupt. */ +#define T2IEN_WUFA_EN (0x1 << 0 ) /* EN. Generate an interrupt when T2VAL reaches T2WUFA. */ + +/* Reset Value for T2STA*/ +#define T2STA_RVAL 0x0 + +/* T2STA[CON] - Indicates when a change in the enable bit is synchronized to the 32 kHz clock domain (Done automatically) */ +#define T2STA_CON_BBA (*(volatile unsigned long *) 0x4204A5A0) +#define T2STA_CON_MSK (0x1 << 8 ) +#define T2STA_CON (0x1 << 8 ) +#define T2STA_CON_CLR (0x0 << 8 ) /* CLR. It returns low when the change in the Enable bit has been synchronised to the 32 kHz clock domain. */ +#define T2STA_CON_SET (0x1 << 8 ) /* SET. This bit is set high when the Enable bit (bit 5) in the Control register is set or cleared and it is not synchronised to tthe 32 kHz clock. */ + +/* T2STA[FREEZE] - Status of T2VAL freeze */ +#define T2STA_FREEZE_BBA (*(volatile unsigned long *) 0x4204A59C) +#define T2STA_FREEZE_MSK (0x1 << 7 ) +#define T2STA_FREEZE (0x1 << 7 ) +#define T2STA_FREEZE_CLR (0x0 << 7 ) /* CLR. Reset low when T2VAL1 is read, indicating T2VAL is unfrozen. */ +#define T2STA_FREEZE_SET (0x1 << 7 ) /* SET. Set high when the T2VAL0 is read, indicating T2VAL is frozen. */ + +/* T2STA[ROLL] - Interrupt status bit for instances when counter rolls over. Only occurs in free running mode. */ +#define T2STA_ROLL_BBA (*(volatile unsigned long *) 0x4204A590) +#define T2STA_ROLL_MSK (0x1 << 4 ) +#define T2STA_ROLL (0x1 << 4 ) +#define T2STA_ROLL_CLR (0x0 << 4 ) /* CLR. Indicate that the timer has not rolled over. */ +#define T2STA_ROLL_SET (0x1 << 4 ) /* SET. Set high when enabled in the interrupt enable register and the T2VALS counter register is equal to all 1s */ + +/* T2STA[WUFD] - T2WUFD interrupt flag */ +#define T2STA_WUFD_BBA (*(volatile unsigned long *) 0x4204A58C) +#define T2STA_WUFD_MSK (0x1 << 3 ) +#define T2STA_WUFD (0x1 << 3 ) +#define T2STA_WUFD_CLR (0x0 << 3 ) /* CLR. Cleared after a write to the corresponding bit in T2CLRI. */ +#define T2STA_WUFD_SET (0x1 << 3 ) /* SET. Indicates that a comparator interrupt has occurred. */ + +/* T2STA[WUFC] - T2WUFC interrupt flag */ +#define T2STA_WUFC_BBA (*(volatile unsigned long *) 0x4204A588) +#define T2STA_WUFC_MSK (0x1 << 2 ) +#define T2STA_WUFC (0x1 << 2 ) +#define T2STA_WUFC_CLR (0x0 << 2 ) /* CLR. Cleared after a write to the corresponding bit in T2CLRI. */ +#define T2STA_WUFC_SET (0x1 << 2 ) /* SET. Indicates that a comparator interrupt has occurred. */ + +/* T2STA[WUFB] - T2WUFB interrupt flag */ +#define T2STA_WUFB_BBA (*(volatile unsigned long *) 0x4204A584) +#define T2STA_WUFB_MSK (0x1 << 1 ) +#define T2STA_WUFB (0x1 << 1 ) +#define T2STA_WUFB_CLR (0x0 << 1 ) /* CLR. Cleared after a write to the corresponding bit in T2CLRI. */ +#define T2STA_WUFB_SET (0x1 << 1 ) /* SET. Indicates that a comparator interrupt has occurred. */ + +/* T2STA[WUFA] - T2WUFA interrupt flag */ +#define T2STA_WUFA_BBA (*(volatile unsigned long *) 0x4204A580) +#define T2STA_WUFA_MSK (0x1 << 0 ) +#define T2STA_WUFA (0x1 << 0 ) +#define T2STA_WUFA_CLR (0x0 << 0 ) /* CLR. Cleared after a write to the corresponding bit in T2CLRI. */ +#define T2STA_WUFA_SET (0x1 << 0 ) /* SET. Indicates that a comparator interrupt has occurred. */ + +/* Reset Value for T2CLRI*/ +#define T2CLRI_RVAL 0x0 + +/* T2CLRI[ROLL] - Clear interrupt on Rollover. Only occurs in free running mode. */ +#define T2CLRI_ROLL_BBA (*(volatile unsigned long *) 0x4204A610) +#define T2CLRI_ROLL_MSK (0x1 << 4 ) +#define T2CLRI_ROLL (0x1 << 4 ) +#define T2CLRI_ROLL_CLR (0x1 << 4 ) /* CLR. Interrupt clear bit for when counter rolls over. */ + +/* T2CLRI[WUFD] - T2WUFD interrupt flag. Cleared automatically after synchronization. */ +#define T2CLRI_WUFD_BBA (*(volatile unsigned long *) 0x4204A60C) +#define T2CLRI_WUFD_MSK (0x1 << 3 ) +#define T2CLRI_WUFD (0x1 << 3 ) +#define T2CLRI_WUFD_CLR (0x1 << 3 ) /* CLR. Clear the T2WUFD interrupt flag. */ + +/* T2CLRI[WUFC] - T2WUFC interrupt flag. Cleared automatically after synchronization. */ +#define T2CLRI_WUFC_BBA (*(volatile unsigned long *) 0x4204A608) +#define T2CLRI_WUFC_MSK (0x1 << 2 ) +#define T2CLRI_WUFC (0x1 << 2 ) +#define T2CLRI_WUFC_CLR (0x1 << 2 ) /* CLR. Clear the T2WUFC interrupt flag. */ + +/* T2CLRI[WUFB] - T2WUFB interrupt flag. Cleared automatically after synchronization. */ +#define T2CLRI_WUFB_BBA (*(volatile unsigned long *) 0x4204A604) +#define T2CLRI_WUFB_MSK (0x1 << 1 ) +#define T2CLRI_WUFB (0x1 << 1 ) +#define T2CLRI_WUFB_CLR (0x1 << 1 ) /* CLR. Clear the T2WUFB interrupt flag. */ + +/* T2CLRI[WUFA] - T2WUFA interrupt flag. Cleared automatically after synchronization. */ +#define T2CLRI_WUFA_BBA (*(volatile unsigned long *) 0x4204A600) +#define T2CLRI_WUFA_MSK (0x1 << 0 ) +#define T2CLRI_WUFA (0x1 << 0 ) +#define T2CLRI_WUFA_CLR (0x1 << 0 ) /* CLR. Clear the T2WUFA interrupt flag. */ + +/* Reset Value for T2WUFA0*/ +#define T2WUFA0_RVAL 0x1900 + +/* T2WUFA0[VALUE] - Lower 16 bits of Compare Register A */ +#define T2WUFA0_VALUE_MSK (0xFFFF << 0 ) + +/* Reset Value for T2WUFA1*/ +#define T2WUFA1_RVAL 0x0 + +/* T2WUFA1[VALUE] - Upper 16 bits of Compare Register A */ +#define T2WUFA1_VALUE_MSK (0xFFFF << 0 ) +// ------------------------------------------------------------------------------------------------ +// ----- WDT ----- +// ------------------------------------------------------------------------------------------------ + + +/** + * @brief Watchdog Timer (pADI_WDT) + */ + +#if (__NO_MMR_STRUCTS__==0) +typedef struct { /*!< pADI_WDT Structure */ + __IO uint16_t T3LD; /*!< 16-bit Load Value */ + __I uint16_t RESERVED0; + __IO uint16_t T3VAL; /*!< 16-bit Timer Value */ + __I uint16_t RESERVED1; + __IO uint16_t T3CON; /*!< Control Register */ + __I uint16_t RESERVED2; + __IO uint16_t T3CLRI; /*!< Clear Interrupt Register */ + __I uint16_t RESERVED3[5]; + __IO uint16_t T3STA; /*!< Status Register */ +} ADI_WDT_TypeDef; +#else // (__NO_MMR_STRUCTS__==0) +#define T3LD (*(volatile unsigned short int *) 0x40002580) +#define T3VAL (*(volatile unsigned short int *) 0x40002584) +#define T3CON (*(volatile unsigned short int *) 0x40002588) +#define T3CLRI (*(volatile unsigned short int *) 0x4000258C) +#define T3STA (*(volatile unsigned short int *) 0x40002598) +#endif // (__NO_MMR_STRUCTS__==0) + +/* Reset Value for T3LD*/ +#define T3LD_RVAL 0x1000 + +/* T3LD[VALUE] - Load value. */ +#define T3LD_VALUE_MSK (0xFFFF << 0 ) + +/* Reset Value for T3VAL*/ +#define T3VAL_RVAL 0x1000 + +/* T3VAL[VALUE] - Current counter value. */ +#define T3VAL_VALUE_MSK (0xFFFF << 0 ) + +/* Reset Value for T3CON*/ +#define T3CON_RVAL 0xE9 + +/* T3CON[MOD] - Timer Mode */ +#define T3CON_MOD_BBA (*(volatile unsigned long *) 0x4204B118) +#define T3CON_MOD_MSK (0x1 << 6 ) +#define T3CON_MOD (0x1 << 6 ) +#define T3CON_MOD_Reserved (0x0 << 6 ) /* Reserved */ +#define T3CON_MOD_PERIODIC (0x1 << 6 ) /* PERIODIC: Operate in periodic mode. */ + +/* T3CON[ENABLE] - Timer enable bit. */ +#define T3CON_ENABLE_BBA (*(volatile unsigned long *) 0x4204B114) +#define T3CON_ENABLE_MSK (0x1 << 5 ) +#define T3CON_ENABLE (0x1 << 5 ) +#define T3CON_ENABLE_DIS (0x0 << 5 ) /* DIS. Disable the timer. Clearing this bit resets the timer, including the T0VAL register. */ +#define T3CON_ENABLE_EN (0x1 << 5 ) /* EN. Enable the timer. The timer starts counting from its initial value. */ + +/* T3CON[PRE] - Prescaler. */ +#define T3CON_PRE_MSK (0x3 << 2 ) +#define T3CON_PRE_DIV1 (0x0 << 2 ) /* DIV1. Source clock/1. */ +#define T3CON_PRE_DIV16 (0x1 << 2 ) /* DIV16. Source clock/16. */ +#define T3CON_PRE_DIV256 (0x2 << 2 ) /* DIV256. Source clock/256. */ +#define T3CON_PRE_DIV4096 (0x3 << 2 ) /* DIV4096. Source clock/4096. */ + +/* T3CON[IRQ] - Timer interrupt. */ +#define T3CON_IRQ_BBA (*(volatile unsigned long *) 0x4204B104) +#define T3CON_IRQ_MSK (0x1 << 1 ) +#define T3CON_IRQ (0x1 << 1 ) +#define T3CON_IRQ_DIS (0x0 << 1 ) /* DIS. Generate a reset on a timeout. */ +#define T3CON_IRQ_EN (0x1 << 1 ) /* EN. Generate an interrupt when the timer times out. This feature is available in active mode only and can be used to debug the watchdog timeout events. */ + +/* T3CON[PD] - Stop count in hibernate mode. */ +#define T3CON_PD_BBA (*(volatile unsigned long *) 0x4204B100) +#define T3CON_PD_MSK (0x1 << 0 ) +#define T3CON_PD (0x1 << 0 ) +#define T3CON_PD_DIS (0x0 << 0 ) /* DIS. The timer continues to count when in hibernate mode. */ +#define T3CON_PD_EN (0x1 << 0 ) /* EN. The timer stops counting when in hibernate mode. */ + +/* Reset Value for T3CLRI*/ +#define T3CLRI_RVAL 0x0 + +/* T3CLRI[VALUE] - Clear watchdog. */ +#define T3CLRI_VALUE_MSK (0xFFFF << 0 ) + +/* Reset Value for T3STA*/ +#define T3STA_RVAL 0x20 + +/* T3STA[LOCK] - Lock status bit. */ +#define T3STA_LOCK_BBA (*(volatile unsigned long *) 0x4204B310) +#define T3STA_LOCK_MSK (0x1 << 4 ) +#define T3STA_LOCK (0x1 << 4 ) +#define T3STA_LOCK_CLR (0x0 << 4 ) /* CLR. Cleared after any reset and until user code sets T3CON[5]. */ +#define T3STA_LOCK_SET (0x1 << 4 ) /* SET. Set automatically in hardware when user code sets T3CON[5]. */ + +/* T3STA[CON] - T3CON write sync in progress. */ +#define T3STA_CON_BBA (*(volatile unsigned long *) 0x4204B30C) +#define T3STA_CON_MSK (0x1 << 3 ) +#define T3STA_CON (0x1 << 3 ) +#define T3STA_CON_CLR (0x0 << 3 ) /* CLR. Timer ready to receive commands to T3CON. The previous change of T3CON has been synchronized in the timer clock domain. */ +#define T3STA_CON_SET (0x1 << 3 ) /* SET. Timer not ready to receive commands to T3CON. Previous change of the T3CON value has not been synchronized in the timer clock domain. */ + +/* T3STA[LD] - T3LD write sync in progress. */ +#define T3STA_LD_BBA (*(volatile unsigned long *) 0x4204B308) +#define T3STA_LD_MSK (0x1 << 2 ) +#define T3STA_LD (0x1 << 2 ) +#define T3STA_LD_CLR (0x0 << 2 ) /* CLR. The previous change of T3LD has been synchronized in the timer clock domain. */ +#define T3STA_LD_SET (0x1 << 2 ) /* SET. Previous change of the T3LD value has not been synchronized in the timer clock domain. */ + +/* T3STA[CLRI] - T3CLRI write sync in progress. */ +#define T3STA_CLRI_BBA (*(volatile unsigned long *) 0x4204B304) +#define T3STA_CLRI_MSK (0x1 << 1 ) +#define T3STA_CLRI (0x1 << 1 ) +#define T3STA_CLRI_CLR (0x0 << 1 ) /* CLR. Cleared when the interrupt is cleared in the timer clock domain. */ +#define T3STA_CLRI_SET (0x1 << 1 ) /* SET. Set automatically when the T3CLRI value is being updated in the timer clock domain, indicating that the timer’s configuration is not yet valid. */ + +/* T3STA[IRQ] - Interrupt pending. */ +#define T3STA_IRQ_BBA (*(volatile unsigned long *) 0x4204B300) +#define T3STA_IRQ_MSK (0x1 << 0 ) +#define T3STA_IRQ (0x1 << 0 ) +#define T3STA_IRQ_CLR (0x0 << 0 ) /* CLR. No timeout event has occurred. */ +#define T3STA_IRQ_SET (0x1 << 0 ) /* SET. A timeout event has occurred. */ + + +/* -------------------- End of section using anonymous unions ------------------- */ +#if defined(__CC_ARM) + #pragma pop +#elif defined(__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined(__TASKING__) + #pragma warning restore +#else + #warning Not supported compiler type +#endif +/******************************************** +** Miscellaneous Definitions ** +*********************************************/ + +//iEiNr in EiCfg() +#define EXTINT0 0x0 +#define EXTINT1 0x1 +#define EXTINT2 0x2 +#define EXTINT3 0x3 +#define EXTINT4 0x4 +#define EXTINT5 0x5 +#define EXTINT6 0x6 +#define EXTINT7 0x7 +#define EXTINT8 0x8 + +//iEnable in EiCfg() +#define INT_DIS 0x0 +#define INT_EN 0x1 + +//iMode in EiCfg() +#define INT_RISE 0x0 +#define INT_FALL 0x1 +#define INT_EDGES 0x2 +#define INT_HIGH 0x3 +#define INT_LOW 0x4 + +//Bit values. +#define BIT0 1 +#define BIT1 2 +#define BIT2 4 +#define BIT3 8 +#define BIT4 0x10 +#define BIT5 0x20 +#define BIT6 0x40 +#define BIT7 0x80 + + +/* ================================================================================ */ +/* ================ Peripheral memory map ================ */ +/* ================================================================================ */ + +#define ADI_ADC0_ADDR 0x40050000UL +#define ADI_CLKCTL_ADDR 0x40002000UL +#define ADI_DMA_ADDR 0x40010000UL +#define ADI_FEE_ADDR 0x40002800UL +#define ADI_GP0_ADDR 0x40006000UL +#define ADI_GP1_ADDR 0x40006030UL +#define ADI_GP2_ADDR 0x40006060UL +#define ADI_GP3_ADDR 0x40006090UL +#define ADI_GP4_ADDR 0x400060C0UL +#define ADI_GPIOCMN_ADDR 0x400060F0UL +#define ADI_MISC_ADDR 0x40008820UL +#define ADI_I2C_ADDR 0x40003000UL +#define ADI_INTERRUPT_ADDR 0x40002420UL +#define ADI_IDENT_ADDR 0x40002020UL +#define ADI_NVIC_ADDR 0xE000E000UL +#define ADI_PWRCTL_ADDR 0x40002400UL +#define ADI_PWM_ADDR 0x40001000UL +#define ADI_RESET_ADDR 0x40002440UL +#define ADI_SPI0_ADDR 0x40004000UL +#define ADI_SPI1_ADDR 0x40004400UL +#define ADI_TM0_ADDR 0x40000000UL +#define ADI_TM1_ADDR 0x40000400UL +#define ADI_UART_ADDR 0x40005000UL +#define ADI_WUT_ADDR 0x40002500UL +#define ADI_WDT_ADDR 0x40002580UL + + +/* ================================================================================ */ +/* ================ Peripheral declaration ================ */ +/* ================================================================================ */ + +#define pADI_ADC0 ((ADI_ADC_TypeDef *)ADI_ADC0_ADDR) +#define pADI_CLKCTL ((ADI_CLKCTL_TypeDef *)ADI_CLKCTL_ADDR) +#define pADI_DMA ((ADI_DMA_TypeDef *)ADI_DMA_ADDR) +#define pADI_FEE ((ADI_FEE_TypeDef *)ADI_FEE_ADDR) +#define pADI_GP0 ((ADI_GPIO_TypeDef *)ADI_GP0_ADDR) +#define pADI_GP1 ((ADI_GPIO_TypeDef *)ADI_GP1_ADDR) +#define pADI_GP2 ((ADI_GPIO_TypeDef *)ADI_GP2_ADDR) +#define pADI_GP3 ((ADI_GPIO_TypeDef *)ADI_GP3_ADDR) +#define pADI_GP4 ((ADI_GPIO_TypeDef *)ADI_GP4_ADDR) +#define pADI_GPIOCMN ((ADI_GPIOCMN_TypeDef *)ADI_GPIOCMN_ADDR) +#define pADI_MISC ((ADI_MISC_TypeDef *)ADI_MISC_ADDR) +#define pADI_I2C ((ADI_I2C_TypeDef *)ADI_I2C_ADDR) +#define pADI_INTERRUPT ((ADI_INTERRUPT_TypeDef *)ADI_INTERRUPT_ADDR) +#define pADI_PWRCTL ((ADI_PWRCTL_TypeDef *)ADI_PWRCTL_ADDR) +#define pADI_PWM ((ADI_PWM_TypeDef *)ADI_PWM_ADDR) +#define pADI_RESET ((ADI_RESET_TypeDef *)ADI_RESET_ADDR) +#define pADI_SPI0 ((ADI_SPI_TypeDef *)ADI_SPI0_ADDR) +#define pADI_SPI1 ((ADI_SPI_TypeDef *)ADI_SPI1_ADDR) +#define pADI_TM0 ((ADI_TIMER_TypeDef *)ADI_TM0_ADDR) +#define pADI_TM1 ((ADI_TIMER_TypeDef *)ADI_TM1_ADDR) +#define pADI_UART ((ADI_UART_TypeDef *)ADI_UART_ADDR) +#define pADI_WUT ((ADI_WUT_TypeDef *)ADI_WUT_ADDR) +#define pADI_WDT ((ADI_WDT_TypeDef *)ADI_WDT_ADDR) + +/** @} */ /* End of group Device_Peripheral_Registers *//** @} */ /* End of group ADUCRF101 */ +/** @} */ /* End of group CMSIS */ + +#ifdef __cplusplus +} +#endif + + +#endif // __ADUCRF101_H__ + diff --git a/cpu/arm/aducrf101/Common/GCC/ADuCRF101.ld b/cpu/arm/aducrf101/Common/GCC/ADuCRF101.ld new file mode 100644 index 000000000..8d553a5f7 --- /dev/null +++ b/cpu/arm/aducrf101/Common/GCC/ADuCRF101.ld @@ -0,0 +1,105 @@ +/** + * Copyright (c) 2014, Analog Devices, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) + +ENTRY(Reset_Handler) + +MEMORY +{ + flash (rx) : org = 0x00000000, len = 128k + ram (rwx) : org = 0x20000000, len = 16k +} + +SECTIONS +{ + .vectors : { + __vectors_start = .; + KEEP(*(.vectors)) + . = ALIGN(4); + } >flash + + .text : { + . = ALIGN(4); + *(.text) + *(.text.*) + etext = .; + } >flash + + .ARM.ex : { + *(.ARM.extab* .gnu.linkonce.armextab.*) + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + } >flash + + .rodata : { + . = ALIGN(4); + *(.rodata) + *(.rodata.*) + . = ALIGN(4); + __rodata_end = .; + } >flash + + .data : { + /* Initialized data is placed in flash, and will get + copied to RAM by crt0.S */ + . = ALIGN(4); + __data_flash_start = LOADADDR(.data); + __data_start = .; + *(.data) + *(.data.*) + + /* Code that goes into RAM also ends up here, and + gets copied along with the data section. */ + *(.ramtext*) + + __data_end = .; + edata = .; + } > ram AT > flash + + .bss : { + /* Stack is in BSS */ + . = ALIGN(8); + __bss_start = .; + *(.bss.stack) + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end = .; + end = .; + } > ram +} diff --git a/cpu/arm/aducrf101/Common/GCC/crt0.S b/cpu/arm/aducrf101/Common/GCC/crt0.S new file mode 100644 index 000000000..592f97902 --- /dev/null +++ b/cpu/arm/aducrf101/Common/GCC/crt0.S @@ -0,0 +1,184 @@ +/** + * Copyright (c) 2014, Analog Devices, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __STACK_SIZE +#define __STACK_SIZE 1024 +#endif + +.equ SCB_VTOR, 0xE000ED08 + +/* Stack */ + .section .bss.stack +stack_start: + .space __STACK_SIZE, 0 +stack_end: + .global stack_end + +/* Vector table */ + .macro handler name + .long \name\() + .weak \name\() + .set \name\(), unhandled_vector + .endm + + .macro handler_reserved + .long 0 + .endm + + .section .vectors, "a", %progbits +vectors: + .long stack_end + .long Reset_Handler + + /* Cortex-M3 core interrupts */ + handler NMI_Handler + handler HardFault_Handler + handler MemManage_Handler + handler BusFault_Handler + handler UsageFault_Handler + handler_reserved + handler_reserved + handler_reserved + handler_reserved + handler SVC_Handler + handler DebugMon_Handler + handler_reserved + handler PendSV_Handler + handler SysTick_Handler + + /* ADuCRF101 external interrupts */ + handler WakeUp_Int_Handler + handler Ext_Int0_Handler + handler Ext_Int1_Handler + handler Ext_Int2_Handler + handler Ext_Int3_Handler + handler Ext_Int4_Handler + handler Ext_Int5_Handler + handler Ext_Int6_Handler + handler Ext_Int7_Handler + handler Ext_Int8_Handler + handler WDog_Tmr_Int_Handler + handler_reserved + handler GP_Tmr0_Int_Handler + handler GP_Tmr1_Int_Handler + handler ADC0_Int_Handler + handler Flsh_Int_Handler + handler UART_Int_Handler + handler SPI0_Int_Handler + handler SPI1_Int_Handler + handler I2C0_Slave_Int_Handler + handler I2C0_Master_Int_Handler + handler_reserved + handler_reserved + handler DMA_Err_Int_Handler + handler DMA_SPI1_TX_Int_Handler + handler DMA_SPI1_RX_Int_Handler + handler DMA_UART_TX_Int_Handler + handler DMA_UART_RX_Int_Handler + handler DMA_I2C0_STX_Int_Handler + handler DMA_I2C0_SRX_Int_Handler + handler DMA_I2C0_MTX_Int_Handler + handler DMA_I2C0_MRX_Int_Handler + handler_reserved + handler_reserved + handler_reserved + handler DMA_ADC_Int_Handler + handler DMA_SPI0_TX_Int_Handler + handler DMA_SPI0_RX_Int_Handler + handler PWMTrip_Int_Handler + handler PWM0_Int_Handler + handler PWM1_Int_Handler + handler PWM2_Int_Handler + handler PWM3_Int_Handler + +/* Reset handler */ + .section .text + .syntax unified + .code 16 + .global Reset_Handler + .thumb_func +Reset_Handler: + /* Set up some basics, in case we came here from a call + rather than system reset. */ + + /* Disable interrupts */ + cpsid i + + /* Privileged mode, main stack, no floating point */ + mov r0, #0 + msr control, r0 + isb + + /* Point vector table to the right place */ + ldr r0, =__vectors_start + ldr r1, =SCB_VTOR + str r0, [r1] + + /* Load initial stack pointer */ + ldr r0, =stack_end + mov sp, r0 + isb + + /* Clear BSS */ + mov r0, #0 + ldr r1, =__bss_start + ldr r2, =__bss_end +zero_bss_loop: + cmp r1, r2 + it lt + strlt r0, [r1], #4 + blt zero_bss_loop + + /* Copy initialized data from flash to RAM */ + ldr r0, =__data_flash_start + ldr r1, =__data_start + ldr r2, =__data_end +copy_data_loop: + ldr r3, [r0], #4 + cmp r1, r2 + it lt + strlt r3, [r1], #4 + blt copy_data_loop + + /* We can run C code now */ + bl main + + /* If main returned, just loop */ + b . + +/* Handler for otherwise unhandled vectors */ + .section .text,"ax",%progbits + .thumb_func +unhandled_vector: + b unhandled_vector diff --git a/cpu/arm/aducrf101/Common/IAR/ADUCRF101.icf b/cpu/arm/aducrf101/Common/IAR/ADUCRF101.icf new file mode 100644 index 000000000..9ebe02a5a --- /dev/null +++ b/cpu/arm/aducrf101/Common/IAR/ADUCRF101.icf @@ -0,0 +1,67 @@ +/** + * Copyright (c) 2014, Analog Devices, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0001FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +do not initialize { section .mainstackarea }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; +place at address mem:0x1FC { readonly section .PageZeroCheckSum }; +place at address mem:0x1FFEC { readonly section .sigprot }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/cpu/arm/aducrf101/Common/IAR/Retarget.c b/cpu/arm/aducrf101/Common/IAR/Retarget.c new file mode 100644 index 000000000..0006d5a05 --- /dev/null +++ b/cpu/arm/aducrf101/Common/IAR/Retarget.c @@ -0,0 +1,99 @@ +/** + * Copyright (c) 2014, Analog Devices, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** + Module : Retarget.c + Description : uart interface + Date : December 2012 + Version : v2.00 + Changelog : v1.00 Initial + v2.00 use of UrtLib functions +*/ +#include +#include "UrtLib.h" +#include +#include +#include + +#define CR 0x0D + + + +/*************************************************************************/ +/* size_t __read(int handle,unsigned char *buf,size_t bufSize) */ +/* Write data to a stream */ +/* Needed for retargetting the IAR DLIB library for the ADUCRF101 */ +/*************************************************************************/ +size_t __read(int handle,unsigned char *buf,size_t bufSize) +{ + size_t i; + for (i=0x0; iCOMLSR & COMLSR_DR))); + buf[i] = pADI_UART->COMRX; + } + return i; +} + +/*************************************************************************/ +/* __write(int handle,const unsigned char *buf,size_t bufSize) */ +/* Read data from a stream */ +/* Needed for retargetting the IAR DLIB library for the ADUCRF101 */ +/*************************************************************************/ +size_t __write(int handle,const unsigned char *buf,size_t bufSize) +{ + size_t i; + for (i=0x0; i +#include +#include + +#pragma import(__use_no_semihosting_swi) + + #define CR 0x0D +struct __FILE { int handle; /* Add whatever you need here */ }; +FILE __stdout; +FILE __stdin; + + +// Re-targetting the Realview library functions +/* + * writes the character specified by c (converted to an unsigned char) to + * the output stream pointed to by stream, at the position indicated by the + * asociated file position indicator (if defined), and advances the + * indicator appropriately. If the file position indicator is not defined, + * the character is appended to the output stream. + * Returns: the character written. If a write error occurs, the error + * indicator is set and fputc returns EOF. + */ +int fputc(int ch, FILE * stream ) +{ + if(ch == '\n') + while(!(COMLSR_THRE==(UrtLinSta(0) & COMLSR_THRE))); + UrtTx(0, CR); /* output CR */ + while(!(COMLSR_THRE==(UrtLinSta(0) & COMLSR_THRE))); + UrtTx(0, ch); + return(ch); +} + +int __backspace(FILE *stream) +{ + return 0x0; + +} +/* + * obtains the next character (if present) as an unsigned char converted to + * an int, from the input stream pointed to by stream, and advances the + * associated file position indicator (if defined). + * Returns: the next character from the input stream pointed to by stream. + * If the stream is at end-of-file, the end-of-file indicator is + * set and fgetc returns EOF. If a read error occurs, the error + * indicator is set and fgetc returns EOF. + */ +int fgetc(FILE * stream) +{ + return (UrtRx(0)); +} + + +int ferror(FILE *f) { + /* Your implementation of ferror */ + return EOF; +} + + +void _ttywrch(int ch) { UrtTx(0, ch); } + + +void _sys_exit(int return_code) { +label: goto label; /* endless loop */ +} diff --git a/cpu/arm/aducrf101/Common/RealView/startup_ADuCRF101.s b/cpu/arm/aducrf101/Common/RealView/startup_ADuCRF101.s new file mode 100644 index 000000000..314f9cb0a --- /dev/null +++ b/cpu/arm/aducrf101/Common/RealView/startup_ADuCRF101.s @@ -0,0 +1,312 @@ +; Copyright (c) 2014, Analog Devices, Inc. All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted (subject to the limitations in the +; disclaimer below) provided that the following conditions are met: +; +; - Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; +; - Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the +; distribution. +; +; - Neither the name of Analog Devices, Inc. nor the names of its +; contributors may be used to endorse or promote products derived +; from this software without specific prior written permission. +; +; NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +; GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +; HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +; WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +; MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +; BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +; WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +; OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +; IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +; Module : startup_ADuCRF101.s +; Description : Cortex-M3 startup file - ADuCRF101 - RealView Version +; Date : 14 January 2013 +; Version : v1.01 +; Changelog : v1.01 Added call to SystemInit +; Changelog : v1.00 Initial + + IMPORT __use_no_semihosting_swi +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; The NMI handler + DCD HardFault_Handler ; The hard fault handler + DCD MemManage_Handler ; The MPU fault handler + DCD BusFault_Handler ; The bus fault handler + DCD UsageFault_Handler ; The usage fault handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall handler + DCD DebugMon_Handler ; Debug monitor handler + DCD 0 ; Reserved + DCD PendSV_Handler ; The PendSV handler + DCD SysTick_Handler ; The SysTick handler + + ; External Interrupts + DCD WakeUp_Int_Handler ; Wake Up Timer [ 0] + DCD Ext_Int0_Handler ; External Interrupt 0 [ 1] + DCD Ext_Int1_Handler ; External Interrupt 1 [ 2] + DCD Ext_Int2_Handler ; External Interrupt 2 [ 3] + DCD Ext_Int3_Handler ; External Interrupt 3 [ 4] + DCD Ext_Int4_Handler ; External Interrupt 4 [ 5] + DCD Ext_Int5_Handler ; External Interrupt 5 [ 6] + DCD Ext_Int6_Handler ; External Interrupt 6 [ 7] + DCD Ext_Int7_Handler ; External Interrupt 7 [ 8] + DCD Ext_Int8_Handler ; External Interrupt 8 [ 9] + DCD WDog_Tmr_Int_Handler ; Watchdog timer handler [10] + DCD UnUsed_Handler ; Reserved [11] + DCD GP_Tmr0_Int_Handler ; General purpose timer 0 [12] + DCD GP_Tmr1_Int_Handler ; General purpose timer 1 [13] + DCD ADC0_Int_Handler ; ADC Interrupt [14] + DCD Flsh_Int_Handler ; Flash IRQ [15] + DCD UART_Int_Handler ; UART0 [16] + DCD SPI0_Int_Handler ; SPI 0 [17] + DCD SPI1_Int_Handler ; SPI 1 [18] + DCD I2C0_Slave_Int_Handler ; I2C0 Slave [19] + DCD I2C0_Master_Int_Handler ; I2C0 Master [20] + DCD UnUsed_Handler ; Reserved [21] + DCD UnUsed_Handler ; Reserved [22] + DCD DMA_Err_Int_Handler ; DMA Error interrupt [23] + DCD DMA_SPI1_TX_Int_Handler ; DMA SPI1 TX [24] + DCD DMA_SPI1_RX_Int_Handler ; DMA SPI1 RX [25] + DCD DMA_UART_TX_Int_Handler ; DMA UART TX [26] + DCD DMA_UART_RX_Int_Handler ; DMA UART RX [27] + DCD DMA_I2C0_STX_Int_Handler ; DMA I2C0 Slave TX [28] + DCD DMA_I2C0_SRX_Int_Handler ; DMA I2C0 Slave RX [29] + DCD DMA_I2C0_MTX_Int_Handler ; DMA I2C0 Master TX [30] + DCD DMA_I2C0_MRX_Int_Handler ; DMA I2C0 Master RX [31] + DCD UnUsed_Handler ; Reserved [32] + DCD UnUsed_Handler ; Reserved [33] + DCD UnUsed_Handler ; Reserved [34] + DCD DMA_ADC_Int_Handler ; DMA ADC [35] + DCD DMA_SPI0_TX_Int_Handler ; DMA SPI0 TX [36] + DCD DMA_SPI0_RX_Int_Handler ; DMA SPI0 RX [37] + DCD PWMTrip_Int_Handler ; PWM Trip [38] + DCD PWM0_Int_Handler ; PWM 0 [39] + DCD PWM1_Int_Handler ; PWM 1 [40] + DCD PWM2_Int_Handler ; PWM 2 [41] + DCD PWM3_Int_Handler ; PWM 3 [42] + DCD UnUsed_Handler ; Unused [43] +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit ; Defined in system_ADuCRF101.c + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WakeUp_Int_Handler [WEAK] + EXPORT Ext_Int0_Handler [WEAK] + EXPORT Ext_Int1_Handler [WEAK] + EXPORT Ext_Int2_Handler [WEAK] + EXPORT Ext_Int3_Handler [WEAK] + EXPORT Ext_Int4_Handler [WEAK] + EXPORT Ext_Int5_Handler [WEAK] + EXPORT Ext_Int6_Handler [WEAK] + EXPORT Ext_Int7_Handler [WEAK] + EXPORT Ext_Int8_Handler [WEAK] + EXPORT WDog_Tmr_Int_Handler [WEAK] + EXPORT GP_Tmr0_Int_Handler [WEAK] + EXPORT GP_Tmr1_Int_Handler [WEAK] + EXPORT ADC0_Int_Handler [WEAK] + EXPORT Flsh_Int_Handler [WEAK] + EXPORT UART_Int_Handler [WEAK] + EXPORT SPI0_Int_Handler [WEAK] + EXPORT SPI1_Int_Handler [WEAK] + EXPORT I2C0_Slave_Int_Handler [WEAK] + EXPORT I2C0_Master_Int_Handler [WEAK] + EXPORT DMA_Err_Int_Handler [WEAK] + EXPORT DMA_SPI1_TX_Int_Handler [WEAK] + EXPORT DMA_SPI1_RX_Int_Handler [WEAK] + EXPORT DMA_UART_TX_Int_Handler [WEAK] + EXPORT DMA_UART_RX_Int_Handler [WEAK] + EXPORT DMA_I2C0_STX_Int_Handler [WEAK] + EXPORT DMA_I2C0_SRX_Int_Handler [WEAK] + EXPORT DMA_I2C0_MTX_Int_Handler [WEAK] + EXPORT DMA_I2C0_MRX_Int_Handler [WEAK] + EXPORT DMA_ADC_Int_Handler [WEAK] + EXPORT DMA_SPI0_TX_Int_Handler [WEAK] + EXPORT DMA_SPI0_RX_Int_Handler [WEAK] + EXPORT PWMTrip_Int_Handler [WEAK] + EXPORT PWM0_Int_Handler [WEAK] + EXPORT PWM1_Int_Handler [WEAK] + EXPORT PWM2_Int_Handler [WEAK] + EXPORT PWM3_Int_Handler [WEAK] + EXPORT UnUsed_Handler [WEAK] + + +WakeUp_Int_Handler +Ext_Int0_Handler +Ext_Int1_Handler +Ext_Int2_Handler +Ext_Int3_Handler +Ext_Int4_Handler +Ext_Int5_Handler +Ext_Int6_Handler +Ext_Int7_Handler +Ext_Int8_Handler +WDog_Tmr_Int_Handler +GP_Tmr0_Int_Handler +GP_Tmr1_Int_Handler +ADC0_Int_Handler +Flsh_Int_Handler +UART_Int_Handler +SPI0_Int_Handler +SPI1_Int_Handler +I2C0_Slave_Int_Handler +I2C0_Master_Int_Handler +DMA_Err_Int_Handler +DMA_SPI1_TX_Int_Handler +DMA_SPI1_RX_Int_Handler +DMA_UART_TX_Int_Handler +DMA_UART_RX_Int_Handler +DMA_I2C0_STX_Int_Handler +DMA_I2C0_SRX_Int_Handler +DMA_I2C0_MTX_Int_Handler +DMA_I2C0_MRX_Int_Handler +DMA_ADC_Int_Handler +DMA_SPI0_TX_Int_Handler +DMA_SPI0_RX_Int_Handler +PWMTrip_Int_Handler +PWM0_Int_Handler +PWM1_Int_Handler +PWM2_Int_Handler +PWM3_Int_Handler +UnUsed_Handler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + diff --git a/cpu/arm/aducrf101/Common/aducrf101-include.h b/cpu/arm/aducrf101/Common/aducrf101-include.h new file mode 100644 index 000000000..1d250d121 --- /dev/null +++ b/cpu/arm/aducrf101/Common/aducrf101-include.h @@ -0,0 +1,61 @@ +/** + * Copyright (c) 2014, Analog Devices, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** + @module include.h + @brief Main Include file + @version V0.2 + @author PAD CSE group, Analog Devices Inc + @date January 2013 + + @par Revision History: + - V0.1, February 2012: initial version. + - V0.2, January 2013: addition of PwmLib, FeeLib and DmaLib + remove uart.h +**/ + +#ifndef __INCLUDE_H +#define __INCLUDE_H + +#include +#include +#include +#include +#include +#include + +#include + +#include "radioeng.h" + +#endif // __INCLUDE_H diff --git a/cpu/arm/aducrf101/Common/defs.h b/cpu/arm/aducrf101/Common/defs.h new file mode 100644 index 000000000..e129c7e58 --- /dev/null +++ b/cpu/arm/aducrf101/Common/defs.h @@ -0,0 +1,42 @@ +/** + * Copyright (c) 2014, Analog Devices, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** + @file defs.h + @brief Global definitions. + @version V0.1 + @author PAD CSE group, Analog Devices Inc + @date January 2012 +**/ + +typedef enum {FALSE = 0, TRUE = !FALSE} boolean; diff --git a/cpu/arm/aducrf101/Common/radioeng.c b/cpu/arm/aducrf101/Common/radioeng.c new file mode 100644 index 000000000..c4431c832 --- /dev/null +++ b/cpu/arm/aducrf101/Common/radioeng.c @@ -0,0 +1,1791 @@ +/** + * Copyright (c) 2014, Analog Devices, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** + @file radioeng.c + @brief Radio Interface Engine Functions + @version v1.0 + @author PAD CSE group, Analog Devices Inc + @date May 08th 2013 +**/ + +#include "aducrf101-include.h" + +// 1.0 of the Engine +#define RIE_ENGINE_MAJOR_VERSION 1UL +#define RIE_ENGINE_MINOR_VERSION 0UL + + +#define RADIO_SPI_CLK_FREQ 4000000 // 4 MHz SPI CLK for radio interface +#define SYSTEM_UCLK 16000000 // 16 MHz UCLK +// Default Radio Parameters +#define DEFAULT_CHNL_FREQ 915000000 +#define FREQ_CNVRT_VAL 0.00252061538 +// Defines for radio memory mapped areas +#define PACKETRAM_START 0x10 +#define PACKETRAM_LEN 240 +#define BBRAM_START 0x100 +#define PR_var_tx_mode_ADR 0x00D + +// PrF Table 35 +#define PARAM_TX_NORMAL_PACKET 0 +#define PARAM_TX_PREAMBLE_FOREVER 2 +#define PARAM_TX_CARRIER_FOREVER 3 + +#define gpio_configure_sport_mode_0 0xA0 +#define gpio_configure_default 0x00 +#define MCR_pa_level_mcr_Adr 0x307 +#define MCR_rssi_readback_Adr 0x312 +#define MCR_gpio_configure_Adr 0x3fa +#define MCR_ext_uc_clk_divide_Adr 0x32e +#define MCR_interrupt_source_0_Adr 0x336 +#define MCR_interrupt_source_1_Adr 0x337 + +// Macros for manual GPIO checking of Radio MISO pin P2.0 (SPI0) +#define RADIO_MISO_IN GP2IN_IN0_BBA +// Macros for manual GPIO control of P2.3 (Radio SPI CS) (SPI0) +#define RADIO_CSN_DEASSERT (pADI_GP2->GPSET = GP2SET_SET3) +#define RADIO_CSN_ASSERT (pADI_GP2->GPCLR = GP2CLR_CLR3) +// Macros for Sending\Receiving single bytes via SPI +#define SEND_SPI(x) pADI_SPI0->SPITX = x +#define WAIT_SPI_RX while((pADI_SPI0->SPISTA & SPISTA_RXFSTA_MSK) == 0x0); +#define READ_SPI pADI_SPI0->SPIRX + +// Bit Manipulation Macros +#define MSKSET_VAL(byte,numbits,offset,value) ((byte & ~(((0x1 << numbits)-1) << offset)) | value) + + + +/*************************************************************************/ +/* Local Types */ +/*************************************************************************/ +/*************************************************************************/ +/* Radio Command Codes */ +/*************************************************************************/ +typedef enum +{ + CMD_SYNC = 0xA2, // Synchronizatio + CMD_PHY_OFF = 0xB0, // Transition to state PHY_OFF + CMD_PHY_ON = 0xB1, // transition to state PHY_ON + CMD_PHY_RX = 0xB2, // transition to state PHY_RX + CMD_PHY_TX = 0xB5, // transition to state PHY_TX + CMD_PHY_SLEEP = 0xBA, // transition to state PHY_SLEEP + CMD_CONFIG_DEV = 0xBB, // Apply Radio Configuration + CMD_GET_RSSI = 0xBC, // Performs an RSSI measurement + CMD_HW_RESET = 0xC8, // Power Down radio + SPI_MEM_WR = 0x18, // Sequential SPI Write + SPI_MEM_RD = 0x38, // Sequential SPI Read + SPI_NOP = 0xFF // No operation +} Radio_CmdCodes; +/*************************************************************************/ +/* Firmware States */ +/*************************************************************************/ +typedef enum +{ + FW_INIT = 0x0F, // Radio Starting Up + FW_BUSY = 0x00, // Radio not completed current operation + FW_RSSI = 0x05, // Performing CMD_GET_RSSI + FW_OFF = 0x11, // Radio is OFF + FW_ON = 0x12, // Radio is ON + FW_RX = 0x13, // Radio is in receive mode + FW_TX = 0x14, // Radio is in transmit mode + +} RadioState; +/*************************************************************************/ +/* Status Byte Masks */ +/*************************************************************************/ +#define STATUS_BYTE_FW_STATE (0x1F << 0) +#define STATUS_BYTE_CMD_READY (0x1 << 5) +#define STATUS_BYTE_IRQ_STATUS (0x1 << 6) +#define STATUS_BYTE_SPI_READY (0x1 << 7) +/*************************************************************************/ +/* SPI Memory Access Defs */ +/*************************************************************************/ +#define SPI_MEMCMD_BYTE0_ADR_MSK (0x3 << 0) +#define SPI_MEMCMD_BYTE0_CMD_BITOFFSET 3 +#define SPI_MEMCMD_BYTE0_CMD_MSK (0x1F << SPI_MEMCMD_BYTE0_CMD_BITOFFSET) +/*************************************************************************/ +/* Radio Configuration Structure */ +/*************************************************************************/ +/** + \internal Hide from Doxegen + \var TyRadioConfiguration + **/ +typedef struct +{ + RIE_U8 interrupt_mask_0_r; // 0x100 + RIE_U8 cfg_101_r; // 0x101 + RIE_U8 cfg_102_r; // 0x102 + RIE_U8 cfg_103_r; // 0x103 + RIE_U8 cfg_104_r; // 0x104 + RIE_U8 cfg_105_r; // 0x105 + RIE_U8 cfg_106_r; // 0x106 + RIE_U8 cfg_107_r; // 0x107 + RIE_U8 cfg_108_r; // 0x108 + RIE_U8 channel_freq_0_r; // 0x109 + RIE_U8 channel_freq_1_r; // 0x10A + RIE_U8 channel_freq_2_r; // 0x10B + RIE_U8 cfg_10C_r; // 0x10C + RIE_U8 cfg_10D_r; // 0x10D + RIE_U8 cfg_10E_r; // 0x10E + RIE_U8 cfg_10F_r; // 0x10F + RIE_U8 cfg_110_r; // 0x110 + RIE_U8 cfg_111_r; // 0x111 + RIE_U8 cfg_112_r; // 0x112 + RIE_U8 cfg_113_r; // 0x113 + RIE_U8 radio_cfg_8_r; // 0x114 + RIE_U8 radio_cfg_9_r; // 0x115 + RIE_U8 cfg_116_r; // 0x116 + RIE_U8 cfg_117_r; // 0x117 + RIE_U8 image_reject_cal_phase_r; // 0x118 + RIE_U8 image_reject_cal_amplitude_r; // 0x119 + RIE_U8 cfg_11A_r; // 0x11A + RIE_U8 cfg_11B_r; // 0x11B + RIE_U8 symbol_mode_r; // 0x11C + RIE_U8 cfg_11D_r; // 0x11D + RIE_U8 cfg_11E_r; // 0x11E + RIE_U8 cfg_11F_r; // 0x11F + RIE_U8 cfg_120_r; // 0x120 + RIE_U8 cfg_121_r; // 0x121 + RIE_U8 cfg_122_r; // 0x122 + RIE_U8 cfg_123_r; // 0x123 + RIE_U8 tx_base_adr_r; // 0x124 + RIE_U8 rx_base_adr_r; // 0x125 + RIE_U8 packet_length_control_r; // 0x126 + RIE_U8 packet_length_max_r; // 0x127 + RIE_U8 cfg_128_r; // 0x128 + RIE_U8 cfg_129_r; // 0x129 + RIE_U8 cfg_12A_r; // 0x12A + RIE_U8 cfg_12B_r; // 0x12B + RIE_U8 cfg_12C_r; // 0x12C + RIE_U8 cfg_12D_r; // 0x12D + RIE_U8 cfg_12E_r; // 0x12E + RIE_U8 cfg_12F_r; // 0x12F + RIE_U8 cfg_130_r; // 0x130 + RIE_U8 cfg_131_r; // 0x131 + RIE_U8 cfg_132_r; // 0x132 + RIE_U8 cfg_133_r; // 0x133 + RIE_U8 cfg_134_r; // 0x134 + RIE_U8 cfg_135_r; // 0x135 + RIE_U8 cfg_136_r; // 0x136 + RIE_U8 cfg_137_r; // 0x137 + RIE_U8 cfg_138_r; // 0x138 + RIE_U8 cfg_139_r; // 0x139 + RIE_U8 cfg_13A_r; // 0x13A + RIE_U8 cfg_13B_r; // 0x13B + RIE_U8 cfg_13C_r; // 0x13C + RIE_U8 cfg_13D_r; // 0x13D + RIE_U8 cfg_13E_r; // 0x13E + RIE_U8 cfg_13F_r; // 0x13F +} TyRadioConfiguration; +/*************************************************************************/ +/* Radio Configuration Constants */ +/*************************************************************************/ +#define interrupt_mask_0_interrupt_tx_eof (0x1 << 4) +#define interrupt_mask_0_interrupt_crc_correct (0x1 << 2) + +#define packet_length_control_length_offset_offset (0) +#define packet_length_control_length_offset_minus0 (0x4 << packet_length_control_length_offset_offset) +#define packet_length_control_data_mode_offset (3) +#define packet_length_control_data_mode_packet (0x0 << packet_length_control_data_mode_offset) +#define packet_length_control_crc_en_yes (0x1 << 5) +#define packet_length_control_packet_len_variable (0x0 << 6) +#define packet_length_control_packet_len_fixed (0x1 << 6) +#define packet_length_control_data_byte_lsb (0x0 << 7) + +#define symbol_mode_symbol_length_8_bit (0 << 0) +#define symbol_mode_data_whitening_disabled (0 << 3) +#define symbol_mode_data_whitening_enabled (1 << 3) +#define symbol_mode_eight_ten_enc_disabled (0 << 4 ) +#define symbol_mode_prog_crc_en_disabled (0 << 5) +#define symbol_mode_manchester_enc_enabled (1 << 6) + +#define radio_cfg_8_pa_single_diff_sel_single_ended (0x0 << 7) +#define radio_cfg_8_pa_single_diff_sel_differential (0x1 << 7) +#define radio_cfg_8_pa_power_numbits (4) +#define radio_cfg_8_pa_power_offset (3) +#define radio_cfg_8_pa_power_setting_63 (0xF << radio_cfg_8_pa_power_offset) +#define radio_cfg_8_pa_ramp_numbits (3) +#define radio_cfg_8_pa_ramp_offset (0) +#define radio_cfg_8_pa_ramp_16 (0x5 << radio_cfg_8_pa_ramp_offset) + +#define radio_cfg_9_demod_scheme_offset (0) +#define radio_cfg_9_demod_scheme_FSK (0x0 << radio_cfg_9_demod_scheme_offset) +#define radio_cfg_9_mod_scheme_numbits (3) +#define radio_cfg_9_mod_scheme_offset (3) +#define radio_cfg_9_mod_scheme_2_level_FSK (0x0 << radio_cfg_9_mod_scheme_offset) +#define radio_cfg_9_mod_scheme_2_level_GFSK (0x1 << radio_cfg_9_mod_scheme_offset) +#define radio_cfg_9_ifbw_numbits (2) +#define radio_cfg_9_ifbw_offset (6) +#define radio_cfg_9_ifbw_100kHz (0x0 << radio_cfg_9_ifbw_offset) +#define radio_cfg_9_ifbw_150kHz (0x1 << radio_cfg_9_ifbw_offset) +#define radio_cfg_9_ifbw_200kHz (0x2 << radio_cfg_9_ifbw_offset) +#define radio_cfg_9_ifbw_300kHz (0x3 << radio_cfg_9_ifbw_offset) + +/*************************************************************************/ +/* Local Variables */ +/*************************************************************************/ +static TyRadioConfiguration RadioConfiguration; +static RIE_BOOL bRadioConfigurationChanged = RIE_FALSE; +static RIE_BOOL bTestModeEnabled = RIE_FALSE; +static RIE_U32 DataRate = 38400; +static volatile RIE_BOOL bPacketTx = RIE_FALSE; +static volatile RIE_BOOL bPacketRx = RIE_FALSE; + +const RIE_U8 DR_38_4kbps_Dev20kHz_Configuration[] = +{ + 0x14,0x00,0x00,0x00,0x00,0x00,0x00,0x33,0x00,0x76,0x62,0x21, + +// 0 1 2 3 4 5 6 7 8 9 A B + 0x80,0x01,0xC8,0x20,0x0E,0x00,0x00,0x00,0xFD,0x00,0x0B,0x37, + 0x16,0x07, + + 0x40,0x0C,0x00,0x0C,0x00,0x00, + 0x10,0x00,0xC3,0x36,0x10,0x10,0x24,0xF0,0x2A,0x00,0x2F,0x19,0x5E,0x46,0x5F,0x78, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 +}; + + +const RIE_U8 DR_300_0kbps_Dev75_0kHz_Configuration[] = +{ + 0x14,0x00,0x00,0x00,0x00,0x00,0x00,0x33,0x00,0x76,0x62,0x21, + +// 0 1 2 3 4 5 6 7 8 9 A B + 0xB8,0x2B,0xEE,0x0B,0x70,0x00,0x03,0x00,0xFD,0xC0,0x0B,0x37, + 0x16,0x07, + + 0x40,0x0C,0x00,0x0C,0x00,0x00, + 0x10,0x00,0xC3,0x36,0x10,0x10,0x24,0xF0,0x2A,0x00,0x2F,0x19,0x5E,0x46,0x5F,0x78, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 +}; + + + +const RIE_U8 DR_1_0kbps_Dev10_0kHz_Configuration[] = +{ + 0x14,0x00,0x00,0x00,0x00,0x00,0x00,0x33,0x00,0x76,0x62,0x21, +// 0 1 2 3 4 5 6 7 8 9 A B + 0x0A,0x00,0x64,0x41,0x01,0x00,0x02,0x00,0xFD,0x00,0x0B,0x37, + 0x16,0x07, + + 0x40,0x0C,0x00,0x0C,0x00,0x00, + 0x10,0x00,0xC3,0x36,0x10,0x10,0x24,0xF0,0x2A,0x00,0x2F,0x19,0x5E,0x46,0x5F,0x78, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 +}; + +/*************************************************************************/ +/* Local Functions */ +/*************************************************************************/ +static RIE_Responses RadioSPIXferByte (RIE_U8 ucByte, + RIE_U8 * pData); +static RIE_Responses RadioSendCommandBytes (RIE_U8 * pCmdBytes, + RIE_U8 NumBytes); +static RIE_Responses RadioSendCommandNoWait (Radio_CmdCodes CmdCode); +static RIE_Responses RadioSendCommandWait (Radio_CmdCodes CmdCode); +static RIE_Responses RadioMMapRead (RIE_U32 ulAdr, + RIE_U32 ulLen, + RIE_U8 * pData); +static RIE_Responses RadioMMapWrite (RIE_U32 ulAdr, + RIE_U32 ulLen, + RIE_U8 * pData); +static RIE_Responses RadioReadState (RadioState * pState); +static RIE_Responses RadioWaitOnState (RadioState FinalState); +static RIE_Responses RadioWaitForPowerUp (void); +static RIE_Responses RadioSyncComms (void); +static RIE_Responses SetRadioConfiguration (RIE_BaseConfigs BaseConfig); +static RIE_Responses RadioCommitRadioConfig (void); +static RIE_Responses RadioConfigure (void); +static RIE_Responses RadioToOnMode (void); +static RIE_Responses RadioToOffMode (void); +static RIE_Responses RadioWaitOnCmdLdr (void); +/*************************************************************************/ +/* Functions Implementations - Start */ +/*************************************************************************/ + +/** + @fn RIE_Responses RadioGetAPIVersion(RIE_U32 *pVersion) + @brief Return the Radio Interface Engine API Version + @param pVersion :{} + pVersion Storage for Radio Interface Engine API version. + @code + RIE_U32 Version; + Response = RadioGetAPIVersion(&Version); + @endcode + @return RIE_Responses Error code. +**/ + +RIE_Responses RadioGetAPIVersion(RIE_U32 *pVersion) +{ + RIE_Responses Response = RIE_Success; + + if (pVersion) + *pVersion = RIE_ENGINE_MINOR_VERSION | (RIE_ENGINE_MAJOR_VERSION << 8); + return Response; +} + + +/** + @fn RIE_U32 RadioSwitchConfig(RIE_BaseConfigs BaseConfig) + @brief Change the Radio to using specified configuration. + @param BaseConfig :{DR_1_0kbps_Dev10_0kHz, DR_38_4kbps_Dev20kHz, DR_300_0kbps_Dev75_0kHz} + - DR_1_0kbps_Dev10_0kHz Base configuration of 1 kbps datarate, 10.0 kHz frequency deviation. + - DR_38_4kbps_Dev20kHz Base configuration of 38.4 kbps datarate, 20 kHz frequency deviation. + - DR_300_0kbps_Dev75_0kHz Base configuration of 300 kbps datarate, 75 kHz frequency deviation. + @pre + RadioInit() must be called before this function is called. + @return RIE_Responses Error code. +**/ + +RIE_Responses RadioSwitchConfig(RIE_BaseConfigs BaseConfig) +{ + RIE_Responses Response = RIE_Success; + if(Response == RIE_Success) + Response = RadioToOffMode(); + if(Response == RIE_Success) + Response = SetRadioConfiguration(BaseConfig); + if(Response == RIE_Success) + Response = RadioCommitRadioConfig(); + if(Response == RIE_Success) + Response = RadioToOnMode(); + return Response; +} + + +/** + @fn RIE_U32 RadioInit(RIE_BaseConfigs BaseConfig) + @brief Initialise the Radio, using specified configuration. + @param BaseConfig :{DR_1_0kbps_Dev10_0kHz , DR_38_4kbps_Dev20kHz ,DR_300_0kbps_Dev75_0kHz } + - DR_1_0kbps_Dev10_0kHz Base configuration of 1 kbps datarate, 10.0 kHz frequency deviation. + - DR_38_4kbps_Dev20kHz Base configuration of 38.4 kbps datarate, 20 kHz frequency deviation. + - DR_300_0kbps_Dev75_0kHz Base configuration of 300 kbps datarate, 75 kHz frequency deviation. + @note + This must be called before any other function is called. + @return RIE_Responses Error code. +**/ + +RIE_Responses RadioInit(RIE_BaseConfigs BaseConfig) +{ + RIE_Responses Response = RIE_Success; + + // Disable the radio interrupt until we have initialised the radio + NVIC_DisableIRQ(UHFTRX_IRQn); + + // Initialise GPIO Port 2 for Radio Use + pADI_GP2->GPCON = GP2CON_CON0_SPI0MISO | GP2CON_CON1_SPI0SCLK | + GP2CON_CON2_SPI0MOSI | GP2CON_CON3_GPIO | + GP2CON_CON4_IRQ8 | GP2CON_CON5_GPIO | + GP2CON_CON6_GPIO | GP2CON_CON7_GPIOIRQ7; + + pADI_GP2->GPOEN = GP2OEN_OEN0_IN | GP2OEN_OEN1_IN | + GP2OEN_OEN2_IN | GP2OEN_OEN3_OUT | + GP2OEN_OEN4_IN | GP2OEN_OEN5_IN | + GP2OEN_OEN6_IN | GP2OEN_OEN7_IN; + + // Disable the PULL-Up on P2.4 which is connected to the radio + GP2PUL_PUL4_BBA = 0x0; + + // Configure the SPI Interface to the Radio and flush it + pADI_SPI0->SPIDIV = ((SYSTEM_UCLK/RADIO_SPI_CLK_FREQ)/2)-0x1; + pADI_SPI0->SPICON = SPICON_MASEN | // Master mode + SPICON_TIM | // Interrupt on transmit + SPICON_TFLUSH | // Flush FIFO + SPICON_RFLUSH | // Flush FIFO + SPICON_ENABLE; + pADI_SPI0->SPICON = SPICON_MASEN | // Master mode + SPICON_TIM | // Interrupt on transmit + SPICON_ENABLE; + + // Initialise the chip select line to starting position + RADIO_CSN_DEASSERT; + + + // Power it down and up again to return to a known state + // which will be PHY_OFF. + // This will clear any pre-existing radio interrupt before + // we enable the Cortex interrupt handling of it + if(Response == RIE_Success) + Response = RadioPowerOff(); + // Configure a "high level" radio interrupt ... + pADI_INTERRUPT->EI2CFG = EI2CFG_IRQ8MDE_HIGHLEVEL | EI2CFG_IRQ8EN; + // ... and set it up in the NVIC so that our interrupt handler is called + // when the radio wants our attention. Clear any pre-existing condition + // before enabling the interrupt. + pADI_INTERRUPT->EICLR = EICLR_IRQ8; + NVIC_ClearPendingIRQ(UHFTRX_IRQn); + NVIC_SetPriority (UHFTRX_IRQn,0x0); + NVIC_EnableIRQ (UHFTRX_IRQn); + + if(Response == RIE_Success) + Response = RadioWaitForPowerUp(); + if(Response == RIE_Success) + Response = RadioSyncComms(); + if(Response == RIE_Success) + Response = RadioToOffMode(); + if(Response == RIE_Success) + Response = SetRadioConfiguration(BaseConfig); + if(Response == RIE_Success) + Response = RadioCommitRadioConfig(); + if(Response == RIE_Success) + Response = RadioToOnMode(); + return Response; +} + +/** + @fn RIE_U32 RadioDeInit(void) + @brief Deinitialise the Radio, and power it down. + @note + This can be called independently of all other functions to power down + the radio + @return RIE_Responses Error code. +**/ + +RIE_Responses RadioDeInit(void) +{ + RIE_Responses Response = RIE_Success; + + // Disable the radio interrupt + NVIC_DisableIRQ(UHFTRX_IRQn); + + // Initialise GPIO Port 2 for Radio Use + pADI_GP2->GPCON = GP2CON_CON0_SPI0MISO | GP2CON_CON1_SPI0SCLK | + GP2CON_CON2_SPI0MOSI | GP2CON_CON3_GPIO | + GP2CON_CON4_IRQ8 | GP2CON_CON5_GPIO | + GP2CON_CON6_GPIO | GP2CON_CON7_GPIOIRQ7; + + pADI_GP2->GPOEN = GP2OEN_OEN0_IN | GP2OEN_OEN1_IN | + GP2OEN_OEN2_IN | GP2OEN_OEN3_OUT | + GP2OEN_OEN4_IN | GP2OEN_OEN5_IN | + GP2OEN_OEN6_IN | GP2OEN_OEN7_IN; + + // Enable the pull-up as we are powering down the radion + GP2PUL_PUL4_BBA = 0x1; + + // Configure the SPI Interface to the Radio and flush it + pADI_SPI0->SPIDIV = ((SYSTEM_UCLK/RADIO_SPI_CLK_FREQ)/2)-0x1; + pADI_SPI0->SPICON = SPICON_MASEN | // Master mode + SPICON_TIM | // Interrupt on transmit + SPICON_TFLUSH | // Flush FIFO + SPICON_RFLUSH | // Flush FIFO + SPICON_ENABLE; + pADI_SPI0->SPICON = SPICON_MASEN | // Master mode + SPICON_TIM | // Interrupt on transmit + SPICON_ENABLE; + + // Initialise the chip select line to starting position + RADIO_CSN_DEASSERT; + + // Power it down + Response = RadioSendCommandNoWait(CMD_HW_RESET); + + return Response; +} + +/** + @fn RIE_Responses RadioPowerOff(void) + @brief Shutdown the radio and place it in its lowest power sleep mode. + @pre + RadioInit() must be called before this function is called. + @return RIE_Response Error code. +**/ + +RIE_Responses RadioPowerOff(void) +{ + volatile RIE_U32 ulDelay; + RIE_Responses Response = RIE_Success; + + Response = RadioSendCommandNoWait(CMD_HW_RESET); + + // Delay for approximately 1 ms + ulDelay = 0x1000; + while (ulDelay--); + + return Response; +} + +/** + @fn RIE_Responses RadioTerminateRadioOp(void) + @brief Terminate a currently running radio RX or TX operation. + @pre RadioInit() must be called before this function is called. + @code + if (RIE_Response == RIE_Success) + RIE_Response = RadioRxPacketFixedLen(12); + // Delay for a while waiting for a packet + if (RIE_Response == RIE_Success) + { + // Abort the waiting + RIE_Response = RadioTerminateRadioOp(); + } + @endcode + @return RIE_Responses Error code +**/ +RIE_Responses RadioTerminateRadioOp (void) +{ + RIE_Responses Response = RIE_Success; + + Response = RadioToOnMode(); + + return Response; +} + +/** + @fn RIE_Responses RadioSetFrequency(RIE_U32 Frequency) + @brief Set frequency for radio communications + @param Frequency :{431000000-928000000} + - This must be within the available bands of the radio: + - 431000000Hz to 464000000Hz and + - 862000000Hz to 928000000Hz. + @pre RadioInit() must be called before this function is called. + @code + if (RIE_Response == RIE_Success) + RIE_Response = RadioSetFrequency(915000000); + @endcode + @return RIE_Responses Error code +**/ +RIE_Responses RadioSetFrequency(RIE_U32 Frequency) +{ + RIE_Responses Response = RIE_Success; + RIE_U32 EncodedFrequency; + + bRadioConfigurationChanged = RIE_TRUE; + + EncodedFrequency = (RIE_U32)(Frequency * FREQ_CNVRT_VAL); + RadioConfiguration.channel_freq_0_r = (EncodedFrequency >> 0) & 0xFF; + RadioConfiguration.channel_freq_1_r = (EncodedFrequency >> 8) & 0xFF; + RadioConfiguration.channel_freq_2_r = (EncodedFrequency >> 16)& 0xFF; + if (Frequency >= 862000000) + { + RadioConfiguration.image_reject_cal_amplitude_r = 0x07; + RadioConfiguration.image_reject_cal_phase_r = 0x16; + } + else + { + RadioConfiguration.image_reject_cal_amplitude_r = 0x03; + RadioConfiguration.image_reject_cal_phase_r = 0x08; + } + return Response; +} + +/** + @fn RIE_Responses RadioSetModulationType(RIE_ModulationTypes ModulationType) + @brief Set the Radio Transmitter Modulation Type. Can be FSK_Modulation or GFSK_Modulation. + @param ModulationType :{DR_1_0kbps_Dev10_0kHz , DR_38_4kbps_Dev20kHz ,DR_300_0kbps_Dev75_0kHz } + - DR_1_0kbps_Dev10_0kHz Base configuration of 1 kbps datarate, 10.0 kHz frequency deviation. + - DR_38_4kbps_Dev20kHz Base configuration of 38.4 kbps datarate, 20 kHz frequency deviation. + - DR_300_0kbps_Dev75_0kHz Base configuration of 300 kbps datarate, 75 kHz frequency deviation. + @pre RadioInit() must be called before this function is called. + @code + Response = RadioSetModulationType(GFSK_Modulation); + @endcode + @note FSK_Modulation is used by default. + @return RIE_Responses Error code +**/ +RIE_Responses RadioSetModulationType(RIE_ModulationTypes ModulationType) +{ + RIE_Responses Response = RIE_Success; + RIE_U8 ucNewCode; + RIE_U8 ucNewRegVal = RadioConfiguration.radio_cfg_9_r; + + switch (ModulationType) + { + case FSK_Modulation: + ucNewCode = radio_cfg_9_mod_scheme_2_level_FSK; + break; + case GFSK_Modulation: + ucNewCode = radio_cfg_9_mod_scheme_2_level_GFSK; + break; + default: + Response = RIE_UnsupportedRadioConfig; + break; + } + if(Response == RIE_Success) + { + ucNewRegVal = MSKSET_VAL(RadioConfiguration.radio_cfg_9_r, + radio_cfg_9_mod_scheme_numbits, + radio_cfg_9_mod_scheme_offset, + ucNewCode); + if (ucNewRegVal != RadioConfiguration.radio_cfg_9_r ) + { + bRadioConfigurationChanged = RIE_TRUE; + RadioConfiguration.radio_cfg_9_r = ucNewRegVal; + } + + } + return Response; +} + +/** + @fn RIE_Responses RadioPayldManchesterEncode(RIE_BOOL bEnable) + @brief Enable or Disable Manchester Encoding of payload data. + + Manchester encoding can be used to ensure a dc-free (zero mean) + transmission. + + A Binary 0 is mapped to 10, and a Binary 1 is mapped to 01. + + Manchester encoding and decoding are applied to the payload data + and the CRC. + + @param bEnable :{RIE_FALSE,RIE_TRUE} + - RIE_TRUE if Manchester Encoding is to be enabled. + - RIE_FALSE if disabled. + + @pre RadioInit() must be called before this function is called. + @code + Response = RadioPayldManchesterEncode(RIE_TRUE); + + @endcode + @note Manchester Encoding is disabled by default. + @return RIE_Responses Error code +**/ +RIE_Responses RadioPayldManchesterEncode(RIE_BOOL bEnable) +{ + RIE_Responses Response = RIE_Success; + RIE_U8 ucNewRegVal = RadioConfiguration.symbol_mode_r; + + switch (bEnable) + { + case RIE_FALSE: + ucNewRegVal &= ~symbol_mode_manchester_enc_enabled; + break; + case RIE_TRUE: + ucNewRegVal |= symbol_mode_manchester_enc_enabled; + break; + default: + Response = RIE_UnsupportedRadioConfig; + break; + } + if(Response == RIE_Success) + { + if (ucNewRegVal != RadioConfiguration.symbol_mode_r ) + { + bRadioConfigurationChanged = RIE_TRUE; + RadioConfiguration.symbol_mode_r = ucNewRegVal; + } + } + return Response; +} +/** + @fn RIE_Responses RadioPayldDataWhitening(RIE_BOOL bEnable) + @brief Enable or Disable Data Whitening of payload data. + + Data whitening can be employed to avoid long runs of 1s or 0s + in the transmitted data stream. + + This ensures sufficient bit transitions in the packet, which + aids in receiver clock and data recovery because the encoding + breaks up long runs of 1s or 0s in the transmit packet. + + The data, excluding the preamble and sync word, is automatically + whitened before transmission by XORing the data with an 8-bit + pseudorandom sequence. + + At the receiver, the data is XORed with the same pseudorandom + sequence, thereby reversing the whitening. + + The linear feedback shift register polynomial used is x7 + x1 + 1. + + @param bEnable :{RIE_FALSE, RIE_TRUE} + - RIE_TRUE if Manchester Encoding is to be enabled. + - RIE_FALSE if disabled. + + @pre RadioInit() must be called before this function is called. + @code + Response = RadioPayldDataWhitening(RIE_TRUE); + + @endcode + @note Data Whitening is disabled by default. + @return RIE_Responses Error code +**/ +RIE_Responses RadioPayldDataWhitening(RIE_BOOL bEnable) +{ + RIE_Responses Response = RIE_Success; + RIE_U8 ucNewRegVal = RadioConfiguration.symbol_mode_r; + + switch (bEnable) + { + case RIE_FALSE: + ucNewRegVal &= ~symbol_mode_data_whitening_enabled; + break; + case RIE_TRUE: + ucNewRegVal |= symbol_mode_data_whitening_enabled; + break; + default: + Response = RIE_UnsupportedRadioConfig; + break; + } + if(Response == RIE_Success) + { + if (ucNewRegVal != RadioConfiguration.symbol_mode_r ) + { + bRadioConfigurationChanged = RIE_TRUE; + RadioConfiguration.symbol_mode_r = ucNewRegVal; + } + } + return Response; +} + +/** + @fn RIE_Responses RadioTxPacketFixedLen(RIE_U8 Len, RIE_U8 *pData) + @brief Transmit a fixed length packet. + @param Len :{1-240} Length of packet to be transmitted. + @param pData :{} Data bytes to be transmitted. + @pre RadioInit() must be called before this function is called. + @code + if (RIE_Response == RIE_Success) + RIE_Response = RadioTxSetPA(DifferentialPA,PowerLevel15); + if (RIE_Response == RIE_Success) + RIE_Response = RadioTxPacketFixedLen(12, "HELLO WORLD"); + while (!RadioTxPacketComplete()); + @endcode + @return RIE_Responses Error code +**/ +RIE_Responses RadioTxPacketFixedLen(RIE_U8 Len, RIE_U8 *pData) +{ + RIE_Responses Response = RIE_Success; + + bPacketTx = RIE_FALSE; + if (Len > PACKETRAM_LEN) + Response = RIE_InvalidParamter; + if (Response == RIE_Success) + Response = RadioToOnMode(); + if (Response == RIE_Success) + Response = RadioMMapWrite(PACKETRAM_START, Len, pData); + if (Response == RIE_Success) + { + RadioConfiguration.packet_length_max_r = Len; + RadioConfiguration.packet_length_control_r |= packet_length_control_packet_len_fixed; + } + if(Response == RIE_Success) + Response = RadioCommitRadioConfig(); + if (Response == RIE_Success) + Response = RadioToOnMode(); + if (Response == RIE_Success) + Response = RadioSendCommandWait(CMD_PHY_TX); + + return Response; +} + +/** + @fn RIE_Responses RadioTxPacketVariableLen(RIE_U8 Len, RIE_U8 *pData) + @brief Transmit a Variable length packet. + @param Len :{1-240} Length of packet to be transmitted. + @param pData :{} Data bytes to be transmitted. + @pre RadioInit() must be called before this function is called. + @code + if (RIE_Response == RIE_Success) + RIE_Response = RadioTxSetPA(DifferentialPA,PowerLevel15); + if (RIE_Response == RIE_Success) + RIE_Response = RadioTxPacketVariableLen(12, "HELLO WORLD"); + while (!RadioTxPacketComplete()); + @endcode + @return RIE_Responses Error code +**/ +RIE_Responses RadioTxPacketVariableLen(RIE_U8 Len, RIE_U8 *pData) +{ + RIE_Responses Response = RIE_Success; + + bPacketTx = RIE_FALSE; + + Len += 0x1; + if (Len > PACKETRAM_LEN) + Response = RIE_InvalidParamter; + if (Response == RIE_Success) + Response = RadioToOnMode(); + if (Response == RIE_Success) + Response = RadioMMapWrite(PACKETRAM_START, 0x1, &Len); + if (Response == RIE_Success) + Response = RadioMMapWrite(PACKETRAM_START+0x1, Len-1, pData); + if (Response == RIE_Success) + { + RadioConfiguration.packet_length_max_r = PACKETRAM_LEN; + RadioConfiguration.packet_length_control_r &= ~packet_length_control_packet_len_fixed; + } + if(Response == RIE_Success) + Response = RadioCommitRadioConfig(); + if (Response == RIE_Success) + Response = RadioToOnMode(); + if (Response == RIE_Success) + Response = RadioSendCommandWait(CMD_PHY_TX); + + return Response; +} + + +/** + @fn RIE_BOOL RadioTxPacketComplete(void) + @brief Checks if a packet has finished transmitting + @pre RadioInit() must be called before this function is called. + @pre RadioRxPacketFixedLen() or equivalent should be called first. + @code + if (RIE_Response == RIE_Success) + RIE_Response = RadioTxSetPA(DifferentialPA,PowerLevel15); + if (RIE_Response == RIE_Success) + RIE_Response = RadioTxPacketFixedLen(12, "HELLO WORLD"); + while (!RadioTxPacketComplete()); + @endcode + @return RIE_BOOL RIE_TRUE if packet has finished transmitting, else RIE_FALSE +**/ +RIE_BOOL RadioTxPacketComplete (void) +{ + return bPacketTx; +} + +/** + @fn RIE_Responses RadioTxSetPA(RIE_PATypes PAType,RIE_PAPowerLevel Power) + @brief Set PA Type and the Transmit Power Level for Radio Transmission. + @param PAType :{DifferentialPA, SingleEndedPA} Select Single Ended or Differential PA Type + @param Power :{PowerLevel0 ,PowerLevel1 ,PowerLevel2 ,PowerLevel3, + PowerLevel4 ,PowerLevel5 ,PowerLevel6 ,PowerLevel7, + PowerLevel8 ,PowerLevel9 ,PowerLevel10,PowerLevel11, + PowerLevel12,PowerLevel13,PowerLevel14,PowerLevel15} + @pre RadioInit() must be called before this function is called. + @code + Response = RadioTxSetPA(SingleEndedPA,PowerLevel8); + @endcode + @note Differential PA is enabled by default. + @note Max TX Power is used by default. + @return RIE_Responses Error code +**/ +RIE_Responses RadioTxSetPA(RIE_PATypes PAType,RIE_PAPowerLevel Power) +{ + RIE_Responses Response = RIE_Success; + RIE_U8 ucNewRegVal = 0x0; + unsigned long pa_level_mcr,pa_ramp, codes_per_bit,min_codes_per_bit; + + switch (PAType) + { + case DifferentialPA: + ucNewRegVal |= radio_cfg_8_pa_single_diff_sel_differential; + break; + case SingleEndedPA: + ucNewRegVal |= radio_cfg_8_pa_single_diff_sel_single_ended; + break; + default: + Response = RIE_UnsupportedRadioConfig; + break; + } + if(Response == RIE_Success) + { + switch (Power) + { + case PowerLevel0 : + case PowerLevel1 : + case PowerLevel2 : + case PowerLevel3 : + case PowerLevel4 : + case PowerLevel5 : + case PowerLevel6 : + case PowerLevel7 : + case PowerLevel8 : + case PowerLevel9 : + case PowerLevel10: + case PowerLevel11: + case PowerLevel12: + case PowerLevel13: + case PowerLevel14: + case PowerLevel15: + ucNewRegVal |= ((RIE_U8)Power << radio_cfg_8_pa_power_offset); + // Calculate the minimum allowable codes per bit + pa_level_mcr = (((RIE_U8)Power)* 4) + 0x3; + min_codes_per_bit = (pa_level_mcr * 2500)/(DataRate/100); + pa_ramp = 0x1; + codes_per_bit = 256; + while (codes_per_bit > min_codes_per_bit) + { + pa_ramp++; + codes_per_bit = 512 >> pa_ramp; + if (pa_ramp >= 7) + break; // This is the maximum + } + ucNewRegVal |= ((RIE_U8)pa_ramp << radio_cfg_8_pa_ramp_offset); + break; + default: + Response = RIE_UnsupportedRadioConfig; + break; + } + } + + if(Response == RIE_Success) + { + if (ucNewRegVal != RadioConfiguration.radio_cfg_8_r ) + { + bRadioConfigurationChanged = RIE_TRUE; + RadioConfiguration.radio_cfg_8_r = ucNewRegVal; + } + } + return Response; +} +/** + @fn RIE_Responses RadioTxCarrier(void) + @brief Transmit a carrier tone + using the current radio configuration. + @pre RadioInit() must be called before this function is called. + @code + Response = RadioTxCarrier(); + @endcode + @note Terminate this mode by calling RadioTerminateRadioOp(); + @return RIE_Responses Error code +**/ +RIE_Responses RadioTxCarrier (void) +{ + RIE_Responses Response = RIE_Success; + RIE_U8 ParamTX = PARAM_TX_CARRIER_FOREVER; + + if(Response == RIE_Success) + Response = RadioCommitRadioConfig(); + bTestModeEnabled = RIE_TRUE; + if (Response == RIE_Success) + Response = RadioToOnMode(); + // Mode needs to be set, before entry to PHY_TX + if (Response == RIE_Success) + Response = RadioMMapWrite(PR_var_tx_mode_ADR,sizeof(ParamTX),&ParamTX); + if (Response == RIE_Success) + Response = RadioSendCommandWait(CMD_PHY_TX); + return Response; +} +/** + @fn RIE_Responses RadioTxPreamble(void) + @brief Transmit a pre-amble (alternating ones and zeros) + using the current radio configuration. + @pre RadioInit() must be called before this function is called. + @code + Response = RadioTxPreamble(); + @endcode + @note Terminate this mode by calling RadioTerminateRadioOp(); + @return RIE_Responses Error code +**/ +RIE_Responses RadioTxPreamble (void) +{ + RIE_Responses Response = RIE_Success; + RIE_U8 ParamTX = PARAM_TX_PREAMBLE_FOREVER; + + if(Response == RIE_Success) + Response = RadioCommitRadioConfig(); + if (Response == RIE_Success) + Response = RadioToOnMode(); + bTestModeEnabled = RIE_TRUE; + // Mode needs to be set, before entry to PHY_TX + if (Response == RIE_Success) + Response = RadioMMapWrite(PR_var_tx_mode_ADR,sizeof(ParamTX),&ParamTX); + if (Response == RIE_Success) + Response = RadioSendCommandWait(CMD_PHY_TX); + return Response; +} + +/** + @fn RIE_Responses RadioRxPacketFixedLen(RIE_U8 Len) + @brief Enter receive mode and wait for a packet to be received. + + Radio will stay in Receive Mode until + 1) A packet is received. + 2) User manually exits Receive Mode with a call to RadioTerminateRadioOp() + + @param Len :{1-240} Fixed Length of packet to be received. + @pre RadioInit() must be called before this function is called. + @return RIE_Responses Error code +**/ +RIE_Responses RadioRxPacketFixedLen(RIE_U8 Len) +{ + RIE_Responses Response = RIE_Success; + + bPacketRx = RIE_FALSE; + if (Len > PACKETRAM_LEN) + Response = RIE_InvalidParamter; + + if (Response == RIE_Success) + { + RadioConfiguration.packet_length_max_r = Len; + RadioConfiguration.packet_length_control_r |= packet_length_control_packet_len_fixed; + } + if(Response == RIE_Success) + Response = RadioCommitRadioConfig(); + if (Response == RIE_Success) + Response = RadioToOnMode(); + if (Response == RIE_Success) + Response = RadioSendCommandWait(CMD_PHY_RX); + return Response; +} + +/** + @fn RIE_Responses RadioRxPacketVariableLen(void) + @brief Enter receive mode and wait for a packet to be received. + + Radio will stay in Receive Mode until + 1) A packet is received. + 2) User manually exits Receive Mode with a call to RadioTerminateRadioOp() + + @pre RadioInit() must be called before this function is called. + @return RIE_Responses Error code +**/ +RIE_Responses RadioRxPacketVariableLen(void) +{ + RIE_Responses Response = RIE_Success; + + bPacketRx = RIE_FALSE; + + if (Response == RIE_Success) + { + RadioConfiguration.packet_length_max_r = PACKETRAM_LEN; + RadioConfiguration.packet_length_control_r &= ~packet_length_control_packet_len_fixed; + } + if(Response == RIE_Success) + Response = RadioCommitRadioConfig(); + if (Response == RIE_Success) + Response = RadioToOnMode(); + if (Response == RIE_Success) + Response = RadioSendCommandWait(CMD_PHY_RX); + return Response; +} + +/** + @fn RIE_BOOL RadioRxPacketAvailable(void) + @brief Checks if a packet has been received. + @pre RadioInit() must be called before this function is called. + @pre RadioRxPacketFixedLen() or equivalent should be called first. + @code + if (RIE_Response == RIE_Success) + RIE_Response = RadioRxPacketFixedLen(12); + if (RIE_Response == RIE_Success) + { + while (!RadioRxPacketAvailable()); + } + if (RIE_Response == RIE_Success) + { + unsigned char Buffer[0x20]; + RIE_U8 PktLen; + RIE_S8 RSSI; + RIE_Response = RadioRxPacketRead(sizeof(Buffer),&PktLen,Buffer,&RSSI); + } + @endcode + @return RIE_BOOL RIE_TRUE if packet received, else RIE_FALSE +**/ +RIE_BOOL RadioRxPacketAvailable(void) +{ + return bPacketRx; + +} + +/** + @fn RIE_Responses RadioRxPacketRead(RIE_U8 BufferLen,RIE_U8 *pPktLen,RIE_U8 *pData,RIE_S8 *pRSSIdBm) + @brief Read the packet that was received by the radio. + @param BufferLen :{1-240} Size of passed in buffer + @param pPktLen :{1-240} Storage for size of actual received packet + @param pData :{} Received Packet will be stored here. + @param pRSSIdBm :{} RSSI of received packet in dBm. + @pre RadioInit() must be called before this function is called. + @pre RadioRxPacketFixedLen() or equivalent should be called first. + @code + if (RIE_Response == RIE_Success) + RIE_Response = RadioRxPacketFixedLen(12); + if (RIE_Response == RIE_Success) + { + while (!RadioRxPacketAvailable()); + } + if (RIE_Response == RIE_Success) + { + unsigned char Buffer[0x20]; + RIE_U8 PktLen; + RIE_S8 RSSI; + RIE_Response = RadioRxPacketRead(sizeof(Buffer),&PktLen,Buffer,&RSSI); + } + @endcode + @note Check for the presence of a packet by calling RadioRxPacketAvailable(); + @return RIE_Responses Error code +**/ +RIE_Responses RadioRxPacketRead(RIE_U8 BufferLen,RIE_U8 *pPktLen,RIE_U8 *pData,RIE_S8 *pRSSIdBm) +{ + RIE_Responses Response = RIE_Success; + + if (RadioRxPacketAvailable()) + { + RIE_U8 RdLen; + if(RadioConfiguration.packet_length_control_r & packet_length_control_packet_len_fixed) + { + if (pPktLen) + *pPktLen = RadioConfiguration.packet_length_max_r; + RdLen = RadioConfiguration.packet_length_max_r; + if (RdLen > BufferLen) + RdLen = BufferLen; + if (Response == RIE_Success) + Response = RadioMMapRead(PACKETRAM_START,RdLen, pData); + } + else + { + if (Response == RIE_Success) + Response = RadioMMapRead(PACKETRAM_START,0x1, &RdLen); + RdLen -= 0x1; + if (pPktLen) + *pPktLen = RdLen; + if (RdLen > BufferLen) + RdLen = BufferLen; + if (Response == RIE_Success) + Response = RadioMMapRead(PACKETRAM_START+0x1,RdLen, pData); + } + + if (pRSSIdBm) + { + if (Response == RIE_Success) + Response = RadioMMapRead(MCR_rssi_readback_Adr,0x1, (RIE_U8 *)pRSSIdBm); + + *pRSSIdBm -= 107; // Convert to dBm + } + + } + else + { + if (pPktLen) + *pPktLen = 0x0; + } + + return Response; +} + +/** + @fn RIE_Responses RadioRxBERTestMode(void) + @brief Enter receiver Bit Error Rate (BER) test mode where the + clock and data appear on GPIO pins. + Clock on P0.6 and Data on P2.6 + @pre RadioInit() must be called before this function is called. + @code + Response = RadioRxBERTestMode(); + @endcode + @note Terminate this mode by calling RadioTerminateRadioOp(); + @return RIE_Responses Error code +**/ +RIE_Responses RadioRxBERTestMode(void) +{ + RIE_Responses Response = RIE_Success; + RIE_U8 Data; + // Enables internal radio signals on external pins + // but overrides some of the standard GPIO muxed + // functionality (UART?) + pADI_MISC->RFTST = 0x7E1; + + if(Response == RIE_Success) + Response = RadioCommitRadioConfig(); + + bTestModeEnabled = RIE_TRUE; + // Enable the RX signals on GPIO pins + Data = gpio_configure_sport_mode_0; + if (Response == RIE_Success) + Response = RadioMMapWrite(MCR_gpio_configure_Adr, 0x1, (RIE_U8 *)&Data); + + // disable ext_uc_clk on GP5 + Data = 0; + if (Response == RIE_Success) + Response = RadioMMapWrite(MCR_ext_uc_clk_divide_Adr, + 0x1, + (RIE_U8 *)&Data); + if (Response == RIE_Success) + Response = RadioSendCommandWait(CMD_PHY_RX); + return Response; +} + +/** + @internal Hide from Doxegen + @fn RIE_Responses RadioCommitRadioConfig(void) + @brief Configures the radio if any changes were made + since the last time. + @return RIE_Responses Error code +**/ +static RIE_Responses RadioCommitRadioConfig(void) +{ + RIE_Responses Response = RIE_Success; + + if(bTestModeEnabled) + { + RIE_U8 Data; + Data = gpio_configure_default; + if (Response == RIE_Success) + Response = RadioMMapWrite(MCR_gpio_configure_Adr, 0x1, (RIE_U8 *)&Data); + Data = 4; + if (Response == RIE_Success) + Response = RadioMMapWrite(MCR_ext_uc_clk_divide_Adr, + 0x1, + (RIE_U8 *)&Data); + + Data = PARAM_TX_NORMAL_PACKET; + if (Response == RIE_Success) + Response = RadioMMapWrite(PR_var_tx_mode_ADR,sizeof(Data),&Data); + bTestModeEnabled = RIE_FALSE; + } + if (bRadioConfigurationChanged) + { + Response = RadioConfigure(); + if(Response == RIE_Success) + bRadioConfigurationChanged = RIE_FALSE; + } + return Response; +} +/** + @fn RIE_Responses RadioReadState(RadioState *pState) + @brief Read the current state + @param pState Pointer to return storage of state + @return RIE_Responses Error code +**/ +static RIE_Responses RadioReadState(RadioState *pState) +{ + RIE_Responses Response = RIE_Success; + RIE_U8 StatusByte; + + NVIC_DisableIRQ(UHFTRX_IRQn); + RADIO_CSN_ASSERT; + if (Response == RIE_Success) + Response = RadioSPIXferByte(SPI_NOP,NULL); + if (Response == RIE_Success) + Response = RadioSPIXferByte(SPI_NOP,&StatusByte); + RADIO_CSN_DEASSERT; + NVIC_EnableIRQ (UHFTRX_IRQn); + if ((Response == RIE_Success) && pState) + *pState = (RadioState)(StatusByte & STATUS_BYTE_FW_STATE); + return Response; +} + +/** + @fn RIE_Responses RadioWaitOnState(RadioState FinalState) + @brief Wait for Final State to be reached + @param FinalState State to wait on + @return RIE_Responses Error code +**/ +static RIE_Responses RadioWaitOnState(RadioState FinalState) +{ + RIE_Responses Response = RIE_Success; + RadioState CurrState; + do + { + Response = RadioReadState(&CurrState); + } + while((Response == RIE_Success) && (CurrState != FinalState)); + return Response; +} + +/** + @fn RIE_Responses RadioWaitOnCmdLdr(void) + @brief Wait for Final State to be reached + @param FinalState State to wait on + @return RIE_Responses Error code +**/ +static RIE_Responses RadioWaitOnCmdLdr(void) +{ + RIE_Responses Response = RIE_Success; + do + { + RIE_U8 StatusByte; + NVIC_DisableIRQ(UHFTRX_IRQn); + RADIO_CSN_ASSERT; + if (Response == RIE_Success) + Response = RadioSPIXferByte(SPI_NOP,NULL); + if (Response == RIE_Success) + Response = RadioSPIXferByte(SPI_NOP,&StatusByte); + RADIO_CSN_DEASSERT; + NVIC_EnableIRQ (UHFTRX_IRQn); + if ((Response == RIE_Success)) + if(StatusByte & STATUS_BYTE_CMD_READY) + break; + } + while((Response == RIE_Success)); + return Response; +} + +/** + @internal Hide from Doxegen + @fn RIE_Responses RadioToOnMode(void) + @brief Transition to On Mode + + Handle all possible states that the radio could be in + and brings it back to PHY_ON state + @param None + @return RIE_Responses Error code +**/ +static RIE_Responses RadioToOnMode(void) +{ + RIE_Responses Response = RIE_Success; + RadioState FwState; + + if (Response == RIE_Success) + Response = RadioReadState(&FwState); + + while ((FwState != FW_ON) && (Response == RIE_Success)) + { + switch (FwState) + { + case FW_BUSY: + break; + case FW_TX: + if(Response == RIE_Success) + Response = RadioSendCommandNoWait(CMD_PHY_ON); + if (Response == RIE_Success) + Response = RadioWaitOnState (FW_ON); + break; + case FW_RX: + if(Response == RIE_Success) + Response = RadioSendCommandNoWait(CMD_PHY_ON); + if (Response == RIE_Success) + Response = RadioWaitOnState (FW_ON); + break; + default: + if(Response == RIE_Success) + Response = RadioSendCommandNoWait(CMD_PHY_ON); + if (Response == RIE_Success) + Response = RadioWaitOnState (FW_ON); + break; + } + if (Response == RIE_Success) + Response = RadioReadState(&FwState); + } + return Response; +} +/** + @internal Hide from Doxegen + @fn RIE_Responses RadioToOffMode(void) + @brief Transition to Off Mode + + Handle all possible states that the radio could be in + and bring it back to PHY_OFF state. + + @param None + @return RIE_Responses Error code +**/ +static RIE_Responses RadioToOffMode(void) +{ + RIE_Responses Response = RIE_Success; + RadioState FwState; + + if (Response == RIE_Success) + Response = RadioReadState(&FwState); + + while ((FwState != FW_OFF) && (Response == RIE_Success)) + { + switch (FwState) + { + case FW_BUSY: + break; + case FW_TX: + if(Response == RIE_Success) + Response = RadioSendCommandNoWait(CMD_PHY_ON); + if (Response == RIE_Success) + Response = RadioWaitOnState (FW_ON); + break; + case FW_RX: + if(Response == RIE_Success) + Response = RadioSendCommandNoWait(CMD_PHY_ON); + if (Response == RIE_Success) + Response = RadioWaitOnState (FW_ON); + break; + default: + if(Response == RIE_Success) + Response = RadioSendCommandNoWait(CMD_PHY_OFF); + if (Response == RIE_Success) + Response = RadioWaitOnState (FW_OFF); + break; + } + if (Response == RIE_Success) + Response = RadioReadState(&FwState); + } + return Response; +} +/** + @internal Hide from Doxegen + @fn RIE_Responses RadioSyncComms (void) + @brief Sync comms with the radio + @param None + @return RIE_Responses Error code +**/ +static RIE_Responses RadioSyncComms (void) +{ + RIE_Responses Response = RIE_Success; + if (Response == RIE_Success) + Response = RadioSendCommandWait(CMD_SYNC); + if (Response == RIE_Success) + Response = RadioWaitOnCmdLdr(); + return Response; +} +/** + @fn RIE_Responses RadioWaitForPowerUp(void) + @brief Wake Up the Part + + Assert SPI chip select which will wake up the radio if asleep + Wait for MISO line to go high indicating SPI comms now possible + + @return RIE_Responses Error code +**/ +static RIE_Responses RadioWaitForPowerUp(void) +{ + RIE_Responses Response = RIE_Success; + int i = 0x0; + RADIO_CSN_ASSERT; + while (!RADIO_MISO_IN && (i < 1000)) + i++; + if (1000 == i)// Timed out waiting for MISO high? + Response = RIE_RadioSPICommsFail; + RADIO_CSN_DEASSERT; + return Response; +} + +/** + \internal Hide from Doxegen + \fn void Ext_Int8_Handler(void) + \brief Radio Interrupt Handler +**/ +extern void aducrf101_rx_packet_hook(void); +void Ext_Int8_Handler (void) +{ + RIE_Responses Response = RIE_Success; + RIE_U8 ucInt0; + RIE_U8 ucInt1; + + if (Response == RIE_Success) + Response = RadioMMapRead(MCR_interrupt_source_0_Adr,0x1, &ucInt0); + if (Response == RIE_Success) + Response = RadioMMapRead(MCR_interrupt_source_1_Adr,0x1,&ucInt1); + if (ucInt0 & interrupt_mask_0_interrupt_tx_eof) + bPacketTx = RIE_TRUE; + if (ucInt0 & interrupt_mask_0_interrupt_crc_correct) { + bPacketRx = RIE_TRUE; + aducrf101_rx_packet_hook(); + } + // Clear all the interrupts that we have just handleed + if (Response == RIE_Success) + Response = RadioMMapWrite(MCR_interrupt_source_0_Adr,0x1, &ucInt0); + if (Response == RIE_Success) + Response = RadioMMapWrite(MCR_interrupt_source_1_Adr,0x1,&ucInt1); + // Clear the interrupt + pADI_INTERRUPT->EICLR = EICLR_IRQ8; +} +/** + \internal Hide from Doxegen + \fn void RadioSPIXferByte(RIE_U8 ucByte,RIE_U8 *pData) + \brief Transfer a byte via SPI to the radio and optionally return + received byte. + Chip Select is manually controlled elsewhere. + \param ucByte Command or data byte to be transferred. + \param pData NULL, or storage for response + \return RIE_Responses Error code +**/ +static RIE_Responses RadioSPIXferByte(RIE_U8 ucByte,RIE_U8 *pData) +{ + RIE_Responses Response = RIE_Success; + + SEND_SPI(ucByte); // Send byte + WAIT_SPI_RX; // wait for data received status bit + if(pData) + *pData = READ_SPI; + else + (void)READ_SPI; + return Response; +} +/** + \internal Hide from Doxegen + \fn RIE_Responses RadioSendCommandBytes(RIE_U8 *pCmdBytes,RIE_U8 NumBytes) + \brief Send a complete command to the radio. + + It is neccessary to disable the radio interrupt when doing this + as a command in progress must finish before a radio interrupt + can be handled. + + \param pCmdBytes Pointer to a number of bytes to be transferred. + \param NumBytes Number of bytes to transfer + + \return RIE_Responses Error code +**/ +static RIE_Responses RadioSendCommandBytes(RIE_U8 *pCmdBytes,RIE_U8 NumBytes) +{ + RIE_Responses Response = RIE_Success; + + NVIC_DisableIRQ(UHFTRX_IRQn); + RADIO_CSN_ASSERT; + while ((NumBytes--) && (Response == RIE_Success)) + Response = RadioSPIXferByte(*(pCmdBytes++),NULL); // Send Command + RADIO_CSN_DEASSERT; // De-assert SPI chip select + NVIC_EnableIRQ (UHFTRX_IRQn); + + return Response; +} +/** + \internal Hide from Doxegen + \fn RIE_Responses RadioSendCommandNoWait (Radio_CmdCodes CmdCode ) + \brief Send a single byte command to the radio. + \param CmdCode Command code to be sent + \return RIE_Responses Error code +**/ +static RIE_Responses RadioSendCommandNoWait (Radio_CmdCodes CmdCode ) +{ + RIE_U8 Command = (RIE_U8)CmdCode; + return RadioSendCommandBytes(&Command,0x1); +} +/** + \internal Hide from Doxegen + \fn RIE_Responses RadioSendCommandWait (Radio_CmdCodes CmdCode ) + \brief Send a single byte command to the radio. + \param CmdCode Command code to be sent + \return RIE_Responses Error code +**/ +static RIE_Responses RadioSendCommandWait (Radio_CmdCodes CmdCode ) +{ + RIE_Responses Response = RIE_Success; + RIE_U8 Command = (RIE_U8)CmdCode; + + if (Response == RIE_Success) + Response = RadioWaitOnCmdLdr(); + if (Response == RIE_Success) + Response = RadioSendCommandBytes(&Command,0x1); + return Response; +} +/** + \fn RIE_Responses RadioMMapRead(RIE_U32 ulAdr, RIE_U32 ulLen, RIE_U8 *pData) + \brief Read bytes from specified memory map address + \param ulAdr Address to read at. + \param ulLen Length of data to read. + \param pData Pointer to location to stored read data. + \return RIE_Responses Error code +**/ +static RIE_Responses RadioMMapRead(RIE_U32 ulAdr, RIE_U32 ulLen, RIE_U8 *pData) +{ + RIE_Responses Response = RIE_Success; + + NVIC_DisableIRQ(UHFTRX_IRQn); + RADIO_CSN_ASSERT; + + if(Response == RIE_Success) // Send first byte (SPI_MEMR_RD + Bytes) + Response = RadioSPIXferByte(SPI_MEM_RD | ((ulAdr & 0x700) >> 8),NULL); + if(Response == RIE_Success)// Send Second byte remainder of address + Response = RadioSPIXferByte((RIE_U8)(ulAdr & 0xFF),NULL); + if(Response == RIE_Success) + Response = RadioSPIXferByte((RIE_U8)SPI_NOP,NULL); + while(ulLen-- && (Response == RIE_Success)) + Response = RadioSPIXferByte(SPI_NOP,pData++); + RADIO_CSN_DEASSERT; + NVIC_EnableIRQ (UHFTRX_IRQn); + + return Response; +} +/** + \fn RIE_Responses RadioMMapWrite(RIE_U32 ulAdr, RIE_U32 ulLen, RIE_U8 *pData) + \brief Read bytes from specified memory map address + \param ulAdr Address to read at. + \param ulLen Length of data to read. + \param pData Pointer to location of data to write. + \return RIE_Responses Error code +**/ +static RIE_Responses RadioMMapWrite(RIE_U32 ulAdr,RIE_U32 ulLen,RIE_U8 * pData) +{ + RIE_Responses Response = RIE_Success; + + NVIC_DisableIRQ(UHFTRX_IRQn); + RADIO_CSN_ASSERT; + if(Response == RIE_Success) // Send first byte (SPI_MEMR_WR + Bytes) + Response = RadioSPIXferByte(SPI_MEM_WR | ((ulAdr & 0x700) >> 8),NULL); + if(Response == RIE_Success) // Send Second byte remainder of addrress + Response = RadioSPIXferByte((RIE_U8)(ulAdr & 0xFF),NULL); + while(ulLen-- && (Response == RIE_Success)) + Response = RadioSPIXferByte(*(pData++),NULL); + RADIO_CSN_DEASSERT; + NVIC_EnableIRQ (UHFTRX_IRQn); + + return Response; +} + +/** + \internal Hide from Doxegen + \fn void SetRadioConfiguration(void) + \brief Create a default radio configuration that all base configurations + are derived from. + + \return RIE_Responses Error code +**/ +static RIE_Responses SetRadioConfiguration(RIE_BaseConfigs BaseConfig) +{ + RIE_Responses Response = RIE_Success; + + bRadioConfigurationChanged = RIE_TRUE; + switch (BaseConfig) + { + case DR_1_0kbps_Dev10_0kHz: + memcpy((void *)&RadioConfiguration, + (void *)DR_1_0kbps_Dev10_0kHz_Configuration, + sizeof(TyRadioConfiguration)); + DataRate = 1000; + break; + case DR_38_4kbps_Dev20kHz: + memcpy((void *)&RadioConfiguration, + (void *)DR_38_4kbps_Dev20kHz_Configuration, + sizeof(TyRadioConfiguration)); + DataRate = 38400; + break; + case DR_300_0kbps_Dev75_0kHz: + memcpy((void *)&RadioConfiguration, + (void *)DR_300_0kbps_Dev75_0kHz_Configuration, + sizeof(TyRadioConfiguration)); + DataRate = 300000; + break; + default: + Response = RIE_UnsupportedRadioConfig; + break; + } + return Response; +} +/** + @internal Hide from Doxegen + @fn RIE_Responses RadioConfigure (void) + @brief Configure the Radio as per the current configuration + @return RIE_Responses Error code +**/ +RIE_Responses RadioConfigure (void) +{ + RIE_Responses Response = RIE_Success; + if(Response == RIE_Success) + Response = RadioToOffMode(); + if(Response == RIE_Success) // Write the configuration to the radio memory + Response = RadioMMapWrite(BBRAM_START, + sizeof(TyRadioConfiguration), + (RIE_U8 *)&RadioConfiguration); + if(Response == RIE_Success) // Apply that configuration to the radio + Response = RadioSendCommandWait(CMD_CONFIG_DEV); + if(Response == RIE_Success) + Response = RadioToOnMode(); + return Response; +} + + +/** + @fn RIE_Responses RadioRadioGetRSSI (RIE_S8 *pRSSIdBm) + @brief Return a Received Signal Strength Indicator value + @param pRSSIdBm :{} detected RSSI in dBm. + @pre RadioInit() must be called before this function is called. + @code + RIE_S8 RSSIdBm; + if (RIE_Response == RIE_Success) + RIE_Response = RadioRadioGetRSSI(&RSSIdBm); + @endcode + @return RIE_Responses Error code +**/ +RIE_Responses RadioRadioGetRSSI (RIE_S8 *pRSSIdBm) +{ + RIE_Responses Response = RIE_Success; + + if(Response == RIE_Success) + Response = RadioCommitRadioConfig(); + if (Response == RIE_Success) + Response = RadioToOnMode(); + if (Response == RIE_Success) + Response = RadioSendCommandWait(CMD_GET_RSSI); + if (Response == RIE_Success) + Response = RadioSyncComms(); // + if (pRSSIdBm) + { + if (Response == RIE_Success) + Response = RadioMMapRead(MCR_rssi_readback_Adr,0x1, (RIE_U8 *)pRSSIdBm); + *pRSSIdBm -= 107; // Convert to dBm + } + return Response; +} + +/** + @fn RIE_Responses RadioTxSetPower(RIE_PAPowerLevel Power) + @brief Set the Transmit Power Level for Radio Transmission. + @param Power :{PowerLevel0 ,PowerLevel1 ,PowerLevel2 ,PowerLevel3, + PowerLevel4 ,PowerLevel5 ,PowerLevel6 ,PowerLevel7, + PowerLevel8 ,PowerLevel9 ,PowerLevel10,PowerLevel11, + PowerLevel12,PowerLevel13,PowerLevel14,PowerLevel15} + @pre RadioInit() must be called before this function is called. + @code + Response = RadioTxSetPower(PowerLevel8); + @endcode + @note Max TX Power is used by default. + @return RIE_Responses Error code +*/ +RIE_Responses RadioTxSetPower (RIE_PAPowerLevel Power) +{ + RIE_Responses Response = RIE_Success; + RIE_U8 ucNewRegVal = RadioConfiguration.radio_cfg_8_r; + unsigned long pa_level_mcr,pa_ramp, codes_per_bit,min_codes_per_bit; + + if (RadioConfiguration.radio_cfg_8_r & radio_cfg_8_pa_single_diff_sel_differential) + ucNewRegVal = radio_cfg_8_pa_single_diff_sel_differential; + else + ucNewRegVal = radio_cfg_8_pa_single_diff_sel_single_ended; + + if(Response == RIE_Success) + { + switch (Power) + { + case PowerLevel0 : + case PowerLevel1 : + case PowerLevel2 : + case PowerLevel3 : + case PowerLevel4 : + case PowerLevel5 : + case PowerLevel6 : + case PowerLevel7 : + case PowerLevel8 : + case PowerLevel9 : + case PowerLevel10: + case PowerLevel11: + case PowerLevel12: + case PowerLevel13: + case PowerLevel14: + case PowerLevel15: + ucNewRegVal |= ((RIE_U8)Power << radio_cfg_8_pa_power_offset); + // Calculate the minimum allowable codes per bit + pa_level_mcr = (((RIE_U8)Power)* 4) + 0x3; + min_codes_per_bit = (pa_level_mcr * 2500)/(DataRate/100); + pa_ramp = 0x1; + codes_per_bit = 256; + while (codes_per_bit > min_codes_per_bit) + { + pa_ramp++; + codes_per_bit = 512 >> pa_ramp; + if (pa_ramp >= 7) + break; // This is the maximum + } + ucNewRegVal |= ((RIE_U8)pa_ramp << radio_cfg_8_pa_ramp_offset); + break; + default: + Response = RIE_UnsupportedRadioConfig; + break; + } + } + + if(Response == RIE_Success) + { + if (ucNewRegVal != RadioConfiguration.radio_cfg_8_r ) + { + // Write directly to the MCR in this case and avoid a reconfigure + if (Response == RIE_Success) + Response = RadioMMapWrite(MCR_pa_level_mcr_Adr, 0x1, (RIE_U8 *)&ucNewRegVal); + RadioConfiguration.radio_cfg_8_r = ucNewRegVal; + } + } + return Response; +} + diff --git a/cpu/arm/aducrf101/Common/radioeng.h b/cpu/arm/aducrf101/Common/radioeng.h new file mode 100644 index 000000000..22f68cc63 --- /dev/null +++ b/cpu/arm/aducrf101/Common/radioeng.h @@ -0,0 +1,174 @@ +/** + * Copyright (c) 2014, Analog Devices, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** +@file radioeng.h +@brief Radio Interface Engine Functions +@version v1.0 +@author PAD CSE group, Analog Devices Inc +@date May 08th 2013 +**/ + +#define RIE_U32 unsigned long +#define RIE_U16 unsigned short int +#define RIE_U8 unsigned char +#define RIE_S8 signed char + +/*! \enum RIE_BaseConfigs + * Variables of this type are used to define the Base Configuration + */ +/*! \var RIE_BaseConfigs DR_1_0kbps_Dev10_0kHz + * Base configuration of 1 kbps datarate, 10.0 kHz frequency deviation. + Use for achieving longer distances. + */ +/*! \var RIE_BaseConfigs DR_38_4kbps_Dev20kHz + * Base configuration of 38.4 kbps datarate, 20 kHz frequency deviation. + Use as a compromise of distance and power. + */ +/*! \var RIE_BaseConfigs DR_300_0kbps_Dev75_0kHz + * Base configuration of 300 kbps datarate, 75 kHz frequency deviation. + Use for achieving faster transmission times hence lower power. + */ +typedef enum +{ + DR_1_0kbps_Dev10_0kHz = 0x0, + DR_38_4kbps_Dev20kHz = 0x1, + DR_300_0kbps_Dev75_0kHz = 0x2, + UnsupportedDRDev +} RIE_BaseConfigs; + +/*! \enum RIE_ModulationTypes + * Variables of this type are used to define a tx modulation type + */ +/*! \var RIE_ModulationTypes FSK_Modulation + * FSK Modulation + */ +/*! \var RIE_ModulationTypes GFSK_Modulation + * GFSK Modulation + */ +typedef enum {FSK_Modulation = 0, GFSK_Modulation = 1} RIE_ModulationTypes; + +/*! \enum RIE_PATypes + * Variables of this type are used to define a PA type + */ +/*! \var RIE_PATypes DifferentialPA + * Differential PA + */ +/*! \var RIE_PATypes SingleEndedPA + * Single Ended PA + */ +typedef enum {DifferentialPA = 0, SingleEndedPA = 1} RIE_PATypes; + + + +typedef enum {PowerLevel0 ,PowerLevel1 ,PowerLevel2 ,PowerLevel3, + PowerLevel4 ,PowerLevel5 ,PowerLevel6 ,PowerLevel7, + PowerLevel8 ,PowerLevel9 ,PowerLevel10,PowerLevel11, + PowerLevel12,PowerLevel13,PowerLevel14,PowerLevel15 + } RIE_PAPowerLevel; + + +/*! \enum RIE_BOOL + * Variables of this type are used to define a TRUE or FALSE condition + */ +/*! \var RIE_BOOL RIE_TRUE + * TRUE condition + */ +/*! \var RIE_BOOL RIE_FALSE + * FALSE condition + */ +typedef enum {RIE_FALSE = 0, RIE_TRUE = !RIE_FALSE} RIE_BOOL; + + +/*! \enum RIE_Responses + * Variables of this type are used to define the return value from functions + */ +/*! \var RIE_Responses RIE_Success + * Successful completion + */ +/*! \var RIE_Responses RIE_RadioSPICommsFail + * SPI communications with the radio failure. + */ +/*! \var RIE_Responses RIE_UnsupportedRadioConfig + * This is an unsupported radio configuration + */ +/*! \var RIE_Responses RIE_Unimplemented + * This feature has not been implemented + */ +/*! \var RIE_Responses RIE_InvalidParamter + * An invaild parameter was passed + */ +typedef enum +{ + RIE_Success = 0x0, + RIE_RadioSPICommsFail = 0x1, + RIE_UnsupportedRadioConfig = 0x2, + RIE_Unimplemented = 0x3, + RIE_InvalidParamter = 0x4, +} RIE_Responses; + +// Added in Radio Interface Engine v0.1 +RIE_Responses RadioGetAPIVersion (RIE_U32 *pVersion); +RIE_Responses RadioInit (RIE_BaseConfigs BaseConfig); +RIE_Responses RadioPowerOff (void); +RIE_Responses RadioTerminateRadioOp (void); +RIE_Responses RadioSetFrequency (RIE_U32 Frequency); +RIE_Responses RadioSetModulationType (RIE_ModulationTypes ModulationType); +RIE_Responses RadioPayldManchesterEncode(RIE_BOOL bEnable); +RIE_Responses RadioPayldDataWhitening (RIE_BOOL bEnable); +RIE_Responses RadioTxPacketFixedLen (RIE_U8 Len, RIE_U8 *pData); +RIE_BOOL RadioTxPacketComplete (void); +RIE_Responses RadioTxSetPA (RIE_PATypes PAType,RIE_PAPowerLevel Power); +RIE_Responses RadioTxCarrier (void); +RIE_Responses RadioTxPreamble (void); +RIE_Responses RadioRxPacketFixedLen (RIE_U8 Len); +RIE_BOOL RadioRxPacketAvailable (void); +RIE_Responses RadioRxPacketRead (RIE_U8 BufferLen,RIE_U8 *pPktLen,RIE_U8 *pData,RIE_S8 *pRSSIdBm); +RIE_Responses RadioRxBERTestMode (void); + +// Added in Radio Interface Engine v0.2 +RIE_Responses RadioSwitchConfig (RIE_BaseConfigs BaseConfig); +RIE_Responses RadioRadioGetRSSI (RIE_S8 *pRSSIdBm); +RIE_Responses RadioTxSetPower (RIE_PAPowerLevel Power); + +// Added in Radio Interface Engine v0.3 +RIE_Responses RadioTxPacketVariableLen (RIE_U8 Len, RIE_U8 *pData); +RIE_Responses RadioRxPacketVariableLen (void); + +// Added in Radio Interface Engine v0.5 +RIE_Responses RadioDeInit (void); + + + + + diff --git a/cpu/arm/aducrf101/Common/system_ADuCRF101.c b/cpu/arm/aducrf101/Common/system_ADuCRF101.c new file mode 100644 index 000000000..0db949554 --- /dev/null +++ b/cpu/arm/aducrf101/Common/system_ADuCRF101.c @@ -0,0 +1,179 @@ +/** + * Copyright (c) 2014, Analog Devices, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** +@file system_ADUCRF101.c +@brief CMSIS Cortex-M3 Device Peripheral Access Layer Implementation File + for the ADuCRF101 +@version v1.0 +@author PAD CSE group, Analog Devices Inc +@date January 14th 2013 +**/ + +#include +#include "ADuCRF101.h" + + +/*---------------------------------------------------------------------------- + DEFINES + *---------------------------------------------------------------------------*/ + +/* Extract the Clock Divider */ +#define __CCLK_DIV (1 << (pADI_CLKCTL->CLKCON & CLKCON_CD_MSK) ) + +/* define the clock multiplexer input frequencies */ +#define __HFOSC 16000000 +#define __LFXTAL 32768 +#define __LFOSC 32768 + +/*---------------------------------------------------------------------------- + Internal Clock Variables + *---------------------------------------------------------------------------*/ +static uint32_t uClk = 0; /* Undivided System Clock Frequency (UCLK) */ +static uint32_t uClkDiv = 0; /* Divided System Clock Frequency (UCLK_DIV) */ + +/* Frequency of the external clock source connected to P0.5 */ +static uint32_t SystemExtClock = 0; + +/*---------------------------------------------------------------------------- + Clock functions + *---------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ +/* pre-processor verification that clock mux mask and allowed values agree */ +#if ((CLKCON_CLKMUX_HFOSC \ + | CLKCON_CLKMUX_LFXTAL \ + | CLKCON_CLKMUX_LFOSC \ + | CLKCON_CLKMUX_EXTP05) \ + == CLKCON_CLKMUX_MSK) + + /* update the system core clock according the the current clock mux setting */ + switch (pADI_CLKCTL->CLKCON & CLKCON_CLKMUX_MSK ) { + + case CLKCON_CLKMUX_HFOSC: + uClk = __HFOSC; + break; + case CLKCON_CLKMUX_LFXTAL: + uClk = __LFXTAL; + break; + case CLKCON_CLKMUX_LFOSC: + uClk = __LFOSC; + break; + case CLKCON_CLKMUX_ECLKIN: + uClk = SystemExtClock; + break; + /* no need to catch default case due to pre-processor test */ + } + + /* update the divided system clock */ + uClkDiv = uClk / __CCLK_DIV; + +#else +#error "Clock mux mask and allowed value mismatch!" +#endif +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemFrequency variable. + */ +void SystemInit (void) +{ + /* reset CLKCON register */ + pADI_CLKCTL->CLKCON = CLKCON_RVAL; + + /* reset XOSCCON register */ + pADI_CLKCTL->XOSCCON = XOSCCON_RVAL; + + /* compute internal clocks */ + SystemCoreClockUpdate(); +} + +/** + * @brief Sets the system external clock frequency + * + * @param ExtClkFreq External clock frequency in Hz + * @return none + * + * Sets the clock frequency of the source connected to P0.5 clock input source + */ +void SetSystemExtClkFreq (uint32_t ExtClkFreq) +{ + SystemExtClock = ExtClkFreq; +} + +/** + * @brief Gets the system external clock frequency + * + * @return External Clock frequency + * + * Gets the clock frequency of the source connected to P0.5 clock input source + */ +uint32_t GetSystemExtClkFreq (void) +{ + return SystemExtClock; +} + + +/* set the system clock dividers */ +void SystemSetClockDivider(uint16_t div) +{ + /* critical region */ + __disable_irq(); + + /* read-modify-write without any interrupts */ + + pADI_CLKCTL->CLKCON &= ~(CLKCON_CD_MSK); /* keep everything else */ + pADI_CLKCTL->CLKCON |= div; /* set new value */ + + /* end critical region */ + __enable_irq(); + + /* refresh internal clock variables */ + SystemCoreClockUpdate(); +} + + +uint32_t SystemGetClockFrequency(void) +{ + return uClkDiv; +} + + + + diff --git a/cpu/arm/aducrf101/Common/system_ADuCRF101.h b/cpu/arm/aducrf101/Common/system_ADuCRF101.h new file mode 100644 index 000000000..c8b5c3210 --- /dev/null +++ b/cpu/arm/aducrf101/Common/system_ADuCRF101.h @@ -0,0 +1,116 @@ +/** + * Copyright (c) 2014, Analog Devices, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** +@file system_ADUCRF101.h +@brief: CMSIS Cortex-M3 Device Peripheral Access Layer Header File + for the ADuCRF101 +@version v0.2 +@author PAD CSE group, Analog Devices Inc +@date March 09th 2012 +**/ + + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup aducrf101_system + * @{ + */ + +#ifndef __SYSTEM_ADUCRF101_H__ +#define __SYSTEM_ADUCRF101_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +/** + * @brief Initialize the system + * + * @param none + * @return none + * + * Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + +/** + * @brief Update internal SystemCoreClock variable + * + * @param none + * @return none + * + * Updates the internal SystemCoreClock with current core + * Clock retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + + +/** + * @brief Sets the system external clock frequency + * + * @param ExtClkFreq External clock frequency in Hz + * @return none + * + * Sets the clock frequency of the source connected to P0.5 clock input source + */ +extern void SetSystemExtClkFreq (uint32_t ExtClkFreq); + + +/** + * @brief Gets the system external clock frequency + * + * @return External Clock frequency + * + * Gets the clock frequency of the source connected to P0.5 clock input source + */ +extern uint32_t GetSystemExtClkFreq (void); + + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_ADUCRF101_H__ */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/cpu/arm/aducrf101/Makefile.aducrf101 b/cpu/arm/aducrf101/Makefile.aducrf101 new file mode 100644 index 000000000..350e89ab8 --- /dev/null +++ b/cpu/arm/aducrf101/Makefile.aducrf101 @@ -0,0 +1,88 @@ +# -*- makefile -*- + +# Copyright (c) 2014, Analog Devices, Inc. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted (subject to the limitations in the +# disclaimer below) provided that the following conditions are met: +# +# - Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# +# - Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the +# distribution. +# +# - Neither the name of Analog Devices, Inc. nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +# GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +# HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +# BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +# OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +# IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +# Author: Jim Paris + +CONTIKI_CPU = $(CONTIKI)/cpu/arm/aducrf101 + +ifdef IAR +include $(CONTIKI_CPU)/Makefile.aducrf101.iar +else +include $(CONTIKI_CPU)/Makefile.aducrf101.gnu +endif + +ifdef SERIAL_ID + CFLAGS += -DSERIAL_ID='$(SERIAL_ID)' +endif + +ifdef __STACK_SIZE + CFLAGS += -D__STACK_SIZE=$(__STACK_SIZE) +endif + +ifdef RF_CHANNEL + CFLAGS += -DRF_CHANNEL=$(RF_CHANNEL) +endif + +# HSI internal oscillator by default +CFLAGS += -DF_CPU=16000000 + +### CPU-dependent directories and source files +CONTIKI_CPU_DIRS += ../common/CMSIS + +CONTIKI_CPU_DIRS += . +CONTIKI_SOURCEFILES += slip-arch.c +CONTIKI_SOURCEFILES += rtimer-arch.c + +CONTIKI_CPU_DIRS += dev +CONTIKI_SOURCEFILES += uart.c +CONTIKI_SOURCEFILES += clock.c +CONTIKI_SOURCEFILES += watchdog.c +CONTIKI_SOURCEFILES += radio.c + +CONTIKI_CPU_DIRS += Common +CONTIKI_SOURCEFILES += system_ADuCRF101.c +CONTIKI_SOURCEFILES += radioeng.c + +ifdef CORE +.PHONY: symbols.c symbols.h +symbols.c symbols.h: + $(NM) -C $(CORE) | grep -v @ | grep -v dll_crt0 | \ + awk -f $(CONTIKI)/tools/mknmlist > symbols.c || rm -f symbols.c +else +symbols.c symbols.h: + cp ${CONTIKI}/tools/empty-symbols.c symbols.c + cp ${CONTIKI}/tools/empty-symbols.h symbols.h +endif + +contiki-$(TARGET).a: ${addprefix $(OBJECTDIR)/,symbols.o} diff --git a/cpu/arm/aducrf101/Makefile.aducrf101.gnu b/cpu/arm/aducrf101/Makefile.aducrf101.gnu new file mode 100644 index 000000000..93de277a2 --- /dev/null +++ b/cpu/arm/aducrf101/Makefile.aducrf101.gnu @@ -0,0 +1,86 @@ +# -*- makefile -*- + +# Copyright (c) 2014, Analog Devices, Inc. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted (subject to the limitations in the +# disclaimer below) provided that the following conditions are met: +# +# - Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# +# - Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the +# distribution. +# +# - Neither the name of Analog Devices, Inc. nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +# GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +# HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +# BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +# OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +# IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +# Author: Jim Paris + +CROSS_COMPILE = arm-none-eabi- + +CC = $(CROSS_COMPILE)gcc +LD = $(CROSS_COMPILE)gcc +AS = $(CROSS_COMPILE)gcc +AR = $(CROSS_COMPILE)ar +NM = $(CROSS_COMPILE)nm +OBJCOPY = $(CROSS_COMPILE)objcopy +OBJDUMP = $(CROSS_COMPILE)objdump +STRIP = $(CROSS_COMPILE)strip + +CFLAGS_OPT ?= -Os +CFLAGS_DEBUG ?= -ggdb3 -fomit-frame-pointer +CFLAGS += $(CFLAGS_OPT) $(CFLAGS_DEBUG) +CFLAGS += -std=gnu99 +CFLAGS += -ffreestanding -mcpu=cortex-m3 -mthumb -mno-thumb-interwork +CFLAGS += -ffunction-sections -fdata-sections -fno-common -fno-builtin +CFLAGS += -flto + +ifdef WERROR + CFLAGS += -Wall -Werror + # These warnings are triggered by existing Contiki code + CFLAGS += -Wno-error=pointer-sign + CFLAGS += -Wno-error=char-subscripts + CFLAGS += -Wno-error=unused-variable + CFLAGS += -Wno-error=unused-but-set-variable +endif + +# UIP code does not follow C aliasing rules +CFLAGS += -fno-strict-aliasing + +LDFLAGS = $(CFLAGS) +LDFLAGS += -specs=nosys.specs -nostartfiles + +# TODO: When it becomes more commonly available, switch to newlib-nano +# for significant size reduction, by uncommenting this: +# LDFLAGS += -specs=nano.specs + +LDFLAGS += -Wl,--gc-sections +LDFLAGS += -Wl,-T$(CONTIKI_CPU)/Common/GCC/ADuCRF101.ld + +ASFLAGS += -c $(CFLAGS) + +# Compiler-specific startup code +CONTIKI_CPU_DIRS += Common/GCC +CONTIKI_SOURCEFILES += crt0.S + +# Rules +%.hex: % + $(OBJCOPY) -O ihex $^ $@ \ No newline at end of file diff --git a/cpu/arm/aducrf101/Makefile.aducrf101.iar b/cpu/arm/aducrf101/Makefile.aducrf101.iar new file mode 100644 index 000000000..08f46be85 --- /dev/null +++ b/cpu/arm/aducrf101/Makefile.aducrf101.iar @@ -0,0 +1,94 @@ +# -*- makefile -*- + +# Copyright (c) 2014, Analog Devices, Inc. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted (subject to the limitations in the +# disclaimer below) provided that the following conditions are met: +# +# - Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# +# - Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the +# distribution. +# +# - Neither the name of Analog Devices, Inc. nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +# GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +# HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +# BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +# OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +# IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +# Author: Jim Paris + +# Filename quoting here is very tricky, and probably depends on which Windows +# build of "make" is being used. This works for mingw32-make. + +ifeq ($(IAR_PATH),) + IAR_SUBPATH := $(shell ls "${PROGRAMFILES}\IAR Systems" 2>/dev/null | tail -1) + ifeq ($(IAR_SUBPATH),) + define iar_error + +Unable to find the IAR installation path. Please specify IAR_PATH. +For example: $(MAKE) IAR_PATH="C:\\Program Files (x86)\\IAR Systems\\Embedded Workbench 7.0\\arm" + endef + $(error $(iar_error)) + endif + IAR_PATH := ${PROGRAMFILES}\IAR Systems\${IAR_SUBPATH}\arm +endif + +CC := "$(IAR_PATH)""\\bin\iccarm" +LD := "$(IAR_PATH)""\\bin\ilinkarm" +AS := "$(IAR_PATH)""\\bin\iasmarm" +AR := "$(IAR_PATH)""\\bin\iarchive" +OBJCOPY := "$(IAR_PATH)""\\bin\ielftool" + +CFLAGS += -Ohz +CFLAGS += --silent +CFLAGS += --debug +CFLAGS += --endian=little +CFLAGS += --cpu=Cortex-M3 +CFLAGS += -I"$(IAR_PATH)""\\inc" +CFLAGS += -D__ICCARM__ + +AROPTS = --create +ASFLAGS = -S -s+ -w+ --cpu Cortex-M3 + +LDFLAGS += --config $(CONTIKI_CPU)/Common/IAR/ADUCRF101.icf + +# Compiler-specific startup code +CONTIKI_CPU_DIRS += Common/IAR +CONTIKI_SOURCEFILES += startup_ADuCRF101.S + +# Rules + +CUSTOM_RULE_C_TO_OBJECTDIR_O = 1 +$(OBJECTDIR)/%.o: %.c | $(OBJECTDIR) + $(TRACE_CC) + $(Q)$(CC) $(CFLAGS) $< --dependencies=m $(@:.o=.d) -o $@ + +CUSTOM_RULE_C_TO_O = 1 +%.co: %.c + $(TRACE_CC) + $(Q)$(CC) $(CFLAGS) $< -o $@ + +CUSTOM_RULE_C_TO_CO = 1 +%.co: %.c + $(TRACE_CC) + $(Q)$(CC) $(CFLAGS) -DAUTOSTART_ENABLE $< -o $@ + +%.hex: % + $(OBJCOPY) --silent --ihex $^ $@ diff --git a/cpu/arm/aducrf101/aducrf101-contiki.h b/cpu/arm/aducrf101/aducrf101-contiki.h new file mode 100644 index 000000000..00fd8765d --- /dev/null +++ b/cpu/arm/aducrf101/aducrf101-contiki.h @@ -0,0 +1,52 @@ +/** + * Copyright (c) 2014, Analog Devices, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** + * \author Jim Paris + */ + +#ifndef ADUCRF101_CONTIKI_H +#define ADUCRF101_CONTIKI_H + +#include + +#include + +typedef uint32_t clock_time_t; +typedef uint16_t uip_stats_t; + +typedef uint32_t rtimer_clock_t; +#define RTIMER_CLOCK_LT(a, b) ((int32_t)((a) - (b)) < 0) +rtimer_clock_t rtimer_arch_now(void); + +#endif diff --git a/cpu/arm/aducrf101/clock.c b/cpu/arm/aducrf101/clock.c new file mode 100644 index 000000000..18e6f7dac --- /dev/null +++ b/cpu/arm/aducrf101/clock.c @@ -0,0 +1,91 @@ +/** + * Copyright (c) 2014, Analog Devices, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** + * \author Jim Paris + */ + +#include +#include +#include + +static volatile clock_time_t current_clock = 0; +static volatile unsigned long current_seconds = 0; +static unsigned int second_countdown = CLOCK_SECOND; + +void +SysTick_Handler(void) +{ + current_clock++; + if(etimer_pending()) { + etimer_request_poll(); + } + if(--second_countdown == 0) { + current_seconds++; + second_countdown = CLOCK_SECOND; + } +} +/*---------------------------------------------------------------------------*/ +void +clock_init() +{ + SysTick_Config(F_CPU / CLOCK_SECOND); +} +/*---------------------------------------------------------------------------*/ +clock_time_t +clock_time(void) +{ + return current_clock; +} +/*---------------------------------------------------------------------------*/ +unsigned long +clock_seconds(void) +{ + return current_seconds; +} +/*---------------------------------------------------------------------------*/ +void +clock_delay_usec(uint16_t usec) +{ + /* Delay by watching the SysTick value change. */ + int32_t remaining = (int32_t)usec * F_CPU / 1000000; + int32_t old = SysTick->VAL; + while(remaining > 0) { + int32_t new = SysTick->VAL; + if(new > old) { /* wraparound */ + old += SysTick->LOAD; + } + remaining -= (old - new); + old = new; + } +} diff --git a/cpu/arm/aducrf101/dev/radio.c b/cpu/arm/aducrf101/dev/radio.c new file mode 100644 index 000000000..6e2b2ca47 --- /dev/null +++ b/cpu/arm/aducrf101/dev/radio.c @@ -0,0 +1,425 @@ +/** + * Copyright (c) 2014, Analog Devices, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** + * \author Jim Paris + */ + +#include +#include + +#include + +#include "contiki.h" +#include "contiki-net.h" +#include "net/netstack.h" +#include "radio.h" + +#define MAX_PACKET_LEN 240 + +static uint8_t tx_buf[MAX_PACKET_LEN]; + +#ifndef ADUCRF101_RADIO_BASE_CONFIG +#define ADUCRF101_RADIO_BASE_CONFIG DR_38_4kbps_Dev20kHz +#endif + +static RIE_BaseConfigs base_config = ADUCRF101_RADIO_BASE_CONFIG; +static int current_channel = 915000000; +static int current_power = 31; +static int radio_is_on = 0; + +/*---------------------------------------------------------------------------*/ +/* Sniffer configuration. We can re-use the CC2538 sniffer application + if we also accept CC2538_RF_CONF_SNIFFER. */ +#ifndef ADUCRF101_RF_CONF_SNIFFER +#if CC2538_RF_CONF_SNIFFER +#define ADUCRF101_RF_CONF_SNIFFER 1 +#endif +#endif + +#if ADUCRF101_RF_CONF_SNIFFER +#include "dev/uart.h" +static const uint8_t magic[] = { 0x53, 0x6E, 0x69, 0x66 }; /* Snif */ +#endif +/*---------------------------------------------------------------------------*/ +/* "Channel" is really frequency, and can be within the bands: + 431000000 Hz to 464000000 Hz + 862000000 Hz to 928000000 Hz + */ +#define MIN_CHANNEL 431000000 +#define MAX_CHANNEL 928000000 +static int +_set_channel(int freq) +{ + if(freq < 431000000) { + freq = 431000000; + } else if(freq > 464000000 && freq < 663000000) { + freq = 464000000; + } else if(freq >= 663000000 && freq < 862000000) { + freq = 862000000; + } else if(freq > 928000000) { + freq = 928000000; + } + current_channel = freq; + if(RadioSetFrequency(freq) != RIE_Success) { + return RADIO_RESULT_ERROR; + } + return RADIO_RESULT_OK; +} +/*---------------------------------------------------------------------------*/ +/* "Power" covers both PA type and power level: + 0 through 15 means single-ended, power level 0 through 15 + 16 through 31 means differential, power level 0 through 15 */ +#define MIN_POWER 0 +#define MAX_POWER 31 +static int +_set_power(int power) +{ + RIE_Responses ret; + if(power < 0) { + power = 0; + } + if(power > 31) { + power = 31; + } + if(power <= 15) { + ret = RadioTxSetPA(SingleEndedPA, power); + } else { + ret = RadioTxSetPA(DifferentialPA, power - 16); + } + current_power = power; + if(ret != RIE_Success) { + return RADIO_RESULT_ERROR; + } + return RADIO_RESULT_OK; +} +/*---------------------------------------------------------------------------*/ +PROCESS(aducrf101_rf_process, "ADuCRF101 RF driver"); +/*---------------------------------------------------------------------------*/ +/** Turn the radio on. */ +static int +on(void) +{ + if(radio_is_on) { + return 1; + } + + /* Power radio on */ + if(RadioInit(base_config) != RIE_Success) { + return 0; + } + + /* Ensure channel and power are set */ + if(_set_channel(current_channel) != RADIO_RESULT_OK) { + return 0; + } + if(_set_power(current_power) != RADIO_RESULT_OK) { + return 0; + } + + /* Enter receive mode */ + RadioRxPacketVariableLen(); + + radio_is_on = 1; + return 1; +} +/*---------------------------------------------------------------------------*/ +/** Turn the radio off. */ +static int +off(void) +{ + if(!radio_is_on) { + return 1; + } + if(RadioPowerOff() != RIE_Success) { + return 0; + } + radio_is_on = 0; + return 1; +} +/*---------------------------------------------------------------------------*/ +static int +init(void) +{ + off(); + on(); + process_start(&aducrf101_rf_process, NULL); + return 1; +} +/*---------------------------------------------------------------------------*/ +/** Prepare the radio with a packet to be sent. */ +static int +prepare(const void *payload, unsigned short payload_len) +{ + /* Truncate long packets */ + if(payload_len > MAX_PACKET_LEN) { + payload_len = MAX_PACKET_LEN; + } + memcpy(tx_buf, payload, payload_len); + return 0; +} +/*---------------------------------------------------------------------------*/ +/** Send the packet that has previously been prepared. */ +static int +transmit(unsigned short transmit_len) +{ + if(!radio_is_on) + return RADIO_TX_ERR; + + /* Transmit the packet */ + if(transmit_len > MAX_PACKET_LEN) { + transmit_len = MAX_PACKET_LEN; + } + if(RadioTxPacketVariableLen(transmit_len, tx_buf) != RIE_Success) { + return RADIO_TX_ERR; + } + while(!RadioTxPacketComplete()) + continue; + + /* Enter receive mode immediately after transmitting a packet */ + RadioRxPacketVariableLen(); + + return RADIO_TX_OK; +} +/*---------------------------------------------------------------------------*/ +/** Prepare & transmit a packet. */ +static int +send(const void *payload, unsigned short payload_len) +{ + prepare(payload, payload_len); + return transmit(payload_len); +} +/*---------------------------------------------------------------------------*/ +/** Read a received packet into a buffer. */ +static int +read(void *buf, unsigned short buf_len) +{ + uint8_t packet_len; + int8_t rssi; + + if(!radio_is_on) + return 0; + + if(buf_len > MAX_PACKET_LEN) { + buf_len = MAX_PACKET_LEN; + } + + /* Read already-received packet */ + if(RadioRxPacketRead(buf_len, &packet_len, buf, &rssi) != RIE_Success) { + return 0; + } + + if(packet_len > buf_len) { + packet_len = buf_len; + } + + /* Re-enter receive mode immediately after receiving a packet */ + RadioRxPacketVariableLen(); + +#if ADUCRF101_RF_CONF_SNIFFER + uart_put(magic[0]); + uart_put(magic[1]); + uart_put(magic[2]); + uart_put(magic[3]); + uart_put(packet_len + 2); + for(int i = 0; i < packet_len; i++) { + uart_put(((uint8_t *)buf)[i]); + } + /* FCS value is Wireshark's "TI CC24xx format" option: */ + uart_put(rssi); /* RSSI */ + uart_put(0x80); /* CRC is OK, LQI correlation is 0 */ +#endif + + return packet_len; +} +/*---------------------------------------------------------------------------*/ +/** Perform a Clear-Channel Assessment (CCA) to find out if there is + a packet in the air or not. */ +static int +channel_clear(void) +{ + /* Not implemented; assume clear */ + return 1; +} +/*---------------------------------------------------------------------------*/ +/** Check if the radio driver is currently receiving a packet */ +static int +receiving_packet(void) +{ + /* Not implemented; assume no. */ + return 0; +} +/*---------------------------------------------------------------------------*/ +/** Check if the radio driver has just received a packet */ +static int +pending_packet(void) +{ + if(RadioRxPacketAvailable()) { + return 1; + } + return 0; +} +/*---------------------------------------------------------------------------*/ +/** Get a radio parameter value. */ +static radio_result_t +get_value(radio_param_t param, radio_value_t *value) +{ + if(!value) { + return RADIO_RESULT_INVALID_VALUE; + } + + switch(param) { + case RADIO_PARAM_RSSI: + { + int8_t dbm; + if(!radio_is_on || RadioRadioGetRSSI(&dbm) != RIE_Success) { + return RADIO_RESULT_ERROR; + } + *value = dbm; + return RADIO_RESULT_OK; + } + + case RADIO_PARAM_CHANNEL: + *value = current_channel; + return RADIO_RESULT_OK; + case RADIO_CONST_CHANNEL_MIN: + *value = MIN_CHANNEL; + return RADIO_RESULT_OK; + case RADIO_CONST_CHANNEL_MAX: + *value = MAX_CHANNEL; + return RADIO_RESULT_OK; + + case RADIO_PARAM_TXPOWER: + *value = current_power; + return RADIO_RESULT_OK; + case RADIO_CONST_TXPOWER_MIN: + *value = MIN_POWER; + return RADIO_RESULT_OK; + case RADIO_CONST_TXPOWER_MAX: + *value = MAX_POWER; + return RADIO_RESULT_OK; + + default: + return RADIO_RESULT_NOT_SUPPORTED; + } +} +/*---------------------------------------------------------------------------*/ +/** Set a radio parameter value. */ +static radio_result_t +set_value(radio_param_t param, radio_value_t value) +{ + switch(param) { + case RADIO_PARAM_CHANNEL: + return _set_channel(value); + + case RADIO_PARAM_TXPOWER: + return _set_power(value); + + default: + return RADIO_RESULT_NOT_SUPPORTED; + } +} +/*---------------------------------------------------------------------------*/ +/** + * Get a radio parameter object. The argument 'dest' must point to a + * memory area of at least 'size' bytes, and this memory area will + * contain the parameter object if the function succeeds. + */ +static radio_result_t +get_object(radio_param_t param, void *dest, size_t size) +{ + return RADIO_RESULT_NOT_SUPPORTED; +} +/*---------------------------------------------------------------------------*/ +/** + * Set a radio parameter object. The memory area referred to by the + * argument 'src' will not be accessed after the function returns. + */ +static radio_result_t +set_object(radio_param_t param, const void *src, size_t size) +{ + return RADIO_RESULT_NOT_SUPPORTED; +} +/*---------------------------------------------------------------------------*/ +/** + * \brief Implementation of the ADuCRF101 RF driver process + * + * This process is started by init(). It waits for events triggered + * by packet reception. + */ +PROCESS_THREAD(aducrf101_rf_process, ev, data) +{ + int len; + PROCESS_BEGIN(); + + while(1) { + PROCESS_YIELD_UNTIL(ev == PROCESS_EVENT_POLL); + + packetbuf_clear(); + len = read(packetbuf_dataptr(), PACKETBUF_SIZE); + + if(len > 0) { + packetbuf_set_datalen(len); + + NETSTACK_RDC.input(); + } + } + + PROCESS_END(); +} +/*---------------------------------------------------------------------------*/ +/** + * \brief Trigger function called by ADI radio engine upon packet RX. + */ +void +aducrf101_rx_packet_hook(void) +{ + process_poll(&aducrf101_rf_process); +} +/*---------------------------------------------------------------------------*/ +const struct radio_driver aducrf101_radio_driver = { + .init = init, + .prepare = prepare, + .transmit = transmit, + .send = send, + .read = read, + .channel_clear = channel_clear, + .receiving_packet = receiving_packet, + .pending_packet = pending_packet, + .on = on, + .off = off, + .get_value = get_value, + .set_value = set_value, + .get_object = get_object, + .set_object = set_object, +}; diff --git a/cpu/arm/aducrf101/dev/uart.c b/cpu/arm/aducrf101/dev/uart.c new file mode 100644 index 000000000..569e54fdd --- /dev/null +++ b/cpu/arm/aducrf101/dev/uart.c @@ -0,0 +1,124 @@ +/** + * Copyright (c) 2014, Analog Devices, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** + * \author Jim Paris + */ + +#include + +static int (*uart_input_handler)(unsigned char c); +static int stdout_enabled; + +void +uart_init(int baud) +{ + /* P1.0 is UARTRXD, P1.1 is UARTTXD */ + pADI_GP1->GPCON &= ~(GP1CON_CON0_MSK | GP1CON_CON1_MSK); + pADI_GP1->GPCON |= GP1CON_CON0_UART0RXD | GP1CON_CON1_UART0TXD; + + /* Set P1.1 as output */ + GP1OEN_OEN1_BBA = 1; + + /* Set baudrate */ + int div = (F_CPU / 32) / baud; + pADI_UART->COMDIV = div; + pADI_UART->COMFBR = 0x8800 | ((((64 * F_CPU) / div) / baud) - 2048); + pADI_UART->COMIEN = 0; + pADI_UART->COMLCR = 3; + + /* Set up RX IRQ */ + pADI_UART->COMIEN = COMIEN_ERBFI_EN; + NVIC_EnableIRQ(UART_IRQn); + __enable_irq(); + + uart_input_handler = NULL; + stdout_enabled = 1; +} +/*---------------------------------------------------------------------------*/ +void +uart_put(unsigned char x) +{ + while(!(pADI_UART->COMLSR & COMLSR_THRE)) + continue; + pADI_UART->COMTX = x; +} +/*---------------------------------------------------------------------------*/ +void +UART_Int_Handler(void) +{ + if(pADI_UART->COMIIR & COMIIR_STA_RXBUFFULL) { + unsigned char x = pADI_UART->COMRX; + if(uart_input_handler) { + uart_input_handler(x); + } + } +} +/*---------------------------------------------------------------------------*/ +void +uart_set_input(int (*input)(unsigned char c)) +{ + uart_input_handler = input; +} +void +uart_enable_stdout(int enabled) +{ + stdout_enabled = enabled; +} +/*---------------------------------------------------------------------------*/ +/* Connect newlib's _write function to the UART. */ +int +_write(int fd, const void *buf, size_t len) +{ + if(stdout_enabled == 0) { + return -1; + } + + if(fd == 1 || fd == 2) { + int n = len; + const unsigned char *p = buf; + while(n--) + uart_put(*p++); + return len; + } + return -1; +} +/*---------------------------------------------------------------------------*/ +#ifdef __ICCARM__ +/* Connect IAR's __write function to the UART. */ +size_t +__write(int fd, const unsigned char *buf, size_t count) +{ + return _write(fd, buf, count); +} +#endif diff --git a/cpu/arm/aducrf101/dev/uart.h b/cpu/arm/aducrf101/dev/uart.h new file mode 100644 index 000000000..deaec627c --- /dev/null +++ b/cpu/arm/aducrf101/dev/uart.h @@ -0,0 +1,47 @@ +/** + * Copyright (c) 2014, Analog Devices, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** + * \author Jim Paris + */ + +#ifndef UART_H +#define UART_H + +void uart_init(int baud); +void uart_put(unsigned char x); +void uart_set_input(int (*input)(unsigned char c)); + +void uart_enable_stdout(int enabled); + +#endif diff --git a/cpu/arm/aducrf101/dev/uart0.h b/cpu/arm/aducrf101/dev/uart0.h new file mode 100644 index 000000000..2f8670044 --- /dev/null +++ b/cpu/arm/aducrf101/dev/uart0.h @@ -0,0 +1,49 @@ +/** + * Copyright (c) 2014, Analog Devices, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** + * \author Jim Paris + * + * \file + * This file exists only because some examples rely on it. + */ + +#ifndef UART1_H +#define UART1_H + +#include "dev/uart.h" +#undef BAUD2UBR +#define BAUD2UBR(x) (x) +#define uart1_set_input(f) uart_set_input(f) + +#endif /* UART1_H */ diff --git a/cpu/arm/aducrf101/dev/uart1.h b/cpu/arm/aducrf101/dev/uart1.h new file mode 100644 index 000000000..6b7ca27df --- /dev/null +++ b/cpu/arm/aducrf101/dev/uart1.h @@ -0,0 +1,49 @@ +/** + * Copyright (c) 2014, Analog Devices, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** + * \author Jim Paris + * + * \file + * This file exists only because some examples rely on it. + */ + +#ifndef UART0_H +#define UART0_H + +#include "dev/uart.h" +#undef BAUD2UBR +#define BAUD2UBR(x) (x) +#define uart0_set_input(f) uart_set_input(f) + +#endif /* UART0_H */ diff --git a/cpu/arm/aducrf101/dev/watchdog.c b/cpu/arm/aducrf101/dev/watchdog.c new file mode 100644 index 000000000..3c5cb4e49 --- /dev/null +++ b/cpu/arm/aducrf101/dev/watchdog.c @@ -0,0 +1,67 @@ +/** + * Copyright (c) 2014, Analog Devices, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** + * \author Jim Paris + */ + +#include +#include + +void +watchdog_init(void) +{ + /* Start disabled. */ + T3CON_ENABLE_BBA = 0; +} +/*---------------------------------------------------------------------------*/ +void +watchdog_start(void) +{ + /* 32 second timeout. This also locks the watchdog configuration. */ + pADI_WDT->T3CON = 0x00E9; + pADI_WDT->T3LD = 0x1000; + pADI_WDT->T3VAL = 0x1000; +} +/*---------------------------------------------------------------------------*/ +void +watchdog_stop(void) +{ + /* Not possible to stop, once enabled */ +} +/*---------------------------------------------------------------------------*/ +void +watchdog_periodic(void) +{ + pADI_WDT->T3CLRI = 0xcccc; +} diff --git a/cpu/arm/aducrf101/mtarch.h b/cpu/arm/aducrf101/mtarch.h new file mode 100644 index 000000000..e968158c0 --- /dev/null +++ b/cpu/arm/aducrf101/mtarch.h @@ -0,0 +1,47 @@ +/** + * Copyright (c) 2014, Analog Devices, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** + * \author Jim Paris + */ + +#ifndef MTARCH_H_ +#define MTARCH_H_ + +/* Multithreading is currently unimplemented for ARM Cortex-M3 */ + +struct mtarch_thread { + short mt_thread; +}; + +#endif /* MTARCH_H_ */ diff --git a/cpu/arm/aducrf101/rtimer-arch.c b/cpu/arm/aducrf101/rtimer-arch.c new file mode 100644 index 000000000..4f6b3caa3 --- /dev/null +++ b/cpu/arm/aducrf101/rtimer-arch.c @@ -0,0 +1,138 @@ +/** + * Copyright (c) 2014, Analog Devices, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** + * \author Jim Paris + */ + +#include +#include "rtimer-arch.h" +#include "aducrf101-contiki.h" + +/* rtimer on the ADuCRF101 is implemented with the "wakeup" timer. + (timer 2). It should be clocked from an external crystal, + but if that doesn't seem to be present, this code will select the + imprecise internal 32.768 KHz oscillator instead. */ + +static void +_timer2_enable(int enable) +{ + T2CON_ENABLE_BBA = enable; + clock_time_t now = clock_time(); + while(T2STA_CON_BBA) { + /* Synchronizing settings may fail if the chosen clock isn't running; + wait no more than 1ms for it */ + if((clock_time() - now) > (CLOCK_SECOND / 1000)) { + break; + } + } +} +static uint32_t +_timer2_val(void) +{ + /* This is atomic because the FREEZE bit is set in T2CON. */ + uint32_t now; + now = pADI_WUT->T2VAL0; + now |= pADI_WUT->T2VAL1 << 16; + return now; +} +static uint32_t +_timer2_measure_freq(void) +{ + const int test_usec = 10000; + uint32_t now = _timer2_val(); + clock_delay_usec(test_usec); + return (_timer2_val() - now) * (1000000 / test_usec); +} +void +rtimer_arch_init(void) +{ + uint32_t freq; + const char *timer = "LFXTAL"; + + _timer2_enable(0); + pADI_WUT->T2CON = T2CON_PRE_DIV1 | T2CON_MOD_FREERUN | T2CON_FREEZE_EN | + T2CON_WUEN_EN; + + /* Try 32.768 KHz crystal */ + pADI_WUT->T2CON |= T2CON_CLK_LFXTAL; + _timer2_enable(1); + freq = _timer2_measure_freq(); + + if(freq < 20000 || freq > 40000) { + /* No good; use 32.768 KHz internal oscillator */ + _timer2_enable(0); + pADI_WUT->T2CON &= ~T2CON_CLK_MSK; + pADI_WUT->T2CON |= T2CON_CLK_LFOSC; + _timer2_enable(1); + freq = _timer2_measure_freq(); + timer = "LFOSC"; + } + + printf("Using %s for rtimer (%ld Hz)\n", timer, freq); + + /* Enable interrupt in NVIC, but disable in WUT for now. */ + pADI_WUT->T2IEN = 0; + NVIC_EnableIRQ(WUT_IRQn); +} +rtimer_clock_t +rtimer_arch_now(void) +{ + /* This is atomic because the FREEZE bit is set in T2CON. */ + return _timer2_val(); +} +void +rtimer_arch_schedule(rtimer_clock_t t) +{ + uint32_t now = _timer2_val(); + + /* Minimum of 5 wakeup timer ticks */ + if((int32_t)(t - now) < 5) { + t = now + 5; + } + + /* Set T2WUFB to match at target time */ + T2IEN_WUFB_BBA = 0; + pADI_WUT->T2WUFB0 = (t & 0xffff); + pADI_WUT->T2WUFB1 = (t >> 16); + T2IEN_WUFB_BBA = 1; +} +void +WakeUp_Int_Handler(void) +{ + /* clear interrupt */ + T2CLRI_WUFB_BBA = 1; + /* disable T2WUFB match */ + T2IEN_WUFB_BBA = 0; + rtimer_run_next(); +} diff --git a/cpu/arm/aducrf101/rtimer-arch.h b/cpu/arm/aducrf101/rtimer-arch.h new file mode 100644 index 000000000..ec28dcf7d --- /dev/null +++ b/cpu/arm/aducrf101/rtimer-arch.h @@ -0,0 +1,47 @@ +/** + * Copyright (c) 2014, Analog Devices, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** + * \author Jim Paris + */ + +#ifndef __RTIMER_ARCH_H__ +#define __RTIMER_ARCH_H__ + +#include + +#define RTIMER_ARCH_SECOND (32768) + +#include "sys/rtimer.h" + +#endif /* __RTIMER_ARCH_H__ */ diff --git a/cpu/arm/aducrf101/slip-arch.c b/cpu/arm/aducrf101/slip-arch.c new file mode 100644 index 000000000..523e30313 --- /dev/null +++ b/cpu/arm/aducrf101/slip-arch.c @@ -0,0 +1,60 @@ +/** + * Copyright (c) 2014, Analog Devices, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** + * \author Jim Paris + */ + +#include + +#include "contiki.h" +#include "dev/slip.h" +#include "uart.h" + +/*---------------------------------------------------------------------------*/ +void +slip_arch_writeb(unsigned char c) +{ + uart_put(c); +} +/*---------------------------------------------------------------------------*/ +/** + * Initalize the RS232 port and the SLIP driver. + * + */ +void +slip_arch_init(unsigned long ubr) +{ + uart_set_input(slip_input_byte); +} +/*---------------------------------------------------------------------------*/ diff --git a/cpu/arm/common/CMSIS/core_cm0.h b/cpu/arm/common/CMSIS/core_cm0.h new file mode 100644 index 000000000..0388d076d --- /dev/null +++ b/cpu/arm/common/CMSIS/core_cm0.h @@ -0,0 +1,702 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V3.30 + * @date 06. May 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#ifdef __cplusplus + extern "C" { +#endif + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M0 + @{ + */ + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) /* Cosmic */ + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI__VFP_SUPPORT____ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000 + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) + are only accessible over DAP and not via processor. Therefore + they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) +#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) +#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + else { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ + else { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CMSIS_GENERIC */ diff --git a/cpu/arm/common/CMSIS/core_cm0plus.h b/cpu/arm/common/CMSIS/core_cm0plus.h new file mode 100644 index 000000000..b2770cef5 --- /dev/null +++ b/cpu/arm/common/CMSIS/core_cm0plus.h @@ -0,0 +1,813 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V3.30 + * @date 06. May 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#ifdef __cplusplus + extern "C" { +#endif + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex-M0+ + @{ + */ + +/* CMSIS CM0P definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \ + __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) /* Cosmic */ + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI__VFP_SUPPORT____ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000 + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0 + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if (__VTOR_PRESENT == 1) + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if (__VTOR_PRESENT == 1) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) + are only accessible over DAP and not via processor. Therefore + they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0+ Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) +#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) +#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + else { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ + else { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CMSIS_GENERIC */ diff --git a/cpu/arm/common/CMSIS/core_cm3.h b/cpu/arm/common/CMSIS/core_cm3.h new file mode 100644 index 000000000..436ac5b11 --- /dev/null +++ b/cpu/arm/common/CMSIS/core_cm3.h @@ -0,0 +1,1638 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V3.30 + * @date 06. May 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#ifdef __cplusplus + extern "C" { +#endif + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M3 + @{ + */ + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) /* Cosmic */ + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI__VFP_SUPPORT____ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200 + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if (__CM3_REV < 0x0201) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CMSIS_GENERIC */ diff --git a/cpu/arm/common/CMSIS/core_cm4.h b/cpu/arm/common/CMSIS/core_cm4.h new file mode 100644 index 000000000..610c4afb4 --- /dev/null +++ b/cpu/arm/common/CMSIS/core_cm4.h @@ -0,0 +1,1790 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V3.30 + * @date 06. May 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#ifdef __cplusplus + extern "C" { +#endif + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M4 + @{ + */ + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x04) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) /* Cosmic */ + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ +#include /* Compiler specific SIMD Intrinsics */ + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000 + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0 + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register */ +#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register */ +#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register */ +#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ +/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ + NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CMSIS_GENERIC */ diff --git a/cpu/arm/common/CMSIS/core_cm4_simd.h b/cpu/arm/common/CMSIS/core_cm4_simd.h new file mode 100644 index 000000000..f9bceff1e --- /dev/null +++ b/cpu/arm/common/CMSIS/core_cm4_simd.h @@ -0,0 +1,697 @@ +/**************************************************************************//** + * @file core_cm4_simd.h + * @brief CMSIS Cortex-M4 SIMD Header File + * @version V3.30 + * @date 17. February 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CM4_SIMD_H +#define __CORE_CM4_SIMD_H + +#ifdef __cplusplus + extern "C" { +#endif + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32) ) >> 32)) + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ +#include + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ +/* not yet supported */ + + +#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +/* Cosmic specific functions */ +#include + +#endif + +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_SIMD_H */ diff --git a/cpu/arm/common/CMSIS/core_cmFunc.h b/cpu/arm/common/CMSIS/core_cmFunc.h new file mode 100644 index 000000000..2c2af69c1 --- /dev/null +++ b/cpu/arm/common/CMSIS/core_cmFunc.h @@ -0,0 +1,637 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V3.30 + * @date 17. February 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief Enable IRQ Interrupts + + This function enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** \brief Disable IRQ Interrupts + + This function disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + uint32_t result; + + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ +#include + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + +#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +/* Cosmic specific functions */ +#include + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + +#endif /* __CORE_CMFUNC_H */ diff --git a/cpu/arm/common/CMSIS/core_cmInstr.h b/cpu/arm/common/CMSIS/core_cmInstr.h new file mode 100644 index 000000000..d2ec262f1 --- /dev/null +++ b/cpu/arm/common/CMSIS/core_cmInstr.h @@ -0,0 +1,687 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V3.30 + * @date 17. February 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __rbit + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW(value, ptr) __strex(value, ptr) + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +#define __CLREX __clrex + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + +#endif /* (__CORTEX_M >= 0x03) */ + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constrant "l" + * Otherwise, use general registers, specified by constrant "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb"); +} + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb"); +} + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb"); +} + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + uint32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32 - op2)); +} + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ +#include + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + +#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +/* Cosmic specific functions */ +#include + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/cpu/arm/common/CMSIS/core_sc000.h b/cpu/arm/common/CMSIS/core_sc000.h new file mode 100644 index 000000000..a32cc40d9 --- /dev/null +++ b/cpu/arm/common/CMSIS/core_sc000.h @@ -0,0 +1,833 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V3.30 + * @date 06. May 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#ifdef __cplusplus + extern "C" { +#endif + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup SC000 + @{ + */ + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_SC (000) /*!< Cortex secure core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) /* Cosmic */ + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI__VFP_SUPPORT____ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000 + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1]; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154]; + __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/* SCB Security Features Register Definitions */ +#define SCB_SFCR_UNIBRTIMING_Pos 0 /*!< SCB SFCR: UNIBRTIMING Position */ +#define SCB_SFCR_UNIBRTIMING_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: UNIBRTIMING Mask */ + +#define SCB_SFCR_SECKEY_Pos 16 /*!< SCB SFCR: SECKEY Position */ +#define SCB_SFCR_SECKEY_Msk (0xFFFFUL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: SECKEY Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2]; + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) + are only accessible over DAP and not via processor. Therefore + they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of SC000 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) +#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) +#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + else { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ + else { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CMSIS_GENERIC */ diff --git a/cpu/arm/common/CMSIS/core_sc300.h b/cpu/arm/common/CMSIS/core_sc300.h new file mode 100644 index 000000000..b22711749 --- /dev/null +++ b/cpu/arm/common/CMSIS/core_sc300.h @@ -0,0 +1,1618 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V3.30 + * @date 06. May 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#ifdef __cplusplus + extern "C" { +#endif + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup SC3000 + @{ + */ + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_SC (300) /*!< Cortex secure core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) /* Cosmic */ + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI__VFP_SUPPORT____ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000 + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + uint32_t RESERVED1[1]; +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CMSIS_GENERIC */ diff --git a/platform/ev-aducrf101mkxz/Makefile.ev-aducrf101mkxz b/platform/ev-aducrf101mkxz/Makefile.ev-aducrf101mkxz new file mode 100644 index 000000000..261f5fe51 --- /dev/null +++ b/platform/ev-aducrf101mkxz/Makefile.ev-aducrf101mkxz @@ -0,0 +1,65 @@ +# -*- makefile -*- + +# Copyright (c) 2014, Analog Devices, Inc. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted (subject to the limitations in the +# disclaimer below) provided that the following conditions are met: +# +# - Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# +# - Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the +# distribution. +# +# - Neither the name of Analog Devices, Inc. nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +# GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +# HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +# BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +# OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +# IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +# Author: Jim Paris + +CONTIKI_TARGET_DIRS = . +CONTIKI_CORE = contiki-main +CONTIKI_TARGET_MAIN = ${CONTIKI_CORE}.o + +CONTIKI_TARGET_SOURCEFILES += $(ARCH) +CONTIKI_TARGET_SOURCEFILES += contiki-main.c +CONTIKI_TARGET_SOURCEFILES += slip.c +CONTIKI_TARGET_SOURCEFILES += button-sensor.c +CONTIKI_TARGET_SOURCEFILES += leds-arch.c + +CONTIKI_SOURCEFILES += $(CONTIKI_TARGET_SOURCEFILES) + +CONTIKI_PLAT_DEFS = + +ifeq ($(UIP_CONF_IPV6),1) +CFLAGS += -DWITH_UIP6=1 +endif + +include $(CONTIKI)/cpu/arm/aducrf101/Makefile.aducrf101 + +MODULES += \ + core/net \ + core/net/rpl \ + core/net/ip \ + core/net/ipv4 \ + core/net/ipv6 \ + core/net/rime \ + core/net/mac \ + core/net/mac/sicslowmac diff --git a/platform/ev-aducrf101mkxz/README.md b/platform/ev-aducrf101mkxz/README.md new file mode 100644 index 000000000..a4cf4dcb4 --- /dev/null +++ b/platform/ev-aducrf101mkxz/README.md @@ -0,0 +1,159 @@ +Building Contiki for the EV-ADuCRF101MKxZ Board +=============================================== + +On Debian/Ubuntu Linux: +----------------------- + +For older versions of Ubuntu (prior to 14.04), add the external +package repository that provides recent versions of GCC for ARM: + + sudo add-apt-repository -y ppa:terry.guo/gcc-arm-embedded + sudo apt-get update + +For all systems, install the required development packages: + + sudo apt-get install git make gcc-arm-none-eabi python-serial + +Obtain the Contiki source code: + + git clone https://github.com/contiki-os/contiki.git + +Build Contiki's `example-abc`: + + make -C contiki/examples/rime \ + TARGET=ev-aducrf101mkxz \ + example-abc.ev-aducrf101mkxz.hex + +The default radio frequency can optionally be specified on the +command-line as follows. A clean rebuild may be needed when changing +it: + + make -C contiki/examples/rime \ + TARGET=ev-aducrf101mkxz \ + RF_CHANNEL=915000000 \ + clean \ + example-abc.ev-aducrf101mkxz.hex + +The code can be flashed to the eval board and tested using +[adi-cm3sd](https://github.com/jimparis/adi-cm3sd.git). Obtain +`adi-cm3sd`: + + git clone https://github.com/jimparis/adi-cm3sd.git + +Connect the evaluation board using its J-Link board, or any other +serial adapter. Flash `example-adc` and open a terminal by running: + + adi-cm3sd/cm3sd.py -a contiki/examples/rime/example-abc.ev-aducrf101mkxz.hex \ + /dev/serial/by-id/usb-SEGGER_J-Link_000541011111-if00 + +replacing `/dev/serial/by-id/usb-SEGGER_J-Link_000541011111-if00` with +the path to the correct serial device. Flash the same code on a +second evaluation board to see them communicate. + +### IPv6 Example ### + +#### Border Router #### + +First, build and run the IPv6 `border-router` example: + + make -C contiki/examples/ipv6/rpl-border-router \ + TARGET=ev-aducrf101mkxz \ + SERIAL_ID='"00001234"' \ + border-router.ev-aducrf101mkxz.hex + + adi-cm3sd/cm3sd.py -a contiki/examples/ipv6/rpl-border-router/border-router.ev-aducrf101mkxz.hex \ + /dev/serial/by-id/usb-SEGGER_J-Link_000541011111-if00 + +After flashing, close the terminal with `CTRL-C`, then build and run +the SLIP tunnel on the host machine: + + make -C contiki/tools tunslip6 + + sudo contiki/tools/tunslip6 \ + -s /dev/serial/by-id/usb-SEGGER_J-Link_000541011111-if00 \ + -B 115200 -v3 aaaa::1/64 + +Open the border router's home page at: http://[aaaa::3230:3030:3132:3334]/ + +#### Web Server #### + +Then, build and flash the IPv6 `webserver6` example on another eval +board. The different `SERIAL_ID` ensures that the webserver uses a +link-local IP address that is different from that of the border +router: + + make -C contiki/examples/webserver-ipv6 \ + TARGET=ev-aducrf101mkxz \ + SERIAL_ID='"00005678"' \ + webserver6.ev-aducrf101mkxz.hex + + adi-cm3sd/cm3sd.py -a contiki/examples/webserver-ipv6/webserver6.ev-aducrf101mkxz.hex \ + /dev/serial/by-id/usb-SEGGER_J-Link_000541022222-if00 + +Open the web server's home page at: http://[aaaa::3230:3030:3536:3738]/ + +On Windows: +----------- + +### Install prerequisites ### + +Install [git](http://git-scm.com/download/win/) with default options. + +Install MinGW as follows: + +* Download and run [mingw-get-setup.exe](https://sourceforge.net/projects/mingw/files/latest/download). +* Select `Install`, `Continue`, and `Continue` again. +* Click `Basic Setup` on the left panel. +* Click the checkbox next to `mingw32-base`, then click `Mark for Installation`. +* Select 'Installation -> Apply Changes' from the menu bar. +* Click 'Apply', then close and quit the MinGW installer. + +### Install toolchain ### + +Contiki can be built with either GCC or IAR: + +* **GCC**: Install + [GNU Tools for ARM Embedded Processors](https://launchpad.net/gcc-arm-embedded/+download). + Use the "Windows installer" version. Ensure that "Add path to + environment variable" is selected in the installer. + +* **IAR**: Install + [IAR Embedded Workbench](http://www.iar.com/ewarm/). + +### Building `example-abc` ### + +Open a shell by right-clicking the desktop or any folder and +selecting `Git Bash`. + +Obtain the Contiki source code: + + git clone https://github.com/contiki-os/contiki.git + +Build Contiki's `example-abc`: + +* **GCC** + + /c/mingw/bin/mingw32-make -C contiki/examples/rime \ + TARGET=ev-aducrf101mkxz \ + example-abc.ev-aducrf101mkxz.hex + +* **IAR** + + /c/mingw/bin/mingw32-make -C contiki/examples/rime \ + IAR=1 \ + TARGET=ev-aducrf101mkxz \ + example-abc.ev-aducrf101mkxz.hex + +Other build options like `RF_CHANNEL` and `SERIAL_ID` can be specified +as in the Linux instructions above. + +### Flashing and running ### + +The resulting file +`contiki/examples/rime/example-abc.ev-aducrf101mkxz.hex` can be +flashed to the evaluation board using ADI's +[CM3WSD](http://www.analog.com/static/imported-files/eval_boards/CM3WSD.zip) +utility. + +Use a terminal emulator (e.g. HyperTerminal) at 115200 baud to see the +program output. diff --git a/platform/ev-aducrf101mkxz/button-sensor.c b/platform/ev-aducrf101mkxz/button-sensor.c new file mode 100644 index 000000000..1e43e6fdf --- /dev/null +++ b/platform/ev-aducrf101mkxz/button-sensor.c @@ -0,0 +1,104 @@ +/** + * Copyright (c) 2014, Analog Devices, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** + * \author Jim Paris + */ + +#include "lib/sensors.h" +#include "dev/button-sensor.h" +#include "platform-conf.h" + +#include + +const struct sensors_sensor button_sensor; +static struct timer debouncetimer; + +/* e.g. pADI_GP0 */ +#define GPIO CC_CONCAT(pADI_GP, BUTTON_GPIO) + +/* e.g. Ext_Int2_Handler */ +#define HANDLER CC_CONCAT(CC_CONCAT(Ext_Int, BUTTON_INT), _Handler) + +/* e.g. EINT2_IRQn */ +#define IRQN CC_CONCAT(CC_CONCAT(EINT, BUTTON_INT), _IRQn) + +void +HANDLER(void) +{ + pADI_INTERRUPT->EICLR = (1 << BUTTON_INT); + if(!timer_expired(&debouncetimer)) { + return; + } + timer_set(&debouncetimer, CLOCK_SECOND / 8); + sensors_changed(&button_sensor); +} +static int +config(int type, int c) +{ + switch(type) { + case SENSORS_HW_INIT: + timer_set(&debouncetimer, 0); + return 1; + case SENSORS_ACTIVE: + /* Set button as a GPIO input with pullup */ + GPIO->GPCON &= ~(3UL << (BUTTON_PIN * 2)); + GPIO->GPOEN &= ~(1UL << BUTTON_PIN); + GPIO->GPPUL |= (1UL << BUTTON_PIN); + + /* Enable interrupt for the button (rise and fall) */ +#if BUTTON_INT <= 3 + pADI_INTERRUPT->EI0CFG |= (0xaUL << (4 * (BUTTON_INT - 0))); +#elif BUTTON_INT <= 7 + pADI_INTERRUPT->EI1CFG |= (0xaUL << (4 * (BUTTON_INT - 4))); +#endif + pADI_INTERRUPT->EICLR = (1 << BUTTON_INT); + NVIC_EnableIRQ(IRQN); + return 1; + } + return 0; +} +static int +status(int type) +{ + switch(type) { + case SENSORS_ACTIVE: + case SENSORS_READY: + if(GPIO->GPIN & (1UL << BUTTON_PIN)) { + return 1; + } + return 0; + } + return 0; +} +SENSORS_SENSOR(button_sensor, BUTTON_SENSOR, NULL, config, status); diff --git a/platform/ev-aducrf101mkxz/contiki-conf.h b/platform/ev-aducrf101mkxz/contiki-conf.h new file mode 100644 index 000000000..98cc0084f --- /dev/null +++ b/platform/ev-aducrf101mkxz/contiki-conf.h @@ -0,0 +1,192 @@ +/** + * Copyright (c) 2014, Analog Devices, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** + * \author Jim Paris + */ + +#ifndef __CONTIKI_CONF_H__ +#define __CONTIKI_CONF_H__ + +#include + +#include "aducrf101-contiki.h" +#include "platform-conf.h" + +/* Clock ticks per second */ +#define CLOCK_CONF_SECOND 1000 + +#define CCIF +#define CLIF + +/* start of conitki config. */ +#define PLATFORM_HAS_LEDS 1 +#define PLATFORM_HAS_BUTTON 1 + +#define LINKADDR_CONF_SIZE 8 + +#if WITH_UIP6 +/* Network setup for IPv6 */ +#define NETSTACK_CONF_NETWORK sicslowpan_driver +#define NETSTACK_CONF_MAC nullmac_driver +#define NETSTACK_CONF_RDC nullrdc_driver +#define NETSTACK_CONF_RADIO aducrf101_radio_driver +#define NETSTACK_CONF_FRAMER framer_802154 + +#define NETSTACK_CONF_RDC_CHANNEL_CHECK_RATE 8 +#define RIME_CONF_NO_POLITE_ANNOUCEMENTS 0 +#define CXMAC_CONF_ANNOUNCEMENTS 0 +#define XMAC_CONF_ANNOUNCEMENTS 0 + +#else /* WITH_UIP6 */ + +/* Network setup for non-IPv6 (rime). */ +#define NETSTACK_CONF_NETWORK rime_driver +#define NETSTACK_CONF_MAC csma_driver +#define NETSTACK_CONF_RDC nullrdc_driver +#define NETSTACK_CONF_RADIO aducrf101_radio_driver +#define NETSTACK_CONF_FRAMER framer_802154 + +#define NETSTACK_CONF_RDC_CHANNEL_CHECK_RATE 8 + +#define COLLECT_CONF_ANNOUNCEMENTS 1 +#define RIME_CONF_NO_POLITE_ANNOUCEMENTS 0 +#define CXMAC_CONF_ANNOUNCEMENTS 0 +#define XMAC_CONF_ANNOUNCEMENTS 0 +#define CONTIKIMAC_CONF_ANNOUNCEMENTS 0 + +#define CONTIKIMAC_CONF_COMPOWER 0 +#define XMAC_CONF_COMPOWER 0 +#define CXMAC_CONF_COMPOWER 0 + +#define COLLECT_NBR_TABLE_CONF_MAX_NEIGHBORS 32 + +#endif /* WITH_UIP6 */ + +#define QUEUEBUF_CONF_NUM 16 + +#define PACKETBUF_CONF_ATTRS_INLINE 1 + +#ifndef RF_CHANNEL +#define RF_CHANNEL 868000000 +#endif /* RF_CHANNEL */ + +#define CONTIKIMAC_CONF_BROADCAST_RATE_LIMIT 0 + +#define IEEE802154_CONF_PANID 0xABCD + +#define PROFILE_CONF_ON 0 +#define ENERGEST_CONF_ON 0 + +#define AODV_COMPLIANCE +#define AODV_NUM_RT_ENTRIES 32 + +#define WITH_ASCII 1 + +#define PROCESS_CONF_NUMEVENTS 8 +#define PROCESS_CONF_STATS 1 + +#ifdef WITH_UIP6 + +#define LINKADDR_CONF_SIZE 8 + +#define UIP_CONF_LL_802154 1 +#define UIP_CONF_LLH_LEN 0 + +#ifndef UIP_CONF_ROUTER +#define UIP_CONF_ROUTER 1 +#endif + +#ifndef UIP_CONF_IPV6_RPL +#define UIP_CONF_IPV6_RPL 1 +#endif + +#define NBR_TABLE_CONF_MAX_NEIGHBORS 30 +#define UIP_CONF_MAX_ROUTES 30 + +#define UIP_CONF_ND6_SEND_RA 0 +#define UIP_CONF_ND6_REACHABLE_TIME 600000 +#define UIP_CONF_ND6_RETRANS_TIMER 10000 + +#define UIP_CONF_IPV6 1 +#define UIP_CONF_IPV6_QUEUE_PKT 0 +#define UIP_CONF_IPV6_CHECKS 1 +#define UIP_CONF_IPV6_REASSEMBLY 0 +#define UIP_CONF_NETIF_MAX_ADDRESSES 3 +#define UIP_CONF_ND6_MAX_PREFIXES 3 +#define UIP_CONF_ND6_MAX_DEFROUTERS 2 +#define UIP_CONF_IP_FORWARD 0 +#define UIP_CONF_BUFFER_SIZE 140 +#define SICSLOWPAN_CONF_FRAG 1 +#define SICSLOWPAN_CONF_MAXAGE 8 + +#define SICSLOWPAN_CONF_COMPRESSION_IPV6 0 +#define SICSLOWPAN_CONF_COMPRESSION_HC1 1 +#define SICSLOWPAN_CONF_COMPRESSION_HC01 2 +#define SICSLOWPAN_CONF_COMPRESSION SICSLOWPAN_COMPRESSION_HC06 +#ifndef SICSLOWPAN_CONF_FRAG +#define SICSLOWPAN_CONF_FRAG 1 +#define SICSLOWPAN_CONF_MAXAGE 8 +#endif /* SICSLOWPAN_CONF_FRAG */ +#define SICSLOWPAN_CONF_CONVENTIONAL_MAC 1 +#define SICSLOWPAN_CONF_MAX_ADDR_CONTEXTS 2 +#else /* WITH_UIP6 */ +#define UIP_CONF_IP_FORWARD 1 +#define UIP_CONF_BUFFER_SIZE 140 +#endif /* WITH_UIP6 */ + +#define UIP_CONF_ICMP_DEST_UNREACH 1 + +#define UIP_CONF_DHCP_LIGHT +#define UIP_CONF_LLH_LEN 0 +#define UIP_CONF_RECEIVE_WINDOW 48 +#define UIP_CONF_TCP_MSS 48 +#define UIP_CONF_MAX_CONNECTIONS 4 +#define UIP_CONF_MAX_LISTENPORTS 4 +#define UIP_CONF_UDP_CONNS 8 +#define UIP_CONF_FWCACHE_SIZE 16 +#define UIP_CONF_BROADCAST 1 +#define UIP_CONF_UDP 1 +#define UIP_CONF_UDP_CHECKSUMS 1 +#define UIP_CONF_PINGADDRCONF 0 +#define UIP_CONF_LOGGING 0 + +#define UIP_CONF_TCP_SPLIT 0 + +/* include the project config */ +/* PROJECT_CONF_H might be defined in the project Makefile */ +#ifdef PROJECT_CONF_H +#include PROJECT_CONF_H +#endif /* PROJECT_CONF_H */ + +#endif /* __CONTIKI_CONF_H__ */ diff --git a/platform/ev-aducrf101mkxz/contiki-main.c b/platform/ev-aducrf101mkxz/contiki-main.c new file mode 100644 index 000000000..134380501 --- /dev/null +++ b/platform/ev-aducrf101mkxz/contiki-main.c @@ -0,0 +1,199 @@ +/** + * Copyright (c) 2014, Analog Devices, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** + * \author Jim Paris + */ + +#include +#include +#include + +#include "contiki.h" +#include "net/netstack.h" + +#include "dev/serial-line.h" + +#include "net/ip/uip.h" + +#include "dev/button-sensor.h" +#include "dev/leds.h" + +#if WITH_UIP6 +#include "net/ipv6/uip-ds6.h" +#endif /* WITH_UIP6 */ + +#include "net/rime/rime.h" + +#include "uart.h" +#include "watchdog.h" + +SENSORS(&button_sensor); + +#ifndef SERIAL_ID +#define SERIAL_ID { 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08 } +#endif + +uint8_t serial_id[] = SERIAL_ID; +uint16_t node_id = 0x0102; + +/*---------------------------------------------------------------------------*/ +static void +set_rime_addr(void) +{ + linkaddr_t addr; + int i; + + memset(&addr, 0, sizeof(linkaddr_t)); +#if UIP_CONF_IPV6 + memcpy(addr.u8, serial_id, sizeof(addr.u8)); +#else + if(node_id == 0) { + for(i = 0; i < sizeof(linkaddr_t); ++i) { + addr.u8[i] = serial_id[7 - i]; + } + } else { + addr.u8[0] = node_id & 0xff; + addr.u8[1] = node_id >> 8; + } +#endif + linkaddr_set_node_addr(&addr); + printf("Rime started with address "); + for(i = 0; i < sizeof(addr.u8) - 1; i++) { + printf("%d.", addr.u8[i]); + } + printf("%d\n", addr.u8[i]); +} +/*---------------------------------------------------------------------------*/ +static void +set_rf_params(void) +{ + int chan; + NETSTACK_RADIO.set_value(RADIO_PARAM_CHANNEL, RF_CHANNEL); + NETSTACK_RADIO.get_value(RADIO_PARAM_CHANNEL, &chan); + printf("RF channel set to %d Hz\n", chan); +} +/*---------------------------------------------------------------------------*/ +int contiki_argc = 0; +char **contiki_argv; + +int +main(int argc, char **argv) +{ + watchdog_init(); + leds_init(); + uart_init(115200); + clock_init(); + +#if UIP_CONF_IPV6 +#if UIP_CONF_IPV6_RPL + printf(CONTIKI_VERSION_STRING " started with IPV6, RPL\n"); +#else + printf(CONTIKI_VERSION_STRING " started with IPV6\n"); +#endif +#else + printf(CONTIKI_VERSION_STRING " started\n"); +#endif + + contiki_argc = argc; + contiki_argv = argv; + + process_init(); + process_start(&etimer_process, NULL); + ctimer_init(); + rtimer_init(); + + set_rime_addr(); + + queuebuf_init(); + + set_rf_params(); + netstack_init(); + printf("MAC %s RDC %s NETWORK %s\n", + NETSTACK_MAC.name, NETSTACK_RDC.name, NETSTACK_NETWORK.name); + +#if WITH_UIP6 + memcpy(&uip_lladdr.addr, serial_id, sizeof(uip_lladdr.addr)); + + process_start(&tcpip_process, NULL); + printf("Tentative link-local IPv6 address "); + { + uip_ds6_addr_t *lladdr; + int i; + lladdr = uip_ds6_get_link_local(-1); + for(i = 0; i < 8; i++) { + printf("%02x%02x%c", lladdr->ipaddr.u8[i * 2], + lladdr->ipaddr.u8[i * 2 + 1], + i == 7 ? '\n' : ':'); + } + /* make it hardcoded... */ + lladdr->state = ADDR_AUTOCONF; + } +#else + process_start(&tcpip_process, NULL); +#endif + + serial_line_init(); + process_start(&sensors_process, NULL); + + autostart_start(autostart_processes); + + while(1) { + watchdog_periodic(); + + process_run(); + } + + return 0; +} +/*---------------------------------------------------------------------------*/ +void +log_message(char *m1, char *m2) +{ + printf("%s%s\n", m1, m2); +} +/*---------------------------------------------------------------------------*/ +void +uip_log(char *m) +{ + printf("%s\n", m); +} +/*---------------------------------------------------------------------------*/ +void +_xassert(const char *file, int line) +{ + printf("%s:%u: failed assertion\n", file, line); + for(;;) { + continue; + } +} diff --git a/platform/ev-aducrf101mkxz/leds-arch.c b/platform/ev-aducrf101mkxz/leds-arch.c new file mode 100644 index 000000000..2a3f5a9c4 --- /dev/null +++ b/platform/ev-aducrf101mkxz/leds-arch.c @@ -0,0 +1,79 @@ +/** + * Copyright (c) 2014, Analog Devices, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** + * \author Jim Paris + */ + +#include "contiki.h" +#include "dev/leds.h" +#include "platform-conf.h" +#include "aducrf101-contiki.h" + +/* e.g. pADI_GP4 */ +#define GPIO CC_CONCAT(pADI_GP, LED_GPIO) + +/*---------------------------------------------------------------------------*/ +void +leds_arch_init(void) +{ + /* Set LED pin as a GPIO output */ + GPIO->GPOEN |= (1UL << LED_PIN); + leds_arch_set(0); +} +/*---------------------------------------------------------------------------*/ +unsigned char +leds_arch_get(void) +{ + if(GPIO->GPOUT & (1UL << LED_PIN)) { + return 0; + } else { + return 1; + } +} +/*---------------------------------------------------------------------------*/ +void +leds_arch_set(unsigned char leds) +{ + if(leds & 1) { + GPIO->GPCLR = (1UL << LED_PIN); + } else { + GPIO->GPSET = (1UL << LED_PIN); + } +} +/*---------------------------------------------------------------------------*/ + +/** + * @} + * @} + */ diff --git a/platform/ev-aducrf101mkxz/platform-conf.h b/platform/ev-aducrf101mkxz/platform-conf.h new file mode 100644 index 000000000..6842aaa5a --- /dev/null +++ b/platform/ev-aducrf101mkxz/platform-conf.h @@ -0,0 +1,48 @@ +/** + * Copyright (c) 2014, Analog Devices, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted (subject to the limitations in the + * disclaimer below) provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE + * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** + * \author Jim Paris + */ + +#ifndef __ADUCRF101_PLATFORM_CONF_H__ +#define __ADUCRF101_PLATFORM_CONF_H__ + +#define LED_GPIO 4 +#define LED_PIN 2 + +#define BUTTON_GPIO 0 +#define BUTTON_PIN 6 +#define BUTTON_INT 2 + +#endif diff --git a/regression-tests/18-compile-arm-ports/Makefile b/regression-tests/18-compile-arm-ports/Makefile new file mode 100644 index 000000000..2de35da6d --- /dev/null +++ b/regression-tests/18-compile-arm-ports/Makefile @@ -0,0 +1,13 @@ +EXAMPLESDIR=../../examples +TOOLSDIR=../../tools + +EXAMPLES = \ +hello-world/ev-aducrf101mkxz \ +ipv6/rpl-border-router/ev-aducrf101mkxz \ +webserver-ipv6/ev-aducrf101mkxz \ +ipv6/multicast/ev-aducrf101mkxz \ +cc2538dk/sniffer/ev-aducrf101mkxz \ + +TOOLS= + +include ../Makefile.compile-test