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split hw config into platform-conf and adapted to new SPI and CC2420 naming

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This commit is contained in:
joxe 2010-06-23 10:18:05 +00:00
parent f7a82a9145
commit 80942abaf7
3 changed files with 228 additions and 178 deletions
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158
platform/sky/contiki-conf.h
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@ -1,10 +1,10 @@
/* -*- C -*- */ /* -*- C -*- */
/* @(#)$Id: contiki-conf.h,v 1.81 2010/06/21 19:57:18 joxe Exp $ */ /* @(#)$Id: contiki-conf.h,v 1.82 2010/06/23 10:18:05 joxe Exp $ */
#ifndef CONTIKI_CONF_H #ifndef CONTIKI_CONF_H
#define CONTIKI_CONF_H #define CONTIKI_CONF_H
#include "platform-conf.h"
#if WITH_UIP6 #if WITH_UIP6
@ -14,7 +14,6 @@
/* #define NETSTACK_CONF_RDC sicslowmac_driver */ /* #define NETSTACK_CONF_RDC sicslowmac_driver */
#define NETSTACK_CONF_MAC csma_driver #define NETSTACK_CONF_MAC csma_driver
#define NETSTACK_CONF_RDC contikimac_driver #define NETSTACK_CONF_RDC contikimac_driver
#define NETSTACK_CONF_RADIO cc2420_driver
#define NETSTACK_CONF_FRAMER framer_802154 #define NETSTACK_CONF_FRAMER framer_802154
#define CC2420_CONF_AUTOACK 1 #define CC2420_CONF_AUTOACK 1
@ -32,7 +31,6 @@
#define NETSTACK_CONF_NETWORK rime_driver #define NETSTACK_CONF_NETWORK rime_driver
#define NETSTACK_CONF_MAC csma_driver #define NETSTACK_CONF_MAC csma_driver
#define NETSTACK_CONF_RDC contikimac_driver #define NETSTACK_CONF_RDC contikimac_driver
#define NETSTACK_CONF_RADIO cc2420_driver
#define NETSTACK_CONF_FRAMER framer_802154 #define NETSTACK_CONF_FRAMER framer_802154
#define CC2420_CONF_AUTOACK 1 #define CC2420_CONF_AUTOACK 1
@ -56,7 +54,6 @@
#define PACKETBUF_CONF_ATTRS_INLINE 1 #define PACKETBUF_CONF_ATTRS_INLINE 1
#define CC2420_CONF_SYMBOL_LOOP_COUNT 800
#ifndef RF_CHANNEL #ifndef RF_CHANNEL
#define RF_CHANNEL 26 #define RF_CHANNEL 26
#endif /* RF_CHANNEL */ #endif /* RF_CHANNEL */
@ -68,52 +65,22 @@
#define SHELL_VARS_CONF_RAM_BEGIN 0x1100 #define SHELL_VARS_CONF_RAM_BEGIN 0x1100
#define SHELL_VARS_CONF_RAM_END 0x2000 #define SHELL_VARS_CONF_RAM_END 0x2000
/* DCO speed resynchronization for more robust UART, etc. */
#define DCOSYNCH_CONF_ENABLED 1
#define DCOSYNCH_CONF_PERIOD 30
#define CFS_CONF_OFFSET_TYPE long
#define PROFILE_CONF_ON 0 #define PROFILE_CONF_ON 0
#define ENERGEST_CONF_ON 1 #define ENERGEST_CONF_ON 1
#define HAVE_STDINT_H
#define MSP430_MEMCPY_WORKAROUND 1
#include "msp430def.h"
#define ELFLOADER_CONF_TEXT_IN_ROM 0 #define ELFLOADER_CONF_TEXT_IN_ROM 0
#define ELFLOADER_CONF_DATAMEMORY_SIZE 0x400 #define ELFLOADER_CONF_DATAMEMORY_SIZE 0x400
#define ELFLOADER_CONF_TEXTMEMORY_SIZE 0x800 #define ELFLOADER_CONF_TEXTMEMORY_SIZE 0x800
#define IRQ_PORT1 0x01
#define IRQ_PORT2 0x02
#define IRQ_ADC 0x03
#define CCIF
#define CLIF
#define CC_CONF_INLINE inline
#define AODV_COMPLIANCE #define AODV_COMPLIANCE
#define AODV_NUM_RT_ENTRIES 32 #define AODV_NUM_RT_ENTRIES 32
#define TMOTE_SKY 1
#define WITH_ASCII 1 #define WITH_ASCII 1
#define PROCESS_CONF_NUMEVENTS 8 #define PROCESS_CONF_NUMEVENTS 8
#define PROCESS_CONF_STATS 1 #define PROCESS_CONF_STATS 1
/*#define PROCESS_CONF_FASTPOLL 4*/ /*#define PROCESS_CONF_FASTPOLL 4*/
/* CPU target speed in Hz */
#define F_CPU 3900000uL /*2457600uL*/
/* Our clock resolution, this is the same as Unix HZ. */
#define CLOCK_CONF_SECOND 128UL
#define BAUD2UBR(baud) ((F_CPU/baud))
#ifdef WITH_UIP6 #ifdef WITH_UIP6
#define RIMEADDR_CONF_SIZE 8 #define RIMEADDR_CONF_SIZE 8
@ -177,127 +144,6 @@
#define UIP_CONF_TCP_SPLIT 0 #define UIP_CONF_TCP_SPLIT 0
/*
* Definitions below are dictated by the hardware and not really
* changeable!
*/
/* LED ports */
#define LEDS_PxDIR P5DIR
#define LEDS_PxOUT P5OUT
#define LEDS_CONF_RED 0x10
#define LEDS_CONF_GREEN 0x20
#define LEDS_CONF_YELLOW 0x40
/* Button sensors. */
#define IRQ_PORT2 0x02
typedef unsigned short uip_stats_t;
typedef unsigned long clock_time_t;
typedef unsigned long off_t;
#define ROM_ERASE_UNIT_SIZE 512
#define XMEM_ERASE_UNIT_SIZE (64*1024L)
/* Use the first 64k of external flash for node configuration */
#define NODE_ID_XMEM_OFFSET (0 * XMEM_ERASE_UNIT_SIZE)
/* Use the second 64k of external flash for codeprop. */
#define EEPROMFS_ADDR_CODEPROP (1 * XMEM_ERASE_UNIT_SIZE)
#define CFS_XMEM_CONF_OFFSET (2 * XMEM_ERASE_UNIT_SIZE)
#define CFS_XMEM_CONF_SIZE (1 * XMEM_ERASE_UNIT_SIZE)
#define CFS_RAM_CONF_SIZE 4096
/*
* SPI bus configuration for the TMote Sky.
*/
/* SPI input/output registers. */
#define SPI_TXBUF U0TXBUF
#define SPI_RXBUF U0RXBUF
/* USART0 Tx ready? */
#define SPI_WAITFOREOTx() while ((U0TCTL & TXEPT) == 0)
/* USART0 Rx ready? */
#define SPI_WAITFOREORx() while ((IFG1 & URXIFG0) == 0)
/* USART0 Tx buffer ready? */
#define SPI_WAITFORTxREADY() while ((IFG1 & UTXIFG0) == 0)
#define SCK 1 /* P3.1 - Output: SPI Serial Clock (SCLK) */
#define MOSI 2 /* P3.2 - Output: SPI Master out - slave in (MOSI) */
#define MISO 3 /* P3.3 - Input: SPI Master in - slave out (MISO) */
/*
* SPI bus - M25P80 external flash configuration.
*/
#define FLASH_PWR 3 /* P4.3 Output */
#define FLASH_CS 4 /* P4.4 Output */
#define FLASH_HOLD 7 /* P4.7 Output */
/* Enable/disable flash access to the SPI bus (active low). */
#define SPI_FLASH_ENABLE() ( P4OUT &= ~BV(FLASH_CS) )
#define SPI_FLASH_DISABLE() ( P4OUT |= BV(FLASH_CS) )
#define SPI_FLASH_HOLD() ( P4OUT &= ~BV(FLASH_HOLD) )
#define SPI_FLASH_UNHOLD() ( P4OUT |= BV(FLASH_HOLD) )
/*
* SPI bus - CC2420 pin configuration.
*/
#define FIFO_P 0 /* P1.0 - Input: FIFOP from CC2420 */
#define FIFO 3 /* P1.3 - Input: FIFO from CC2420 */
#define CCA 4 /* P1.4 - Input: CCA from CC2420 */
#define SFD 1 /* P4.1 - Input: SFD from CC2420 */
#define CSN 2 /* P4.2 - Output: SPI Chip Select (CS_N) */
#define VREG_EN 5 /* P4.5 - Output: VREG_EN to CC2420 */
#define RESET_N 6 /* P4.6 - Output: RESET_N to CC2420 */
/* Pin status. */
#define FIFO_IS_1 (!!(P1IN & BV(FIFO)))
#define CCA_IS_1 (!!(P1IN & BV(CCA) ))
#define RESET_IS_1 (!!(P4IN & BV(RESET_N)))
#define VREG_IS_1 (!!(P4IN & BV(VREG_EN)))
#define FIFOP_IS_1 (!!(P1IN & BV(FIFO_P)))
#define SFD_IS_1 (!!(P4IN & BV(SFD)))
/* The CC2420 reset pin. */
#define SET_RESET_INACTIVE() ( P4OUT |= BV(RESET_N) )
#define SET_RESET_ACTIVE() ( P4OUT &= ~BV(RESET_N) )
/* CC2420 voltage regulator enable pin. */
#define SET_VREG_ACTIVE() ( P4OUT |= BV(VREG_EN) )
#define SET_VREG_INACTIVE() ( P4OUT &= ~BV(VREG_EN) )
/* CC2420 rising edge trigger for external interrupt 0 (FIFOP). */
#define FIFOP_INT_INIT() do {\
P1IES &= ~BV(FIFO_P);\
CLEAR_FIFOP_INT();\
} while (0)
/* FIFOP on external interrupt 0. */
#define ENABLE_FIFOP_INT() do { P1IE |= BV(FIFO_P); } while (0)
#define DISABLE_FIFOP_INT() do { P1IE &= ~BV(FIFO_P); } while (0)
#define CLEAR_FIFOP_INT() do { P1IFG &= ~BV(FIFO_P); } while (0)
/* Enables/disables CC2420 access to the SPI bus (not the bus).
*
* These guys should really be renamed but are compatible with the
* original Chipcon naming.
*
* SPI_CC2420_ENABLE/SPI_CC2420_DISABLE???
* CC2420_ENABLE_SPI/CC2420_DISABLE_SPI???
*/
#define SPI_ENABLE() ( P4OUT &= ~BV(CSN) ) /* ENABLE CSn (active low) */
#define SPI_DISABLE() ( P4OUT |= BV(CSN) ) /* DISABLE CSn (active low) */
#define SPI_IS_ENABLED() ( (P4OUT & BV(CSN)) != BV(CSN) )
#ifdef PROJECT_CONF_H #ifdef PROJECT_CONF_H
#include PROJECT_CONF_H #include PROJECT_CONF_H

42
platform/sky/dev/xmem.c
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@ -26,7 +26,7 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE. * SUCH DAMAGE.
* *
* @(#)$Id: xmem.c,v 1.10 2009/09/07 11:31:26 nifi Exp $ * @(#)$Id: xmem.c,v 1.11 2010/06/23 10:18:05 joxe Exp $
*/ */
/** /**
@ -77,8 +77,7 @@ write_enable(void)
s = splhigh(); s = splhigh();
SPI_FLASH_ENABLE(); SPI_FLASH_ENABLE();
FASTSPI_TX(SPI_FLASH_INS_WREN); SPI_WRITE(SPI_FLASH_INS_WREN);
SPI_WAITFORTx_ENDED();
SPI_FLASH_DISABLE(); SPI_FLASH_DISABLE();
splx(s); splx(s);
@ -94,11 +93,10 @@ read_status_register(void)
s = splhigh(); s = splhigh();
SPI_FLASH_ENABLE(); SPI_FLASH_ENABLE();
FASTSPI_TX(SPI_FLASH_INS_RDSR); SPI_WRITE(SPI_FLASH_INS_RDSR);
SPI_WAITFORTx_ENDED();
FASTSPI_CLEAR_RX(); SPI_FLUSH();
FASTSPI_RX(u); SPI_READ(u);
SPI_FLASH_DISABLE(); SPI_FLASH_DISABLE();
splx(s); splx(s);
@ -133,10 +131,10 @@ erase_sector(unsigned long offset)
s = splhigh(); s = splhigh();
SPI_FLASH_ENABLE(); SPI_FLASH_ENABLE();
FASTSPI_TX(SPI_FLASH_INS_SE); SPI_WRITE_FAST(SPI_FLASH_INS_SE);
FASTSPI_TX(offset >> 16); /* MSB */ SPI_WRITE_FAST(offset >> 16); /* MSB */
FASTSPI_TX(offset >> 8); SPI_WRITE_FAST(offset >> 8);
FASTSPI_TX(offset >> 0); /* LSB */ SPI_WRITE_FAST(offset >> 0); /* LSB */
SPI_WAITFORTx_ENDED(); SPI_WAITFORTx_ENDED();
SPI_FLASH_DISABLE(); SPI_FLASH_DISABLE();
@ -171,16 +169,16 @@ xmem_pread(void *_p, int size, unsigned long offset)
s = splhigh(); s = splhigh();
SPI_FLASH_ENABLE(); SPI_FLASH_ENABLE();
FASTSPI_TX(SPI_FLASH_INS_READ); SPI_WRITE_FAST(SPI_FLASH_INS_READ);
FASTSPI_TX(offset >> 16); /* MSB */ SPI_WRITE_FAST(offset >> 16); /* MSB */
FASTSPI_TX(offset >> 8); SPI_WRITE_FAST(offset >> 8);
FASTSPI_TX(offset >> 0); /* LSB */ SPI_WRITE_FAST(offset >> 0); /* LSB */
SPI_WAITFORTx_ENDED(); SPI_WAITFORTx_ENDED();
FASTSPI_CLEAR_RX(); SPI_FLUSH();
for(; p < end; p++) { for(; p < end; p++) {
unsigned char u; unsigned char u;
FASTSPI_RX(u); SPI_READ(u);
*p = ~u; *p = ~u;
} }
@ -205,13 +203,13 @@ program_page(unsigned long offset, const unsigned char *p, int nbytes)
s = splhigh(); s = splhigh();
SPI_FLASH_ENABLE(); SPI_FLASH_ENABLE();
FASTSPI_TX(SPI_FLASH_INS_PP); SPI_WRITE_FAST(SPI_FLASH_INS_PP);
FASTSPI_TX(offset >> 16); /* MSB */ SPI_WRITE_FAST(offset >> 16); /* MSB */
FASTSPI_TX(offset >> 8); SPI_WRITE_FAST(offset >> 8);
FASTSPI_TX(offset >> 0); /* LSB */ SPI_WRITE_FAST(offset >> 0); /* LSB */
for(; p < end; p++) { for(; p < end; p++) {
FASTSPI_TX(~*p); SPI_WRITE_FAST(~*p);
} }
SPI_WAITFORTx_ENDED(); SPI_WAITFORTx_ENDED();

206
platform/sky/platform-conf.h Normal file
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@ -0,0 +1,206 @@
/*
* Copyright (c) 2010, Swedish Institute of Computer Science.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the Institute nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: platform-conf.h,v 1.1 2010/06/23 10:18:05 joxe Exp $
*/
/**
* \file
* A brief description of what this file is
* \author
* Niclas Finne <nfi@sics.se>
* Joakim Eriksson <joakime@sics.se>
*/
#ifndef __PLATFORM_CONF_H__
#define __PLATFORM_CONF_H__
/*
* Definitions below are dictated by the hardware and not really
* changeable!
*/
/* Platform TMOTE_SKY */
#define TMOTE_SKY 1
/* CPU target speed in Hz */
#define F_CPU 3900000uL /*2457600uL*/
/* Our clock resolution, this is the same as Unix HZ. */
#define CLOCK_CONF_SECOND 128UL
#define BAUD2UBR(baud) ((F_CPU/baud))
#define CCIF
#define CLIF
#define CC_CONF_INLINE inline
#define HAVE_STDINT_H
#define MSP430_MEMCPY_WORKAROUND 1
#include "msp430def.h"
/* Types for clocks and uip_stats */
typedef unsigned short uip_stats_t;
typedef unsigned long clock_time_t;
typedef unsigned long off_t;
/* the low-level radio driver */
#define NETSTACK_CONF_RADIO cc2420_driver
/* LED ports */
#define LEDS_PxDIR P5DIR
#define LEDS_PxOUT P5OUT
#define LEDS_CONF_RED 0x10
#define LEDS_CONF_GREEN 0x20
#define LEDS_CONF_YELLOW 0x40
/* DCO speed resynchronization for more robust UART, etc. */
#define DCOSYNCH_CONF_ENABLED 1
#define DCOSYNCH_CONF_PERIOD 30
#define ROM_ERASE_UNIT_SIZE 512
#define XMEM_ERASE_UNIT_SIZE (64*1024L)
#define CFS_CONF_OFFSET_TYPE long
/* Use the first 64k of external flash for node configuration */
#define NODE_ID_XMEM_OFFSET (0 * XMEM_ERASE_UNIT_SIZE)
/* Use the second 64k of external flash for codeprop. */
#define EEPROMFS_ADDR_CODEPROP (1 * XMEM_ERASE_UNIT_SIZE)
#define CFS_XMEM_CONF_OFFSET (2 * XMEM_ERASE_UNIT_SIZE)
#define CFS_XMEM_CONF_SIZE (1 * XMEM_ERASE_UNIT_SIZE)
#define CFS_RAM_CONF_SIZE 4096
/*
* SPI bus configuration for the TMote Sky.
*/
/* SPI input/output registers. */
#define SPI_TXBUF U0TXBUF
#define SPI_RXBUF U0RXBUF
/* USART0 Tx ready? */
#define SPI_WAITFOREOTx() while ((U0TCTL & TXEPT) == 0)
/* USART0 Rx ready? */
#define SPI_WAITFOREORx() while ((IFG1 & URXIFG0) == 0)
/* USART0 Tx buffer ready? */
#define SPI_WAITFORTxREADY() while ((IFG1 & UTXIFG0) == 0)
#define SCK 1 /* P3.1 - Output: SPI Serial Clock (SCLK) */
#define MOSI 2 /* P3.2 - Output: SPI Master out - slave in (MOSI) */
#define MISO 3 /* P3.3 - Input: SPI Master in - slave out (MISO) */
/*
* SPI bus - M25P80 external flash configuration.
*/
#define FLASH_PWR 3 /* P4.3 Output */
#define FLASH_CS 4 /* P4.4 Output */
#define FLASH_HOLD 7 /* P4.7 Output */
/* Enable/disable flash access to the SPI bus (active low). */
#define SPI_FLASH_ENABLE() ( P4OUT &= ~BV(FLASH_CS) )
#define SPI_FLASH_DISABLE() ( P4OUT |= BV(FLASH_CS) )
#define SPI_FLASH_HOLD() ( P4OUT &= ~BV(FLASH_HOLD) )
#define SPI_FLASH_UNHOLD() ( P4OUT |= BV(FLASH_HOLD) )
/*
* SPI bus - CC2420 pin configuration.
*/
#define CC2420_CONF_SYMBOL_LOOP_COUNT 800
/* P1.0 - Input: FIFOP from CC2420 */
#define CC2420_FIFOP_PORT(type) P1##type
#define CC2420_FIFOP_PIN 0
/* P1.3 - Input: FIFO from CC2420 */
#define CC2420_FIFO_PORT(type) P1##type
#define CC2420_FIFO_PIN 3
/* P1.4 - Input: CCA from CC2420 */
#define CC2420_CCA_PORT(type) P1##type
#define CC2420_CCA_PIN 4
/* P4.1 - Input: SFD from CC2420 */
#define CC2420_SFD_PORT(type) P4##type
#define CC2420_SFD_PIN 1
/* P4.2 - Output: SPI Chip Select (CS_N) */
#define CC2420_CSN_PORT(type) P4##type
#define CC2420_CSN_PIN 2
/* P4.5 - Output: VREG_EN to CC2420 */
#define CC2420_VREG_PORT(type) P4##type
#define CC2420_VREG_PIN 5
/* P4.6 - Output: RESET_N to CC2420 */
#define CC2420_RESET_PORT(type) P4##type
#define CC2420_RESET_PIN 6
#define CC2420_IRQ_VECTOR PORT1_VECTOR
/* Pin status. */
#define CC2420_FIFOP_IS_1 (!!(CC2420_FIFOP_PORT(IN) & BV(CC2420_FIFOP_PIN)))
#define CC2420_FIFO_IS_1 (!!(CC2420_FIFO_PORT(IN) & BV(CC2420_FIFO_PIN)))
#define CC2420_CCA_IS_1 (!!(CC2420_CCA_PORT(IN) & BV(CC2420_CCA_PIN)))
#define CC2420_SFD_IS_1 (!!(CC2420_SFD_PORT(IN) & BV(CC2420_SFD_PIN)))
/* The CC2420 reset pin. */
#define SET_RESET_INACTIVE() (CC2420_RESET_PORT(OUT) |= BV(CC2420_RESET_PIN))
#define SET_RESET_ACTIVE() (CC2420_RESET_PORT(OUT) &= ~BV(CC2420_RESET_PIN))
/* CC2420 voltage regulator enable pin. */
#define SET_VREG_ACTIVE() (CC2420_VREG_PORT(OUT) |= BV(CC2420_VREG_PIN))
#define SET_VREG_INACTIVE() (CC2420_VREG_PORT(OUT) &= ~BV(CC2420_VREG_PIN))
/* CC2420 rising edge trigger for external interrupt 0 (FIFOP). */
#define CC2420_FIFOP_INT_INIT() do { \
CC2420_FIFOP_PORT(IES) &= ~BV(CC2420_FIFOP_PIN); \
CC2420_CLEAR_FIFOP_INT(); \
} while(0)
/* FIFOP on external interrupt 0. */
#define CC2420_ENABLE_FIFOP_INT() do {CC2420_FIFOP_PORT(IE) |= BV(CC2420_FIFOP_PIN);} while(0)
#define CC2420_DISABLE_FIFOP_INT() do {CC2420_FIFOP_PORT(IE) &= ~BV(CC2420_FIFOP_PIN);} while(0)
#define CC2420_CLEAR_FIFOP_INT() do {CC2420_FIFOP_PORT(IFG) &= ~BV(CC2420_FIFOP_PIN);} while(0)
/*
* Enables/disables CC2420 access to the SPI bus (not the bus).
* (Chip Select)
*/
/* ENABLE CSn (active low) */
#define CC2420_SPI_ENABLE() (CC2420_CSN_PORT(OUT) &= ~BV(CC2420_CSN_PIN))
/* DISABLE CSn (active low) */
#define CC2420_SPI_DISABLE() (CC2420_CSN_PORT(OUT) |= BV(CC2420_CSN_PIN))
#define CC2420_SPI_IS_ENABLED() ((CC2420_CSN_PORT(OUT) & BV(CC2420_CSN_PIN)) != BV(CC2420_CSN_PIN))
#endif /* __PLATFORM_CONF_H__ */