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@ -48,35 +48,35 @@ static void (*callbacks[DMA_LINES])(void);
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interrupt(DACDMA_VECTOR) irq_dacdma(void)
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interrupt(DACDMA_VECTOR) irq_dacdma(void)
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{
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{
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if (DMA0CTL & DMAIFG) {
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if(DMA0CTL & DMAIFG) {
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DMA0CTL &= ~(DMAIFG | DMAIE);
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DMA0CTL &= ~(DMAIFG | DMAIE);
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if (callbacks[0] != NULL) {
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if(callbacks[0] != NULL) {
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callbacks[0]();
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callbacks[0]();
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}
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}
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LPM_AWAKE();
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LPM_AWAKE();
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}
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}
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if (DMA1CTL & DMAIFG) {
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if(DMA1CTL & DMAIFG) {
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DMA1CTL &= ~(DMAIFG | DMAIE);
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DMA1CTL &= ~(DMAIFG | DMAIE);
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if (callbacks[1] != NULL) {
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if(callbacks[1] != NULL) {
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callbacks[1]();
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callbacks[1]();
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}
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}
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LPM_AWAKE();
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LPM_AWAKE();
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}
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}
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if (DMA2CTL & DMAIFG) {
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if(DMA2CTL & DMAIFG) {
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DMA2CTL &= ~(DMAIFG | DMAIE);
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DMA2CTL &= ~(DMAIFG | DMAIE);
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if (callbacks[2] != NULL) {
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if(callbacks[2] != NULL) {
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callbacks[2]();
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callbacks[2]();
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}
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}
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LPM_AWAKE();
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LPM_AWAKE();
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}
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}
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if (DAC12_0CTL & DAC12IFG) {
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if(DAC12_0CTL & DAC12IFG) {
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DAC12_0CTL &= ~(DAC12IFG | DAC12IE);
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DAC12_0CTL &= ~(DAC12IFG | DAC12IE);
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}
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}
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if (DAC12_1CTL & DAC12IFG) {
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if(DAC12_1CTL & DAC12IFG) {
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DAC12_1CTL &= ~(DAC12IFG | DAC12IE);
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DAC12_1CTL &= ~(DAC12IFG | DAC12IE);
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}
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}
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}
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}
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@ -84,8 +84,9 @@ interrupt(DACDMA_VECTOR) irq_dacdma(void)
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int
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int
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dma_subscribe(int line, void (*callback)(void))
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dma_subscribe(int line, void (*callback)(void))
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{
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{
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if (line >= DMA_LINES)
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if(line >= DMA_LINES) {
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return -1;
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return -1;
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}
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callbacks[line] = callback;
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callbacks[line] = callback;
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return 0;
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return 0;
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@ -94,10 +95,10 @@ dma_subscribe(int line, void (*callback)(void))
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void
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void
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dma_transfer(unsigned char *dst, unsigned char *src, unsigned len)
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dma_transfer(unsigned char *dst, unsigned char *src, unsigned len)
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{
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{
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// Configure DMA Channel 0 for UART0 TXIFG.
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/* Configure DMA Channel 0 for UART0 TXIFG. */
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DMACTL0 = DMA0TSEL_4;
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DMACTL0 = DMA0TSEL_4;
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// No DMAONFETCH, ROUNDROBIN, ENNMI.
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/* No DMAONFETCH, ROUNDROBIN, ENNMI. */
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DMACTL1 = 0x0000;
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DMACTL1 = 0x0000;
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/*
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/*
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@ -116,6 +117,6 @@ dma_transfer(unsigned char *dst, unsigned char *src, unsigned len)
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DMA0DA = (unsigned) dst;
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DMA0DA = (unsigned) dst;
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DMA0SZ = len;
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DMA0SZ = len;
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DMA0CTL |= DMAEN | DMAIE; // enable DMA and interrupts
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DMA0CTL |= DMAEN | DMAIE; /* enable DMA and interrupts */
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U0CTL &= ~SWRST; // enable UART state machine, starts transfer
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U0CTL &= ~SWRST; /* enable the UART state machine */
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}
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}
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@ -60,7 +60,7 @@ Berlin, 2007
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void
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void
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infomem_read(void *buffer, unsigned int offset, unsigned char size)
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infomem_read(void *buffer, unsigned int offset, unsigned char size)
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{
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{
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uint8_t *address = (uint8_t *) INFOMEM_START + offset;
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uint8_t *address = (uint8_t *)INFOMEM_START + offset;
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memcpy(buffer, address, size);
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memcpy(buffer, address, size);
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}
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}
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@ -76,21 +76,22 @@ infomem_write(unsigned int offset, unsigned char count, ...)
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uint8_t *data;
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uint8_t *data;
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int s;
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int s;
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if (offset > (2 * INFOMEM_BLOCK_SIZE))
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if(offset > (2 * INFOMEM_BLOCK_SIZE)) {
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return FALSE;
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return FALSE;
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}
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flash = (uint8_t *) INFOMEM_START + offset;
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flash = (uint8_t *)INFOMEM_START + offset;
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s = splhigh();
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s = splhigh();
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// backup into RAM
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/* backup into RAM */
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memcpy(backup, flash, INFOMEM_BLOCK_SIZE);
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memcpy(backup, flash, INFOMEM_BLOCK_SIZE);
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// merge backup with new data
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/* merge backup with new data */
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va_start(argp, count);
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va_start(argp, count);
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buffer = (uint8_t *) backup;
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buffer = (uint8_t *)backup;
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for (i = 0; i < count; i++) {
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for(i = 0; i < count; i++) {
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data = va_arg(argp, uint8_t*);
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data = va_arg(argp, uint8_t*);
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size = va_arg(argp, uint16_t);
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size = va_arg(argp, uint16_t);
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memcpy(buffer, data, size);
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memcpy(buffer, data, size);
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@ -99,18 +100,18 @@ infomem_write(unsigned int offset, unsigned char count, ...)
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va_end(argp);
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va_end(argp);
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// init flash access
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/* init flash access */
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FCTL2 = FWKEY + FSSEL1 + FN2;
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FCTL2 = FWKEY + FSSEL1 + FN2;
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FCTL3 = FWKEY;
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FCTL3 = FWKEY;
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// erase flash
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/* erase flash */
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FCTL1 = FWKEY + ERASE;
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FCTL1 = FWKEY + ERASE;
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*flash = 0;
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*flash = 0;
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// write flash
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/* write flash */
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FCTL1 = FWKEY + WRT;
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FCTL1 = FWKEY + WRT;
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buffer = (uint8_t *) backup;
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buffer = (uint8_t *)backup;
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for (i = 0; i < INFOMEM_BLOCK_SIZE; i++) {
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for(i = 0; i < INFOMEM_BLOCK_SIZE; i++) {
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*flash++ = *buffer++;
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*flash++ = *buffer++;
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}
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}
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@ -69,73 +69,71 @@ volatile uint8_t uart_edge = 0;
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static unsigned char uart_speed_br0[UART_NUM_MODES];
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static unsigned char uart_speed_br0[UART_NUM_MODES];
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static unsigned char uart_speed_br1[UART_NUM_MODES];
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static unsigned char uart_speed_br1[UART_NUM_MODES];
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static unsigned char uart_speed_bmn[UART_NUM_MODES];
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static unsigned char uart_speed_bmn[UART_NUM_MODES];
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static fp_uart_handler uart_handler[UART_NUM_MODES] = {NULL, NULL};
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static uart_handler_t uart_handler[UART_NUM_MODES] = {NULL, NULL};
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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static void
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static void
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uart_configure(unsigned mode)
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uart_configure(unsigned mode)
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{
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{
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_DINT(); // disable interrupts
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_DINT(); /* disable interrupts */
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UART_WAIT_TXDONE(); // wait till all buffered data has been transmitted
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UART_WAIT_TXDONE(); /* wait till all buffered data has been transmitted */
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// configure
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if(mode == UART_MODE_RS232) {
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if(mode == UART_MODE_RS232) {
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P5OUT |= 0x01;
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P5OUT |= 0x01;
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// unselect SPI
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/* unselect SPI */
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P3SEL |= 0xC0;
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P3SEL |= 0xC0;
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// select rs232
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/* select rs232 */
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// to RS232 mode
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UCTL1 = SWRST | CHAR; /* 8-bit character */
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UCTL1 = SWRST | CHAR; // 8-bit character
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UTCTL1 |= SSEL1; /* UCLK = MCLK */
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UTCTL1 |= SSEL1; // UCLK = MCLK
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/* activate */
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// activate
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U1ME |= UTXE1 | URXE1; /* Enable USART1 TXD/RXD */
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U1ME |= UTXE1 | URXE1; // Enable USART1 TXD/RXD
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} else if(mode == UART_MODE_SPI) {
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} else if(mode == UART_MODE_SPI) {
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P3SEL &= ~0xC0; // unselect RS232
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P3SEL &= ~0xC0; /* unselect RS232 */
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// to SPI mode
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// to SPI mode
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UCTL1 = SWRST | CHAR | SYNC | MM; // 8-bit SPI Master
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UCTL1 = SWRST | CHAR | SYNC | MM; /* 8-bit SPI Master */
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/*
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/*
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* SMCLK, 3-pin mode, clock idle low, data valid on
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* SMCLK, 3-pin mode, clock idle low, data valid on
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* rising edge, UCLK delayed
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* rising edge, UCLK delayed
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*/
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*/
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UTCTL1 |= CKPH | SSEL1 | SSEL0 | STC; // activate
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UTCTL1 |= CKPH | SSEL1 | SSEL0 | STC; /* activate */
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U1ME |= USPIE1; // Enable USART1 SPI
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U1ME |= USPIE1; /* Enable USART1 SPI */
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}
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}
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// restore speed settings
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/* restore speed settings */
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UBR01 = uart_speed_br0[mode]; // set baudrate
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UBR01 = uart_speed_br0[mode]; /* set baudrate */
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UBR11 = uart_speed_br1[mode];
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UBR11 = uart_speed_br1[mode];
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UMCTL1 = uart_speed_bmn[mode]; // set modulation
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UMCTL1 = uart_speed_bmn[mode]; /* set modulation */
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UCTL1 &= ~SWRST; // clear reset flag
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UCTL1 &= ~SWRST; /* clear reset flag */
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_EINT(); // enable interrupts
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_EINT(); /* enable interrupts */
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}
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}
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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void
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void
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uart_set_speed(unsigned mode, unsigned ubr0,
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uart_set_speed(unsigned mode, unsigned ubr0,
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unsigned ubr1, unsigned umctl)
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unsigned ubr1, unsigned umctl)
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{
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{
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// store setting
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/* store the setting */
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uart_speed_br0[mode] = ubr0; // baudrate
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uart_speed_br0[mode] = ubr0; /* baudrate */
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uart_speed_br1[mode] = ubr1; // baudrate
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uart_speed_br1[mode] = ubr1; /* baudrate */
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uart_speed_bmn[mode] = umctl; // modulation
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uart_speed_bmn[mode] = umctl; /* modulation */
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// reconfigure, if mode active
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/* reconfigure, if mode active */
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if (uart_mode == mode) {
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if(uart_mode == mode) {
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uart_configure(mode);
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uart_configure(mode);
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}
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}
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}
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}
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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void
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void
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uart_set_handler(unsigned mode, fp_uart_handler fpHandler)
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uart_set_handler(unsigned mode, uart_handler_t handler)
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{
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{
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// store setting
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/* store the setting */
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uart_handler[mode] = fpHandler;
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uart_handler[mode] = handler;
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if(mode == uart_mode) {
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if(mode == uart_mode) {
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if (fpHandler == NULL) {
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if(handler == NULL) {
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IE2 &= ~URXIE1; // Disable USART1 RX interrupt
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IE2 &= ~URXIE1; /* Disable USART1 RX interrupt */
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} else {
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} else {
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IE2 |= URXIE1; // Enable USART1 RX interrupt
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IE2 |= URXIE1; /* Enable USART1 RX interrupt */
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}
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}
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}
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}
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}
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}
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@ -143,14 +141,14 @@ uart_set_handler(unsigned mode, fp_uart_handler fpHandler)
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int
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int
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uart_lock(unsigned mode)
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uart_lock(unsigned mode)
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{
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{
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// already locked?
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/* already locked? */
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if(uart_mode != mode && uart_lockcnt > 0) {
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if(uart_mode != mode && uart_lockcnt > 0) {
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return 0;
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return 0;
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}
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}
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// increase lock count
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/* increase lock count */
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uart_lockcnt++;
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uart_lockcnt++;
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// switch mode (if neccessary)
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/* switch mode (if neccessary) */
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uart_set_mode(mode);
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uart_set_mode(mode);
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return 1;
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return 1;
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}
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}
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@ -173,10 +171,10 @@ uart_unlock(unsigned mode)
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return 0;
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return 0;
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}
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}
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// decrement lock
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/* decrement lock */
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if (uart_lockcnt > 0) {
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if(uart_lockcnt > 0) {
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uart_lockcnt--;
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uart_lockcnt--;
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// if no more locks, switch back to default mode
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/* if no more locks, switch back to default mode */
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if(uart_lockcnt == 0) {
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if(uart_lockcnt == 0) {
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uart_set_mode(UART_MODE_DEFAULT);
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uart_set_mode(UART_MODE_DEFAULT);
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}
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}
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@ -188,17 +186,17 @@ uart_unlock(unsigned mode)
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void
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void
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uart_set_mode(unsigned mode)
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uart_set_mode(unsigned mode)
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{
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{
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// do nothing if mode already set
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/* do nothing if the mode is already set */
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if(mode == uart_mode) {
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if(mode == uart_mode) {
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return;
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return;
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}
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}
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IE2 &= ~(URXIE1 | UTXIE1); // disable irq
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IE2 &= ~(URXIE1 | UTXIE1); /* disable irq */
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uart_configure(mode); // configure uart parameters
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uart_configure(mode); /* configure uart parameters */
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uart_mode = mode;
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uart_mode = mode;
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if(uart_handler[mode] != NULL) {
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if(uart_handler[mode] != NULL) {
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IE2 |= URXIE1; // Enable USART1 RX interrupt
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IE2 |= URXIE1; /* Enable USART1 RX interrupt */
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}
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}
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}
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}
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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@ -211,11 +209,11 @@ uart_get_mode(void)
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interrupt(UART1RX_VECTOR)
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interrupt(UART1RX_VECTOR)
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uart_rx(void)
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uart_rx(void)
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{
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{
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fp_uart_handler handler = uart_handler[uart_mode];
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uart_handler_t handler = uart_handler[uart_mode];
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int c;
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int c;
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if(!(IFG2 & URXIFG1)) {
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if(!(IFG2 & URXIFG1)) {
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// If start edge detected, toggle & return
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/* If rising edge is detected, toggle & return */
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uart_edge = 1;
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uart_edge = 1;
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U1TCTL &= ~URXSE;
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U1TCTL &= ~URXSE;
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U1TCTL |= URXSE;
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U1TCTL |= URXSE;
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@ -229,7 +227,7 @@ uart_rx(void)
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_BIC_SR_IRQ(LPM3_bits);
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_BIC_SR_IRQ(LPM3_bits);
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}
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}
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} else {
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} else {
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// read out the char to clear the I-flags, etc.
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/* read out the char to clear the interrupt flags. */
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c = UART_RX;
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c = UART_RX;
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}
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}
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}
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}
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@ -56,8 +56,8 @@ Berlin, 2007
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* \author Michael Baar <baar@inf.fu-berlin.de>
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* \author Michael Baar <baar@inf.fu-berlin.de>
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*/
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*/
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#ifndef MSB430_UART_H
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#ifndef MSB430_UART1_H
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#define MSB430_UART_H
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#define MSB430_UART1_H
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#define UART_RX RXBUF1
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#define UART_RX RXBUF1
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#define UART_TX TXBUF1
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#define UART_TX TXBUF1
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@ -84,10 +84,10 @@ extern volatile unsigned char uart_lockcnt;
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#define UART_MODE_RESET (0xFFu) ///< reset with current settings
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#define UART_MODE_RESET (0xFFu) ///< reset with current settings
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/** @} */
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/** @} */
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#define UART_WAIT_LOCK(x) ( (uart_mode != x ) && (uart_lockcnt) )
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#define UART_WAIT_LOCK(x) ((uart_mode != x) && (uart_lockcnt))
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#define UART_MODE_IS(x) ( uart_mode == x )
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#define UART_MODE_IS(x) (uart_mode == x)
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typedef int(*fp_uart_handler)(unsigned char);
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typedef int(*uart_handler_t)(unsigned char);
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/**
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/**
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* \brief Initialize the UART module
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* \brief Initialize the UART module
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@ -98,14 +98,14 @@ typedef int(*fp_uart_handler)(unsigned char);
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void uart_init(void);
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void uart_init(void);
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void uart_set_speed(unsigned, unsigned, unsigned, unsigned);
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void uart_set_speed(unsigned, unsigned, unsigned, unsigned);
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void uart_set_handler(unsigned, fp_uart_handler);
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void uart_set_handler(unsigned, uart_handler_t);
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int uart_lock(unsigned);
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int uart_lock(unsigned);
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int uart_lock_wait(unsigned);
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int uart_lock_wait(unsigned);
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int uart_unlock(unsigned);
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int uart_unlock(unsigned);
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void uart_set_mode(unsigned);
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void uart_set_mode(unsigned);
|
||||||
int uart_get_mode(void);
|
int uart_get_mode(void);
|
||||||
|
|
||||||
#endif /* !UART_H */
|
#endif /* !MSB430_UART1_H */
|
||||||
|
|
||||||
/** @} */
|
/** @} */
|
||||||
/** @} */
|
/** @} */
|
||||||
|
@ -28,7 +28,7 @@
|
|||||||
*
|
*
|
||||||
* This file is part of the Contiki operating system.
|
* This file is part of the Contiki operating system.
|
||||||
*
|
*
|
||||||
* @(#)$Id: rs232.c,v 1.8 2009/04/08 14:56:03 nvt-se Exp $
|
* @(#)$Id: rs232.c,v 1.9 2009/06/29 12:46:50 nvt-se Exp $
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/** \addtogroup esbrs232
|
/** \addtogroup esbrs232
|
||||||
@ -108,8 +108,8 @@ rs232_set_speed(enum rs232_speed speed)
|
|||||||
void
|
void
|
||||||
rs232_print(char *cptr)
|
rs232_print(char *cptr)
|
||||||
{
|
{
|
||||||
// lock UART for print operation
|
/* lock UART for the print operation */
|
||||||
if (uart_lock(UART_MODE_RS232)) {
|
if(uart_lock(UART_MODE_RS232)) {
|
||||||
while(*cptr != 0) {
|
while(*cptr != 0) {
|
||||||
rs232_send(*cptr);
|
rs232_send(*cptr);
|
||||||
++cptr;
|
++cptr;
|
||||||
@ -119,7 +119,7 @@ rs232_print(char *cptr)
|
|||||||
}
|
}
|
||||||
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
||||||
void
|
void
|
||||||
rs232_set_input(fp_uart_handler f)
|
rs232_set_input(uart_handler_t f)
|
||||||
{
|
{
|
||||||
uart_set_handler(UART_MODE_RS232, f);
|
uart_set_handler(UART_MODE_RS232, f);
|
||||||
}
|
}
|
||||||
|
@ -28,7 +28,7 @@
|
|||||||
*
|
*
|
||||||
* This file is part of the Contiki operating system.
|
* This file is part of the Contiki operating system.
|
||||||
*
|
*
|
||||||
* @(#)$Id: rs232.h,v 1.5 2009/03/12 12:23:22 nvt-se Exp $
|
* @(#)$Id: rs232.h,v 1.6 2009/06/29 12:46:50 nvt-se Exp $
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/** \addtogroup esb
|
/** \addtogroup esb
|
||||||
@ -84,7 +84,7 @@ void rs232_init(void);
|
|||||||
* take place. If the input handler returns zero, the CPU
|
* take place. If the input handler returns zero, the CPU
|
||||||
* is kept sleeping.
|
* is kept sleeping.
|
||||||
*/
|
*/
|
||||||
void rs232_set_input(fp_uart_handler f);
|
void rs232_set_input(uart_handler_t f);
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* \brief Configure the speed of the RS232 hardware
|
* \brief Configure the speed of the RS232 hardware
|
||||||
|
@ -23,7 +23,7 @@ putchar(int c)
|
|||||||
#define SLIP_END 0300
|
#define SLIP_END 0300
|
||||||
static char debug_frame = 0;
|
static char debug_frame = 0;
|
||||||
|
|
||||||
if (!debug_frame) { /* Start of debug output */
|
if(!debug_frame) { /* Start of debug output */
|
||||||
slip_arch_writeb(SLIP_END);
|
slip_arch_writeb(SLIP_END);
|
||||||
slip_arch_writeb('\r'); /* Type debug line == '\r' */
|
slip_arch_writeb('\r'); /* Type debug line == '\r' */
|
||||||
debug_frame = 1;
|
debug_frame = 1;
|
||||||
@ -35,7 +35,7 @@ putchar(int c)
|
|||||||
* Line buffered output, a newline marks the end of debug output and
|
* Line buffered output, a newline marks the end of debug output and
|
||||||
* implicitly flushes debug output.
|
* implicitly flushes debug output.
|
||||||
*/
|
*/
|
||||||
if (c == '\n') {
|
if(c == '\n') {
|
||||||
slip_arch_writeb(SLIP_END);
|
slip_arch_writeb(SLIP_END);
|
||||||
debug_frame = 0;
|
debug_frame = 0;
|
||||||
}
|
}
|
||||||
|
Loading…
Reference in New Issue
Block a user