From a5046e83c7b35a3c8a826b3970553e9566bdab17 Mon Sep 17 00:00:00 2001 From: Adam Dunkels Date: Fri, 15 Mar 2013 16:14:09 +0100 Subject: [PATCH] Cleanup and refactoring of the STM32w port This is a general cleanup of things like code style issues and code structure of the STM32w port to make it more like the rest of Contiki is structured. --- cpu/stm32w108/Makefile.stm32w108 | 36 +- cpu/stm32w108/board-sensors.h | 49 +- cpu/stm32w108/cfs-coffee-arch.c | 269 +- cpu/stm32w108/cfs-coffee-arch.h | 63 +- cpu/stm32w108/clock.c | 103 +- .../{cortexm3_macro.h => cortexm3-macro.h} | 23 +- cpu/stm32w108/dev/stm32w-conf.h | 227 ++ cpu/stm32w108/dev/stm32w-radio.c | 645 ++--- cpu/stm32w108/dev/stm32w-radio.h | 17 +- cpu/stm32w108/dev/stm32w-systick.c | 150 ++ .../{stm32w_systick.h => stm32w-systick.h} | 63 +- cpu/stm32w108/dev/stm32w_conf.h | 174 -- cpu/stm32w108/dev/stm32w_systick.c | 181 -- cpu/stm32w108/dev/uart1-putchar.c | 79 +- cpu/stm32w108/dev/uart1.c | 164 +- cpu/stm32w108/dev/uart1.h | 16 +- cpu/stm32w108/e_stdio/Makefile | 8 +- .../src/{small_dtoa.c => small-dtoa.c} | 10 +- .../src/{small_mprec.c => small-mprec.c} | 2 +- .../src/{small_mprec.h => small-mprec.h} | 0 .../src/{small_strtod.c => small-strtod.c} | 10 +- .../{small_vfsscanf.c => small-vfsscanf.c} | 0 .../src/{small_wcrtomb.c => small-wcrtomb.c} | 0 .../{small_wcsrtombs.c => small-wcsrtombs.c} | 0 .../{small_wctomb_r.c => small-wctomb-r.c} | 0 .../e_stdio/src/{_SP_printf.c => sp-printf.c} | 0 .../e_stdio/src/{_SP_puts.c => sp-puts.c} | 0 .../src/{_SP_snprintf.c => sp-snprintf.c} | 4 +- .../src/{_SP_sprintf.c => sp-sprintf.c} | 0 .../src/{_SP_vfprintf.c => sp-vfprintf.c} | 0 .../e_stdio/src/{test_mes.c => test-mes.c} | 0 .../src/{test_printf.c => test-printf.c} | 0 .../src/{test_scanf.c => test-scanf.c} | 0 cpu/stm32w108/elfloader-arch.c | 151 +- cpu/stm32w108/hal/error.h | 2 +- cpu/stm32w108/hal/micro/adc.h | 22 +- cpu/stm32w108/hal/micro/button.h | 4 +- cpu/stm32w108/hal/micro/cortexm3/adc.c | 60 +- cpu/stm32w108/hal/micro/cortexm3/board.c | 12 +- .../cortexm3/bootloader/fib-bootloader.h | 10 +- cpu/stm32w108/hal/micro/cortexm3/button.c | 8 +- cpu/stm32w108/hal/micro/cortexm3/clocks.c | 24 +- .../hal/micro/cortexm3/compiler/gnu.h | 25 +- .../hal/micro/cortexm3/compiler/iar.h | 22 +- .../hal/micro/cortexm3/context-switch.s79 | 2 +- cpu/stm32w108/hal/micro/cortexm3/cstartup_M.s | 149 -- cpu/stm32w108/hal/micro/cortexm3/flash.c | 68 +- cpu/stm32w108/hal/micro/cortexm3/flash.h | 6 +- cpu/stm32w108/hal/micro/cortexm3/led.c | 2 +- cpu/stm32w108/hal/micro/cortexm3/memmap-fat.h | 6 +- cpu/stm32w108/hal/micro/cortexm3/memmap.h | 4 +- cpu/stm32w108/hal/micro/cortexm3/mems.c | 44 +- cpu/stm32w108/hal/micro/cortexm3/mfg-token.c | 20 +- cpu/stm32w108/hal/micro/cortexm3/mfg-token.h | 6 +- .../micro/cortexm3/micro-common-internal.c | 46 +- .../hal/micro/cortexm3/micro-common.c | 28 +- .../hal/micro/cortexm3/micro-common.h | 22 +- cpu/stm32w108/hal/micro/cortexm3/micro.c | 38 +- cpu/stm32w108/hal/micro/cortexm3/nvm.c | 72 +- cpu/stm32w108/hal/micro/cortexm3/nvm.h | 12 +- cpu/stm32w108/hal/micro/cortexm3/sleep.c | 62 +- cpu/stm32w108/hal/micro/cortexm3/spmr.s79 | 6 +- .../hal/micro/cortexm3/stm32w108/board.h | 22 +- .../{crt_stm32w108.c => crt-stm32w108.c} | 18 +- .../{low_level_init.c => low-level-init.c} | 18 +- .../hal/micro/cortexm3/stm32w108/memmap.h | 8 +- .../hal/micro/cortexm3/stm32w108/regs.h | 2260 ++++++++--------- .../{stm32w108_type.h => stm32w108-type.h} | 2 +- .../hal/micro/cortexm3/system-timer.c | 24 +- ...perature_sensor.c => temperature-sensor.c} | 12 +- .../hal/micro/cortexm3/token-manufacturing.h | 112 +- cpu/stm32w108/hal/micro/cortexm3/uart.c | 22 +- cpu/stm32w108/hal/micro/cortexm3/uart.h | 4 +- .../micro/generic/compiler/platform-common.h | 127 +- cpu/stm32w108/hal/micro/led.h | 2 +- .../hal/micro/{mems_regs.h => mems-regs.h} | 6 +- cpu/stm32w108/hal/micro/mems.h | 18 +- cpu/stm32w108/hal/micro/micro-common.h | 10 +- cpu/stm32w108/hal/micro/system-timer.h | 8 +- ...perature_sensor.h => temperature-sensor.h} | 4 +- cpu/stm32w108/hal/token-phy.h | 8 +- cpu/stm32w108/leds-arch.c | 33 +- cpu/stm32w108/mtarch.h | 42 +- cpu/stm32w108/rand.c | 29 +- cpu/stm32w108/rtimer-arch.c | 168 +- cpu/stm32w108/rtimer-arch.h | 72 +- cpu/stm32w108/sleep.h | 10 - cpu/stm32w108/{slip_uart1.c => slip-uart1.c} | 23 +- .../{small_printf => small-printf}/Makefile | 15 +- cpu/stm32w108/small-printf/sp-printf.c | 84 + cpu/stm32w108/small-printf/sp-puts.c | 39 + .../sp-snprintf.c} | 13 +- .../sp-sprintf.c} | 8 +- .../sp-vfprintf.c} | 14 +- .../{small_printf => small-printf}/vfieeefp.h | 39 +- cpu/stm32w108/small_printf/_SP_printf.c | 78 - cpu/stm32w108/small_printf/_SP_puts.c | 34 - cpu/stm32w108/{uip_arch.c => uip-arch.c} | 34 +- cpu/stm32w108/watchdog.c | 24 +- platform/mb851/Makefile.mb851 | 3 - platform/mb851/apps/shell-sensors.c | 45 +- platform/mb851/apps/shell-sensors.h | 7 +- platform/mb851/board-mb851.c | 258 +- platform/mb851/contiki-conf.h | 72 +- platform/mb851/contiki-init-net.c | 91 +- platform/mb851/contiki-init-net.h | 40 +- platform/mb851/contiki-main.c | 178 +- platform/mb851/dev/acc-sensor.c | 137 +- platform/mb851/dev/acc-sensor.h | 32 +- platform/mb851/dev/button-sensor.c | 104 +- platform/mb851/dev/irq.c | 45 +- platform/mb851/dev/mems-regs.h | 123 + platform/mb851/dev/mems.c | 546 ++-- platform/mb851/dev/mems.h | 64 +- platform/mb851/dev/mems_regs.h | 139 - platform/mb851/dev/temperature-sensor.c | 72 +- platform/mb851/dev/temperature-sensor.h | 33 +- platform/mb851/platform-conf.h | 92 +- 118 files changed, 4470 insertions(+), 4281 deletions(-) rename cpu/stm32w108/dev/{cortexm3_macro.h => cortexm3-macro.h} (75%) create mode 100644 cpu/stm32w108/dev/stm32w-conf.h create mode 100644 cpu/stm32w108/dev/stm32w-systick.c rename cpu/stm32w108/dev/{stm32w_systick.h => stm32w-systick.h} (77%) delete mode 100644 cpu/stm32w108/dev/stm32w_conf.h delete mode 100644 cpu/stm32w108/dev/stm32w_systick.c rename cpu/stm32w108/e_stdio/src/{small_dtoa.c => small-dtoa.c} (99%) rename cpu/stm32w108/e_stdio/src/{small_mprec.c => small-mprec.c} (99%) rename cpu/stm32w108/e_stdio/src/{small_mprec.h => small-mprec.h} (100%) rename cpu/stm32w108/e_stdio/src/{small_strtod.c => small-strtod.c} (98%) rename cpu/stm32w108/e_stdio/src/{small_vfsscanf.c => small-vfsscanf.c} (100%) rename cpu/stm32w108/e_stdio/src/{small_wcrtomb.c => small-wcrtomb.c} (100%) rename cpu/stm32w108/e_stdio/src/{small_wcsrtombs.c => small-wcsrtombs.c} (100%) rename cpu/stm32w108/e_stdio/src/{small_wctomb_r.c => small-wctomb-r.c} (100%) rename cpu/stm32w108/e_stdio/src/{_SP_printf.c => sp-printf.c} (100%) rename cpu/stm32w108/e_stdio/src/{_SP_puts.c => sp-puts.c} (100%) rename cpu/stm32w108/e_stdio/src/{_SP_snprintf.c => sp-snprintf.c} (96%) rename cpu/stm32w108/e_stdio/src/{_SP_sprintf.c => sp-sprintf.c} (100%) rename cpu/stm32w108/e_stdio/src/{_SP_vfprintf.c => sp-vfprintf.c} (100%) rename cpu/stm32w108/e_stdio/src/{test_mes.c => test-mes.c} (100%) rename cpu/stm32w108/e_stdio/src/{test_printf.c => test-printf.c} (100%) rename cpu/stm32w108/e_stdio/src/{test_scanf.c => test-scanf.c} (100%) delete mode 100644 cpu/stm32w108/hal/micro/cortexm3/cstartup_M.s rename cpu/stm32w108/hal/micro/cortexm3/stm32w108/{crt_stm32w108.c => crt-stm32w108.c} (96%) rename cpu/stm32w108/hal/micro/cortexm3/stm32w108/{low_level_init.c => low-level-init.c} (94%) rename cpu/stm32w108/hal/micro/cortexm3/stm32w108/{stm32w108_type.h => stm32w108-type.h} (98%) rename cpu/stm32w108/hal/micro/cortexm3/{temperature_sensor.c => temperature-sensor.c} (87%) rename cpu/stm32w108/hal/micro/{mems_regs.h => mems-regs.h} (94%) rename cpu/stm32w108/hal/micro/{temperature_sensor.h => temperature-sensor.h} (90%) delete mode 100644 cpu/stm32w108/sleep.h rename cpu/stm32w108/{slip_uart1.c => slip-uart1.c} (94%) rename cpu/stm32w108/{small_printf => small-printf}/Makefile (82%) create mode 100644 cpu/stm32w108/small-printf/sp-printf.c create mode 100644 cpu/stm32w108/small-printf/sp-puts.c rename cpu/stm32w108/{small_printf/_SP_snprintf.c => small-printf/sp-snprintf.c} (94%) rename cpu/stm32w108/{small_printf/_SP_sprintf.c => small-printf/sp-sprintf.c} (99%) rename cpu/stm32w108/{small_printf/_SP_vfprintf.c => small-printf/sp-vfprintf.c} (99%) rename cpu/stm32w108/{small_printf => small-printf}/vfieeefp.h (91%) delete mode 100644 cpu/stm32w108/small_printf/_SP_printf.c delete mode 100644 cpu/stm32w108/small_printf/_SP_puts.c rename cpu/stm32w108/{uip_arch.c => uip-arch.c} (76%) create mode 100644 platform/mb851/dev/mems-regs.h delete mode 100644 platform/mb851/dev/mems_regs.h diff --git a/cpu/stm32w108/Makefile.stm32w108 b/cpu/stm32w108/Makefile.stm32w108 index 9c7788134..c5748d84f 100644 --- a/cpu/stm32w108/Makefile.stm32w108 +++ b/cpu/stm32w108/Makefile.stm32w108 @@ -21,17 +21,17 @@ CONTIKI_CPU=$(CONTIKI)/cpu/stm32w108 CONTIKI_CPU_DIRS = . dev hal simplemac hal/micro/cortexm3 hal/micro/cortexm3/stm32w108 -STM32W_C = leds-arch.c leds.c clock.c watchdog.c uart1.c uart1-putchar.c slip_uart1.c slip.c\ - stm32w-radio.c stm32w_systick.c uip_arch.c rtimer-arch.c adc.c micro.c sleep.c \ +STM32W_C = leds-arch.c leds.c clock.c watchdog.c uart1.c uart1-putchar.c slip-uart1.c slip.c\ + stm32w-radio.c stm32w-systick.c uip-arch.c rtimer-arch.c adc.c micro.c sleep.c \ micro-common.c micro-common-internal.c clocks.c mfg-token.c nvm.c flash.c rand.c system-timer.c STM32W_S = spmr.s79 context-switch.s79 ifdef IAR -STM32W_C += low_level_init.c -STM32W_S += cstartup_M.s +STM32W_C += low-level-init.c +STM32W_S += cstartup-m.s else -STM32W_C += crt_stm32w108.c +STM32W_C += crt-stm32w108.c endif ifdef ELF_LOADER @@ -104,9 +104,14 @@ CFLAGSNO = -mthumb -mcpu=cortex-m3 -D "PLATFORM_HEADER=\"hal/micro/cortexm3/comp CFLAGS += $(CFLAGSNO) $(OPTI) ASFLAGS = -mthumb -mcpu=cortex-m3 -c -g -Wall -Os -ffunction-sections \ -mlittle-endian -fshort-enums -x assembler-with-cpp -Wa,-EL + +ifndef CPU_LD_CONFIG +CPU_LD_CONFIG=$(CONTIKI_CPU)/gnu.ld +endif # CPU_LD_CONFIG + LDFLAGS += -mcpu=cortex-m3 \ -mthumb \ - -Wl,-T -Xlinker $(CONTIKI_CPU)/gnu.ld \ + -Wl,-T -Xlinker $(CPU_LD_CONFIG) \ -Wl,-static \ -u Default_Handler \ -nostartfiles \ @@ -185,9 +190,8 @@ FLASHEROPTS = -f -i rs232 -p $(PORT) -r ifdef BTM #if already in bootloader mode FLASHEROPTS += -b - endif + endif endif - ### Custom rules @@ -216,7 +220,7 @@ $(OBJECTDIR)/%.o: %.c $(CC) $(CFLAGS) $< --dependencies=m $(@:.o=.P) -o $@ @$(SEDCOMMAND); rm -f $(@:.o=.P) @$(FINALIZE_DEPENDENCY) - + CUSTOM_RULE_C_TO_CO = 1 %.co: %.c $(CC) $(CFLAGS) -DAUTOSTART_ENABLE $< -o $@ @@ -231,11 +235,11 @@ CUSTOM_RULE_LINK = 1 ifdef CORE ifeq ($(wildcard $(CORE)),) - ${error $(CORE) doesn't exist} + ${error $(CORE) doesn\'t exist} endif .PHONY: symbols.c symbols.h symbols.c: - $(NM) $(CORE) | awk -f $(CONTIKI)/tools/mknmlist > symbols.c + $(NM) $(CORE) | awk -f $(CONTIKI)/tools/mknmlist > symbols.c else symbols.c symbols.h: cp ${CONTIKI}/tools/empty-symbols.c symbols.c @@ -268,18 +272,18 @@ stm-motes: $(OBJECTDIR)/%.o: %.s79 $(AS) $(ASFLAGS) -o $@ $< - + $(OBJECTDIR)/%.o: %.s - $(AS) $(ASFLAGS) -o $@ $< - + $(AS) $(ASFLAGS) -o $@ $< + %.bin: %.$(TARGET) - $(OBJCOPY) $(OBJOPTS) $< $@ + $(OBJCOPY) $(OBJOPTS) $< $@ # reset all stm32w devices sequentially, as stm32w_flasher cannot access different ports in parallel stm-reset: $(foreach PORT, $(MOTES), $(FLASHER) -r -p $(PORT);$(\n)) @echo Done - + ifdef MOTE %.upload: %.bin $(FLASHER) $(FLASHEROPTS) $< -p $(word $(MOTE), $(MOTES)) diff --git a/cpu/stm32w108/board-sensors.h b/cpu/stm32w108/board-sensors.h index 5c5fde709..9c773d4df 100644 --- a/cpu/stm32w108/board-sensors.h +++ b/cpu/stm32w108/board-sensors.h @@ -1,3 +1,39 @@ +/** + * \addtogroup mb851-platform + * + * @{ + */ + +/* + * Copyright (c) 2010, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ + /** * \file * Declarations for sensor-related functions that are @@ -7,19 +43,24 @@ * \author Salvatore Pitrulli */ +#ifndef BOARD_SENSORS_H +#define BOARD_SENSORS_H /** * Remember state of sensors (if active or not), in order to - * resume their original state after calling powerUpSensors(). + * resume their original state after calling board_sensors_power_up(). * Useful when entering in sleep mode, since all system * peripherals have to be reinitialized. */ -void sensorsPowerDown(); +void board_sensors_power_down(void); /** * Resume the state of all on-board sensors on to the state - * that they had when sensorsPowerDown() was called. + * that they had when board_sensors_power_down() was called. * Useful when sensors have to be used after the micro was put * in deep sleep mode. */ -void sensorsPowerUp(); +void board_sensors_power_up(void); + +#endif /* BOARD_SENSORS_H */ +/** @} */ diff --git a/cpu/stm32w108/cfs-coffee-arch.c b/cpu/stm32w108/cfs-coffee-arch.c index 99b8e967b..1b7a08d9a 100644 --- a/cpu/stm32w108/cfs-coffee-arch.c +++ b/cpu/stm32w108/cfs-coffee-arch.c @@ -1,3 +1,9 @@ +/** + * \addtogroup mb851-platform + * + * @{ + */ + /* * Copyright (c) 2009, Swedish Institute of Computer Science * All rights reserved. @@ -26,8 +32,6 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * This file is part of the Contiki operating system. - * */ /** @@ -38,7 +42,6 @@ * Salvatore Pitrulli */ - #include "cfs-coffee-arch.h" #define DEBUG 1 @@ -69,6 +72,7 @@ #define FILE_SIZE 512 +/*--------------------------------------------------------------------------*/ int coffee_file_test(void) { @@ -83,13 +87,12 @@ coffee_file_test(void) cfs_remove("T3"); cfs_remove("T4"); cfs_remove("T5"); - wfd = rfd = afd = -1; for(r = 0; r < sizeof(buf); r++) { buf[r] = r; } - + PRINTF("TEST 1\n"); /* Test 1: Open for writing. */ @@ -97,7 +100,7 @@ coffee_file_test(void) if(wfd < 0) { FAIL(-1); } - + PRINTF("PASSED\n"); PRINTF("TEST "); PRINTF("2\n"); @@ -109,7 +112,7 @@ coffee_file_test(void) } else if(r < sizeof(buf)) { FAIL(-3); } - + PRINTF("PASSED\n"); PRINTF("TEST "); PRINTF("3\n"); @@ -119,7 +122,7 @@ coffee_file_test(void) if(r >= 0) { FAIL(-4); } - + PRINTF("PASSED\n"); PRINTF("TEST "); PRINTF("4\n"); @@ -129,7 +132,7 @@ coffee_file_test(void) if(rfd < 0) { FAIL(-5); } - + PRINTF("PASSED\n"); PRINTF("TEST "); PRINTF("5\n"); @@ -139,7 +142,6 @@ coffee_file_test(void) if(r >= 0) { FAIL(-6); } - PRINTF("PASSED\n"); PRINTF("TEST "); PRINTF("7\n"); @@ -153,7 +155,7 @@ coffee_file_test(void) PRINTF_CFS("r=%d\n", r); FAIL(-9); } - + PRINTF("PASSED\n"); PRINTF("TEST "); PRINTF("8\n"); @@ -165,7 +167,7 @@ coffee_file_test(void) FAIL(-10); } } - + PRINTF("PASSED\n"); PRINTF("TEST "); PRINTF("9\n"); @@ -174,7 +176,7 @@ coffee_file_test(void) if(cfs_seek(wfd, 0, CFS_SEEK_SET) != 0) { FAIL(-11); } - + PRINTF("PASSED\n"); PRINTF("TEST "); PRINTF("10\n"); @@ -186,7 +188,7 @@ coffee_file_test(void) } else if(r < sizeof(buf)) { FAIL(-13); } - + PRINTF("PASSED\n"); PRINTF("TEST "); PRINTF("11\n"); @@ -200,7 +202,7 @@ coffee_file_test(void) } else if(r < sizeof(buf)) { FAIL(-15); } - + PRINTF("PASSED\n"); PRINTF("TEST "); PRINTF("12\n"); @@ -211,7 +213,7 @@ coffee_file_test(void) FAIL(-16); } } - + PRINTF("PASSED\n"); PRINTF("TEST "); PRINTF("13\n"); @@ -232,7 +234,7 @@ coffee_file_test(void) if(cfs_seek(rfd, 0, CFS_SEEK_SET) != 0) { FAIL(-20); } - + PRINTF("PASSED\n"); PRINTF("TEST "); PRINTF("14\n"); @@ -247,7 +249,7 @@ coffee_file_test(void) PRINTF_CFS("r = %d\n", r); FAIL(-22); } - + PRINTF("PASSED\n"); PRINTF("TEST "); PRINTF("15\n"); @@ -265,7 +267,7 @@ coffee_file_test(void) if(cfs_coffee_reserve("T2", FILE_SIZE) < 0) { FAIL(-24); } - + PRINTF("PASSED\n"); PRINTF("TEST "); PRINTF("16\n"); @@ -276,30 +278,23 @@ coffee_file_test(void) if(wfd < 0) { FAIL(-25); } - offset = random_rand() % FILE_SIZE; - for(r = 0; r < sizeof(buf); r++) { buf[r] = r; } - if(cfs_seek(wfd, offset, CFS_SEEK_SET) != offset) { FAIL(-26); } - if(cfs_write(wfd, buf, sizeof(buf)) != sizeof(buf)) { FAIL(-27); } - if(cfs_seek(wfd, offset, CFS_SEEK_SET) != offset) { FAIL(-28); } - memset(buf, 0, sizeof(buf)); if(cfs_read(wfd, buf, sizeof(buf)) != sizeof(buf)) { FAIL(-29); } - for(i = 0; i < sizeof(buf); i++) { if(buf[i] != i) { PRINTF_CFS("buf[%d] != %d\n", i, buf[i]); @@ -310,30 +305,30 @@ coffee_file_test(void) PRINTF("PASSED\n"); PRINTF("TEST "); PRINTF("17\n"); + /* Test 17: Append data to the same file many times. */ #define APPEND_BYTES 3000 #define BULK_SIZE 10 - for (i = 0; i < APPEND_BYTES; i += BULK_SIZE) { + for(i = 0; i < APPEND_BYTES; i += BULK_SIZE) { afd = cfs_open("T3", CFS_WRITE | CFS_APPEND); - if (afd < 0) { + if(afd < 0) { FAIL(-31); } - for (j = 0; j < BULK_SIZE; j++) { + for(j = 0; j < BULK_SIZE; j++) { buf[j] = 1 + ((i + j) & 0x7f); } - if ((r = cfs_write(afd, buf, BULK_SIZE)) != BULK_SIZE) { + if((r = cfs_write(afd, buf, BULK_SIZE)) != BULK_SIZE) { PRINTF_CFS("Count:%d, r=%d\n", i, r); FAIL(-32); } cfs_close(afd); } - + PRINTF("PASSED\n"); PRINTF("TEST "); PRINTF("18\n"); - /* Test 18: Read back the data written in Test 17 and verify that it - is correct. */ + /* Test 18: Read back the data written in Test 17 and verify. */ afd = cfs_open("T3", CFS_READ); if(afd < 0) { FAIL(-33); @@ -342,192 +337,202 @@ coffee_file_test(void) while((r = cfs_read(afd, buf2, sizeof(buf2))) > 0) { for(j = 0; j < r; j++) { if(buf2[j] != 1 + ((total_read + j) & 0x7f)) { - FAIL(-34); + FAIL(-34); } } total_read += r; } if(r < 0) { - PRINTF_CFS("FAIL:-35 r=%d\n",r); + PRINTF_CFS("FAIL:-35 r=%d\n", r); FAIL(-35); } if(total_read != APPEND_BYTES) { - PRINTF_CFS("FAIL:-35 total_read=%d\n",total_read); + PRINTF_CFS("FAIL:-35 total_read=%d\n", total_read); FAIL(-35); } cfs_close(afd); - + PRINTF("PASSED\n"); PRINTF("TEST "); PRINTF("19\n"); -/***************T4********************/ -/* file T4 and T5 writing forces to use garbage collector in greedy mode - * this test is designed for 10kb of file system - * */ + /* T4 */ + /* + * file T4 and T5 writing forces to use garbage collector in greedy mode + * this test is designed for 10kb of file system + */ #define APPEND_BYTES_1 2000 #define BULK_SIZE_1 10 - for (i = 0; i < APPEND_BYTES_1; i += BULK_SIZE_1) { + for(i = 0; i < APPEND_BYTES_1; i += BULK_SIZE_1) { afd = cfs_open("T4", CFS_WRITE | CFS_APPEND); - if (afd < 0) { - FAIL(-36); + if(afd < 0) { + FAIL(-36); } - for (j = 0; j < BULK_SIZE_1; j++) { + for(j = 0; j < BULK_SIZE_1; j++) { buf[j] = 1 + ((i + j) & 0x7f); } - if ((r = cfs_write(afd, buf, BULK_SIZE_1)) != BULK_SIZE_1) { - PRINTF_CFS("Count:%d, r=%d\n", i, r); - FAIL(-37); - } - cfs_close(afd); - } + if((r = cfs_write(afd, buf, BULK_SIZE_1)) != BULK_SIZE_1) { + PRINTF_CFS("Count:%d, r=%d\n", i, r); + FAIL(-37); + } + cfs_close(afd); + } afd = cfs_open("T4", CFS_READ); if(afd < 0) { FAIL(-38); } + total_read = 0; while((r = cfs_read(afd, buf2, sizeof(buf2))) > 0) { for(j = 0; j < r; j++) { if(buf2[j] != 1 + ((total_read + j) & 0x7f)) { - PRINTF_CFS("FAIL:-39, total_read=%d r=%d\n",total_read,r); - FAIL(-39); + PRINTF_CFS("FAIL:-39, total_read=%d r=%d\n", total_read, r); + FAIL(-39); } } total_read += r; } if(r < 0) { - PRINTF_CFS("FAIL:-40 r=%d\n",r); + PRINTF_CFS("FAIL:-40 r=%d\n", r); FAIL(-40); } if(total_read != APPEND_BYTES_1) { - PRINTF_CFS("FAIL:-41 total_read=%d\n",total_read); + PRINTF_CFS("FAIL:-41 total_read=%d\n", total_read); FAIL(-41); } cfs_close(afd); - /***************T5********************/ + + /* T5 */ PRINTF("PASSED\n"); PRINTF("TEST "); PRINTF("20\n"); #define APPEND_BYTES_2 1000 #define BULK_SIZE_2 10 - for (i = 0; i < APPEND_BYTES_2; i += BULK_SIZE_2) { - afd = cfs_open("T5", CFS_WRITE | CFS_APPEND); - if (afd < 0) { - FAIL(-42); - } - for (j = 0; j < BULK_SIZE_2; j++) { - buf[j] = 1 + ((i + j) & 0x7f); - } - - if ((r = cfs_write(afd, buf, BULK_SIZE_2)) != BULK_SIZE_2) { - PRINTF_CFS("Count:%d, r=%d\n", i, r); - FAIL(-43); - } - - cfs_close(afd); - } - - afd = cfs_open("T5", CFS_READ); + for(i = 0; i < APPEND_BYTES_2; i += BULK_SIZE_2) { + afd = cfs_open("T5", CFS_WRITE | CFS_APPEND); if(afd < 0) { - FAIL(-44); + FAIL(-42); } - total_read = 0; - while((r = cfs_read(afd, buf2, sizeof(buf2))) > 0) { - for(j = 0; j < r; j++) { - if(buf2[j] != 1 + ((total_read + j) & 0x7f)) { - PRINTF_CFS("FAIL:-45, total_read=%d r=%d\n",total_read,r); - FAIL(-45); - } - } - total_read += r; + for(j = 0; j < BULK_SIZE_2; j++) { + buf[j] = 1 + ((i + j) & 0x7f); } - if(r < 0) { - PRINTF_CFS("FAIL:-46 r=%d\n",r); - FAIL(-46); - } - if(total_read != APPEND_BYTES_2) { - PRINTF_CFS("FAIL:-47 total_read=%d\n",total_read); - FAIL(-47); + + if((r = cfs_write(afd, buf, BULK_SIZE_2)) != BULK_SIZE_2) { + PRINTF_CFS("Count:%d, r=%d\n", i, r); + FAIL(-43); } + cfs_close(afd); - - PRINTF("PASSED\n"); + } + + afd = cfs_open("T5", CFS_READ); + if(afd < 0) { + FAIL(-44); + } + total_read = 0; + while((r = cfs_read(afd, buf2, sizeof(buf2))) > 0) { + for(j = 0; j < r; j++) { + if(buf2[j] != 1 + ((total_read + j) & 0x7f)) { + PRINTF_CFS("FAIL:-45, total_read=%d r=%d\n", total_read, r); + FAIL(-45); + } + } + total_read += r; + } + if(r < 0) { + PRINTF_CFS("FAIL:-46 r=%d\n", r); + FAIL(-46); + } + if(total_read != APPEND_BYTES_2) { + PRINTF_CFS("FAIL:-47 total_read=%d\n", total_read); + FAIL(-47); + } + cfs_close(afd); + + PRINTF("PASSED\n"); error = 0; end: - cfs_close(wfd); cfs_close(rfd); cfs_close(afd); + cfs_close(wfd); + cfs_close(rfd); + cfs_close(afd); return error; } #endif /* TESTCOFFEE */ - -void stm32w_flash_read(int32u address, void * data, int32u length) +/*--------------------------------------------------------------------------*/ +void +stm32w_flash_read(uint32_t address, void *data, uint32_t length) { - int8u * pdata = (int8u *)address; + uint8_t *pdata = (uint8_t *) address; + ENERGEST_ON(ENERGEST_TYPE_FLASH_READ); memcpy(data, pdata, length); ENERGEST_OFF(ENERGEST_TYPE_FLASH_READ); } - -void stm32w_flash_erase(int8u sector) +/*--------------------------------------------------------------------------*/ +void +stm32w_flash_erase(uint8_t sector) { - //halInternalFlashErase(MFB_PAGE_ERASE, COFFEE_START + (sector) * COFFEE_SECTOR_SIZE); - - int16u data = 0; - int32u addr = COFFEE_START + (sector) * COFFEE_SECTOR_SIZE; - int32u end = addr + COFFEE_SECTOR_SIZE; - + /* halInternalFlashErase(MFB_PAGE_ERASE, COFFEE_START + + (sector) * COFFEE_SECTOR_SIZE); */ + uint16_t data = 0; + uint32_t addr = COFFEE_START + (sector) * COFFEE_SECTOR_SIZE; + uint32_t end = addr + COFFEE_SECTOR_SIZE; + /* This prevents from accidental write to CIB. */ - if (!(addr >= MFB_BOTTOM && end <= MFB_TOP + 1)) { + if(!(addr >= MFB_BOTTOM && end <= MFB_TOP + 1)) { return; } - - for(; addr < end; addr += 2){ + + for(; addr < end; addr += 2) { halInternalFlashWrite(addr, &data, 1); } } - -// Allocates a buffer of FLASH_PAGE_SIZE bytes statically (rather than on the stack). +/*--------------------------------------------------------------------------*/ +/* + * Allocates a buffer of FLASH_PAGE_SIZE bytes statically (rather than on + * the stack). + */ #ifndef STATIC_FLASH_BUFFER -#define STATIC_FLASH_BUFFER 1 +#define STATIC_FLASH_BUFFER 1 #endif -void stm32w_flash_write(int32u address, const void * data, int32u length) +void +stm32w_flash_write(uint32_t address, const void *data, uint32_t length) { - const int32u end = address + length; - int32u i; - int32u next_page, curr_page; - int16u offset; - + const uint32_t end = address + length; + uint32_t i; + uint32_t next_page, curr_page; + uint16_t offset; #if STATIC_FLASH_BUFFER - static int8u buf[FLASH_PAGE_SIZE]; + static uint8_t buf[FLASH_PAGE_SIZE]; #else - int8u buf[FLASH_PAGE_SIZE]; + uint8_t buf[FLASH_PAGE_SIZE]; #endif - + for(i = address; i < end;) { - next_page = (i | (FLASH_PAGE_SIZE-1)) + 1; - curr_page = i & ~(FLASH_PAGE_SIZE-1); - offset = i-curr_page; + next_page = (i | (FLASH_PAGE_SIZE - 1)) + 1; + curr_page = i & ~(FLASH_PAGE_SIZE - 1); + offset = i - curr_page; if(next_page > end) { next_page = end; } - // Read a page from flash and put it into a mirror buffer. + /* Read a page from flash and put it into a mirror buffer. */ stm32w_flash_read(curr_page, buf, FLASH_PAGE_SIZE); - // Update flash mirror data with new data. + /* Update flash mirror data with new data. */ memcpy(buf + offset, data, next_page - i); - // Erase flash page. + /* Erase flash page. */ ENERGEST_ON(ENERGEST_TYPE_FLASH_WRITE); halInternalFlashErase(MFB_PAGE_ERASE, i); - // Write modified data form mirror buffer into the flash. - halInternalFlashWrite(curr_page, (int16u *)buf, FLASH_PAGE_SIZE/2); + /* Write modified data form mirror buffer into the flash. */ + halInternalFlashWrite(curr_page, (uint16_t *) buf, FLASH_PAGE_SIZE / 2); ENERGEST_OFF(ENERGEST_TYPE_FLASH_WRITE); - - data = (uint8_t *)data + next_page - i; + + data = (uint8_t *) data + next_page - i; i = next_page; } - } - +/** @} */ diff --git a/cpu/stm32w108/cfs-coffee-arch.h b/cpu/stm32w108/cfs-coffee-arch.h index e529b0123..7ce8473a7 100644 --- a/cpu/stm32w108/cfs-coffee-arch.h +++ b/cpu/stm32w108/cfs-coffee-arch.h @@ -1,3 +1,9 @@ +/** + * \addtogroup mb851-platform + * + * @{ + */ + /* * Copyright (c) 2010, STMicroelectronics. * All rights reserved. @@ -26,15 +32,12 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * This file is part of the Contiki operating system. - * */ /** * \file * Coffee architecture-dependent header for the STM32W108-based mb851 - * platform. - * STM32W108 has 128KB of program flash. + * platform. STM32W108 has 128KB of program flash. * \author * Salvatore Pitrulli */ @@ -47,32 +50,34 @@ #include "hal/error.h" #include "hal/micro/cortexm3/flash.h" -/* STM32W108 has 128 pages of 1024 bytes each = 128KB +/* + * STM32W108 has 128KB of program flash in 128 pages of 1024 bytes each = 128KB. * The smallest erasable unit is one page and the smallest writable * unit is an aligned 16-bit half-word. */ - -/* Byte page size, starting address on page boundary, and size of the file system */ +/* Byte page size, starting address on page boundary, and size of file system */ #define FLASH_START 0x8000000 /* Minimum erasable unit. */ #define FLASH_PAGE_SIZE 1024 /* Last 3 pages reserved for NVM. */ #define FLASH_PAGES 125 - /* Minimum reservation unit for Coffee. It can be changed by the user. */ #define COFFEE_PAGE_SIZE (FLASH_PAGE_SIZE/4) - -/* If using IAR, COFFEE_ADDRESS reflects the static value in the linker script - iar-cfg-coffee.icf, so it can't be passed as a parameter for Make.*/ +/* + * If using IAR, COFFEE_ADDRESS reflects the static value in the linker script + * iar-cfg-coffee.icf, so it can't be passed as a parameter for Make. + */ #ifdef __ICCARM__ #define COFFEE_ADDRESS 0x8010c00 #endif -#if (COFFEE_ADDRESS & 0x3FF) !=0 - #error "COFFEE_ADDRESS not aligned to a 1024-bytes page boundary." +#if (COFFEE_ADDRESS & 0x3FF) != 0 +#error "COFFEE_ADDRESS not aligned to a 1024-bytes page boundary." #endif -#define COFFEE_PAGES ((FLASH_PAGES*FLASH_PAGE_SIZE-(COFFEE_ADDRESS-FLASH_START))/COFFEE_PAGE_SIZE) + +#define COFFEE_PAGES ((FLASH_PAGES*FLASH_PAGE_SIZE- \ + (COFFEE_ADDRESS-FLASH_START))/COFFEE_PAGE_SIZE) #define COFFEE_START (COFFEE_ADDRESS & ~(COFFEE_PAGE_SIZE-1)) #define COFFEE_SIZE (COFFEE_PAGES*COFFEE_PAGE_SIZE) @@ -80,21 +85,23 @@ #define COFFEE_SECTOR_SIZE FLASH_PAGE_SIZE #define COFFEE_NAME_LENGTH 20 -///* These are used internally by the AVR flash read routines */ -///* Word reads are faster but take 130 bytes more PROGMEM */ -//#define FLASH_WORD_READS 1 -///* 1=Slower reads, but no page writes after erase and 18 bytes less PROGMEM. Best for dynamic file system */ -//#define FLASH_COMPLEMENT_DATA 0 +/* These are used internally by the AVR flash read routines */ +/* Word reads are faster but take 130 bytes more PROGMEM */ + /* #define FLASH_WORD_READS 1 */ +/* + * 1 = Slower reads, but no page writes after erase and 18 bytes less PROGMEM. + * Best for dynamic file system + */ + /* #define FLASH_COMPLEMENT_DATA 0 */ /* These are used internally by the coffee file system */ -/* Micro logs are not needed for single page sectors */ #define COFFEE_MAX_OPEN_FILES 4 #define COFFEE_FD_SET_SIZE 8 #define COFFEE_DYN_SIZE (COFFEE_PAGE_SIZE*1) +/* Micro logs are not needed for single page sectors */ #define COFFEE_MICRO_LOGS 0 -#define COFFEE_LOG_TABLE_LIMIT 16 // It doesnt' matter as -#define COFFEE_LOG_SIZE 128 // COFFEE_MICRO_LOGS is 0. - +#define COFFEE_LOG_TABLE_LIMIT 16 /* It doesnt' matter as */ +#define COFFEE_LOG_SIZE 128 /* COFFEE_MICRO_LOGS is 0. */ #if COFFEE_PAGES <= 127 #define coffee_page_t int8_t @@ -102,7 +109,6 @@ #define coffee_page_t int16_t #endif - #define COFFEE_WRITE(buf, size, offset) \ stm32w_flash_write(COFFEE_START + offset, buf, size) @@ -113,10 +119,13 @@ stm32w_flash_erase(sector) -void stm32w_flash_read(int32u address, void * data, int32u length); -void stm32w_flash_write(int32u address, const void * data, int32u length); -void stm32w_flash_erase(int8u sector); +void stm32w_flash_read(uint32_t address, void *data, uint32_t length); + +void stm32w_flash_write(uint32_t address, const void *data, uint32_t length); + +void stm32w_flash_erase(uint8_t sector); int coffee_file_test(void); #endif /* !COFFEE_ARCH_H */ +/** @} */ diff --git a/cpu/stm32w108/clock.c b/cpu/stm32w108/clock.c index 52ff38366..6df0ac5c0 100644 --- a/cpu/stm32w108/clock.c +++ b/cpu/stm32w108/clock.c @@ -1,3 +1,9 @@ +/** + * \addtogroup mb851-platform + * + * @{ + */ + /* * Copyright (c) 2010, STMicroelectronics. * All rights reserved. @@ -27,22 +33,20 @@ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * This file is part of the Contiki OS - * */ -/*---------------------------------------------------------------------------*/ + /** * \file * Clock. * \author * Salvatore Pitrulli */ -/*---------------------------------------------------------------------------*/ #include PLATFORM_HEADER +#include #include "hal/error.h" #include "hal/hal.h" -#include "dev/stm32w_systick.h" +#include "dev/stm32w-systick.h" #include "contiki.h" #include "sys/clock.h" @@ -54,46 +58,39 @@ #define DEBUG DEBUG_NONE #include "net/uip-debug.h" +/*--------------------------------------------------------------------------*/ /* The value that will be load in the SysTick value register. */ -#define RELOAD_VALUE 24000-1 /* 1 ms with a 24 MHz clock */ +#define RELOAD_VALUE 24000-1 /* 1 ms with a 24 MHz clock */ static volatile clock_time_t count; static volatile unsigned long current_seconds = 0; static unsigned int second_countdown = CLOCK_SECOND; - /*---------------------------------------------------------------------------*/ void SysTick_Handler(void) { count++; - if(etimer_pending()) { etimer_request_poll(); } - - if (--second_countdown == 0) { + + if(--second_countdown == 0) { current_seconds++; second_countdown = CLOCK_SECOND; } - + } /*---------------------------------------------------------------------------*/ void clock_init(void) -{ - +{ ATOMIC( - - //Counts the number of ticks. - count = 0; - - SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK); - SysTick_SetReload(RELOAD_VALUE); - SysTick_ITConfig(ENABLE); - SysTick_CounterCmd(SysTick_Counter_Enable); - - ) - + /* Counts the number of ticks. */ + count = 0; + SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK); + SysTick_SetReload(RELOAD_VALUE); + SysTick_ITConfig(ENABLE); + SysTick_CounterCmd(SysTick_Counter_Enable);) } /*---------------------------------------------------------------------------*/ clock_time_t @@ -108,16 +105,16 @@ clock_time(void) void clock_delay(unsigned int i) { - for (; i > 0; i--) { /* Needs fixing XXX */ + for(; i > 0; i--) { /* Needs fixing XXX */ unsigned j; - for (j = 50; j > 0; j--) - asm ("nop"); + for(j = 50; j > 0; j--) { + asm("nop"); + } } } /*---------------------------------------------------------------------------*/ /** * Wait for a multiple of 1 ms. - * */ void clock_wait(clock_time_t i) @@ -125,7 +122,7 @@ clock_wait(clock_time_t i) clock_time_t start; start = clock_time(); - while(clock_time() - start < (clock_time_t)i); + while(clock_time() - start < (clock_time_t) i); } /*---------------------------------------------------------------------------*/ unsigned long @@ -133,49 +130,5 @@ clock_seconds(void) { return current_seconds; } - -#include - -void -sleep_seconds(int seconds) -{ - int32u quarter_seconds = seconds * 4; - uint8_t radio_on; - - halPowerDown(); - radio_on = stm32w_radio_is_on(); - stm32w_radio_driver.off(); - - halSleepForQsWithOptions(&quarter_seconds, 0); - - - ATOMIC( - - halPowerUp(); - - /* Update OS system ticks. */ - current_seconds += seconds - quarter_seconds / 4 ; /* Passed seconds */ - count += seconds * CLOCK_SECOND - quarter_seconds * CLOCK_SECOND / 4 ; - - if(etimer_pending()) { - etimer_request_poll(); - } - - SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK); - SysTick_SetReload(RELOAD_VALUE); - SysTick_ITConfig(ENABLE); - SysTick_CounterCmd(SysTick_Counter_Enable); - ) - - stm32w_radio_driver.init(); - if(radio_on) { - stm32w_radio_driver.on(); - } - - uart1_init(115200); - leds_init(); - rtimer_init(); - - PRINTF("WakeInfo: %04x\r\n", halGetWakeInfo()); - -} +/*--------------------------------------------------------------------------*/ +/** @} */ diff --git a/cpu/stm32w108/dev/cortexm3_macro.h b/cpu/stm32w108/dev/cortexm3-macro.h similarity index 75% rename from cpu/stm32w108/dev/cortexm3_macro.h rename to cpu/stm32w108/dev/cortexm3-macro.h index b16dc0c41..946ac669a 100644 --- a/cpu/stm32w108/dev/cortexm3_macro.h +++ b/cpu/stm32w108/dev/cortexm3-macro.h @@ -1,5 +1,11 @@ +/** + * \addtogroup stm32w-cpu + * + * @{ + */ + /******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** -* File Name : cortexm3_macro.h +* File Name : cortexm3-macro.h * Author : MCD Application Team * Version : V2.0.3 * Date : 09/22/2008 @@ -13,17 +19,11 @@ * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *******************************************************************************/ -/* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __CORTEXM3_MACRO_H #define __CORTEXM3_MACRO_H -/* Includes ------------------------------------------------------------------*/ #include "stm32w_type.h" -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ void __WFI(void); void __WFE(void); void __SEV(void); @@ -31,23 +31,30 @@ void __ISB(void); void __DSB(void); void __DMB(void); void __SVC(void); + u32 __MRS_CONTROL(void); void __MSR_CONTROL(u32 Control); + u32 __MRS_PSP(void); void __MSR_PSP(u32 TopOfProcessStack); + u32 __MRS_MSP(void); void __MSR_MSP(u32 TopOfMainStack); + void __RESETPRIMASK(void); void __SETPRIMASK(void); u32 __READ_PRIMASK(void); void __RESETFAULTMASK(void); void __SETFAULTMASK(void); u32 __READ_FAULTMASK(void); + void __BASEPRICONFIG(u32 NewPriority); + u32 __GetBASEPRI(void); + u16 __REV_HalfWord(u16 Data); u32 __REV_Word(u32 Data); #endif /* __CORTEXM3_MACRO_H */ - /******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ +/** @} */ diff --git a/cpu/stm32w108/dev/stm32w-conf.h b/cpu/stm32w108/dev/stm32w-conf.h new file mode 100644 index 000000000..aa5c2bc9c --- /dev/null +++ b/cpu/stm32w108/dev/stm32w-conf.h @@ -0,0 +1,227 @@ +/** + * \addtogroup stm32w-cpu + * + * @{ + */ + +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32w-conf.h +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : Library configuration file. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +#ifndef __STM32F10x_CONF_H +#define __STM32F10x_CONF_H + +#include "stm32w108-type.h" + +/* + * Uncomment the line below to compile the library in DEBUG mode, this will + * expand the "assert_param" macro in the firmware library code (see "Exported + * macro" section below) + */ +/*#define DEBUG 1*/ + +/*---------------------------------------------------------------------------*/ +/* Comment any line below to disable the specific peripheral inclusion */ +/* + * ADC + */ +/* #define _ADC */ +/* #define _ADC1 */ +/* #define _ADC2 */ +/* #define _ADC3 */ + +/* + * BKP + */ +/* #define _BKP */ + +/* + * CAN + */ +/* #define _CAN */ + +/* + * CRC + */ +/* #define _CRC */ + +/* + * DAC + */ +/* #define _DAC */ + +/* + * DBGMCU + */ +/* #define _DBGMCU */ + +/* + * DMA + */ +/* #define _DMA */ +/* #define _DMA1_Channel1 */ +/* #define _DMA1_Channel2 */ +/* #define _DMA1_Channel3 */ +/* #define _DMA1_Channel4 */ +/* #define _DMA1_Channel5 */ +/* #define _DMA1_Channel6 */ +/* #define _DMA1_Channel7 */ +/* #define _DMA2_Channel1 */ +/* #define _DMA2_Channel2 */ +/* #define _DMA2_Channel3 */ +/* #define _DMA2_Channel4 */ +/* #define _DMA2_Channel5 */ + +/* + * EXTI + */ + /* #define _EXTI */ + +/* + * FLASH and Option Bytes + */ +#define _FLASH +/* + * Uncomment the line below to enable FLASH program/erase/protections functions, + * otherwise only FLASH configuration (latency, prefetch, half cycle) functions + * are enabled + */ +/* #define _FLASH_PROG */ + +/* + * FSMC + */ +/* #define _FSMC */ + +/* + * GPIO + */ +#define _GPIO +/* #define _GPIOA */ +/* #define _GPIOB */ +#define _GPIOC +/* #define _GPIOD */ +/* #define _GPIOE */ +#define _GPIOF +/* #define _GPIOG */ +#define _AFIO + +/* + * I2C + */ +/* #define _I2C */ +/* #define _I2C1 */ +/* #define _I2C2 */ + +/* + * IWDG + */ +/* #define _IWDG */ + +/* + * NVIC + */ +#define _NVIC + +/* + * PWR + */ +/* #define _PWR */ + +/* + * RCC + */ +#define _RCC + +/* + * RTC + */ +/* #define _RTC */ + +/* + * SDIO + */ +/* #define _SDIO */ + +/* + * SPI + */ +/* #define _SPI */ +/* #define _SPI1 */ +/* #define _SPI2 */ +/* #define _SPI3 */ + +/* + * SysTick + */ +#define _SysTick + +/* + * TIM + */ +/* #define _TIM */ +/* #define _TIM1 */ +/* #define _TIM2 */ +/* #define _TIM3 */ +/* #define _TIM4 */ +/* #define _TIM5 */ +/* #define _TIM6 */ +/* #define _TIM7 */ +/* #define _TIM8 */ + +/* + * USART + */ +/* #define _USART */ +/* #define _USART1 */ +/* #define _USART2 */ +/* #define _USART3 */ +/* #define _UART4 */ +/* #define _UART5 */ + +/* + * WWDG + */ +/* #define _WWDG */ + +/* + * In the following line adjust the value of External High Speed oscillator + * (HSE) used in your application + */ +#define HSE_Value ((u32)8000000) /* Value of the External oscillator in Hz */ + +/* + * In the following line adjust the External High Speed oscillator (HSE) Startup + * Timeout value. + */ +#define HSEStartUp_TimeOut ((u16)0x0500) /* Time out for HSE start up */ + +#ifdef DEBUG +/** + * \brief The assert_param macro is used for function's parameters check. + * It is used only if the library is compiled in DEBUG mode. + * \param expr If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + */ +#define assert_param(expr) ((expr) ? (void)0 : assert_failed((u8 *)__FILE__, __LINE__)) +void assert_failed(u8 * file, u32 line); +#else +#define assert_param(expr) ((void)0) +#endif /* DEBUG */ + +#endif /* __STM32F10x_CONF_H */ +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ +/** @} */ diff --git a/cpu/stm32w108/dev/stm32w-radio.c b/cpu/stm32w108/dev/stm32w-radio.c index 8962e0324..eb9815e6b 100644 --- a/cpu/stm32w108/dev/stm32w-radio.c +++ b/cpu/stm32w108/dev/stm32w-radio.c @@ -1,3 +1,9 @@ +/** + * \addtogroup stm32w-cpu + * + * @{ + */ + /* * Copyright (c) 2010, STMicroelectronics. * All rights reserved. @@ -27,10 +33,8 @@ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * This file is part of the Contiki OS - * */ -/*---------------------------------------------------------------------------*/ + /** * \file * Machine dependent STM32W radio code. @@ -39,7 +43,6 @@ * Chi-Anh La la@imag.fr * Simon Duquennoy */ -/*---------------------------------------------------------------------------*/ #include PLATFORM_HEADER #include "hal/error.h" @@ -72,39 +75,38 @@ #define LED_ACTIVITY 1 #else #define LED_RDC 0 -#endif - +#endif /* RDC_CONF_DEBUG_LED */ #if DEBUG > 0 #include #define PRINTF(...) printf(__VA_ARGS__) #else #define PRINTF(...) do {} while (0) -#endif +#endif /* DEBUG > 0 */ #if LED_ACTIVITY #define LED_TX_ON() leds_on(LEDS_GREEN) #define LED_TX_OFF() leds_off(LEDS_GREEN) -#define LED_RX_ON() { \ +#define LED_RX_ON() do { \ if(LED_RDC == 0){ \ leds_on(LEDS_RED); \ } \ - } -#define LED_RX_OFF() { \ + } while (0) +#define LED_RX_OFF() do { \ if(LED_RDC == 0){ \ - leds_off(LEDS_RED); \ + leds_off(LEDS_RED); \ } \ - } -#define LED_RDC_ON() { \ + } while (0) +#define LED_RDC_ON() do { \ if(LED_RDC == 1){ \ leds_on(LEDS_RED); \ } \ - } -#define LED_RDC_OFF() { \ + } while (0) +#define LED_RDC_OFF() do { \ if(LED_RDC == 1){ \ - leds_off(LEDS_RED); \ + leds_off(LEDS_RED); \ } \ - } + } while (0) #else #define LED_TX_ON() #define LED_TX_OFF() @@ -112,63 +114,59 @@ #define LED_RX_OFF() #define LED_RDC_ON() #define LED_RDC_OFF() -#endif +#endif /* LED_ACTIVITY */ #if RDC_CONF_HARDWARE_CSMA #define MAC_RETRIES 0 -#endif +#endif /* RDC_CONF_HARDWARE_CSMA */ #ifndef MAC_RETRIES #define MAC_RETRIES 1 -#endif +#endif /* MAC_RETRIES */ #if MAC_RETRIES - - int8_t mac_retries_left; - - #define INIT_RETRY_CNT() (mac_retries_left = packetbuf_attr(PACKETBUF_ATTR_MAX_MAC_TRANSMISSIONS)) - #define DEC_RETRY_CNT() (mac_retries_left--) - #define RETRY_CNT_GTZ() (mac_retries_left > 0) - +int8_t mac_retries_left; +#define INIT_RETRY_CNT() (mac_retries_left = packetbuf_attr(PACKETBUF_ATTR_MAX_MAC_TRANSMISSIONS)) +#define DEC_RETRY_CNT() (mac_retries_left--) +#define RETRY_CNT_GTZ() (mac_retries_left > 0) #else - - #define INIT_RETRY_CNT() - #define DEC_RETRY_CNT() - #define RETRY_CNT_GTZ() 0 - -#endif +#define INIT_RETRY_CNT() +#define DEC_RETRY_CNT() +#define RETRY_CNT_GTZ() 0 +#endif /* MAC_RETRIES */ /* If set to 1, a send() returns only after the packet has been transmitted. This is necessary if you use the x-mac module, for example. */ #ifndef RADIO_WAIT_FOR_PACKET_SENT #define RADIO_WAIT_FOR_PACKET_SENT 1 -#endif +#endif /* RADIO_WAIT_FOR_PACKET_SENT */ -#define TO_PREV_STATE() { \ +#define TO_PREV_STATE() do { \ if(onoroff == OFF){ \ ST_RadioSleep(); \ ENERGEST_OFF(ENERGEST_TYPE_LISTEN); \ } \ - } + } while(0) #if RDC_CONF_HARDWARE_CSMA #define ST_RADIO_CHECK_CCA FALSE #define ST_RADIO_CCA_ATTEMPT_MAX 0 #define ST_BACKOFF_EXP_MIN 0 #define ST_BACKOFF_EXP_MAX 0 -#else +#else /* RDC_CONF_HARDWARE_CSMA */ #define ST_RADIO_CHECK_CCA TRUE #define ST_RADIO_CCA_ATTEMPT_MAX 4 #define ST_BACKOFF_EXP_MIN 2 #define ST_BACKOFF_EXP_MAX 6 -#endif +#endif /* RDC_CONF_HARDWARE_CSMA */ + const RadioTransmitConfig radioTransmitConfig = { - TRUE, // waitForAck; - ST_RADIO_CHECK_CCA, // checkCca; // Set to FALSE with low-power MACs. - ST_RADIO_CCA_ATTEMPT_MAX, // ccaAttemptMax; - ST_BACKOFF_EXP_MIN, // backoffExponentMin; - ST_BACKOFF_EXP_MAX, // backoffExponentMax; - TRUE // appendCrc; + TRUE, /* waitForAck; */ + ST_RADIO_CHECK_CCA, /* checkCca;Set to FALSE with low-power MACs. */ + ST_RADIO_CCA_ATTEMPT_MAX, /* ccaAttemptMax; */ + ST_BACKOFF_EXP_MIN, /* backoffExponentMin; */ + ST_BACKOFF_EXP_MAX, /* backoffExponentMax; */ + TRUE /* appendCrc; */ }; #define MAC_RETRIES 0 @@ -178,38 +176,38 @@ const RadioTransmitConfig radioTransmitConfig = { */ #ifndef RADIO_RXBUFS #define RADIO_RXBUFS 1 -#endif +#endif /* RADIO_RXBUFS */ -static uint8_t stm32w_rxbufs[RADIO_RXBUFS][STM32W_MAX_PACKET_LEN+1]; // +1 because of the first byte, which will contain the length of the packet. +/* +1 because of the first byte, which will contain the length of the packet. */ +static uint8_t stm32w_rxbufs[RADIO_RXBUFS][STM32W_MAX_PACKET_LEN + 1]; #if RADIO_RXBUFS > 1 -static volatile int8_t first = -1, last=0; -#else -static const int8_t first=0, last=0; -#endif +static volatile int8_t first = -1, last = 0; +#else /* RADIO_RXBUFS > 1 */ +static const int8_t first = 0, last = 0; +#endif /* RADIO_RXBUFS > 1 */ #if RADIO_RXBUFS > 1 - #define CLEAN_RXBUFS() do{first = -1; last = 0;}while(0) - #define RXBUFS_EMPTY() (first == -1) - -int RXBUFS_FULL(){ - - int8_t first_tmp = first; - return first_tmp == last; +#define CLEAN_RXBUFS() do{first = -1; last = 0;}while(0) +#define RXBUFS_EMPTY() (first == -1) +int +RXBUFS_FULL() +{ + int8_t first_tmp = first; + return first_tmp == last; } - #else /* RADIO_RXBUFS > 1 */ - #define CLEAN_RXBUFS() (stm32w_rxbufs[0][0] = 0) - #define RXBUFS_EMPTY() (stm32w_rxbufs[0][0] == 0) - #define RXBUFS_FULL() (stm32w_rxbufs[0][0] != 0) +#define CLEAN_RXBUFS() (stm32w_rxbufs[0][0] = 0) +#define RXBUFS_EMPTY() (stm32w_rxbufs[0][0] == 0) +#define RXBUFS_FULL() (stm32w_rxbufs[0][0] != 0) #endif /* RADIO_RXBUFS > 1 */ -static uint8_t __attribute__(( aligned(2) )) stm32w_txbuf[STM32W_MAX_PACKET_LEN+1]; +static uint8_t + __attribute__ ((aligned(2))) stm32w_txbuf[STM32W_MAX_PACKET_LEN + 1]; #define CLEAN_TXBUF() (stm32w_txbuf[0] = 0) #define TXBUF_EMPTY() (stm32w_txbuf[0] == 0) - #define CHECKSUM_LEN 2 /* @@ -218,65 +216,76 @@ static uint8_t __attribute__(( aligned(2) )) stm32w_txbuf[STM32W_MAX_PACKET_LEN+ #define ON 0 #define OFF 1 +#define BUSYWAIT_UNTIL(cond, max_time) \ + do { \ + rtimer_clock_t t0; \ + t0 = RTIMER_NOW(); \ + while(!(cond) && RTIMER_CLOCK_LT(RTIMER_NOW(), t0 + (max_time))); \ + } while(0) + +#define GET_LOCK() locked++ + static volatile uint8_t onoroff = OFF; static uint8_t receiving_packet = 0; -static s8 last_rssi; +static int8_t last_rssi; static volatile StStatus last_tx_status; - -#define BUSYWAIT_UNTIL(cond, max_time) \ - do { \ - rtimer_clock_t t0; \ - t0 = RTIMER_NOW(); \ - while(!(cond) && RTIMER_CLOCK_LT(RTIMER_NOW(), t0 + (max_time))); \ - } while(0) - static uint8_t locked; -#define GET_LOCK() locked++ -static void RELEASE_LOCK(void) { - if(locked>0) - locked--; -} static volatile uint8_t is_transmit_ack; +/*--------------------------------------------------------------------------*/ +static void +RELEASE_LOCK(void) +{ + if(locked > 0) + locked--; +} /*---------------------------------------------------------------------------*/ PROCESS(stm32w_radio_process, "STM32W radio driver"); /*---------------------------------------------------------------------------*/ - static int stm32w_radio_init(void); -static int stm32w_radio_prepare(const void *payload, unsigned short payload_len); + +static int stm32w_radio_prepare(const void *payload, + unsigned short payload_len); static int stm32w_radio_transmit(unsigned short payload_len); + static int stm32w_radio_send(const void *data, unsigned short len); + static int stm32w_radio_read(void *buf, unsigned short bufsize); + static int stm32w_radio_channel_clear(void); + static int stm32w_radio_receiving_packet(void); + static int stm32w_radio_pending_packet(void); + static int stm32w_radio_on(void); + static int stm32w_radio_off(void); static int add_to_rxbuf(uint8_t * src); -static int read_from_rxbuf(void * dest, unsigned short len); - -const struct radio_driver stm32w_radio_driver = - { - stm32w_radio_init, - stm32w_radio_prepare, - stm32w_radio_transmit, - stm32w_radio_send, - stm32w_radio_read, - stm32w_radio_channel_clear, - stm32w_radio_receiving_packet, - stm32w_radio_pending_packet, - stm32w_radio_on, - stm32w_radio_off, - }; +static int read_from_rxbuf(void *dest, unsigned short len); +/*--------------------------------------------------------------------------*/ +const struct radio_driver stm32w_radio_driver = { + stm32w_radio_init, + stm32w_radio_prepare, + stm32w_radio_transmit, + stm32w_radio_send, + stm32w_radio_read, + stm32w_radio_channel_clear, + stm32w_radio_receiving_packet, + stm32w_radio_pending_packet, + stm32w_radio_on, + stm32w_radio_off, +}; /*---------------------------------------------------------------------------*/ -static int stm32w_radio_init(void) +static int +stm32w_radio_init(void) { - // A channel needs also to be setted. + /* A channel also needs to be set. */ ST_RadioSetChannel(RF_CHANNEL); - // Initialize radio (analog section, digital baseband and MAC). - // Leave radio powered up in non-promiscuous rx mode. + /* Initialize radio (analog section, digital baseband and MAC). */ + /* Leave radio powered up in non-promiscuous rx mode. */ ST_RadioInit(ST_RADIO_POWER_MODE_OFF); onoroff = OFF; @@ -297,172 +306,185 @@ static int stm32w_radio_init(void) return 0; } /*---------------------------------------------------------------------------*/ -int stm32w_radio_set_channel(uint8_t channel) +void +stm32w_radio_set_promiscous(uint8_t on) { - if (ST_RadioSetChannel(channel) == ST_SUCCESS) - return 0; - else - return 1; + if(on) { + ST_RadioEnableAddressFiltering(0); + } else { + ST_RadioEnableAddressFiltering(ST_RADIO_AUTOACK); + } } /*---------------------------------------------------------------------------*/ -static int wait_for_tx(void){ - +int +stm32w_radio_set_channel(uint8_t channel) +{ + if (ST_RadioSetChannel(channel) == ST_SUCCESS) { + return 0; + } else { + return 1; + } +} +/*---------------------------------------------------------------------------*/ +static int +wait_for_tx(void) +{ struct timer t; - - timer_set(&t, CLOCK_SECOND/10); - while(!TXBUF_EMPTY()){ - if(timer_expired(&t)){ + timer_set(&t, CLOCK_SECOND / 10); + while(!TXBUF_EMPTY()) { + if(timer_expired(&t)) { PRINTF("stm32w: tx buffer full.\r\n"); return 1; } /* Put CPU in sleep mode. */ - halSleepWithOptions(SLEEPMODE_IDLE,0); + halSleepWithOptions(SLEEPMODE_IDLE, 0); } return 0; } /*---------------------------------------------------------------------------*/ -static int stm32w_radio_prepare(const void *payload, unsigned short payload_len) +static int +stm32w_radio_prepare(const void *payload, unsigned short payload_len) { - if(payload_len > STM32W_MAX_PACKET_LEN){ - PRINTF("stm32w: payload length=%d is too long.\r\n", payload_len); - return RADIO_TX_ERR; - } - + if(payload_len > STM32W_MAX_PACKET_LEN) { + PRINTF("stm32w: payload length=%d is too long.\r\n", payload_len); + return RADIO_TX_ERR; + } #if !RADIO_WAIT_FOR_PACKET_SENT - /* Check if the txbuf is empty. - * Wait for a finite time. - * This sould not occur if we wait for the end of transmission in stm32w_radio_transmit(). - */ - if(wait_for_tx()){ - PRINTF("stm32w: tx buffer full.\r\n"); - return RADIO_TX_ERR; - } + /* + * Check if the txbuf is empty. Wait for a finite time. + * This should not occur if we wait for the end of transmission in + * stm32w_radio_transmit(). + */ + if(wait_for_tx()) { + PRINTF("stm32w: tx buffer full.\r\n"); + return RADIO_TX_ERR; + } #endif /* RADIO_WAIT_FOR_PACKET_SENT */ - /* Copy to the txbuf. - * The first byte must be the packet length. - */ - CLEAN_TXBUF(); - memcpy(stm32w_txbuf + 1, payload, payload_len); - - return RADIO_TX_OK; + /* + * Copy to the txbuf. + * The first byte must be the packet length. + */ + CLEAN_TXBUF(); + memcpy(stm32w_txbuf + 1, payload, payload_len); + return RADIO_TX_OK; } /*---------------------------------------------------------------------------*/ -static int stm32w_radio_transmit(unsigned short payload_len) +static int +stm32w_radio_transmit(unsigned short payload_len) { - stm32w_txbuf[0] = payload_len + CHECKSUM_LEN; - - INIT_RETRY_CNT(); - - if(onoroff == OFF){ - PRINTF("stm32w: Radio is off, turning it on.\r\n"); - ST_RadioWake(); - ENERGEST_ON(ENERGEST_TYPE_LISTEN); - } + stm32w_txbuf[0] = payload_len + CHECKSUM_LEN; + INIT_RETRY_CNT(); + if(onoroff == OFF) { + PRINTF("stm32w: Radio is off, turning it on.\r\n"); + ST_RadioWake(); + ENERGEST_ON(ENERGEST_TYPE_LISTEN); + } #if RADIO_WAIT_FOR_PACKET_SENT - GET_LOCK(); + GET_LOCK(); #endif /* RADIO_WAIT_FOR_PACKET_SENT */ - last_tx_status = -1; - LED_TX_ON(); - if(ST_RadioTransmit(stm32w_txbuf)==ST_SUCCESS){ - - ENERGEST_OFF(ENERGEST_TYPE_LISTEN); - ENERGEST_ON(ENERGEST_TYPE_TRANSMIT); - - PRINTF("stm32w: sending %d bytes\r\n", payload_len); + last_tx_status = -1; + LED_TX_ON(); + if(ST_RadioTransmit(stm32w_txbuf) == ST_SUCCESS) { + ENERGEST_OFF(ENERGEST_TYPE_LISTEN); + ENERGEST_ON(ENERGEST_TYPE_TRANSMIT); + PRINTF("stm32w: sending %d bytes\r\n", payload_len); #if DEBUG > 1 - for(uint8_t c=1; c <= stm32w_txbuf[0]-2; c++){ - PRINTF("%x:",stm32w_txbuf[c]); - } - PRINTF("\r\n"); + for(uint8_t c = 1; c <= stm32w_txbuf[0] - 2; c++) { + PRINTF("%x:", stm32w_txbuf[c]); + } + PRINTF("\r\n"); #endif #if RADIO_WAIT_FOR_PACKET_SENT - if(wait_for_tx()){ - PRINTF("stm32w: unknown tx error.\r\n"); - TO_PREV_STATE(); - LED_TX_OFF(); - RELEASE_LOCK(); - return RADIO_TX_ERR; - } + if(wait_for_tx()) { + PRINTF("stm32w: unknown tx error.\r\n"); TO_PREV_STATE(); - if(last_tx_status == ST_SUCCESS || last_tx_status == ST_PHY_ACK_RECEIVED || last_tx_status == ST_MAC_NO_ACK_RECEIVED){ - RELEASE_LOCK(); - if(last_tx_status == ST_PHY_ACK_RECEIVED){ - return RADIO_TX_OK; /* ACK status */ - } - else if (last_tx_status == ST_MAC_NO_ACK_RECEIVED || last_tx_status == ST_SUCCESS){ - return RADIO_TX_NOACK; - } - } LED_TX_OFF(); RELEASE_LOCK(); return RADIO_TX_ERR; + } + + TO_PREV_STATE(); + if(last_tx_status == ST_SUCCESS || last_tx_status == ST_PHY_ACK_RECEIVED || + last_tx_status == ST_MAC_NO_ACK_RECEIVED) { + RELEASE_LOCK(); + if(last_tx_status == ST_PHY_ACK_RECEIVED) { + return RADIO_TX_OK; /* ACK status */ + } else if(last_tx_status == ST_MAC_NO_ACK_RECEIVED || + last_tx_status == ST_SUCCESS) { + return RADIO_TX_NOACK; + } + } + LED_TX_OFF(); + RELEASE_LOCK(); + return RADIO_TX_ERR; #else /* RADIO_WAIT_FOR_PACKET_SENT */ - - TO_PREV_STATE(); - LED_TX_OFF(); - return RADIO_TX_OK; + TO_PREV_STATE(); + LED_TX_OFF(); + return RADIO_TX_OK; #endif /* RADIO_WAIT_FOR_PACKET_SENT */ - - } + } #if RADIO_WAIT_FOR_PACKET_SENT - RELEASE_LOCK(); + RELEASE_LOCK(); #endif /* RADIO_WAIT_FOR_PACKET_SENT */ - TO_PREV_STATE(); + TO_PREV_STATE(); - PRINTF("stm32w: transmission never started.\r\n"); - /* TODO: Do we have to retransmit? */ - - CLEAN_TXBUF(); - LED_TX_OFF(); - return RADIO_TX_ERR; + PRINTF("stm32w: transmission never started.\r\n"); + /* TODO: Do we have to retransmit? */ + CLEAN_TXBUF(); + LED_TX_OFF(); + return RADIO_TX_ERR; } /*---------------------------------------------------------------------------*/ -static int stm32w_radio_send(const void *payload, unsigned short payload_len) +static int +stm32w_radio_send(const void *payload, unsigned short payload_len) { - if(stm32w_radio_prepare(payload, payload_len) == RADIO_TX_ERR) + if (stm32w_radio_prepare(payload, payload_len) == RADIO_TX_ERR) { return RADIO_TX_ERR; - + } return stm32w_radio_transmit(payload_len); - } /*---------------------------------------------------------------------------*/ -static int stm32w_radio_channel_clear(void) +static int +stm32w_radio_channel_clear(void) { return ST_RadioChannelIsClear(); } /*---------------------------------------------------------------------------*/ -static int stm32w_radio_receiving_packet(void) +static int +stm32w_radio_receiving_packet(void) { return receiving_packet; } /*---------------------------------------------------------------------------*/ -static int stm32w_radio_pending_packet(void) +static int +stm32w_radio_pending_packet(void) { return !RXBUFS_EMPTY(); } /*---------------------------------------------------------------------------*/ -static int stm32w_radio_off(void) +static int +stm32w_radio_off(void) { /* Any transmit or receive packets in progress are aborted. * Waiting for end of transmission or reception have to be done. */ - if(locked) - { - PRINTF("stm32w: try to off while sending/receiving (lock=%u).\r\n", locked); + if(locked) { + PRINTF("stm32w: try to off while sending/receiving (lock=%u).\r\n", + locked); return 0; } /* off only if there is no transmission or reception of packet. */ - if(onoroff == ON && TXBUF_EMPTY() && !receiving_packet){ + if(onoroff == ON && TXBUF_EMPTY() && !receiving_packet) { LED_RDC_OFF(); ST_RadioSleep(); onoroff = OFF; @@ -475,10 +497,11 @@ static int stm32w_radio_off(void) return 1; } /*---------------------------------------------------------------------------*/ -static int stm32w_radio_on(void) +static int +stm32w_radio_on(void) { PRINTF("stm32w: turn radio on\n"); - if(onoroff == OFF){ + if(onoroff == OFF) { LED_RDC_ON(); ST_RadioWake(); onoroff = ON; @@ -489,24 +512,23 @@ static int stm32w_radio_on(void) return 1; } /*---------------------------------------------------------------------------*/ -int stm32w_radio_is_on(void) +int +stm32w_radio_is_on(void) { return onoroff == ON; } /*---------------------------------------------------------------------------*/ - - -void ST_RadioReceiveIsrCallback(u8 *packet, - boolean ackFramePendingSet, - u32 time, - u16 errors, - s8 rssi) +void +ST_RadioReceiveIsrCallback(uint8_t *packet, + boolean ackFramePendingSet, + uint32_t time, uint16_t errors, int8_t rssi) { LED_RX_ON(); PRINTF("stm32w: incomming packet received\n"); receiving_packet = 0; + /* Copy packet into the buffer. It is better to do this here. */ - if(add_to_rxbuf(packet)){ + if(add_to_rxbuf(packet)) { process_poll(&stm32w_radio_process); last_rssi = rssi; } @@ -516,83 +538,76 @@ void ST_RadioReceiveIsrCallback(u8 *packet, /* Wait for sending ACK */ BUSYWAIT_UNTIL(!is_transmit_ack, RTIMER_SECOND / 1500); RELEASE_LOCK(); - } - -void ST_RadioTxAckIsrCallback (void) +/*--------------------------------------------------------------------------*/ +void +ST_RadioTxAckIsrCallback(void) { - /* This callback is for simplemac 1.1.0. - Till now we block (RTIMER_SECOND / 1500) - to prevent radio off during ACK transmission */ + /* + * This callback is for simplemac 1.1.0. + * Till now we block (RTIMER_SECOND / 1500) + * to prevent radio off during ACK transmission. + */ is_transmit_ack = 0; - //RELEASE_LOCK(); + /* RELEASE_LOCK(); */ } - - -void ST_RadioTransmitCompleteIsrCallback(StStatus status, - u32 txSyncTime, - boolean framePending) +/*--------------------------------------------------------------------------*/ +void +ST_RadioTransmitCompleteIsrCallback(StStatus status, + uint32_t txSyncTime, boolean framePending) { - ENERGEST_OFF(ENERGEST_TYPE_TRANSMIT); ENERGEST_ON(ENERGEST_TYPE_LISTEN); LED_TX_OFF(); last_tx_status = status; - if(status == ST_SUCCESS || status == ST_PHY_ACK_RECEIVED){ + if(status == ST_SUCCESS || status == ST_PHY_ACK_RECEIVED) { + CLEAN_TXBUF(); + } else { + if(RETRY_CNT_GTZ()) { + + /* Retransmission */ + LED_TX_ON(); + if(ST_RadioTransmit(stm32w_txbuf) == ST_SUCCESS) { + ENERGEST_OFF(ENERGEST_TYPE_LISTEN); + ENERGEST_ON(ENERGEST_TYPE_TRANSMIT); + PRINTF("stm32w: retransmission.\r\n"); + DEC_RETRY_CNT(); + } else { + CLEAN_TXBUF(); + LED_TX_OFF(); + PRINTF("stm32w: retransmission failed.\r\n"); + } + } else { CLEAN_TXBUF(); - } - else { - - if(RETRY_CNT_GTZ()){ - // Retransmission - LED_TX_ON(); - if(ST_RadioTransmit(stm32w_txbuf)==ST_SUCCESS){ - - ENERGEST_OFF(ENERGEST_TYPE_LISTEN); - ENERGEST_ON(ENERGEST_TYPE_TRANSMIT); - - PRINTF("stm32w: retransmission.\r\n"); - - DEC_RETRY_CNT(); - } - else { - CLEAN_TXBUF(); - LED_TX_OFF(); - PRINTF("stm32w: retransmission failed.\r\n"); - } - } - else { - CLEAN_TXBUF(); - } + } } /* Debug outputs. */ - if(status == ST_SUCCESS || status == ST_PHY_ACK_RECEIVED){ - PRINTF("stm32w: return status TX_END\r\n"); - } - else if (status == ST_MAC_NO_ACK_RECEIVED){ - PRINTF("stm32w: return status TX_END_NOACK\r\n"); - } - else if (status == ST_PHY_TX_CCA_FAIL){ - PRINTF("stm32w: return status TX_END_CCA_FAIL\r\n"); - } - else if(status == ST_PHY_TX_UNDERFLOW){ - PRINTF("stm32w: return status TX_END_UNDERFLOW\r\n"); - } - else { - PRINTF("stm32w: return status TX_END_INCOMPLETE\r\n"); + if(status == ST_SUCCESS || status == ST_PHY_ACK_RECEIVED) { + PRINTF("stm32w: return status TX_END\r\n"); + } else if(status == ST_MAC_NO_ACK_RECEIVED) { + PRINTF("stm32w: return status TX_END_NOACK\r\n"); + } else if(status == ST_PHY_TX_CCA_FAIL) { + PRINTF("stm32w: return status TX_END_CCA_FAIL\r\n"); + } else if(status == ST_PHY_TX_UNDERFLOW) { + PRINTF("stm32w: return status TX_END_UNDERFLOW\r\n"); + } else { + PRINTF("stm32w: return status TX_END_INCOMPLETE\r\n"); } } - - -boolean ST_RadioDataPendingShortIdIsrCallback(int16u shortId) { +/*--------------------------------------------------------------------------*/ +boolean +ST_RadioDataPendingShortIdIsrCallback(uint16_t shortId) +{ receiving_packet = 1; return FALSE; } - -boolean ST_RadioDataPendingLongIdIsrCallback(int8u* longId) { +/*--------------------------------------------------------------------------*/ +boolean +ST_RadioDataPendingLongIdIsrCallback(uint8_t * longId) +{ receiving_packet = 1; return FALSE; } @@ -600,20 +615,16 @@ boolean ST_RadioDataPendingLongIdIsrCallback(int8u* longId) { PROCESS_THREAD(stm32w_radio_process, ev, data) { int len; - PROCESS_BEGIN(); - PRINTF("stm32w_radio_process: started\r\n"); while(1) { - PROCESS_YIELD_UNTIL(ev == PROCESS_EVENT_POLL); - PRINTF("stm32w_radio_process: calling receiver callback\r\n"); #if DEBUG > 1 - for(uint8_t c=1; c <= RCVD_PACKET_LEN; c++){ - PRINTF("%x",stm32w_rxbuf[c]); + for(uint8_t c = 1; c <= RCVD_PACKET_LEN; c++) { + PRINTF("%x", stm32w_rxbuf[c]); } PRINTF("\r\n"); #endif @@ -624,84 +635,88 @@ PROCESS_THREAD(stm32w_radio_process, ev, data) packetbuf_set_datalen(len); NETSTACK_RDC.input(); } - if(!RXBUFS_EMPTY()){ - // Some data packet still in rx buffer (this happens because process_poll doesn't queue requests), - // so stm32w_radio_process need to be called again. + if(!RXBUFS_EMPTY()) { + /* + * Some data packet still in rx buffer (this happens because process_poll + * doesn't queue requests), so stm32w_radio_process needs to be called + * again. + */ process_poll(&stm32w_radio_process); } } - PROCESS_END(); } /*---------------------------------------------------------------------------*/ -static int stm32w_radio_read(void *buf, unsigned short bufsize) +static int +stm32w_radio_read(void *buf, unsigned short bufsize) { - return read_from_rxbuf(buf,bufsize); + return read_from_rxbuf(buf, bufsize); } - /*---------------------------------------------------------------------------*/ -void ST_RadioOverflowIsrCallback(void) +void +ST_RadioOverflowIsrCallback(void) { PRINTF("stm32w: radio overflow\r\n"); } /*---------------------------------------------------------------------------*/ -void ST_RadioSfdSentIsrCallback(u32 sfdSentTime) +void +ST_RadioSfdSentIsrCallback(uint32_t sfdSentTime) { } /*---------------------------------------------------------------------------*/ -void ST_RadioMacTimerCompareIsrCallback(void) +void +ST_RadioMacTimerCompareIsrCallback(void) { } /*---------------------------------------------------------------------------*/ -static int add_to_rxbuf(uint8_t * src) +static int +add_to_rxbuf(uint8_t *src) { - if(RXBUFS_FULL()){ - return 0; - } + if(RXBUFS_FULL()) { + return 0; + } - memcpy(stm32w_rxbufs[last], src, src[0] + 1); + memcpy(stm32w_rxbufs[last], src, src[0] + 1); #if RADIO_RXBUFS > 1 - last = (last + 1) % RADIO_RXBUFS; - if(first == -1){ - first = 0; - } + last = (last + 1) % RADIO_RXBUFS; + if(first == -1) { + first = 0; + } #endif - return 1; + return 1; } /*---------------------------------------------------------------------------*/ -static int read_from_rxbuf(void * dest, unsigned short len) +static int +read_from_rxbuf(void *dest, unsigned short len) { + if(RXBUFS_EMPTY()) { /* Buffers are all empty */ + return 0; + } - if(RXBUFS_EMPTY()){ // Buffers are all empty - return 0; - } - - if(stm32w_rxbufs[first][0] > len){ // Too large packet for dest. - len = 0; - } - else { - len = stm32w_rxbufs[first][0]; - memcpy(dest,stm32w_rxbufs[first]+1,len); - packetbuf_set_attr(PACKETBUF_ATTR_RSSI, last_rssi); - } + if(stm32w_rxbufs[first][0] > len) { /* Too large packet for dest. */ + len = 0; + } else { + len = stm32w_rxbufs[first][0]; + memcpy(dest, stm32w_rxbufs[first] + 1, len); + packetbuf_set_attr(PACKETBUF_ATTR_RSSI, last_rssi); + } #if RADIO_RXBUFS > 1 - ATOMIC( - first = (first + 1) % RADIO_RXBUFS; - int first_tmp = first; - if(first_tmp == last){ - CLEAN_RXBUFS(); - } - ) + ATOMIC(first = (first + 1) % RADIO_RXBUFS; + int first_tmp = first; if(first_tmp == last) { + CLEAN_RXBUFS();} + ) #else - CLEAN_RXBUFS(); + CLEAN_RXBUFS(); #endif - return len; + return len; } /*---------------------------------------------------------------------------*/ -short last_packet_rssi(){ - return last_rssi; +short +last_packet_rssi() +{ + return last_rssi; } - +/** @} */ diff --git a/cpu/stm32w108/dev/stm32w-radio.h b/cpu/stm32w108/dev/stm32w-radio.h index b8b14407b..7b73f573a 100644 --- a/cpu/stm32w108/dev/stm32w-radio.h +++ b/cpu/stm32w108/dev/stm32w-radio.h @@ -1,3 +1,9 @@ +/** + * \addtogroup stm32w-cpu + * + * @{ + */ + /* * Copyright (c) 2007, Swedish Institute of Computer Science. * All rights reserved. @@ -26,8 +32,6 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * This file is part of the Contiki operating system. - * */ /** @@ -45,14 +49,15 @@ #include "hal/hal.h" #include "simplemac/include/phy-library.h" -int stm32w_radio_set_channel(uint8_t channel); -short last_packet_rssi(); - #define STM32W_MAX_PACKET_LEN 127 extern const struct radio_driver stm32w_radio_driver; +int stm32w_radio_set_channel(uint8_t channel); + +short last_packet_rssi(); + int stm32w_radio_is_on(void); - #endif /* __STM32W_H__ */ +/** @} */ diff --git a/cpu/stm32w108/dev/stm32w-systick.c b/cpu/stm32w108/dev/stm32w-systick.c new file mode 100644 index 000000000..d719490e2 --- /dev/null +++ b/cpu/stm32w108/dev/stm32w-systick.c @@ -0,0 +1,150 @@ +/** + * \addtogroup stm32w-cpu + * + * @{ + */ + +/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** +* File Name : stm32w108_systick.c +* Author : MCD Application Team +* Version : V2.0.3 +* Date : 09/22/2008 +* Description : This file provides all the SysTick firmware functions. +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +#include +#include "stm32w-systick.h" + +/* SysTick registers bit mask */ +/* CTRL TICKINT Mask */ +#define CTRL_TICKINT_Set ((uint32_t)0x00000002) +#define CTRL_TICKINT_Reset ((uint32_t)0xFFFFFFFD) +/*--------------------------------------------------------------------------*/ +/** + * \brief Configures the SysTick clock source. + * \param SysTick_CLKSource specifies the SysTick clock source. + * This parameter can be one of the following values: + * SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 + * selected as SysTick clock source. + * SysTick_CLKSource_HCLK: AHB clock selected as + * SysTick clock source. + */ +void +SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource) +{ + /* Check the parameters */ + assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource)); + + if(SysTick_CLKSource == SysTick_CLKSource_HCLK) { + SysTick->CTRL |= SysTick_CLKSource_HCLK; + } else { + SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; + } +} +/*--------------------------------------------------------------------------*/ +/** + * \brief Sets SysTick Reload value. + * \param Reload SysTick Reload new value. Must be between 1 and 0xFFFFFF. + */ +void +SysTick_SetReload(uint32_t Reload) +{ + /* Check the parameters */ + assert_param(IS_SYSTICK_RELOAD(Reload)); + SysTick->LOAD = Reload; +} +/*--------------------------------------------------------------------------*/ +/** + * \brief Enables or disables the SysTick counter. + * \param SysTick_Counter new state of the SysTick counter. +* This parameter can be one of the following values: +* - SysTick_Counter_Disable: Disable counter +* - SysTick_Counter_Enable: Enable counter +* - SysTick_Counter_Clear: Clear counter value to 0 + */ +void +SysTick_CounterCmd(uint32_t SysTick_Counter) +{ + /* Check the parameters */ + assert_param(IS_SYSTICK_COUNTER(SysTick_Counter)); + + if(SysTick_Counter == SysTick_Counter_Enable) { + SysTick->CTRL |= SysTick_Counter_Enable; + } else if(SysTick_Counter == SysTick_Counter_Disable) { + SysTick->CTRL &= SysTick_Counter_Disable; + } else { /* SysTick_Counter == SysTick_Counter_Clear */ + SysTick->VAL = SysTick_Counter_Clear; + } +} +/*--------------------------------------------------------------------------*/ +/** + * \brief Enables or disables the SysTick Interrupt. + * \param NewState new state of the SysTick Interrupt. +* This parameter can be: ENABLE or DISABLE. + */ +void +SysTick_ITConfig(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if(NewState != DISABLE) { + SysTick->CTRL |= CTRL_TICKINT_Set; + } else { + SysTick->CTRL &= CTRL_TICKINT_Reset; + } +} +/*--------------------------------------------------------------------------*/ +/** + * \brief Gets SysTick counter value. + * \return SysTick current value + */ +uint32_t +SysTick_GetCounter(void) +{ + return (SysTick->VAL); +} +/*--------------------------------------------------------------------------*/ +/** + * \brief Checks whether the specified SysTick flag is set or not. + * \param SysTick_FLAG specifies the flag to check. +* This parameter can be one of the following values: +* - SysTick_FLAG_COUNT +* - SysTick_FLAG_SKEW +* - SysTick_FLAG_NOREF + */ +FlagStatus +SysTick_GetFlagStatus(uint8_t SysTick_FLAG) +{ + uint32_t statusreg = 0, tmp = 0; + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_SYSTICK_FLAG(SysTick_FLAG)); + + /* Get the SysTick register index */ + tmp = SysTick_FLAG >> 3; + + if(tmp == 2) { /* The flag to check is in CTRL register */ + statusreg = SysTick->CTRL; + } else { /* The flag to check is in CALIB register */ + + statusreg = SysTick->CALIB; + } + + if((statusreg & ((uint32_t) 1 << SysTick_FLAG)) != (uint32_t) RESET) { + bitstatus = SET; + } else { + bitstatus = RESET; + } + return bitstatus; +} +/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ +/** @} */ diff --git a/cpu/stm32w108/dev/stm32w_systick.h b/cpu/stm32w108/dev/stm32w-systick.h similarity index 77% rename from cpu/stm32w108/dev/stm32w_systick.h rename to cpu/stm32w108/dev/stm32w-systick.h index 415be6429..6027c5d87 100644 --- a/cpu/stm32w108/dev/stm32w_systick.h +++ b/cpu/stm32w108/dev/stm32w-systick.h @@ -1,3 +1,9 @@ +/** + * \addtogroup stm32w-cpu + * + * @{ + */ + /******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** * File Name : stm32f10x_systick.h * Author : MCD Application Team @@ -14,19 +20,17 @@ * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *******************************************************************************/ -/* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32W_SYSTICK_H #define __STM32W_SYSTICK_H -#include "stm32w108_type.h" -#include "stm32w_conf.h" +#include "stm32w108-type.h" +#include "stm32w-conf.h" #ifndef EXT - #define EXT extern +#define EXT extern #endif /* EXT */ -typedef struct -{ +typedef struct { vu32 CTRL; vu32 LOAD; vu32 VAL; @@ -41,39 +45,47 @@ typedef struct #define SCB_BASE (SCS_BASE + 0x0D00) #ifdef _SysTick - #define SysTick ((SysTick_TypeDef *) SysTick_BASE) +#define SysTick ((SysTick_TypeDef *) SysTick_BASE) #endif /*_SysTick */ /***************** Bit definition for SysTick_CTRL register *****************/ -#define SysTick_CTRL_ENABLE ((u32)0x00000001) /* Counter enable */ -#define SysTick_CTRL_TICKINT ((u32)0x00000002) /* Counting down to 0 pends the SysTick handler */ -#define SysTick_CTRL_CLKSOURCE ((u32)0x00000004) /* Clock source */ -#define SysTick_CTRL_COUNTFLAG ((u32)0x00010000) /* Count Flag */ +/* Counter enable */ +#define SysTick_CTRL_ENABLE ((u32)0x00000001) +/* Counting down to 0 pends the SysTick handler */ +#define SysTick_CTRL_TICKINT ((u32)0x00000002) +/* Clock source */ +#define SysTick_CTRL_CLKSOURCE ((u32)0x00000004) +/* Count Flag */ +#define SysTick_CTRL_COUNTFLAG ((u32)0x00010000) /***************** Bit definition for SysTick_LOAD register *****************/ -#define SysTick_LOAD_RELOAD ((u32)0x00FFFFFF) /* Value to load into the SysTick Current Value Register when the counter reaches 0 */ +/* + * Value to load into the SysTick Current Value Register when the + * counter reaches 0 + */ +#define SysTick_LOAD_RELOAD ((u32)0x00FFFFFF) /***************** Bit definition for SysTick_VAL register ******************/ -#define SysTick_VAL_CURRENT ((u32)0x00FFFFFF) /* Current value at the time the register is accessed */ +/* Current value at the time the register is accessed */ +#define SysTick_VAL_CURRENT ((u32)0x00FFFFFF) /***************** Bit definition for SysTick_CALIB register ****************/ -#define SysTick_CALIB_TENMS ((u32)0x00FFFFFF) /* Reload value to use for 10ms timing */ -#define SysTick_CALIB_SKEW ((u32)0x40000000) /* Calibration value is not exactly 10 ms */ -#define SysTick_CALIB_NOREF ((u32)0x80000000) /* The reference clock is not provided */ +/* Reload value to use for 10ms timing */ +#define SysTick_CALIB_TENMS ((u32)0x00FFFFFF) +/* Calibration value is not exactly 10 ms */ +#define SysTick_CALIB_SKEW ((u32)0x40000000) +/* The reference clock is not provided */ +#define SysTick_CALIB_NOREF ((u32)0x80000000) -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/* SysTick clock source */ #define SysTick_CLKSource_HCLK_Div8 ((u32)0xFFFFFFFB) #define SysTick_CLKSource_HCLK ((u32)0x00000004) - #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \ - ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) + ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) /* SysTick counter state */ #define SysTick_Counter_Disable ((u32)0xFFFFFFFE) @@ -95,15 +107,18 @@ typedef struct #define IS_SYSTICK_RELOAD(RELOAD) (((RELOAD) > 0) && ((RELOAD) <= 0xFFFFFF)) -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ void SysTick_CLKSourceConfig(u32 SysTick_CLKSource); + void SysTick_SetReload(u32 Reload); + void SysTick_CounterCmd(u32 SysTick_Counter); + void SysTick_ITConfig(FunctionalState NewState); + u32 SysTick_GetCounter(void); + FlagStatus SysTick_GetFlagStatus(u8 SysTick_FLAG); #endif /* __STM32F10x_SYSTICK_H */ - /******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ +/** @} */ diff --git a/cpu/stm32w108/dev/stm32w_conf.h b/cpu/stm32w108/dev/stm32w_conf.h deleted file mode 100644 index 84aa3d6ec..000000000 --- a/cpu/stm32w108/dev/stm32w_conf.h +++ /dev/null @@ -1,174 +0,0 @@ -/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** -* File Name : stm32w_conf.h -* Author : MCD Application Team -* Version : V2.0.3 -* Date : 09/22/2008 -* Description : Library configuration file. -******************************************************************************** -* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_CONF_H -#define __STM32F10x_CONF_H - -/* Includes ------------------------------------------------------------------*/ -#include "stm32w108_type.h" - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/* Uncomment the line below to compile the library in DEBUG mode, this will expanse - the "assert_param" macro in the firmware library code (see "Exported macro" - section below) */ -/*#define DEBUG 1*/ - -/* Comment the line below to disable the specific peripheral inclusion */ -/************************************* ADC ************************************/ -//#define _ADC -//#define _ADC1 -//#define _ADC2 -//#define _ADC3 - -/************************************* BKP ************************************/ -//#define _BKP - -/************************************* CAN ************************************/ -//#define _CAN - -/************************************* CRC ************************************/ -//#define _CRC - -/************************************* DAC ************************************/ -//#define _DAC - -/************************************* DBGMCU *********************************/ -//#define _DBGMCU - -/************************************* DMA ************************************/ -//#define _DMA -//#define _DMA1_Channel1 -//#define _DMA1_Channel2 -//#define _DMA1_Channel3 -//#define _DMA1_Channel4 -//#define _DMA1_Channel5 -//#define _DMA1_Channel6 -//#define _DMA1_Channel7 -//#define _DMA2_Channel1 -//#define _DMA2_Channel2 -//#define _DMA2_Channel3 -//#define _DMA2_Channel4 -//#define _DMA2_Channel5 - -/************************************* EXTI ***********************************/ -//#define _EXTI - -/************************************* FLASH and Option Bytes *****************/ -#define _FLASH -/* Uncomment the line below to enable FLASH program/erase/protections functions, - otherwise only FLASH configuration (latency, prefetch, half cycle) functions - are enabled */ -/* #define _FLASH_PROG */ - -/************************************* FSMC ***********************************/ -//#define _FSMC - -/************************************* GPIO ***********************************/ -#define _GPIO -//#define _GPIOA -//#define _GPIOB -#define _GPIOC -//#define _GPIOD -//#define _GPIOE -#define _GPIOF -//#define _GPIOG -#define _AFIO - -/************************************* I2C ************************************/ -//#define _I2C -//#define _I2C1 -//#define _I2C2 - -/************************************* IWDG ***********************************/ -//#define _IWDG - -/************************************* NVIC ***********************************/ -#define _NVIC - -/************************************* PWR ************************************/ -//#define _PWR - -/************************************* RCC ************************************/ -#define _RCC - -/************************************* RTC ************************************/ -//#define _RTC - -/************************************* SDIO ***********************************/ -//#define _SDIO - -/************************************* SPI ************************************/ -//#define _SPI -//#define _SPI1 -//#define _SPI2 -//#define _SPI3 - -/************************************* SysTick ********************************/ -#define _SysTick - -/************************************* TIM ************************************/ -//#define _TIM -//#define _TIM1 -//#define _TIM2 -//#define _TIM3 -//#define _TIM4 -//#define _TIM5 -//#define _TIM6 -//#define _TIM7 -//#define _TIM8 - -/************************************* USART **********************************/ -//#define _USART -//#define _USART1 -//#define _USART2 -//#define _USART3 -//#define _UART4 -//#define _UART5 - -/************************************* WWDG ***********************************/ -//#define _WWDG - -/* In the following line adjust the value of External High Speed oscillator (HSE) - used in your application */ -#define HSE_Value ((u32)8000000) /* Value of the External oscillator in Hz*/ - -/* In the following line adjust the External High Speed oscillator (HSE) Startup - Timeout value */ -#define HSEStartUp_TimeOut ((u16)0x0500) /* Time out for HSE start up */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef DEBUG -/******************************************************************************* -* Macro Name : assert_param -* Description : The assert_param macro is used for function's parameters check. -* It is used only if the library is compiled in DEBUG mode. -* Input : - expr: If expr is false, it calls assert_failed function -* which reports the name of the source file and the source -* line number of the call that failed. -* If expr is true, it returns no value. -* Return : None -*******************************************************************************/ - #define assert_param(expr) ((expr) ? (void)0 : assert_failed((u8 *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(u8* file, u32 line); -#else - #define assert_param(expr) ((void)0) -#endif /* DEBUG */ - -#endif /* __STM32F10x_CONF_H */ - -/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/cpu/stm32w108/dev/stm32w_systick.c b/cpu/stm32w108/dev/stm32w_systick.c deleted file mode 100644 index de34f8c44..000000000 --- a/cpu/stm32w108/dev/stm32w_systick.c +++ /dev/null @@ -1,181 +0,0 @@ -/******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** -* File Name : stm32w108_systick.c -* Author : MCD Application Team -* Version : V2.0.3 -* Date : 09/22/2008 -* Description : This file provides all the SysTick firmware functions. -******************************************************************************** -* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32w_systick.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* ---------------------- SysTick registers bit mask -------------------- */ -/* CTRL TICKINT Mask */ -#define CTRL_TICKINT_Set ((u32)0x00000002) -#define CTRL_TICKINT_Reset ((u32)0xFFFFFFFD) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/******************************************************************************* -* Function Name : SysTick_CLKSourceConfig -* Description : Configures the SysTick clock source. -* Input : - SysTick_CLKSource: specifies the SysTick clock source. -* This parameter can be one of the following values: -* - SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 -* selected as SysTick clock source. -* - SysTick_CLKSource_HCLK: AHB clock selected as -* SysTick clock source. -* Output : None -* Return : None -*******************************************************************************/ -void SysTick_CLKSourceConfig(u32 SysTick_CLKSource) -{ - /* Check the parameters */ - assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource)); - - if (SysTick_CLKSource == SysTick_CLKSource_HCLK) - { - SysTick->CTRL |= SysTick_CLKSource_HCLK; - } - else - { - SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; - } -} - -/******************************************************************************* -* Function Name : SysTick_SetReload -* Description : Sets SysTick Reload value. -* Input : - Reload: SysTick Reload new value. -* This parameter must be a number between 1 and 0xFFFFFF. -* Output : None -* Return : None -*******************************************************************************/ -void SysTick_SetReload(u32 Reload) -{ - /* Check the parameters */ - assert_param(IS_SYSTICK_RELOAD(Reload)); - - SysTick->LOAD = Reload; -} - -/******************************************************************************* -* Function Name : SysTick_CounterCmd -* Description : Enables or disables the SysTick counter. -* Input : - SysTick_Counter: new state of the SysTick counter. -* This parameter can be one of the following values: -* - SysTick_Counter_Disable: Disable counter -* - SysTick_Counter_Enable: Enable counter -* - SysTick_Counter_Clear: Clear counter value to 0 -* Output : None -* Return : None -*******************************************************************************/ -void SysTick_CounterCmd(u32 SysTick_Counter) -{ - /* Check the parameters */ - assert_param(IS_SYSTICK_COUNTER(SysTick_Counter)); - - if (SysTick_Counter == SysTick_Counter_Enable) - { - SysTick->CTRL |= SysTick_Counter_Enable; - } - else if (SysTick_Counter == SysTick_Counter_Disable) - { - SysTick->CTRL &= SysTick_Counter_Disable; - } - else /* SysTick_Counter == SysTick_Counter_Clear */ - { - SysTick->VAL = SysTick_Counter_Clear; - } -} - -/******************************************************************************* -* Function Name : SysTick_ITConfig -* Description : Enables or disables the SysTick Interrupt. -* Input : - NewState: new state of the SysTick Interrupt. -* This parameter can be: ENABLE or DISABLE. -* Output : None -* Return : None -*******************************************************************************/ -void SysTick_ITConfig(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - SysTick->CTRL |= CTRL_TICKINT_Set; - } - else - { - SysTick->CTRL &= CTRL_TICKINT_Reset; - } -} - -/******************************************************************************* -* Function Name : SysTick_GetCounter -* Description : Gets SysTick counter value. -* Input : None -* Output : None -* Return : SysTick current value -*******************************************************************************/ -u32 SysTick_GetCounter(void) -{ - return(SysTick->VAL); -} - -/******************************************************************************* -* Function Name : SysTick_GetFlagStatus -* Description : Checks whether the specified SysTick flag is set or not. -* Input : - SysTick_FLAG: specifies the flag to check. -* This parameter can be one of the following values: -* - SysTick_FLAG_COUNT -* - SysTick_FLAG_SKEW -* - SysTick_FLAG_NOREF -* Output : None -* Return : None -*******************************************************************************/ -FlagStatus SysTick_GetFlagStatus(u8 SysTick_FLAG) -{ - u32 statusreg = 0, tmp = 0 ; - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_SYSTICK_FLAG(SysTick_FLAG)); - - /* Get the SysTick register index */ - tmp = SysTick_FLAG >> 3; - - if (tmp == 2) /* The flag to check is in CTRL register */ - { - statusreg = SysTick->CTRL; - } - else /* The flag to check is in CALIB register */ - { - statusreg = SysTick->CALIB; - } - - if ((statusreg & ((u32)1 << SysTick_FLAG)) != (u32)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ diff --git a/cpu/stm32w108/dev/uart1-putchar.c b/cpu/stm32w108/dev/uart1-putchar.c index 323e3d476..216fd9291 100644 --- a/cpu/stm32w108/dev/uart1-putchar.c +++ b/cpu/stm32w108/dev/uart1-putchar.c @@ -1,3 +1,39 @@ +/** + * \addtogroup stm32w-cpu + * + * @{ + */ + +/* + * Copyright (c) 2010, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ + #include #include "dev/uart1.h" @@ -5,7 +41,7 @@ #include PLATFORM_HEADER #include "hal/micro/micro-common.h" #include "hal/micro/cortexm3/micro-common.h" -//#include "uart.h" + /* #include "uart.h" */ #ifdef __GNUC__ # define _LLIO_STDIN ((int) stdin) @@ -19,38 +55,40 @@ #endif #undef putchar - -int __attribute__(( weak )) putchar(int c) +/*--------------------------------------------------------------------------*/ +int + __attribute__ ((weak)) putchar(int c) { uart1_writeb(c); return c; } - -void __io_putchar(char c) +/*--------------------------------------------------------------------------*/ +void +__io_putchar(char c) { putchar(c); } - -size_t _write(int handle, const unsigned char * buffer, size_t size) +/*--------------------------------------------------------------------------*/ +size_t +_write(int handle, const unsigned char *buffer, size_t size) { size_t nChars = 0; - if (handle != _LLIO_STDOUT && handle != _LLIO_STDERR) { + if(handle != _LLIO_STDOUT && handle != _LLIO_STDERR) { return _LLIO_ERROR; } - - if (buffer == 0) { - // This means that we should flush internal buffers. - //spin until TX complete (TX is idle) - while ((SC1_UARTSTAT&SC_UARTTXIDLE)!=SC_UARTTXIDLE) {} + if(buffer == 0) { + /* This means that we should flush internal buffers. */ + /* spin until TX complete (TX is idle) */ + while((SC1_UARTSTAT & SC_UARTTXIDLE) != SC_UARTTXIDLE) { + } return 0; } - - // ensure port is configured for UART + + /* ensure port is configured for UART */ if(SC1_MODE != SC1_MODE_UART) { return _LLIO_ERROR; } - while(size--) { __io_putchar(*buffer++); ++nChars; @@ -59,9 +97,10 @@ size_t _write(int handle, const unsigned char * buffer, size_t size) return nChars; } - -size_t _read(int handle, unsigned char * buffer, size_t size) +/*--------------------------------------------------------------------------*/ +size_t +_read(int handle, unsigned char *buffer, size_t size) { - return 0; + return 0; } - +/** @} */ diff --git a/cpu/stm32w108/dev/uart1.c b/cpu/stm32w108/dev/uart1.c index b1dd0bf92..87b05e4f6 100644 --- a/cpu/stm32w108/dev/uart1.c +++ b/cpu/stm32w108/dev/uart1.c @@ -1,3 +1,9 @@ +/** + * \addtogroup stm32w-cpu + * + * @{ + */ + /* * Copyright (c) 2010, STMicroelectronics. * All rights reserved. @@ -27,10 +33,9 @@ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * This file is part of the Contiki OS * */ -/*---------------------------------------------------------------------------*/ + /** * \file * Machine dependent STM32W UART1 code. @@ -41,53 +46,42 @@ * \since * 03.04.2010 */ -/*---------------------------------------------------------------------------*/ #include #include -//#include -//#include - #include "sys/energest.h" #include "dev/uart1.h" #include "dev/watchdog.h" - #include "lib/ringbuf.h" - #include "dev/leds.h" -static int (*uart1_input_handler)(unsigned char c); +static int (*uart1_input_handler) (unsigned char c); + +void uart1_rx_interrupt(void); + +void uart1_tx_interrupt(void); static volatile uint8_t transmitting; #ifdef UART1_CONF_TX_WITH_INTERRUPT #define TX_WITH_INTERRUPT UART1_CONF_TX_WITH_INTERRUPT #else /* UART1_CONF_TX_WITH_INTERRUPT */ -#define TX_WITH_INTERRUPT 1 +#define TX_WITH_INTERRUPT 1 #endif /* UART1_CONF_TX_WITH_INTERRUPT */ #if TX_WITH_INTERRUPT - #ifdef UART1_CONF_TX_BUFSIZE #define UART1_TX_BUFSIZE UART1_CONF_TX_BUFSIZE #else /* UART1_CONF_TX_BUFSIZE */ #define UART1_TX_BUFSIZE 64 #endif /* UART1_CONF_TX_BUFSIZE */ - static struct ringbuf txbuf; static uint8_t txbuf_data[UART1_TX_BUFSIZE]; #endif /* TX_WITH_INTERRUPT */ - -/*---------------------------------------------------------------------------*/ -//uint8_t -//uart1_active(void) -//{ -// return ((~ UTCTL1) & TXEPT) | transmitting; -//} /*---------------------------------------------------------------------------*/ void -uart1_set_input(int (*input)(unsigned char c)) +uart1_set_input(int (*input) (unsigned char c)) { uart1_input_handler = input; } @@ -97,21 +91,23 @@ uart1_writeb(unsigned char c) { watchdog_periodic(); #if TX_WITH_INTERRUPT - - /* Put the outgoing byte on the transmission buffer. If the buffer - is full, we just keep on trying to put the byte into the buffer - until it is possible to put it there. */ + /* + * Put the outgoing byte on the transmission buffer. If the buffer + * is full, we just keep on trying to put the byte into the buffer + * until it is possible to put it there. + */ while(ringbuf_put(&txbuf, c) == 0); - /* If there is no transmission going, we need to start it by putting - the first byte into the UART. */ + /* + * If there is no transmission going, we need to start it by putting + * the first byte into the UART. + */ if(transmitting == 0) { - transmitting = 1; + transmitting = 1; SC1_DATA = ringbuf_get(&txbuf); INT_SC1FLAG = INT_SCTXFREE; INT_SC1CFG |= INT_SCTXFREE; } - #else /* TX_WITH_INTERRUPT */ /* Loop until the transmission buffer is available. */ @@ -119,107 +115,97 @@ uart1_writeb(unsigned char c) /* Transmit the data. */ SC1_DATA = c; - + INT_SC1FLAG = INT_SCTXFREE; #endif /* TX_WITH_INTERRUPT */ } /*---------------------------------------------------------------------------*/ -#if ! WITH_UIP /* If WITH_UIP is defined, putchar() is defined by the SLIP driver */ +#if ! WITH_UIP +/* If WITH_UIP is defined, putchar() is defined by the SLIP driver */ #endif /* ! WITH_UIP */ /*---------------------------------------------------------------------------*/ -/** +/* * Initalize the RS232 port. - * */ void uart1_init(unsigned long ubr) { - - GPIO_PBCFGL &= 0xF00F; - GPIO_PBCFGL |= 0x0490; - - uint16_t uartper = (uint32_t)24e6/(2*ubr); - uint32_t rest = (uint32_t)24e6%(2*ubr); - - SC1_UARTFRAC = 0; - - if(rest > (2*ubr)/4 && rest < (3*2*ubr)/4){ - SC1_UARTFRAC = 1; // + 0.5 - } - else if(rest >= (3*2*ubr)/4){ - uartper++; // + 1 - } - - SC1_UARTPER = uartper; - - SC1_UARTCFG = SC_UART8BIT; - - SC1_MODE = SC1_MODE_UART; - - SC1_INTMODE = SC_RXVALLEVEL | SC_TXFREELEVEL; // Receive buffer has data interrupt mode and Transmit buffer free interrupt mode: Level triggered. - - INT_SC1CFG = INT_SCRXVAL; // Receive buffer has data interrupt enable + uint16_t uartper; + uint32_t rest; + + GPIO_PBCFGL &= 0xF00F; + GPIO_PBCFGL |= 0x0490; + + uartper = (uint32_t) 24e6 / (2 * ubr); + rest = (uint32_t) 24e6 % (2 * ubr); + + SC1_UARTFRAC = 0; + if(rest > (2 * ubr) / 4 && rest < (3 * 2 * ubr) / 4) { + SC1_UARTFRAC = 1; /* + 0.5 */ + } else if(rest >= (3 * 2 * ubr) / 4) { + uartper++; /* + 1 */ + } + + SC1_UARTPER = uartper; + SC1_UARTCFG = SC_UART8BIT; + SC1_MODE = SC1_MODE_UART; + /* + * Receive buffer has data interrupt mode and Transmit buffer free interrupt + * mode: Level triggered. + */ + SC1_INTMODE = SC_RXVALLEVEL | SC_TXFREELEVEL; + INT_SC1CFG = INT_SCRXVAL; /* Receive buffer has data interrupt enable */ transmitting = 0; - + #if TX_WITH_INTERRUPT - ringbuf_init(&txbuf, txbuf_data, sizeof(txbuf_data)); -#endif /* TX_WITH_INTERRUPT */ - - + ringbuf_init(&txbuf, txbuf_data, sizeof(txbuf_data)); +#endif /* TX_WITH_INTERRUPT */ + INT_SC1FLAG = 0xFFFF; - INT_CFGSET = INT_SC1; } /*---------------------------------------------------------------------------*/ -void uart1_rx_interrupt(void); -void uart1_tx_interrupt(void); - -void halSc1Isr(void) +void +halSc1Isr(void) { - ENERGEST_ON(ENERGEST_TYPE_IRQ); - - if(INT_SC1FLAG & INT_SCRXVAL){ + + if(INT_SC1FLAG & INT_SCRXVAL) { uart1_rx_interrupt(); - INT_SC1FLAG = INT_SCRXVAL; + INT_SC1FLAG = INT_SCRXVAL; } - #if TX_WITH_INTERRUPT - else if(INT_SC1FLAG & INT_SCTXFREE){ +#if TX_WITH_INTERRUPT + else if(INT_SC1FLAG & INT_SCTXFREE) { uart1_tx_interrupt(); INT_SC1FLAG = INT_SCTXFREE; - } - #endif /* TX_WITH_INTERRUPT */ - + } +#endif /* TX_WITH_INTERRUPT */ - ENERGEST_OFF(ENERGEST_TYPE_IRQ); - } - -void uart1_rx_interrupt(void) +/*--------------------------------------------------------------------------*/ +void +uart1_rx_interrupt(void) { - uint8_t c; - + uint8_t c; + c = SC1_DATA; - if(uart1_input_handler != NULL) { uart1_input_handler(c); - } - + } } /*---------------------------------------------------------------------------*/ #if TX_WITH_INTERRUPT -void uart1_tx_interrupt(void) +void +uart1_tx_interrupt(void) { - if(ringbuf_elements(&txbuf) == 0) { transmitting = 0; INT_SC1CFG &= ~INT_SCTXFREE; } else { SC1_DATA = ringbuf_get(&txbuf); } - } #endif /* TX_WITH_INTERRUPT */ -/*---------------------------------------------------------------------------*/ +/** @} */ diff --git a/cpu/stm32w108/dev/uart1.h b/cpu/stm32w108/dev/uart1.h index c43707653..bc684838e 100644 --- a/cpu/stm32w108/dev/uart1.h +++ b/cpu/stm32w108/dev/uart1.h @@ -1,3 +1,9 @@ +/** + * \addtogroup stm32w-cpu + * + * @{ + */ + /* * Copyright (c) 2007, Swedish Institute of Computer Science. * All rights reserved. @@ -26,8 +32,6 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * This file is part of the Contiki operating system. - * */ /** @@ -42,9 +46,13 @@ #define BAUD2UBR(baud) baud -void uart1_set_input(int (*input)(unsigned char c)); +void uart1_set_input(int (*input) (unsigned char c)); + void uart1_writeb(unsigned char c); + void uart1_init(unsigned long ubr); -//uint8_t uart1_active(void); + + /* uint8_t uart1_active(void); */ #endif /* __UART1_H__ */ +/** @} */ diff --git a/cpu/stm32w108/e_stdio/Makefile b/cpu/stm32w108/e_stdio/Makefile index 0440c67f0..849fe9d19 100644 --- a/cpu/stm32w108/e_stdio/Makefile +++ b/cpu/stm32w108/e_stdio/Makefile @@ -9,10 +9,10 @@ CFLAGS = -mthumb -mcpu=cortex-m3 -I "." -I "C:/Program\ Files/Raisonance/Ride/L AROPTS = cq SOURCE_DIR = src -SOURCE_FILES = small_mprec.c syscalls.c \ - _SP_printf.c _SP_vfprintf.c _SP_puts.c _SP_sprintf.c _SP_snprintf.c\ - small_dtoa.c small_wcsrtombs.c small_wcrtomb.c small_wctomb_r.c \ - scanf.c small_vfsscanf.c sscanf.c small_strtod.c +SOURCE_FILES = small-mprec.c syscalls.c \ + sp-printf.c sp-vfprintf.c sp-puts.c sp-sprintf.c sp-snprintf.c\ + small-dtoa.c small-wcsrtombs.c small-wcrtomb.c small-wctomb-r.c \ + scanf.c small-vfsscanf.c sscanf.c small-strtod.c vpath %.c $(SOURCE_DIR) diff --git a/cpu/stm32w108/e_stdio/src/small_dtoa.c b/cpu/stm32w108/e_stdio/src/small-dtoa.c similarity index 99% rename from cpu/stm32w108/e_stdio/src/small_dtoa.c rename to cpu/stm32w108/e_stdio/src/small-dtoa.c index b83e5d653..9c1fd71ed 100644 --- a/cpu/stm32w108/e_stdio/src/small_dtoa.c +++ b/cpu/stm32w108/e_stdio/src/small-dtoa.c @@ -56,7 +56,7 @@ #endif #include -#include "small_mprec.h" +#include "small-mprec.h" static int _DEFUN (quorem, @@ -203,8 +203,8 @@ _DEFUN (quorem, */ - /* Scanf and printf call both the small_mprec.c file if small_printf - * has not been specfied optimizations concerning small_mprec.c and + /* Scanf and printf call both the small-mprec.c file if small_printf + * has not been specfied optimizations concerning small-mprec.c and * call of balloc will be performed anyway for printf. */ @@ -292,8 +292,8 @@ _DEFUN (_dtoa_r, * provided by Balloc variables are initialized to the beginning of the array. * - For some variables many buffers have been declared, in fact for each call of small_lshift we used a * buffer that has not been used at the moment - * - This buffers are used in the call of function declared in small_mprec.h - * To have more informations look at small_mprec.c + * - This buffers are used in the call of function declared in small-mprec.h + * To have more informations look at small-mprec.c */ _Bigint tab_b[BUF_LSHIFT_SIZE],tab_b1[BUF_SIZE],tab_delta[BUF_SIZE],tab_mlo[BUF_SIZE],tab_mhi[BUF_LSHIFT_SIZE],tab_S[BUF_LSHIFT_SIZE]; diff --git a/cpu/stm32w108/e_stdio/src/small_mprec.c b/cpu/stm32w108/e_stdio/src/small-mprec.c similarity index 99% rename from cpu/stm32w108/e_stdio/src/small_mprec.c rename to cpu/stm32w108/e_stdio/src/small-mprec.c index f7df01d59..b9b6417b5 100644 --- a/cpu/stm32w108/e_stdio/src/small_mprec.c +++ b/cpu/stm32w108/e_stdio/src/small-mprec.c @@ -86,7 +86,7 @@ #include #include #include -#include "small_mprec.h" +#include "small-mprec.h" /* reent.c knows this value */ #define _Kmax 15 diff --git a/cpu/stm32w108/e_stdio/src/small_mprec.h b/cpu/stm32w108/e_stdio/src/small-mprec.h similarity index 100% rename from cpu/stm32w108/e_stdio/src/small_mprec.h rename to cpu/stm32w108/e_stdio/src/small-mprec.h diff --git a/cpu/stm32w108/e_stdio/src/small_strtod.c b/cpu/stm32w108/e_stdio/src/small-strtod.c similarity index 98% rename from cpu/stm32w108/e_stdio/src/small_strtod.c rename to cpu/stm32w108/e_stdio/src/small-strtod.c index f415da126..119af7cac 100644 --- a/cpu/stm32w108/e_stdio/src/small_strtod.c +++ b/cpu/stm32w108/e_stdio/src/small-strtod.c @@ -98,8 +98,8 @@ Supporting OS subroutines required: <>, <>, <>, */ -/* Scanf and printf call both the small_mprec.c file if small_scanf - * has not been specfied optimizations concerning small_mprec.c and +/* Scanf and printf call both the small-mprec.c file if small_scanf + * has not been specfied optimizations concerning small-mprec.c and * call of balloc will be performed anyway for scanf. */ @@ -113,7 +113,7 @@ Supporting OS subroutines required: <>, <>, <>, #include <_ansi.h> #include #include -#include "small_mprec.h" +#include "small-mprec.h" double _DEFUN (_strtod_r, (ptr, s00, se), @@ -141,8 +141,8 @@ _DEFUN (_strtod_r, (ptr, s00, se), * provided by Balloc variables are initialized to the beginning of the array. * - For some variables many buffers have been declared, in fact for each call of small_lshift we used a * buffer that has not been used at the moment - * - This buffers are used in the call of function declared in small_mprec.h - * To have more informations look at small_mprec.c + * - This buffers are used in the call of function declared in small-mprec.h + * To have more informations look at small-mprec.c */ diff --git a/cpu/stm32w108/e_stdio/src/small_vfsscanf.c b/cpu/stm32w108/e_stdio/src/small-vfsscanf.c similarity index 100% rename from cpu/stm32w108/e_stdio/src/small_vfsscanf.c rename to cpu/stm32w108/e_stdio/src/small-vfsscanf.c diff --git a/cpu/stm32w108/e_stdio/src/small_wcrtomb.c b/cpu/stm32w108/e_stdio/src/small-wcrtomb.c similarity index 100% rename from cpu/stm32w108/e_stdio/src/small_wcrtomb.c rename to cpu/stm32w108/e_stdio/src/small-wcrtomb.c diff --git a/cpu/stm32w108/e_stdio/src/small_wcsrtombs.c b/cpu/stm32w108/e_stdio/src/small-wcsrtombs.c similarity index 100% rename from cpu/stm32w108/e_stdio/src/small_wcsrtombs.c rename to cpu/stm32w108/e_stdio/src/small-wcsrtombs.c diff --git a/cpu/stm32w108/e_stdio/src/small_wctomb_r.c b/cpu/stm32w108/e_stdio/src/small-wctomb-r.c similarity index 100% rename from cpu/stm32w108/e_stdio/src/small_wctomb_r.c rename to cpu/stm32w108/e_stdio/src/small-wctomb-r.c diff --git a/cpu/stm32w108/e_stdio/src/_SP_printf.c b/cpu/stm32w108/e_stdio/src/sp-printf.c similarity index 100% rename from cpu/stm32w108/e_stdio/src/_SP_printf.c rename to cpu/stm32w108/e_stdio/src/sp-printf.c diff --git a/cpu/stm32w108/e_stdio/src/_SP_puts.c b/cpu/stm32w108/e_stdio/src/sp-puts.c similarity index 100% rename from cpu/stm32w108/e_stdio/src/_SP_puts.c rename to cpu/stm32w108/e_stdio/src/sp-puts.c diff --git a/cpu/stm32w108/e_stdio/src/_SP_snprintf.c b/cpu/stm32w108/e_stdio/src/sp-snprintf.c similarity index 96% rename from cpu/stm32w108/e_stdio/src/_SP_snprintf.c rename to cpu/stm32w108/e_stdio/src/sp-snprintf.c index 2dfcd8599..a36c14c0b 100644 --- a/cpu/stm32w108/e_stdio/src/_SP_snprintf.c +++ b/cpu/stm32w108/e_stdio/src/sp-snprintf.c @@ -14,8 +14,8 @@ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. */ -/* doc in _SP_sprintf.c */ -/* This code created by modifying _SP_sprintf.c so copyright inherited. */ +/* doc in sp-sprintf.c */ +/* This code created by modifying sp-sprintf.c so copyright inherited. */ #include #ifdef _HAVE_STDC diff --git a/cpu/stm32w108/e_stdio/src/_SP_sprintf.c b/cpu/stm32w108/e_stdio/src/sp-sprintf.c similarity index 100% rename from cpu/stm32w108/e_stdio/src/_SP_sprintf.c rename to cpu/stm32w108/e_stdio/src/sp-sprintf.c diff --git a/cpu/stm32w108/e_stdio/src/_SP_vfprintf.c b/cpu/stm32w108/e_stdio/src/sp-vfprintf.c similarity index 100% rename from cpu/stm32w108/e_stdio/src/_SP_vfprintf.c rename to cpu/stm32w108/e_stdio/src/sp-vfprintf.c diff --git a/cpu/stm32w108/e_stdio/src/test_mes.c b/cpu/stm32w108/e_stdio/src/test-mes.c similarity index 100% rename from cpu/stm32w108/e_stdio/src/test_mes.c rename to cpu/stm32w108/e_stdio/src/test-mes.c diff --git a/cpu/stm32w108/e_stdio/src/test_printf.c b/cpu/stm32w108/e_stdio/src/test-printf.c similarity index 100% rename from cpu/stm32w108/e_stdio/src/test_printf.c rename to cpu/stm32w108/e_stdio/src/test-printf.c diff --git a/cpu/stm32w108/e_stdio/src/test_scanf.c b/cpu/stm32w108/e_stdio/src/test-scanf.c similarity index 100% rename from cpu/stm32w108/e_stdio/src/test_scanf.c rename to cpu/stm32w108/e_stdio/src/test-scanf.c diff --git a/cpu/stm32w108/elfloader-arch.c b/cpu/stm32w108/elfloader-arch.c index 1b794b421..6a04d45f0 100644 --- a/cpu/stm32w108/elfloader-arch.c +++ b/cpu/stm32w108/elfloader-arch.c @@ -1,3 +1,39 @@ +/** + * \addtogroup mb851-platform + * + * @{ + */ + +/* + * Copyright (c) 2009, Swedish Institute of Computer Science + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Institute nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ + #include "contiki.h" #include "elfloader-arch.h" #include "cfs-coffee-arch.h" @@ -12,20 +48,22 @@ #define ELF32_R_TYPE(info) ((unsigned char)(info)) /* Supported relocations */ - #define R_ARM_ABS32 2 #define R_ARM_THM_CALL 10 /* Adapted from elfloader-arm.c */ +/* word aligned */ +static uint32_t datamemory_aligned[(ELFLOADER_DATAMEMORY_SIZE + 3) / 4]; +static uint8_t *datamemory = (uint8_t *) datamemory_aligned; -static uint32_t datamemory_aligned[(ELFLOADER_DATAMEMORY_SIZE+3)/4]; //word aligned -static uint8_t* datamemory = (uint8_t *)datamemory_aligned; -VAR_AT_SEGMENT (static const uint16_t textmemory[ELFLOADER_TEXTMEMORY_SIZE/2],".elf_text") = {0}; //halfword aligned +/* halfword aligned */ +VAR_AT_SEGMENT(static const uint16_t + textmemory[ELFLOADER_TEXTMEMORY_SIZE / 2], ".elf_text") = {0}; /*---------------------------------------------------------------------------*/ void * elfloader_arch_allocate_ram(int size) { - if(size > sizeof(datamemory_aligned)){ + if(size > sizeof(datamemory_aligned)) { PRINTF("RESERVED RAM TOO SMALL\n"); } return datamemory; @@ -34,7 +72,7 @@ elfloader_arch_allocate_ram(int size) void * elfloader_arch_allocate_rom(int size) { - if(size > sizeof(textmemory)){ + if(size > sizeof(textmemory)) { PRINTF("RESERVED FLASH TOO SMALL\n"); } return (void *)textmemory; @@ -42,50 +80,43 @@ elfloader_arch_allocate_rom(int size) /*---------------------------------------------------------------------------*/ #define READSIZE sizeof(datamemory_aligned) -void elfloader_arch_write_rom(int fd, unsigned short textoff, unsigned int size, char *mem) +void +elfloader_arch_write_rom(int fd, unsigned short textoff, unsigned int size, + char *mem) { - int32u ptr; - int nbytes; - + uint32_t ptr; + int nbytes; cfs_seek(fd, textoff, CFS_SEEK_SET); - cfs_seek(fd, textoff, CFS_SEEK_SET); for(ptr = 0; ptr < size; ptr += READSIZE) { - /* Read data from file into RAM. */ nbytes = cfs_read(fd, (unsigned char *)datamemory, READSIZE); - /* Write data to flash. */ - stm32w_flash_write((int32u)mem, datamemory, nbytes); + stm32w_flash_write((uint32_t) mem, datamemory, nbytes); } } /*---------------------------------------------------------------------------*/ - - -void elfloader_arch_relocate(int fd, - unsigned int sectionoffset, - char *sectionaddr, +void +elfloader_arch_relocate(int fd, + unsigned int sectionoffset, + char *sectionaddr, struct elf32_rela *rela, char *addr) { unsigned int type; - type = ELF32_R_TYPE(rela->r_info); - cfs_seek(fd, sectionoffset + rela->r_offset, CFS_SEEK_SET); - /* PRINTF("elfloader_arch_relocate: type %d\n", type); */ /* PRINTF("Addr: %p, Addend: %ld\n", addr, rela->r_addend); */ - switch(type) { + switch (type) { case R_ARM_ABS32: { int32_t addend; - cfs_read(fd, (char*)&addend, 4); + cfs_read(fd, (char *)&addend, 4); addr += addend; cfs_seek(fd, -4, CFS_SEEK_CUR); - cfs_write(fd,&addr,4); - //elfloader_output_write_segment(output,(char*) &addr, 4); - PRINTF("%p: addr: %p\n", sectionaddr +rela->r_offset, - addr); + cfs_write(fd, &addr, 4); + /* elfloader_output_write_segment(output,(char*) &addr, 4); */ + PRINTF("%p: addr: %p\n", sectionaddr + rela->r_offset, addr); } break; case R_ARM_THM_CALL: @@ -93,49 +124,53 @@ void elfloader_arch_relocate(int fd, uint16_t instr[2]; int32_t offset; char *base; - cfs_read(fd, (char*)instr, 4); + cfs_read(fd, (char *)instr, 4); cfs_seek(fd, -4, CFS_SEEK_CUR); - /* Ignore the addend since it will be zero for calls to symbols, - and I can't think of a case when doing a relative call to - a non-symbol position */ - base = sectionaddr + (rela->r_offset + 4); - if (((instr[1]) & 0xe800) == 0xe800) { - /* BL or BLX */ - if (((uint32_t)addr) & 0x1) { - /* BL */ - instr[1] |= 0x1800; - } else { + /* + * Ignore the addend since it will be zero for calls to symbols, + * and I can't think of a case when doing a relative call to + * a non-symbol position + */ + base = sectionaddr + (rela->r_offset + 4); + if(((instr[1]) & 0xe800) == 0xe800) { + /* BL or BLX */ + if(((uint32_t) addr) & 0x1) { + /* BL */ + instr[1] |= 0x1800; + } else { #if defined(__ARM_ARCH_4T__) - return ELFLOADER_UNHANDLED_RELOC; + return ELFLOADER_UNHANDLED_RELOC; #else - /* BLX */ - instr[1] &= ~0x1800; - instr[1] |= 0x0800; + /* BLX */ + instr[1] &= ~0x1800; + instr[1] |= 0x0800; #endif - } + } } + /* Adjust address for BLX */ - if ((instr[1] & 0x1800) == 0x0800) { - addr = (char*)((((uint32_t)addr) & 0xfffffffd) - | (((uint32_t)base) & 0x00000002)); + if((instr[1] & 0x1800) == 0x0800) { + addr = (char *)((((uint32_t) addr) & 0xfffffffd) | + (((uint32_t) base) & 0x00000002)); } - offset = addr - (sectionaddr + (rela->r_offset + 4)); + offset = addr - (sectionaddr + (rela->r_offset + 4)); PRINTF("elfloader-arm.c: offset %d\n", (int)offset); - if (offset < -(1<<22) || offset >= (1<<22)) { - PRINTF("elfloader-arm.c: offset %d too large for relative call\n", - (int)offset); + if(offset < -(1 << 22) || offset >= (1 << 22)) { + PRINTF("elfloader-arm.c: offset %d too large for relative call\n", + (int)offset); } - /* PRINTF("%p: %04x %04x offset: %d addr: %p\n", sectionaddr +rela->r_offset, instr[0], instr[1], (int)offset, addr); */ - instr[0] = (instr[0] & 0xf800) | ((offset>>12)&0x07ff); - instr[1] = (instr[1] & 0xf800) | ((offset>>1)&0x07ff); - cfs_write(fd,&instr,4); - //elfloader_output_write_segment(output, (char*)instr, 4); - /* PRINTF("cfs_write: %04x %04x\n",instr[0], instr[1]); */ + /* PRINTF("%p: %04x %04x offset: %d addr: %p\n", sectionaddr +rela->r_offset, instr[0], instr[1], (int)offset, addr); */ + instr[0] = (instr[0] & 0xf800) | ((offset >> 12) & 0x07ff); + instr[1] = (instr[1] & 0xf800) | ((offset >> 1) & 0x07ff); + cfs_write(fd, &instr, 4); + /* elfloader_output_write_segment(output, (char*)instr, 4); */ + /* PRINTF("cfs_write: %04x %04x\n",instr[0], instr[1]); */ } break; - + default: PRINTF("elfloader-arm.c: unsupported relocation type %d\n", type); } } +/** @} */ diff --git a/cpu/stm32w108/hal/error.h b/cpu/stm32w108/hal/error.h index 768cf486c..68ce42eb6 100644 --- a/cpu/stm32w108/hal/error.h +++ b/cpu/stm32w108/hal/error.h @@ -15,7 +15,7 @@ */ #ifndef __STSTATUS_TYPE__ #define __STSTATUS_TYPE__ - typedef int8u StStatus; + typedef uint8_t StStatus; #endif //__STSTATUS_TYPE__ /** diff --git a/cpu/stm32w108/hal/micro/adc.h b/cpu/stm32w108/hal/micro/adc.h index 8bd755c04..c60067cd3 100644 --- a/cpu/stm32w108/hal/micro/adc.h +++ b/cpu/stm32w108/hal/micro/adc.h @@ -37,7 +37,7 @@ #ifdef CORTEXM3_STM32W108 // A type for the ADC User enumeration. -typedef int8u ADCUser; +typedef uint8_t ADCUser; enum { /** LQI User ID. */ @@ -55,7 +55,7 @@ enum // A type for the reference enumeration. -typedef int8u ADCReferenceType; +typedef uint8_t ADCReferenceType; enum { /** AREF pin reference. */ @@ -67,7 +67,7 @@ enum }; // A type for the rate enumeration. -typedef int8u ADCRateType; +typedef uint8_t ADCRateType; enum { /** Rate 32 us, 5 effective bits in ADC_DATA[15:11] */ @@ -173,7 +173,7 @@ enum /** @brief A type for the channel enumeration * (such as ::ADC_SOURCE_ADC0_GND) */ -typedef int8u ADCChannelType; +typedef uint8_t ADCChannelType; /** @brief Returns the ADC channel from a given GPIO. Its value can can be used * inside the ADC_SOURCE(P,N) macro to retrieve the input pair for @@ -184,7 +184,7 @@ typedef int8u ADCChannelType; * * @return The ADC_MUX value connected to the given GPIO. */ -int8u halGetADCChannelFromGPIO(int32u io); +uint8_t halGetADCChannelFromGPIO(uint32_t io); /** @brief Initializes and powers-up the ADC. @@ -226,7 +226,7 @@ StStatus halStartAdcConversion(ADCUser id, * * @param id An ADC user. * - * @param value Pointer to an int16u to be loaded with the new value. + * @param value Pointer to an uint16_t to be loaded with the new value. * * @return One of the following: * - ::ST_ADC_CONVERSION_DONE if the conversion is complete. @@ -237,7 +237,7 @@ StStatus halStartAdcConversion(ADCUser id, * - ::ST_ADC_NO_CONVERSION_PENDING if \c id does not have a pending * conversion. */ -StStatus halRequestAdcData(ADCUser id, int16u *value); +StStatus halRequestAdcData(ADCUser id, uint16_t *value); /** @brief Waits for the user's request to complete and then, @@ -248,14 +248,14 @@ StStatus halRequestAdcData(ADCUser id, int16u *value); * * @param id An ADC user. * - * @param value Pointer to an int16u to be loaded with the new value. + * @param value Pointer to an uint16_t to be loaded with the new value. * * @return One of the following: * - ::ST_ADC_CONVERSION_DONE if the conversion is complete. * - ::ST_ADC_NO_CONVERSION_PENDING if \c id does not have a pending * conversion. */ -StStatus halReadAdcBlocking(ADCUser id, int16u *value); +StStatus halReadAdcBlocking(ADCUser id, uint16_t *value); /** @brief Calibrates or recalibrates the ADC system. @@ -284,11 +284,11 @@ StStatus halAdcCalibrate(ADCUser id); * * @appusage Use this function to get a human useful value. * - * @param value An int16u to be converted. + * @param value An uint16_t to be converted. * * @return Volts as signed fixed point with units 10^-4 Volts. */ -int16s halConvertValueToVolts(int16u value); +int16_t halConvertValueToVolts(uint16_t value); /** @brief Calibrates Vref to be 1.2V +/-10mV. diff --git a/cpu/stm32w108/hal/micro/button.h b/cpu/stm32w108/hal/micro/button.h index 409b69887..9dcbf0027 100644 --- a/cpu/stm32w108/hal/micro/button.h +++ b/cpu/stm32w108/hal/micro/button.h @@ -13,7 +13,7 @@ #define BUTTON_UNKNOWN 3 -typedef int8u HalBoardButton; +typedef uint8_t HalBoardButton; /* Functions -----------------------------------------------------------------*/ @@ -21,7 +21,7 @@ typedef int8u HalBoardButton; void halInitButton(void); /** @brief Get button status */ -int8u halGetButtonStatus(HalBoardButton button); +uint8_t halGetButtonStatus(HalBoardButton button); #endif /* _BUTTON_H_ */ diff --git a/cpu/stm32w108/hal/micro/cortexm3/adc.c b/cpu/stm32w108/hal/micro/cortexm3/adc.c index e1904ede5..67a8a8feb 100644 --- a/cpu/stm32w108/hal/micro/cortexm3/adc.c +++ b/cpu/stm32w108/hal/micro/cortexm3/adc.c @@ -10,18 +10,18 @@ #if (NUM_ADC_USERS > 8) - #error NUM_ADC_USERS must not be greater than 8, or int8u variables in adc.c must be changed + #error NUM_ADC_USERS must not be greater than 8, or uint8_t variables in adc.c must be changed #endif -static int16u adcData; // conversion result written by DMA -static int8u adcPendingRequests; // bitmap of pending requests -volatile static int8u adcPendingConversion; // id of pending conversion -static int8u adcReadingValid; // bitmap of valid adcReadings -static int16u adcReadings[NUM_ADC_USERS]; -static int16u adcConfig[NUM_ADC_USERS]; +static uint16_t adcData; // conversion result written by DMA +static uint8_t adcPendingRequests; // bitmap of pending requests +volatile static uint8_t adcPendingConversion; // id of pending conversion +static uint8_t adcReadingValid; // bitmap of valid adcReadings +static uint16_t adcReadings[NUM_ADC_USERS]; +static uint16_t adcConfig[NUM_ADC_USERS]; static boolean adcCalibrated; -static int16s Nvss; -static int16s Nvdd; +static int16_t Nvss; +static int16_t Nvdd; /* Modified the original ADC driver for enabling the ADC extended range mode required for supporting the STLM20 temperature sensor. NOTE: @@ -30,10 +30,10 @@ static int16s Nvdd; the temperature values */ #ifdef ENABLE_ADC_EXTENDED_RANGE_BROKEN -static int16s Nvref; -static int16s Nvref2; +static int16_t Nvref; +static int16_t Nvref2; #endif /* ENABLE_ADC_EXTENDED_RANGE_BROKEN */ -static int16u adcStaticConfig; +static uint16_t adcStaticConfig; void halAdcSetClock(boolean slow) { @@ -73,8 +73,8 @@ boolean halAdcGetRange(void) void halAdcIsr(void) { - int8u i; - int8u conversion = adcPendingConversion; //fix 'volatile' warning; costs no flash + uint8_t i; + uint8_t conversion = adcPendingConversion; //fix 'volatile' warning; costs no flash // make sure data is ready and the desired conversion is valid if ( (INT_ADCFLAG & INT_ADCULDFULL) @@ -105,7 +105,7 @@ void halAdcIsr(void) // otherwise. ADCUser startNextConversion() { - int8u i; + uint8_t i; ATOMIC ( // start the next requested conversion if any @@ -143,7 +143,7 @@ void halInternalInitAdc(void) ADC_OFFSET = ADC_OFFSET_RESET; ADC_GAIN = ADC_GAIN_RESET; ADC_DMACFG = ADC_DMARST; - ADC_DMABEG = (int32u)&adcData; + ADC_DMABEG = (uint32_t)&adcData; ADC_DMASIZE = 1; ADC_DMACFG = (ADC_DMAAUTOWRAP | ADC_DMALOAD); @@ -186,7 +186,7 @@ StStatus halStartAdcConversion(ADCUser id, return ST_ADC_CONVERSION_DEFERRED; } -StStatus halRequestAdcData(ADCUser id, int16u *value) +StStatus halRequestAdcData(ADCUser id, uint16_t *value) { //Both the ADC interrupt and the global interrupt need to be enabled, //otherwise the ADC ISR cannot be serviced. @@ -220,7 +220,7 @@ StStatus halRequestAdcData(ADCUser id, int16u *value) return stat; } -StStatus halReadAdcBlocking(ADCUser id, int16u *value) +StStatus halReadAdcBlocking(ADCUser id, uint16_t *value) { StStatus stat; @@ -250,13 +250,13 @@ StStatus halAdcCalibrate(ADCUser id) ADC_SOURCE_VREF_VREF2, ADC_CONVERSION_TIME_US_4096); - stat = halReadAdcBlocking(id, (int16u *)(&Nvref)); + stat = halReadAdcBlocking(id, (uint16_t *)(&Nvref)); if (stat == ST_ADC_CONVERSION_DONE) { halStartAdcConversion(id, ADC_REF_INT, ADC_SOURCE_VREF2_VREF2, ADC_CONVERSION_TIME_US_4096); - stat = halReadAdcBlocking(id, (int16u *)(&Nvref2)); + stat = halReadAdcBlocking(id, (uint16_t *)(&Nvref2)); } if (stat == ST_ADC_CONVERSION_DONE) { adcCalibrated = TRUE; @@ -272,13 +272,13 @@ StStatus halAdcCalibrate(ADCUser id) ADC_REF_INT, ADC_SOURCE_GND_VREF2, ADC_CONVERSION_TIME_US_4096); - stat = halReadAdcBlocking(id, (int16u *)(&Nvss)); + stat = halReadAdcBlocking(id, (uint16_t *)(&Nvss)); if (stat == ST_ADC_CONVERSION_DONE) { halStartAdcConversion(id, ADC_REF_INT, ADC_SOURCE_VREG2_VREF2, ADC_CONVERSION_TIME_US_4096); - stat = halReadAdcBlocking(id, (int16u *)(&Nvdd)); + stat = halReadAdcBlocking(id, (uint16_t *)(&Nvdd)); } if (stat == ST_ADC_CONVERSION_DONE) { Nvdd -= Nvss; @@ -297,11 +297,11 @@ StStatus halAdcCalibrate(ADCUser id) // FIXME: support high voltage range // use Vref-Vref/2 to calibrate // FIXME: check for mfg token specifying measured VDD_PADSA -int16s halConvertValueToVolts(int16u value) +int16_t halConvertValueToVolts(uint16_t value) { - int32s N; - int16s V; - int32s nvalue; + int32_t N; + int16_t V; + int32_t nvalue; if (!adcCalibrated) { halAdcCalibrate(ADC_USER_LQI); @@ -317,10 +317,10 @@ int16s halConvertValueToVolts(int16u value) #ifdef ENABLE_ADC_EXTENDED_RANGE_BROKEN if(halAdcGetRange()){ // High range. - N = (((int32s)value + Nvref - 2*Nvref2) << 16)/(2*(Nvref-Nvref2)); + N = (((int32_t)value + Nvref - 2*Nvref2) << 16)/(2*(Nvref-Nvref2)); // Calculate voltage with: V = (N * VREF) / (2^16) where VDD = 1.2 volts // Mutiplying by 1.2*10000 makes the result of this equation 100 uVolts - V = (int16s)((N*12000L) >> 16); + V = (int16_t)((N*12000L) >> 16); if (V > 21000) { // VDD_PADS ? V = 21000; } @@ -336,7 +336,7 @@ int16s halConvertValueToVolts(int16u value) // Mutiplying by0.9*10000 makes the result of this equation 100 uVolts // (in fixed point E-4 which allows for 13.5 bits vs millivolts // which is only 10.2 bits). - V = (int16s)((N*9000L) >> 16); + V = (int16_t)((N*9000L) >> 16); if (V > 12000) { V = 12000; } @@ -349,7 +349,7 @@ int16s halConvertValueToVolts(int16u value) return V; } -int8u halGetADCChannelFromGPIO(int32u io) +uint8_t halGetADCChannelFromGPIO(uint32_t io) { switch(io) { diff --git a/cpu/stm32w108/hal/micro/cortexm3/board.c b/cpu/stm32w108/hal/micro/cortexm3/board.c index 456be9b40..62ef23c52 100644 --- a/cpu/stm32w108/hal/micro/cortexm3/board.c +++ b/cpu/stm32w108/hal/micro/cortexm3/board.c @@ -250,7 +250,7 @@ BoardResourcesType const *boardDescription = NULL; void halBoardInit(void) { char boardName[16]; - int8s i; + int8_t i; boardDescription = NULL; #ifdef EMBERZNET_HAL halCommonGetToken(boardName, TOKEN_MFG_BOARD_NAME); @@ -318,7 +318,7 @@ void halBoardPowerDown(void) /* Configure GPIO for BUTTONSs */ { ButtonResourceType *buttons = (ButtonResourceType *) boardDescription->io->buttons; - int8u i; + uint8_t i; for (i = 0; i < boardDescription->buttons; i++) { halGpioConfig(PORTx_PIN(buttons[i].gpioPort, buttons[i].gpioPin), GPIOCFG_IN_PUD); halGpioSet(PORTx_PIN(buttons[i].gpioPort, buttons[i].gpioPin), GPIOOUT_PULLUP); @@ -328,7 +328,7 @@ void halBoardPowerDown(void) /* Configure GPIO for LEDs */ { LedResourceType *leds = (LedResourceType *) boardDescription->io->leds; - int8u i; + uint8_t i; for (i = 0; i < boardDescription->leds; i++) { /* LED default off */ halGpioConfig(PORTx_PIN(leds[i].gpioPort, leds[i].gpioPin), GPIOCFG_OUT); @@ -394,7 +394,7 @@ void halBoardPowerUp(void) /* Configure GPIO for LEDs */ { LedResourceType *leds = (LedResourceType *) boardDescription->io->leds; - int8u i; + uint8_t i; for (i = 0; i < boardDescription->leds; i++) { /* LED default off */ halGpioConfig(PORTx_PIN(leds[i].gpioPort, leds[i].gpioPin), GPIOCFG_OUT); @@ -404,7 +404,7 @@ void halBoardPowerUp(void) /* Configure GPIO for BUTTONSs */ { ButtonResourceType *buttons = (ButtonResourceType *) boardDescription->io->buttons; - int8u i; + uint8_t i; for (i = 0; i < boardDescription->buttons; i++) { halGpioConfig(PORTx_PIN(buttons[i].gpioPort, buttons[i].gpioPin), GPIOCFG_IN_PUD); halGpioSet(PORTx_PIN(buttons[i].gpioPort, buttons[i].gpioPin), GPIOOUT_PULLUP); @@ -448,7 +448,7 @@ void printButtons (ButtonResourceType *buttons) void boardPrintStringDescription(void) { - int8u i = 0; + uint8_t i = 0; while (boardList[i] != NULL) { if ((boardDescription == boardList[i]) || (boardDescription == NULL)) { diff --git a/cpu/stm32w108/hal/micro/cortexm3/bootloader/fib-bootloader.h b/cpu/stm32w108/hal/micro/cortexm3/bootloader/fib-bootloader.h index fe7775935..b0b631fe0 100644 --- a/cpu/stm32w108/hal/micro/cortexm3/bootloader/fib-bootloader.h +++ b/cpu/stm32w108/hal/micro/cortexm3/bootloader/fib-bootloader.h @@ -22,7 +22,7 @@ //------------------------------------------------------------------------------ // Status values. -typedef int32u FibStatus; +typedef uint32_t FibStatus; #define FIB_SUCCESS 0 #define FIB_ERR_UNALIGNED 1 @@ -36,7 +36,7 @@ typedef int32u FibStatus; //------------------------------------------------------------------------------ // Erase types. -typedef int32u FibEraseType; +typedef uint32_t FibEraseType; #define MFB_MASS_ERASE 0x01 #define MFB_PAGE_ERASE 0x02 @@ -48,9 +48,9 @@ typedef int32u FibEraseType; //------------------------------------------------------------------------------ // Shared flash functions. -FibStatus fibFlashWrite(int32u address, int8u *data, - int32u writeLength, int32u verifyLength); +FibStatus fibFlashWrite(uint32_t address, uint8_t *data, + uint32_t writeLength, uint32_t verifyLength); -FibStatus fibFlashErase(FibEraseType eraseType, int32u address); +FibStatus fibFlashErase(FibEraseType eraseType, uint32_t address); #endif //__FIB_BOOTLOADER_H__ diff --git a/cpu/stm32w108/hal/micro/cortexm3/button.c b/cpu/stm32w108/hal/micro/cortexm3/button.c index 0cbae3aab..6aee5d4ae 100644 --- a/cpu/stm32w108/hal/micro/cortexm3/button.c +++ b/cpu/stm32w108/hal/micro/cortexm3/button.c @@ -12,7 +12,7 @@ void halInitButton(void) { - int8u i; + uint8_t i; /* Configure GPIO for BUTTONSs */ ButtonResourceType *buttons = (ButtonResourceType *) boardDescription->io->buttons; for (i = 0; i < boardDescription->buttons; i++) { @@ -22,10 +22,10 @@ void halInitButton(void) }/* end halInitButton() */ -int8u halGetButtonStatus(HalBoardButton button) +uint8_t halGetButtonStatus(HalBoardButton button) { - int8u port = (button >> 3) & 0xf; - int8u pin = button & 0x7; + uint8_t port = (button >> 3) & 0xf; + uint8_t pin = button & 0x7; if (button != DUMMY_BUTTON) { diff --git a/cpu/stm32w108/hal/micro/cortexm3/clocks.c b/cpu/stm32w108/hal/micro/cortexm3/clocks.c index 3b42719ca..d092207c6 100644 --- a/cpu/stm32w108/hal/micro/cortexm3/clocks.c +++ b/cpu/stm32w108/hal/micro/cortexm3/clocks.c @@ -59,10 +59,10 @@ #define CLK1K_NUMERATOR 384000000 void halInternalCalibrateSlowRc( void ) { - int8u i; - int32u average=0; - int16s delta; - int32u period; + uint8_t i; + uint32_t average=0; + int16_t delta; + uint32_t period; CALDBG( stSerialPrintf(ST_ASSERT_SERIAL_PORT, "halInternalCalibrateSlowRc:\r\n"); @@ -85,7 +85,7 @@ void halInternalCalibrateSlowRc( void ) stSerialPrintf(ST_ASSERT_SERIAL_PORT, "period: %u, ", CLK_PERIOD); stSerialPrintf(ST_ASSERT_SERIAL_PORT, "%u Hz\r\n", - ((int16u)(((int32u)192000000)/((int32u)CLK_PERIOD)))); + ((uint16_t)(((uint32_t)192000000)/((uint32_t)CLK_PERIOD)))); ) //For 10kHz, the ideal CLK_PERIOD is 19200. Calculate the PERIOD delta. //It's possible for a chip's 10kHz source RC to be too far out of range @@ -120,7 +120,7 @@ void halInternalCalibrateSlowRc( void ) stSerialPrintf(ST_ASSERT_SERIAL_PORT, "period: %u, ", CLK_PERIOD); stSerialPrintf(ST_ASSERT_SERIAL_PORT, "%u Hz\r\n", - ((int16u)(((int32u)192000000)/((int32u)CLK_PERIOD)))); + ((uint16_t)(((uint32_t)192000000)/((uint32_t)CLK_PERIOD)))); ) //The analog section should now be producing an output of ~10kHz @@ -138,11 +138,11 @@ void halInternalCalibrateSlowRc( void ) average = (average+(SLOWRC_PERIOD_SAMPLES/2))/SLOWRC_PERIOD_SAMPLES; CALDBG( stSerialPrintf(ST_ASSERT_SERIAL_PORT, "average: %u, %u Hz\r\n", - ((int16u)average), ((int16u)(((int32u)192000000)/((int32u)average)))); + ((uint16_t)average), ((uint16_t)(((uint32_t)192000000)/((uint32_t)average)))); ) //using an average period sample, calculate the clk1k divisor - CLK1K_CAL = (int16u)(CLK1K_NUMERATOR/average); + CLK1K_CAL = (uint16_t)(CLK1K_NUMERATOR/average); CALDBG( stSerialPrintf(ST_ASSERT_SERIAL_PORT,"CLK1K_CAL=%2X\r\n",CLK1K_CAL); ) @@ -167,7 +167,7 @@ void halInternalCalibrateSlowRc( void ) // CLK_PERIOD void halInternalCalibrateFastRc(void) { - int32s newTune = -16; + int32_t newTune = -16; CALDBG( stSerialPrintf(ST_ASSERT_SERIAL_PORT, "halInternalCalibrateFastRc:\r\n"); @@ -188,7 +188,7 @@ void halInternalCalibrateFastRc(void) stSerialPrintf(ST_ASSERT_SERIAL_PORT, "period: %u, ", CLK_PERIOD); stSerialPrintf(ST_ASSERT_SERIAL_PORT, "%u kHz\r\n", - ((int16u)((((int32u)3072000000)/((int32u)CLK_PERIOD))/1000))); + ((uint16_t)((((uint32_t)3072000000)/((uint32_t)CLK_PERIOD))/1000))); ) //For 12MHz, the ideal CLK_PERIOD is 256. Tune the frequency down until //the period is <= 256, which says the frequency is as close to 12MHz as @@ -211,7 +211,7 @@ void halInternalCalibrateFastRc(void) stSerialPrintf(ST_ASSERT_SERIAL_PORT, "period: %u, ", CLK_PERIOD); stSerialPrintf(ST_ASSERT_SERIAL_PORT, "%u kHz\r\n", - ((int16u)((((int32u)3072000000)/((int32u)CLK_PERIOD))/1000))); + ((uint16_t)((((uint32_t)3072000000)/((uint32_t)CLK_PERIOD))/1000))); ) //The analog section should now be producing an output of 11.5MHz - 12.0MHz @@ -337,7 +337,7 @@ static boolean setBiasCheckLow(void) void halInternalSearchForBiasTrim(void) { - int8u bit; + uint8_t bit; //Enable the XTAL so we can search for the proper bias trim (NOTE: This //will also forcefully ensure we're on the OSCHF so that we don't diff --git a/cpu/stm32w108/hal/micro/cortexm3/compiler/gnu.h b/cpu/stm32w108/hal/micro/cortexm3/compiler/gnu.h index 2ed3edbf2..158ccb4ba 100644 --- a/cpu/stm32w108/hal/micro/cortexm3/compiler/gnu.h +++ b/cpu/stm32w108/hal/micro/cortexm3/compiler/gnu.h @@ -18,6 +18,9 @@ #ifndef __GNU_H__ #define __GNU_H__ +#include + + #ifndef __GNUC__ #error Improper PLATFORM_HEADER #endif @@ -40,7 +43,7 @@ #include #if defined (CORTEXM3_STM32W108) #include "micro/cortexm3/stm32w108/regs.h" - #include "micro/cortexm3/stm32w108/stm32w108_type.h" + #include "micro/cortexm3/stm32w108/stm32w108-type.h" #else #error Unknown CORTEXM3 micro #endif @@ -90,12 +93,12 @@ * @brief A typedef to make the size of the variable explicitly known. */ typedef unsigned char boolean; -typedef unsigned char int8u; -typedef signed char int8s; -typedef unsigned short int16u; -typedef signed short int16s; -typedef unsigned int int32u; -typedef signed int int32s; +//typedef unsigned char uint8_t; +//typedef signed char int8_t; +//typedef unsigned short uint16_t; +//typedef signed short int16_t; +//typedef unsigned int uint32_t; +//typedef signed int int32_t; typedef unsigned int PointerType; //@} \\END MASTER VARIABLE TYPES @@ -363,7 +366,7 @@ void _executeBarrierInstructions(void); * declarations section of any function which calls DISABLE_INTERRUPTS() * or RESTORE_INTERRUPTS(). */ - #define DECLARE_INTERRUPT_STATE int8u _emIsrState + #define DECLARE_INTERRUPT_STATE uint8_t _emIsrState // Prototypes for the BASEPRI and PRIMASK access functions. They are very // basic and instantiated in assembly code in the file spmr.s37 (since @@ -372,13 +375,13 @@ void _executeBarrierInstructions(void); // with a priority equal to or less than the BASEPRI value. // Note that the priority values used by these functions are 5 bits and // right-aligned - extern int8u _readBasePri(void); - extern void _writeBasePri(int8u priority); + extern uint8_t _readBasePri(void); + extern void _writeBasePri(uint8_t priority); // Prototypes for BASEPRI functions used to disable and enable interrupts // while still allowing enabled faults to trigger. extern void _enableBasePri(void); - extern int8u _disableBasePri(void); + extern uint8_t _disableBasePri(void); extern boolean _basePriIsDisabled(void); // Prototypes for setting and clearing PRIMASK for global interrupt diff --git a/cpu/stm32w108/hal/micro/cortexm3/compiler/iar.h b/cpu/stm32w108/hal/micro/cortexm3/compiler/iar.h index 69e4a05b5..68f0353d4 100644 --- a/cpu/stm32w108/hal/micro/cortexm3/compiler/iar.h +++ b/cpu/stm32w108/hal/micro/cortexm3/compiler/iar.h @@ -33,7 +33,7 @@ #include #if defined (CORTEXM3_STM32W108) #include "micro/cortexm3/stm32w108/regs.h" - #include "micro/cortexm3/stm32w108/stm32w108_type.h" + #include "micro/cortexm3/stm32w108/stm32w108-type.h" #elif defined (CORTEXM3_STM32F103) #include "stm32f10x.h" #else @@ -87,12 +87,12 @@ * @brief A typedef to make the size of the variable explicitly known. */ typedef unsigned char boolean; -typedef unsigned char int8u; -typedef signed char int8s; -typedef unsigned short int16u; -typedef signed short int16s; -typedef unsigned int int32u; -typedef signed int int32s; +typedef unsigned char uint8_t; +typedef signed char int8_t; +typedef unsigned short uint16_t; +typedef signed short int16_t; +typedef unsigned int uint32_t; +typedef signed int int32_t; typedef unsigned int PointerType; //@} \\END MASTER VARIABLE TYPES @@ -359,7 +359,7 @@ void _executeBarrierInstructions(void); * declarations section of any function which calls DISABLE_INTERRUPTS() * or RESTORE_INTERRUPTS(). */ - #define DECLARE_INTERRUPT_STATE int8u _emIsrState + #define DECLARE_INTERRUPT_STATE uint8_t _emIsrState // Prototypes for the BASEPRI and PRIMASK access functions. They are very // basic and instantiated in assembly code in the file spmr.s37 (since @@ -368,13 +368,13 @@ void _executeBarrierInstructions(void); // with a priority equal to or less than the BASEPRI value. // Note that the priority values used by these functions are 5 bits and // right-aligned - extern int8u _readBasePri(void); - extern void _writeBasePri(int8u priority); + extern uint8_t _readBasePri(void); + extern void _writeBasePri(uint8_t priority); // Prototypes for BASEPRI functions used to disable and enable interrupts // while still allowing enabled faults to trigger. extern void _enableBasePri(void); - extern int8u _disableBasePri(void); + extern uint8_t _disableBasePri(void); extern boolean _basePriIsDisabled(void); // Prototypes for setting and clearing PRIMASK for global interrupt diff --git a/cpu/stm32w108/hal/micro/cortexm3/context-switch.s79 b/cpu/stm32w108/hal/micro/cortexm3/context-switch.s79 index 1fea855e4..91f74d58e 100644 --- a/cpu/stm32w108/hal/micro/cortexm3/context-switch.s79 +++ b/cpu/stm32w108/hal/micro/cortexm3/context-switch.s79 @@ -53,7 +53,7 @@ halPendSvSaveContext: //------------------------------------------------------------------------------ -// int32u savedMSP +// uint32_t savedMSP // // Private storage to hold the saved stack pointer. This variable is only used // in this file and should not be extern'ed. In our current design we diff --git a/cpu/stm32w108/hal/micro/cortexm3/cstartup_M.s b/cpu/stm32w108/hal/micro/cortexm3/cstartup_M.s deleted file mode 100644 index e28e353b7..000000000 --- a/cpu/stm32w108/hal/micro/cortexm3/cstartup_M.s +++ /dev/null @@ -1,149 +0,0 @@ -/************************************************** - * - * Part one of the system initialization code, contains low-level - * initialization, plain thumb variant. - * - - * Customized by St Corporation for STM32W - * - * - **************************************************/ - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - PUBLIC __vector_table - - DATA -__vector_table - DCD sfe(CSTACK) - DCD __iar_program_start - - ;; Standard Cortex-M3 Vectors - DCD NMI_Handler ;;NMI Handler - DCD HardFault_Handler ;;Hard Fault Handler - DCD MemManage_Handler ;;Memory Fault Handler - DCD BusFault_Handler ;;Bus Fault Handler - DCD UsageFault_Handler ;;Usage Fault Handler - DCD 0 ;;Reserved - DCD 0 ;;Reserved - DCD 0 ;;Reserved - DCD 0 ;;Reserved - DCD SVC_Handler ;;SVCall Handler - DCD DebugMon_Handler ;;Debug Monitor Handler - DCD 0 ;;Reserved - DCD PendSV_Handler ;;PendSV Handler - DCD SysTick_Handler ;;SysTick Handler - - ;; STM32W Vectors - DCD halTimer1Isr ;;Timer 1 Handler - DCD halTimer2Isr ;;Timer 2 Handler - DCD halManagementIsr ;;Management Handler - DCD halBaseBandIsr ;;BaseBand Handler - DCD halSleepTimerIsr ;;Sleep Timer Handler - DCD halSc1Isr ;;SC1 Handler - DCD halSc2Isr ;;SC2 Handler - DCD halSecurityIsr ;;Security Handler - DCD halStackMacTimerIsr ;;MAC Timer Handler - DCD stmRadioTransmitIsr ;;MAC TX Handler - DCD stmRadioReceiveIsr ;;MAC RX Handler - DCD halAdcIsr ;;ADC Handler - DCD halIrqAIsr ;;GPIO IRQA Handler - DCD halIrqBIsr ;;GPIO IRQB Handler - DCD halIrqCIsr ;;GPIO IRQC Handler - DCD halIrqDIsr ;;GPIO IRQD Handler - DCD halDebugIsr ;;Debug Handler - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - - PUBWEAK NMI_Handler - PUBWEAK HardFault_Handler - PUBWEAK MemManage_Handler - PUBWEAK BusFault_Handler - PUBWEAK UsageFault_Handler - PUBWEAK SVC_Handler - PUBWEAK DebugMon_Handler - PUBWEAK PendSV_Handler - PUBWEAK SysTick_Handler - - PUBWEAK halTimer1Isr - PUBWEAK halTimer2Isr - PUBWEAK halManagementIsr - PUBWEAK halBaseBandIsr - PUBWEAK halSleepTimerIsr - PUBWEAK halSc1Isr - PUBWEAK halSc2Isr - PUBWEAK halSecurityIsr - PUBWEAK halStackMacTimerIsr - PUBWEAK stmRadioTransmitIsr - PUBWEAK stmRadioReceiveIsr - PUBWEAK halAdcIsr - PUBWEAK halIrqAIsr - PUBWEAK halIrqBIsr - PUBWEAK halIrqCIsr - PUBWEAK halIrqDIsr - PUBWEAK halDebugIsr - - - - - - - SECTION .text:CODE:REORDER(1) - THUMB - -NMI_Handler -HardFault_Handler -MemManage_Handler -BusFault_Handler -UsageFault_Handler -SVC_Handler -DebugMon_Handler -PendSV_Handler -SysTick_Handler -halTimer1Isr -halTimer2Isr -halManagementIsr -halBaseBandIsr -halSleepTimerIsr -halSc1Isr -halSc2Isr -halSecurityIsr -halStackMacTimerIsr -stmRadioTransmitIsr -stmRadioReceiveIsr -halAdcIsr -halIrqAIsr -halIrqBIsr -halIrqCIsr -halIrqDIsr -halDebugIsr -Default_Handler - B Default_Handler - - END diff --git a/cpu/stm32w108/hal/micro/cortexm3/flash.c b/cpu/stm32w108/hal/micro/cortexm3/flash.c index ef411d962..0612af672 100644 --- a/cpu/stm32w108/hal/micro/cortexm3/flash.c +++ b/cpu/stm32w108/hal/micro/cortexm3/flash.c @@ -85,10 +85,10 @@ static void disableFlitf(void) FLASH_CTRL = FLASH_CTRL_LOCK; //lock the flash from further accesses } -static FibStatus fibFlashWrite(int32u address, int8u *data, int32u length, int32u dummy) +static FibStatus fibFlashWrite(uint32_t address, uint8_t *data, uint32_t length, uint32_t dummy) { - int32u i; - int16u *ptr; + uint32_t i; + uint16_t *ptr; FibStatus status = FIB_SUCCESS; // Address and length must be half-word aligned. if ((address & 1) || (length & 1)) { @@ -100,10 +100,10 @@ static FibStatus fibFlashWrite(int32u address, int8u *data, int32u length, int32 return FIB_ERR_INVALID_ADDRESS; } enableFlitf(); - ptr = (int16u *)address; + ptr = (uint16_t *)address; for (i = 0; i < length; i += 2) { - int16u currentData = *ptr; - int16u newData = HIGH_LOW_TO_INT(data[i + 1], data[i]); + uint16_t currentData = *ptr; + uint16_t newData = HIGH_LOW_TO_INT(data[i + 1], data[i]); // Only program the data if it makes sense to do so. if (currentData == newData) { // If the new data matches the flash, don't bother doing anything. @@ -111,7 +111,7 @@ static FibStatus fibFlashWrite(int32u address, int8u *data, int32u length, int32 // If the flash is 0xFFFF we're allowed to write anything. // If the new data is 0x0000 it doesn't matter what the flash is. // OPTWREN must stay set to keep CIB unlocked. - if ((CIB_OB_BOTTOM <= (int32u)ptr) && ((int32u)ptr <= CIB_OB_TOP)) { + if ((CIB_OB_BOTTOM <= (uint32_t)ptr) && ((uint32_t)ptr <= CIB_OB_TOP)) { FLASH_CTRL = (FLASH_CTRL_OPTWREN | FLASH_CTRL_OPTPROG); } else { FLASH_CTRL = (FLASH_CTRL_OPTWREN | FLASH_CTRL_PROG); @@ -144,10 +144,10 @@ static FibStatus fibFlashWrite(int32u address, int8u *data, int32u length, int32 return status; } -static FibStatus fibFlashWriteVerify(int32u address, int8u *data, int32u length) +static FibStatus fibFlashWriteVerify(uint32_t address, uint8_t *data, uint32_t length) { - int32u i; - int8u *ptr = (int8u *)address; + uint32_t i; + uint8_t *ptr = (uint8_t *)address; for (i = 0; i < length; i++) { if (*ptr != data[i]) { return FIB_ERR_VERIFY_FAILED; @@ -157,26 +157,26 @@ static FibStatus fibFlashWriteVerify(int32u address, int8u *data, int32u length) return FIB_SUCCESS; } -static FibStatus fibFlashErase(FibEraseType eraseType, int32u address) +static FibStatus fibFlashErase(FibEraseType eraseType, uint32_t address) { - int32u eraseOp; - int32u *ptr; - int32u length; + uint32_t eraseOp; + uint32_t *ptr; + uint32_t length; FibStatus status = FIB_SUCCESS; if (BYTE_0(eraseType) == MFB_MASS_ERASE) { eraseOp = FLASH_CTRL_MASSERASE; - ptr = (int32u *)MFB_BOTTOM; + ptr = (uint32_t *)MFB_BOTTOM; length = MFB_SIZE_W; } else if (BYTE_0(eraseType) == MFB_PAGE_ERASE) { if (address < MFB_BOTTOM || address > MFB_TOP) { return FIB_ERR_INVALID_ADDRESS; } eraseOp = FLASH_CTRL_PAGEERASE; - ptr = (int32u *)(address & MFB_PAGE_MASK_B); + ptr = (uint32_t *)(address & MFB_PAGE_MASK_B); length = MFB_PAGE_SIZE_W; } else if (BYTE_0(eraseType) == CIB_ERASE) { eraseOp = FLASH_CTRL_OPTWREN | FLASH_CTRL_OPTERASE; - ptr = (int32u *)CIB_BOTTOM; + ptr = (uint32_t *)CIB_BOTTOM; length = CIB_SIZE_W; } else { return FIB_ERR_INVALID_TYPE; @@ -203,7 +203,7 @@ static FibStatus fibFlashErase(FibEraseType eraseType, int32u address) } if (status == FIB_SUCCESS && (eraseType & DO_VERIFY) != 0) { - int32u i; + uint32_t i; for (i = 0; i < length; i++) { if (*ptr != 0xFFFFFFFF) { return FIB_ERR_VERIFY_FAILED; @@ -228,7 +228,7 @@ static boolean verifyFib(void) //The parameter 'eraseType' chooses which erasure will be performed while //the 'address' parameter chooses the page to be erased during MFB page erase. -StStatus halInternalFlashErase(int8u eraseType, int32u address) +StStatus halInternalFlashErase(uint8_t eraseType, uint32_t address) { FibStatus status; @@ -239,10 +239,10 @@ StStatus halInternalFlashErase(int8u eraseType, int32u address) // Always try to use the FIB bootloader if its present if(verifyFib()) { status = halFixedAddressTable.fibFlashErase( - (((int32u)eraseType) | DO_ERASE), + (((uint32_t)eraseType) | DO_ERASE), address); } else { - status = fibFlashErase((((int32u)eraseType) | DO_ERASE), address); + status = fibFlashErase((((uint32_t)eraseType) | DO_ERASE), address); } #else @@ -250,7 +250,7 @@ StStatus halInternalFlashErase(int8u eraseType, int32u address) assert(verifyFib()); status = halFixedAddressTable.fibFlashErase( - (((int32u)eraseType) | DO_ERASE), + (((uint32_t)eraseType) | DO_ERASE), address); #endif ) @@ -270,14 +270,14 @@ StStatus halInternalFlashErase(int8u eraseType, int32u address) // Always try to use the FIB bootloader if its present if(verifyFib()) { status = halFixedAddressTable.fibFlashErase( - (((int32u)eraseType) | DO_VERIFY), + (((uint32_t)eraseType) | DO_VERIFY), address); } else { - status = fibFlashErase((((int32u)eraseType) | DO_VERIFY), address); + status = fibFlashErase((((uint32_t)eraseType) | DO_VERIFY), address); } #else status = halFixedAddressTable.fibFlashErase( - (((int32u)eraseType) | DO_VERIFY), + (((uint32_t)eraseType) | DO_VERIFY), address); #endif return fibToStStatus[status]; @@ -291,7 +291,7 @@ StStatus halInternalFlashErase(int8u eraseType, int32u address) //half-words contained in 'data' to be written to flash. //NOTE: This function can NOT write the option bytes and will throw an error //if that is attempted. -StStatus halInternalFlashWrite(int32u address, int16u * data, int32u length) +StStatus halInternalFlashWrite(uint32_t address, uint16_t * data, uint32_t length) { FibStatus status; @@ -303,11 +303,11 @@ StStatus halInternalFlashWrite(int32u address, int16u * data, int32u length) // Always try to use the FIB bootloader if its present if(verifyFib()) { status = halFixedAddressTable.fibFlashWrite(address, - (int8u *)data, + (uint8_t *)data, length, 0); } else { - status = fibFlashWrite(address, (int8u *)data, length, 0); + status = fibFlashWrite(address, (uint8_t *)data, length, 0); } #else @@ -316,7 +316,7 @@ StStatus halInternalFlashWrite(int32u address, int16u * data, int32u length) // Ensure that a programmed FIB of a proper version is present assert(verifyFib()); status = halFixedAddressTable.fibFlashWrite(address, - (int8u *)data, + (uint8_t *)data, length, 0); #endif @@ -331,15 +331,15 @@ StStatus halInternalFlashWrite(int32u address, int16u * data, int32u length) // Always try to use the FIB bootloader if its present if(verifyFib()) { status = halFixedAddressTable.fibFlashWrite(address, - (int8u *)data, + (uint8_t *)data, 0, length); } else { - status = fibFlashWriteVerify(address, (int8u *)data, length); + status = fibFlashWriteVerify(address, (uint8_t *)data, length); } #else status = halFixedAddressTable.fibFlashWrite(address, - (int8u *)data, + (uint8_t *)data, 0, length); #endif @@ -352,9 +352,9 @@ StStatus halInternalFlashWrite(int32u address, int16u * data, int32u length) //parameter can have a value of 0 through 7. 'data' is the 8bit value to be //programmed into the option byte since the hardware will calculate the //compliment and program the full 16bit option byte. -StStatus halInternalCibOptionByteWrite(int8u byte, int8u data) +StStatus halInternalCibOptionByteWrite(uint8_t byte, uint8_t data) { - int16u dataAndInverse = HIGH_LOW_TO_INT(~data, data); + uint16_t dataAndInverse = HIGH_LOW_TO_INT(~data, data); // There are only 8 option bytes, don't try to program more than that. if (byte > 7) { return ST_ERR_FLASH_PROG_FAIL; diff --git a/cpu/stm32w108/hal/micro/cortexm3/flash.h b/cpu/stm32w108/hal/micro/cortexm3/flash.h index 32899892f..90d6c20c9 100644 --- a/cpu/stm32w108/hal/micro/cortexm3/flash.h +++ b/cpu/stm32w108/hal/micro/cortexm3/flash.h @@ -65,7 +65,7 @@ boolean halFlashEraseIsActive(void); * - ST_ERR_FLASH_VERIFY_FAILED if erase verification failed * - ST_SUCCESS if erasure completed and verified properly */ -StStatus halInternalFlashErase(int8u eraseType, int32u address); +StStatus halInternalFlashErase(uint8_t eraseType, uint32_t address); /** @brief Writes a block of words to flash. A page is erased * to 0xFFFF at every address. Only two writes can be performed to the same @@ -96,7 +96,7 @@ StStatus halInternalFlashErase(int8u eraseType, int32u address); * - ST_ERR_FLASH_VERIFY_FAILED if write verification failed * - ST_SUCCESS if writing completed and verified properly */ -StStatus halInternalFlashWrite(int32u address, int16u * data, int32u length); +StStatus halInternalFlashWrite(uint32_t address, uint16_t * data, uint32_t length); /** @brief Writes an option byte to the customer information block. Only * two writes can be performed to the same address between erasures and this @@ -116,7 +116,7 @@ StStatus halInternalFlashWrite(int32u address, int16u * data, int32u length); * - ST_ERR_FLASH_VERIFY_FAILED if write verification failed * - ST_SUCCESS if writing completed and verified properly */ -StStatus halInternalCibOptionByteWrite(int8u byte, int8u data); +StStatus halInternalCibOptionByteWrite(uint8_t byte, uint8_t data); #endif //DOXYGEN_SHOULD_SKIP_THIS diff --git a/cpu/stm32w108/hal/micro/cortexm3/led.c b/cpu/stm32w108/hal/micro/cortexm3/led.c index dd0d5f58f..9f5f90fb8 100644 --- a/cpu/stm32w108/hal/micro/cortexm3/led.c +++ b/cpu/stm32w108/hal/micro/cortexm3/led.c @@ -36,7 +36,7 @@ void halToggleLed(HalBoardLed led) //purposes, we disable interrupts since this is a read-modify-write ATOMIC( if(led/8 < 3) { - *((volatile int32u *)(GPIO_PxOUT_BASE+(GPIO_Px_OFFSET*(led/8)))) ^= BIT(led&7); + *((volatile uint32_t *)(GPIO_PxOUT_BASE+(GPIO_Px_OFFSET*(led/8)))) ^= BIT(led&7); } ) } diff --git a/cpu/stm32w108/hal/micro/cortexm3/memmap-fat.h b/cpu/stm32w108/hal/micro/cortexm3/memmap-fat.h index 845ae67f0..0587e1fa8 100644 --- a/cpu/stm32w108/hal/micro/cortexm3/memmap-fat.h +++ b/cpu/stm32w108/hal/micro/cortexm3/memmap-fat.h @@ -29,9 +29,9 @@ typedef struct { HalBootloaderAddressTableType *bootloaderAddressTable; void *startOfUnusedRam; // ** pointers to shared functions ** - FibStatus (* fibFlashWrite)(int32u address, int8u *data, - int32u writeLength, int32u verifyLength); - FibStatus (* fibFlashErase)(FibEraseType eraseType, int32u address); + FibStatus (* fibFlashWrite)(uint32_t address, uint8_t *data, + uint32_t writeLength, uint32_t verifyLength); + FibStatus (* fibFlashErase)(FibEraseType eraseType, uint32_t address); } HalFixedAddressTableType; extern const HalFixedAddressTableType halFixedAddressTable; diff --git a/cpu/stm32w108/hal/micro/cortexm3/memmap.h b/cpu/stm32w108/hal/micro/cortexm3/memmap.h index 8feb1b997..4849a4b23 100644 --- a/cpu/stm32w108/hal/micro/cortexm3/memmap.h +++ b/cpu/stm32w108/hal/micro/cortexm3/memmap.h @@ -53,8 +53,8 @@ typedef struct { void (*resetVector)(void); void (*nmiHandler)(void); void (*hardFaultHandler)(void); - int16u type; - int16u version; + uint16_t type; + uint16_t version; const HalVectorTableType *vectorTable; // Followed by more fields depending on the specific address table type } HalBaseAddressTableType; diff --git a/cpu/stm32w108/hal/micro/cortexm3/mems.c b/cpu/stm32w108/hal/micro/cortexm3/mems.c index 6bbd6b387..4a0437feb 100644 --- a/cpu/stm32w108/hal/micro/cortexm3/mems.c +++ b/cpu/stm32w108/hal/micro/cortexm3/mems.c @@ -19,19 +19,19 @@ #define WAIT_TX_FIN() do{}while((SC2_TWISTAT&SC_TWITXFIN)!=SC_TWITXFIN) #define WAIT_RX_FIN() do{}while((SC2_TWISTAT&SC_TWIRXFIN)!=SC_TWIRXFIN) -static int8u i2c_MEMS_Init (void); -static int8u i2c_MEMS_Read (t_mems_data *mems_data); +static uint8_t i2c_MEMS_Init (void); +static uint8_t i2c_MEMS_Read (t_mems_data *mems_data); //extern void halInternalResetWatchDog(void); -static int8u i2c_Send_Frame (int8u DeviceAddress, int8u *pBuffer, int8u NoOfBytes); -static int8u i2c_Send_Frame (int8u DeviceAddress, int8u *pBuffer, int8u NoOfBytes); -int8u i2c_write_reg (int8u slave_addr, int8u reg_addr, int8u reg_value); -static int8u i2c_MEMS_Init (void); -static int8u i2c_MEMS_Read (t_mems_data *mems_data); +static uint8_t i2c_Send_Frame (uint8_t DeviceAddress, uint8_t *pBuffer, uint8_t NoOfBytes); +static uint8_t i2c_Send_Frame (uint8_t DeviceAddress, uint8_t *pBuffer, uint8_t NoOfBytes); +uint8_t i2c_write_reg (uint8_t slave_addr, uint8_t reg_addr, uint8_t reg_value); +static uint8_t i2c_MEMS_Init (void); +static uint8_t i2c_MEMS_Read (t_mems_data *mems_data); /* Functions -----------------------------------------------------------------*/ -int8u mems_Init(void) +uint8_t mems_Init(void) { - int8u ret = 0; + uint8_t ret = 0; // GPIO assignments // PA1: SC2SDA (Serial Data) @@ -60,9 +60,9 @@ int8u mems_Init(void) return ret; }/* end mems_Init */ -int8u mems_GetValue(t_mems_data *mems_data) +uint8_t mems_GetValue(t_mems_data *mems_data) { - int8u i; + uint8_t i; i = i2c_MEMS_Read(mems_data); return i; }/* end mems_GetValue() */ @@ -79,9 +79,9 @@ int8u mems_GetValue(t_mems_data *mems_data) * Output : None * Return : status *******************************************************************************/ -static int8u i2c_Send_Frame (int8u DeviceAddress, int8u *pBuffer, int8u NoOfBytes) +static uint8_t i2c_Send_Frame (uint8_t DeviceAddress, uint8_t *pBuffer, uint8_t NoOfBytes) { - int8u i, data; + uint8_t i, data; SC2_TWICTRL1 |= SC_TWISTART; // send start WAIT_CMD_FIN(); @@ -115,9 +115,9 @@ static int8u i2c_Send_Frame (int8u DeviceAddress, int8u *pBuffer, int8u NoOfByte * Output : buffer * Return : status *******************************************************************************/ -static int8u i2c_Receive_Frame (int8u slave_addr, int8u reg_addr, int8u *pBuffer, int8u NoOfBytes) +static uint8_t i2c_Receive_Frame (uint8_t slave_addr, uint8_t reg_addr, uint8_t *pBuffer, uint8_t NoOfBytes) { - int8u i, addr = reg_addr; + uint8_t i, addr = reg_addr; if (NoOfBytes > 1) addr += REPETIR; @@ -168,9 +168,9 @@ static int8u i2c_Receive_Frame (int8u slave_addr, int8u reg_addr, int8u *pBuffer * Output : None * Return : I2C frame *******************************************************************************/ -int8u i2c_write_reg (int8u slave_addr, int8u reg_addr, int8u reg_value) +uint8_t i2c_write_reg (uint8_t slave_addr, uint8_t reg_addr, uint8_t reg_value) { - int8u i2c_buffer[2]; + uint8_t i2c_buffer[2]; i2c_buffer[0] = reg_addr; i2c_buffer[1] = reg_value; @@ -188,7 +188,7 @@ int8u i2c_write_reg (int8u slave_addr, int8u reg_addr, int8u reg_value) * Output : None * Return : I2C frame *******************************************************************************/ -int8u i2c_read_reg (int8u slave_addr, int8u reg_addr, int8u *pBuffer, int8u NoOfBytes) +uint8_t i2c_read_reg (uint8_t slave_addr, uint8_t reg_addr, uint8_t *pBuffer, uint8_t NoOfBytes) { return i2c_Receive_Frame (slave_addr, reg_addr, pBuffer, NoOfBytes); }/* end i2c_read_reg() */ @@ -201,9 +201,9 @@ int8u i2c_read_reg (int8u slave_addr, int8u reg_addr, int8u *pBuffer, int8u NoOf * Output : None * Return : status *******************************************************************************/ -static int8u i2c_MEMS_Init (void) +static uint8_t i2c_MEMS_Init (void) { - int8u i = 0; + uint8_t i = 0; i += i2c_write_reg (kLIS3L02DQ_SLAVE_ADDR, STATUS_REG, 0x00); //no flag i += i2c_write_reg (kLIS3L02DQ_SLAVE_ADDR, FF_WU_CFG, 0x00); // all off @@ -224,9 +224,9 @@ static int8u i2c_MEMS_Init (void) * Output : mems_data * Return : I2C frame *******************************************************************************/ -static int8u i2c_MEMS_Read (t_mems_data *mems_data) +static uint8_t i2c_MEMS_Read (t_mems_data *mems_data) { - int8u i, i2c_buffer[8]; + uint8_t i, i2c_buffer[8]; /* Wait for new set of data to be available */ while (1) { diff --git a/cpu/stm32w108/hal/micro/cortexm3/mfg-token.c b/cpu/stm32w108/hal/micro/cortexm3/mfg-token.c index 537a4ac34..c6c0b532c 100644 --- a/cpu/stm32w108/hal/micro/cortexm3/mfg-token.c +++ b/cpu/stm32w108/hal/micro/cortexm3/mfg-token.c @@ -13,7 +13,7 @@ #define DEFINETOKENS #define TOKEN_MFG(name,creator,iscnt,isidx,type,arraysize,...) \ - const int16u TOKEN_##name = TOKEN_##name##_ADDRESS; + const uint16_t TOKEN_##name = TOKEN_##name##_ADDRESS; #include "hal/micro/cortexm3/token-manufacturing.h" #undef TOKEN_DEF #undef TOKEN_MFG @@ -26,12 +26,12 @@ -static const int8u nullEui[] = { 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF }; +static const uint8_t nullEui[] = { 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF }; -void halInternalGetMfgTokenData(void *data, int16u ID, int8u index, int8u len) +void halInternalGetMfgTokenData(void *data, uint16_t ID, uint8_t index, uint8_t len) { - int8u *ram = (int8u*)data; + uint8_t *ram = (uint8_t*)data; //0x7F is a non-indexed token. Remap to 0 for the address calculation index = (index==0x7F) ? 0 : index; @@ -53,8 +53,8 @@ void halInternalGetMfgTokenData(void *data, int16u ID, int8u index, int8u len) //bottom 16bits of the token's actual address. Since the info blocks //exist in the range DATA_BIG_INFO_BASE-DATA_BIG_INFO_END, we need //to OR the ID with DATA_BIG_INFO_BASE to get the real address. - int32u realAddress = (DATA_BIG_INFO_BASE|ID) + (len*index); - int8u *flash = (int8u *)realAddress; + uint32_t realAddress = (DATA_BIG_INFO_BASE|ID) + (len*index); + uint8_t *flash = (uint8_t *)realAddress; @@ -74,12 +74,12 @@ void halInternalGetMfgTokenData(void *data, int16u ID, int8u index, int8u len) } -void halInternalSetMfgTokenData(int16u token, void *data, int8u len) +void halInternalSetMfgTokenData(uint16_t token, void *data, uint8_t len) { StStatus flashStatus; - int32u realAddress = (DATA_BIG_INFO_BASE|token); - int8u * flash = (int8u *)realAddress; - int32u i; + uint32_t realAddress = (DATA_BIG_INFO_BASE|token); + uint8_t * flash = (uint8_t *)realAddress; + uint32_t i; //The flash library (and hardware) requires the address and length to both //be multiples of 16bits. Since this API is only valid for writing to diff --git a/cpu/stm32w108/hal/micro/cortexm3/mfg-token.h b/cpu/stm32w108/hal/micro/cortexm3/mfg-token.h index 534cb920e..b7a14ed20 100644 --- a/cpu/stm32w108/hal/micro/cortexm3/mfg-token.h +++ b/cpu/stm32w108/hal/micro/cortexm3/mfg-token.h @@ -26,7 +26,7 @@ * will be stored. This parameter is generated with a macro above. */ #define TOKEN_MFG(name,creator,iscnt,isidx,type,arraysize,...) \ - extern const int16u TOKEN_##name; + extern const uint16_t TOKEN_##name; #include "hal/micro/cortexm3/token-manufacturing.h" #undef TOKEN_MFG @@ -125,7 +125,7 @@ enum { * @param len: The length of the token being worked on. This value is * automatically set by the API to be the size of the token. */ -void halInternalGetMfgTokenData(void *data, int16u token, int8u index, int8u len); +void halInternalGetMfgTokenData(void *data, uint16_t token, uint8_t index, uint8_t len); /** * @description Sets the value of a token in non-volatile storage. This is @@ -147,7 +147,7 @@ void halInternalGetMfgTokenData(void *data, int16u token, int8u index, int8u len * @param len: The length of the token being worked on. This value is * automatically set by the API to be the size of the token. */ -void halInternalSetMfgTokenData(int16u token, void *data, int8u len); +void halInternalSetMfgTokenData(uint16_t token, void *data, uint8_t len); #define halCommonGetMfgToken( data, token ) \ halInternalGetMfgTokenData(data, token, 0x7F, token##_SIZE) diff --git a/cpu/stm32w108/hal/micro/cortexm3/micro-common-internal.c b/cpu/stm32w108/hal/micro/cortexm3/micro-common-internal.c index 1bdeb36fa..bd35a1d51 100644 --- a/cpu/stm32w108/hal/micro/cortexm3/micro-common-internal.c +++ b/cpu/stm32w108/hal/micro/cortexm3/micro-common-internal.c @@ -54,8 +54,8 @@ void stCalibrateVref(void) assert(FALSE); } else { //The bias trim token is set, so use the trim directly - int16u temp_value; - int16u mask = 0xFFFF; + uint16_t temp_value; + uint16_t mask = 0xFFFF; // halClearLed(BOARDLED3); @@ -95,11 +95,11 @@ void calDisableAdc(void) { // These routines maintain the same signature as their hal- counterparts to // facilitate simple support between phys. // It is assumed (hoped?) that the compiler will optimize out unused arguments. -StStatus calStartAdcConversion(int8u dummy1, // Not used. - int8u dummy2, // Not used. - int8u channel, - int8u rate, - int8u clock) { +StStatus calStartAdcConversion(uint8_t dummy1, // Not used. + uint8_t dummy2, // Not used. + uint8_t channel, + uint8_t rate, + uint8_t clock) { // Disable the Calibration ADC interrupt so that we can poll it. INT_MGMTCFG &= ~INT_MGMTCALADC; @@ -118,14 +118,14 @@ StStatus calStartAdcConversion(int8u dummy1, // Not used. } -StStatus calReadAdcBlocking(int8u dummy, - int16u *value) { +StStatus calReadAdcBlocking(uint8_t dummy, + uint16_t *value) { // Wait for conversion to complete. while ( ! (INT_MGMTFLAG & INT_MGMTCALADC) ); // Clear the interrupt for this conversion. INT_MGMTFLAG = INT_MGMTCALADC; // Get the result. - *value = (int16u)CAL_ADC_DATA; + *value = (uint16_t)CAL_ADC_DATA; return ST_SUCCESS; } @@ -137,12 +137,12 @@ StStatus calReadAdcBlocking(int8u dummy, //the fastest conversions with the greatest reasonable accuracy. Variation //across successive conversions appears to be +/-20mv of the average //conversion. Overall function time is <150us. -int16u stMeasureVddFast(void) +uint16_t stMeasureVddFast(void) { - int16u value; - int32u Ngnd; - int32u Nreg; - int32u Nvdd; + uint16_t value; + uint32_t Ngnd; + uint32_t Nreg; + uint32_t Nvdd; tokTypeMfgRegVoltage1V8 vregOutTok; halCommonGetMfgToken(&vregOutTok, TOKEN_MFG_1V8_REG_VOLTAGE); @@ -153,7 +153,7 @@ int16u stMeasureVddFast(void) ADC_SAMPLE_CLOCKS_128, ADC_6MHZ_CLOCK); calReadAdcBlocking(DUMMY, &value); - Ngnd = (int32u)value; + Ngnd = (uint32_t)value; //Measure VREG_OUT/2 calStartAdcConversion(DUMMY, @@ -162,7 +162,7 @@ int16u stMeasureVddFast(void) ADC_SAMPLE_CLOCKS_128, ADC_6MHZ_CLOCK); calReadAdcBlocking(DUMMY, &value); - Nreg = (int32u)value; + Nreg = (uint32_t)value; //Measure VDD_PADS/4 calStartAdcConversion(DUMMY, @@ -171,7 +171,7 @@ int16u stMeasureVddFast(void) ADC_SAMPLE_CLOCKS_128, ADC_6MHZ_CLOCK); calReadAdcBlocking(DUMMY, &value); - Nvdd = (int32u)value; + Nvdd = (uint32_t)value; calDisableAdc(); @@ -202,8 +202,8 @@ void halCommonCalibratePads(void) void halInternalSetRegTrim(boolean boostMode) { tokTypeMfgRegTrim regTrim; - int8u trim1V2; - int8u trim1V8; + uint8_t trim1V2; + uint8_t trim1V8; halCommonGetMfgToken(®Trim, TOKEN_MFG_REG_TRIM); // The compiler can optimize this function a bit more and keep the @@ -247,9 +247,9 @@ void halInternalSetRegTrim(boolean boostMode) // OSCHF, though, the clock speed is cut in half, so the input parameter // is divided by two. With respect to accuracy, we're now limited by // the accuracy of OSCHF (much lower than XTAL). -void halCommonDelayMicroseconds(int16u us) +void halCommonDelayMicroseconds(uint16_t us) { - int32u beginTime = ReadRegister(MAC_TIMER); + uint32_t beginTime = ReadRegister(MAC_TIMER); //If we're not using the XTAL, the MAC Timer is running off OSCHF, //that means the clock is half speed, 6MHz. We need to halve our delay @@ -281,7 +281,7 @@ void halCommonDelayMicroseconds(int16u us) //necessary in some situations. If you have to burn more than 65ms of time, //the halCommonDelayMicroseconds function becomes cumbersome, so this //function gives you millisecond granularity. -void halCommonDelayMilliseconds(int16u ms) +void halCommonDelayMilliseconds(uint16_t ms) { if(ms==0) { return; diff --git a/cpu/stm32w108/hal/micro/cortexm3/micro-common.c b/cpu/stm32w108/hal/micro/cortexm3/micro-common.c index 965b25c58..6312aa219 100644 --- a/cpu/stm32w108/hal/micro/cortexm3/micro-common.c +++ b/cpu/stm32w108/hal/micro/cortexm3/micro-common.c @@ -28,7 +28,7 @@ void halInternalResetWatchDog(void) WDOG_RESET = 1; } -void halInternalDisableWatchDog(int8u magicKey) +void halInternalDisableWatchDog(uint8_t magicKey) { if (magicKey == MICRO_DISABLE_WATCH_DOG_KEY) { WDOG_KEY = 0xDEAD; @@ -45,33 +45,33 @@ boolean halInternalWatchDogEnabled(void) } } -void halGpioConfig(int32u io, int32u config) +void halGpioConfig(uint32_t io, uint32_t config) { - static volatile int32u *const configRegs[] = - { (volatile int32u *)GPIO_PACFGL_ADDR, - (volatile int32u *)GPIO_PACFGH_ADDR, - (volatile int32u *)GPIO_PBCFGL_ADDR, - (volatile int32u *)GPIO_PBCFGH_ADDR, - (volatile int32u *)GPIO_PCCFGL_ADDR, - (volatile int32u *)GPIO_PCCFGH_ADDR }; - int32u portcfg; + static volatile uint32_t *const configRegs[] = + { (volatile uint32_t *)GPIO_PACFGL_ADDR, + (volatile uint32_t *)GPIO_PACFGH_ADDR, + (volatile uint32_t *)GPIO_PBCFGL_ADDR, + (volatile uint32_t *)GPIO_PBCFGH_ADDR, + (volatile uint32_t *)GPIO_PCCFGL_ADDR, + (volatile uint32_t *)GPIO_PCCFGH_ADDR }; + uint32_t portcfg; portcfg = *configRegs[io/4]; // get current config portcfg = portcfg & ~((0xF)<<((io&3)*4)); // mask out config of this pin *configRegs[io/4] = portcfg | (config <<((io&3)*4)); } -void halGpioSet(int32u gpio, boolean value) +void halGpioSet(uint32_t gpio, boolean value) { if(gpio/8 < 3) { if (value) { - *((volatile int32u *)(GPIO_PxSET_BASE+(GPIO_Px_OFFSET*(gpio/8)))) = BIT(gpio&7); + *((volatile uint32_t *)(GPIO_PxSET_BASE+(GPIO_Px_OFFSET*(gpio/8)))) = BIT(gpio&7); } else { - *((volatile int32u *)(GPIO_PxCLR_BASE+(GPIO_Px_OFFSET*(gpio/8)))) = BIT(gpio&7); + *((volatile uint32_t *)(GPIO_PxCLR_BASE+(GPIO_Px_OFFSET*(gpio/8)))) = BIT(gpio&7); } } } -int16u halInternalStartSystemTimer(void) +uint16_t halInternalStartSystemTimer(void) { //Since the SleepTMR is the only timer maintained during deep sleep, it is //used as the System Timer (RTC). We maintain a 32 bit hardware timer diff --git a/cpu/stm32w108/hal/micro/cortexm3/micro-common.h b/cpu/stm32w108/hal/micro/cortexm3/micro-common.h index b538e6f08..b7117c123 100644 --- a/cpu/stm32w108/hal/micro/cortexm3/micro-common.h +++ b/cpu/stm32w108/hal/micro/cortexm3/micro-common.h @@ -20,7 +20,7 @@ //This is necessary here because halSleepForQsWithOptions returns an //StStatus and not adding this typedef to this file breaks a //whole lot of builds. - typedef int8u StStatus; + typedef uint8_t StStatus; #endif //__STSTATUS_TYPE__ #endif // DOXYGEN_SHOULD_SKIP_THIS @@ -71,7 +71,7 @@ void halInternalResetWatchDog( void ); * @param config The configuration mode to use. * */ -void halGpioConfig(int32u io, int32u config); +void halGpioConfig(uint32_t io, uint32_t config); /** * @brief Set/Clear single GPIO bit @@ -81,7 +81,7 @@ void halGpioConfig(int32u io, int32u config); * @param value A flag indicating whether to set or clear the io. * */ -void halGpioSet(int32u io, boolean value); +void halGpioSet(uint32_t io, boolean value); /** @@ -111,7 +111,7 @@ void halInternalSetRegTrim(boolean boostMode); * * @return A slow measurement of VDD_PADS in millivolts. */ -int16u stMeasureVddSlow(void); +uint16_t stMeasureVddSlow(void); /** @brief Takes a fast ADC measurement of VDD_PADS in millivolts. @@ -121,7 +121,7 @@ int16u stMeasureVddSlow(void); * * @return A fast measurement of VDD_PADS in millivolts. */ -int16u stMeasureVddFast(void); +uint16_t stMeasureVddFast(void); /** @@ -164,7 +164,7 @@ void halInternalSearchForBiasTrim(void); * * @param ms The specified time, in milliseconds. */ -void halCommonDelayMilliseconds(int16u ms); +void halCommonDelayMilliseconds(uint16_t ms); /** @brief Puts the microcontroller to sleep in a specified mode, allows @@ -183,7 +183,7 @@ void halCommonDelayMilliseconds(int16u ms); * * @sa ::SleepModes */ -void halSleepWithOptions(SleepModes sleepMode, int32u gpioWakeBitMask); +void halSleepWithOptions(SleepModes sleepMode, uint32_t gpioWakeBitMask); /** @@ -218,7 +218,7 @@ void halSleepWithOptions(SleepModes sleepMode, int32u gpioWakeBitMask); * @return An StStatus value indicating the success or * failure of the command. */ -StStatus halSleepForQsWithOptions(int32u *duration, int32u gpioWakeBitMask); +StStatus halSleepForQsWithOptions(uint32_t *duration, uint32_t gpioWakeBitMask); /** * @brief Provides access to assembly code which triggers idle sleep. @@ -262,7 +262,7 @@ void halInternalSleep(SleepModes sleepMode); * * @return The events that caused the last wake from sleep. */ -int32u halGetWakeInfo(void); +uint32_t halGetWakeInfo(void); /** @brief Seeds the ::halCommonGetRandom() pseudorandom number @@ -273,7 +273,7 @@ int32u halGetWakeInfo(void); * * @param seed A seed for the pseudorandom number generator. */ -void halCommonSeedRandom(int32u seed); +void halCommonSeedRandom(uint32_t seed); /** @brief Runs a standard LFSR to generate pseudorandom numbers. * @@ -283,7 +283,7 @@ void halCommonSeedRandom(int32u seed); * ability to avoid collisions in large networks, but it is \b critical to * implement this function to return quickly. */ -int16u halCommonGetRandom(void); +uint16_t halCommonGetRandom(void); #endif //__STM32W108XX_MICRO_COMMON_H__ diff --git a/cpu/stm32w108/hal/micro/cortexm3/micro.c b/cpu/stm32w108/hal/micro/cortexm3/micro.c index 34cbf0957..e9208b7df 100644 --- a/cpu/stm32w108/hal/micro/cortexm3/micro.c +++ b/cpu/stm32w108/hal/micro/cortexm3/micro.c @@ -70,22 +70,22 @@ void halPowerUp(void) halBoardPowerUp(); } -static int16u seed0 = 0xbeef; -static int16u seed1 = 0xface; +static uint16_t seed0 = 0xbeef; +static uint16_t seed1 = 0xface; -void halCommonSeedRandom(int32u seed) +void halCommonSeedRandom(uint32_t seed) { - seed0 = (int16u) seed; + seed0 = (uint16_t) seed; if (seed0 == 0) seed0 = 0xbeef; - seed1 = (int16u) (seed >> 16); + seed1 = (uint16_t) (seed >> 16); if (seed1 == 0) seed1 = 0xface; } -static int16u shift(int16u *val, int16u taps) +static uint16_t shift(uint16_t *val, uint16_t taps) { - int16u newVal = *val; + uint16_t newVal = *val; if (newVal & 0x8000) newVal ^= taps; @@ -93,44 +93,44 @@ static int16u shift(int16u *val, int16u taps) return newVal; } -int16u halCommonGetRandom(void) +uint16_t halCommonGetRandom(void) { return (shift(&seed0, 0x0062) ^ shift(&seed1, 0x100B)); } -void halCommonMemCopy(void *dest, const void *source, int8u bytes) +void halCommonMemCopy(void *dest, const void *source, uint8_t bytes) { memcpy(dest, source, bytes); } -int8s halCommonMemCompare(const void *source0, const void *source1, int8u bytes) +int8_t halCommonMemCompare(const void *source0, const void *source1, uint8_t bytes) { return memcmp(source0, source1, bytes); } -void halCommonMemSet(void *dest, int8u val, int16u bytes) +void halCommonMemSet(void *dest, uint8_t val, uint16_t bytes) { memset(dest, val, bytes); } #pragma pack(1) typedef struct appSwitchStruct { - int32u signature; - int8u mode; - int8u channel; + uint32_t signature; + uint8_t mode; + uint8_t channel; union { - int16u panID; - int16u offset; + uint16_t panID; + uint16_t offset; } param; } appSwitchStructType; #pragma pack() static appSwitchStructType *appSwitch = (appSwitchStructType *) RAM_BOTTOM; -StStatus halBootloaderStart(int8u mode, int8u channel, int16u panID) +StStatus halBootloaderStart(uint8_t mode, uint8_t channel, uint16_t panID) { if (mode == IAP_BOOTLOADER_MODE_UART) { - int8u cut = *(volatile int8u *) 0x08040798; + uint8_t cut = *(volatile uint8_t *) 0x08040798; if (!( (halFixedAddressTable.baseTable.type == FIXED_ADDRESS_TABLE_TYPE) && ( ( (halFixedAddressTable.baseTable.version & FAT_MAJOR_VERSION_MASK) == 0x0000 ) && @@ -140,7 +140,7 @@ StStatus halBootloaderStart(int8u mode, int8u channel, int16u panID) return ST_ERR_FATAL; } else { /* Check that OTA bootloader is at the base of the flash */ - if (*((int32u *) (MFB_BOTTOM + 28)) == IAP_BOOTLOADER_APP_SWITCH_SIGNATURE) { + if (*((uint32_t *) (MFB_BOTTOM + 28)) == IAP_BOOTLOADER_APP_SWITCH_SIGNATURE) { appSwitch->channel = ((channel >= 11) && (channel <= 26)) ? channel :IAP_BOOTLOADER_DEFAULT_CHANNEL; appSwitch->param.panID = panID; } else { diff --git a/cpu/stm32w108/hal/micro/cortexm3/nvm.c b/cpu/stm32w108/hal/micro/cortexm3/nvm.c index 2aff89c99..4fed3da50 100644 --- a/cpu/stm32w108/hal/micro/cortexm3/nvm.c +++ b/cpu/stm32w108/hal/micro/cortexm3/nvm.c @@ -13,7 +13,7 @@ #ifdef NVM_RAM_EMULATION -static int16u calibrationData[32+2]={ +static uint16_t calibrationData[32+2]={ 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, @@ -21,14 +21,14 @@ static int16u calibrationData[32+2]={ 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, }; -int8u halCommonReadFromNvm(void *data, int32u offset, int16u length) +uint8_t halCommonReadFromNvm(void *data, uint32_t offset, uint16_t length) { - halCommonMemCopy(data, ((int8u *) calibrationData) + offset, length); + halCommonMemCopy(data, ((uint8_t *) calibrationData) + offset, length); return ST_SUCCESS; } -int8u halCommonWriteToNvm(const void *data, int32u offset, int16u length) +uint8_t halCommonWriteToNvm(const void *data, uint32_t offset, uint16_t length) { - halCommonMemCopy(((int8u *) calibrationData) + offset, data, length); + halCommonMemCopy(((uint8_t *) calibrationData) + offset, data, length); return ST_SUCCESS; } @@ -50,14 +50,14 @@ int8u halCommonWriteToNvm(const void *data, int32u offset, int16u length) //are not required to be continuous memory blocks so they can be define //separately. The linker is responsible for placing these storage containers //on flash page boundaries. -NO_STRIPPING __no_init VAR_AT_SEGMENT (const int8u nvmStorageLeft[NVM_DATA_SIZE_B], __NVM__); -NO_STRIPPING __no_init VAR_AT_SEGMENT (const int8u nvmStorageRight[NVM_DATA_SIZE_B], __NVM__); +NO_STRIPPING __no_init VAR_AT_SEGMENT (const uint8_t nvmStorageLeft[NVM_DATA_SIZE_B], __NVM__); +NO_STRIPPING __no_init VAR_AT_SEGMENT (const uint8_t nvmStorageRight[NVM_DATA_SIZE_B], __NVM__); -static int8u determineState(void) +static uint8_t determineState(void) { - int32u leftMgmt = *(int32u *)NVM_LEFT_PAGE; - int32u rightMgmt = *(int32u *)NVM_RIGHT_PAGE; - int8u state=0; + uint32_t leftMgmt = *(uint32_t *)NVM_LEFT_PAGE; + uint32_t rightMgmt = *(uint32_t *)NVM_RIGHT_PAGE; + uint8_t state=0; if((leftMgmt==0xFFFF0000) && (rightMgmt==0xFFFFFFFF)) { //State 1 and state 4 use identical mgmt words. The function @@ -95,12 +95,12 @@ static int8u determineState(void) } -int8u halCommonReadFromNvm(void *data, int32u offset, int16u length) +uint8_t halCommonReadFromNvm(void *data, uint32_t offset, uint16_t length) { - int16u i; - int16u *flash; + uint16_t i; + uint16_t *flash; //Remember: all flash writes are 16bits. - int16u *ram = (int16u*)data; + uint16_t *ram = (uint16_t*)data; //The NVM data storage system cannot function if the LEFT and RIGHT //storage are not aligned to physical flash pages. @@ -121,7 +121,7 @@ int8u halCommonReadFromNvm(void *data, int32u offset, int16u length) case 4: case 9: case 10: - flash = (int16u *)(NVM_LEFT_PAGE+offset); + flash = (uint16_t *)(NVM_LEFT_PAGE+offset); for(i=0;i<(length/2);i++) { ram[i] = flash[i]; } @@ -130,7 +130,7 @@ int8u halCommonReadFromNvm(void *data, int32u offset, int16u length) case 6: case 7: case 8: - flash = (int16u *)(NVM_RIGHT_PAGE+offset); + flash = (uint16_t *)(NVM_RIGHT_PAGE+offset); for(i=0;i<(length/2);i++) { ram[i] = flash[i]; } @@ -155,9 +155,9 @@ int8u halCommonReadFromNvm(void *data, int32u offset, int16u length) return ST_SUCCESS; } -int16u *halCommonGetAddressFromNvm(int32u offset) +uint16_t *halCommonGetAddressFromNvm(uint32_t offset) { - int16u *flash; + uint16_t *flash; //The NVM data storage system cannot function if the LEFT and RIGHT //storage are not aligned to physical flash pages. @@ -174,22 +174,22 @@ int16u *halCommonGetAddressFromNvm(int32u offset) case 4: case 9: case 10: - flash = (int16u *)(NVM_LEFT_PAGE+offset); + flash = (uint16_t *)(NVM_LEFT_PAGE+offset); break; case 5: case 6: case 7: case 8: - flash = (int16u *)(NVM_RIGHT_PAGE+offset); + flash = (uint16_t *)(NVM_RIGHT_PAGE+offset); break; case 0: default: // Flash is in an invalid state // Fix it with a dummy write and then return the flash page left { - int16u dummy = 0xFFFF; + uint16_t dummy = 0xFFFF; halCommonWriteToNvm(&dummy, 0, 2); - flash = (int16u *)(NVM_LEFT_PAGE+offset); + flash = (uint16_t *)(NVM_LEFT_PAGE+offset); } } @@ -197,12 +197,12 @@ int16u *halCommonGetAddressFromNvm(int32u offset) } -static int8u erasePage(int32u page) +static uint8_t erasePage(uint32_t page) { StStatus status; - int32u i, k; - int32u address; - int8u *flash; + uint32_t i, k; + uint32_t address; + uint8_t *flash; //Erasing a LEFT or RIGHT page requires erasing all of the flash pages. //Since the mgmt bytes are stored at the bottom of a page, the flash pages @@ -211,7 +211,7 @@ static int8u erasePage(int32u page) //words are still valid the next time determineState() is called. for(i=NVM_FLASH_PAGE_COUNT;i>0;i--) { address = (page+((i-1)*MFB_PAGE_SIZE_B)); - flash = (int8u *)address; + flash = (uint8_t *)address; //Scan the page to determine if it is fully erased already. //If the flash is not erased, erase it. The purpose of scanning //first is to save a little time if erasing is not required. @@ -248,7 +248,7 @@ static int8u erasePage(int32u page) do { \ /*Copy all data below the new data from the srcPage to the destPage*/ \ status = halInternalFlashWrite(destPage+NVM_MGMT_SIZE_B, \ - (int16u *)(srcPage+NVM_MGMT_SIZE_B), \ + (uint16_t *)(srcPage+NVM_MGMT_SIZE_B), \ (offset-NVM_MGMT_SIZE_B)/2); \ if(status != ST_SUCCESS) { return status; } \ /*Write the new data*/ \ @@ -258,7 +258,7 @@ static int8u erasePage(int32u page) if(status != ST_SUCCESS) { return status; } \ /*Copy all data above the new data from the srcPage to the destPage*/ \ status = halInternalFlashWrite(destPage+offset+length, \ - (int16u *)(srcPage+offset+length), \ + (uint16_t *)(srcPage+offset+length), \ (NVM_DATA_SIZE_B- \ length-offset- \ NVM_MGMT_SIZE_B)/2); \ @@ -269,7 +269,7 @@ static int8u erasePage(int32u page) //the proper management address. #define WRITE_MGMT_16BITS(address, data) \ do{ \ - int16u value = data; \ + uint16_t value = data; \ status = halInternalFlashWrite((address), &value, 1); \ if(status != ST_SUCCESS) { \ return status; \ @@ -277,14 +277,14 @@ static int8u erasePage(int32u page) } while(0) -int8u halCommonWriteToNvm(const void *data, int32u offset, int16u length) +uint8_t halCommonWriteToNvm(const void *data, uint32_t offset, uint16_t length) { StStatus status; - int8u state, exitState; - int32u srcPage; - int32u destPage; + uint8_t state, exitState; + uint32_t srcPage; + uint32_t destPage; //Remember: NVM data storage works on 16bit quantities. - int16u *ram = (int16u*)data; + uint16_t *ram = (uint16_t*)data; //The NVM data storage system cannot function if the LEFT and RIGHT //storage are not aligned to physical flash pages. diff --git a/cpu/stm32w108/hal/micro/cortexm3/nvm.h b/cpu/stm32w108/hal/micro/cortexm3/nvm.h index 3f0328801..a1f0e3591 100644 --- a/cpu/stm32w108/hal/micro/cortexm3/nvm.h +++ b/cpu/stm32w108/hal/micro/cortexm3/nvm.h @@ -137,7 +137,7 @@ * - Refer to nvm-def.h for a list of offset/length that define the data * stored in NVM storage space. * - All writes to flash are 16bit granularity and therefore the internal - * flash writes cast the data to int16u. Length is also required to be + * flash writes cast the data to uint16_t. Length is also required to be * a multiple of 16bits. * - Flash page erase uses a granularity of a single flash page. The size * of a flash page depends on the chip and is defined in memmap.h with @@ -198,7 +198,7 @@ * - ST_ERR_FATAL if the NVM storage management indicated an invalid * state. The function will return entirely 0xFF in the data parameter. */ -StStatus halCommonReadFromNvm(void *data, int32u offset, int16u length); +StStatus halCommonReadFromNvm(void *data, uint32_t offset, uint16_t length); /** * @brief Return the address of the token in NVM @@ -208,7 +208,7 @@ StStatus halCommonReadFromNvm(void *data, int32u offset, int16u length); * * @return The address requested */ -int16u *halCommonGetAddressFromNvm(int32u offset); +uint16_t *halCommonGetAddressFromNvm(uint32_t offset); /** * @brief Write the NVM data from the provided location RAM into flash. @@ -226,7 +226,7 @@ int16u *halCommonGetAddressFromNvm(int32u offset); * - Any other status value is an error code generated by the low level * flash erase and write API. Refer to flash.h for details. */ -StStatus halCommonWriteToNvm(const void *data, int32u offset, int16u length); +StStatus halCommonWriteToNvm(const void *data, uint32_t offset, uint16_t length); /** * @brief Define the number of physical flash pages that comprise a NVM page. @@ -256,14 +256,14 @@ StStatus halCommonWriteToNvm(const void *data, int32u offset, int16u length); * is defined by nvmStorageLeft[NVM_DATA_SIZE_B] and placed by the linker * using the segment "NVM". */ -#define NVM_LEFT_PAGE ((int32u)nvmStorageLeft) +#define NVM_LEFT_PAGE ((uint32_t)nvmStorageLeft) /** * @brief Define the absolute address of the RIGHT page. RIGHT page storage * is defined by nvmStorageRight[NVM_DATA_SIZE_B] and placed by the linker * using the segment "NVM". */ -#define NVM_RIGHT_PAGE ((int32u)nvmStorageRight) +#define NVM_RIGHT_PAGE ((uint32_t)nvmStorageRight) /** * @brief Define the number of bytes that comprise the NVM management bytes. diff --git a/cpu/stm32w108/hal/micro/cortexm3/sleep.c b/cpu/stm32w108/hal/micro/cortexm3/sleep.c index 4d6dd9f0f..ece156cb4 100644 --- a/cpu/stm32w108/hal/micro/cortexm3/sleep.c +++ b/cpu/stm32w108/hal/micro/cortexm3/sleep.c @@ -117,9 +117,9 @@ //place in the halInternalWakeEvent variable #define INTERNAL_WAKE_EVENT_BIT_SHIFT 20 -static int32u halInternalWakeEvent=0; +static uint32_t halInternalWakeEvent=0; -int32u halGetWakeInfo(void) +uint32_t halGetWakeInfo(void) { return halInternalWakeEvent; } @@ -129,7 +129,7 @@ void halInternalSleep(SleepModes sleepMode) //Timer restoring always takes place during the wakeup sequence. We save //the state here in case SLEEPMODE_NOTIMER is invoked, which would disable //the clocks. - int32u SLEEPTMR_CLKEN_SAVED = SLEEPTMR_CLKEN; + uint32_t SLEEPTMR_CLKEN_SAVED = SLEEPTMR_CLKEN; //This code assumes all wake source registers are properly configured. //As such, it should be called from halSleepWithOptions() or from @@ -138,7 +138,7 @@ void halInternalSleep(SleepModes sleepMode) //The parameter gpioWakeSel is a bitfield composite of the GPIO wake //sources derived from the 3 ports, indicating which of the 24 GPIO //are configured as a wake source. - int32u gpioWakeSel = (GPIO_PAWAKE<<0); + uint32_t gpioWakeSel = (GPIO_PAWAKE<<0); gpioWakeSel |= (GPIO_PBWAKE<<8); gpioWakeSel |= (GPIO_PCWAKE<<16); @@ -248,38 +248,38 @@ deepSleepCore: //MAC_TIMER_INT_MASK - reinitialized by stStackPowerUp() //BB_INT_MASK - reinitialized by stStackPowerUp() //SEC_INT_MASK - reinitialized by stStackPowerUp() - int32u INT_SLEEPTMRCFG_SAVED = INT_SLEEPTMRCFG_REG; - int32u INT_MGMTCFG_SAVED = INT_MGMTCFG_REG; + uint32_t INT_SLEEPTMRCFG_SAVED = INT_SLEEPTMRCFG_REG; + uint32_t INT_MGMTCFG_SAVED = INT_MGMTCFG_REG; //INT_TIM1CFG - reinitialized by halPowerUp() or similar //INT_TIM2CFG - reinitialized by halPowerUp() or similar //INT_SC1CFG - reinitialized by halPowerUp() or similar //INT_SC2CFG - reinitialized by halPowerUp() or similar //INT_ADCCFG - reinitialized by halPowerUp() or similar - int32u GPIO_INTCFGA_SAVED = GPIO_INTCFGA_REG; - int32u GPIO_INTCFGB_SAVED = GPIO_INTCFGB_REG; - int32u GPIO_INTCFGC_SAVED = GPIO_INTCFGC_REG; - int32u GPIO_INTCFGD_SAVED = GPIO_INTCFGD_REG; + uint32_t GPIO_INTCFGA_SAVED = GPIO_INTCFGA_REG; + uint32_t GPIO_INTCFGB_SAVED = GPIO_INTCFGB_REG; + uint32_t GPIO_INTCFGC_SAVED = GPIO_INTCFGC_REG; + uint32_t GPIO_INTCFGD_SAVED = GPIO_INTCFGD_REG; //SC1_INTMODE - reinitialized by halPowerUp() or similar //SC2_INTMODE - reinitialized by halPowerUp() or similar //----CM_LV - int32u OSC24M_BIASTRIM_SAVED = OSC24M_BIASTRIM_REG; - int32u OSCHF_TUNE_SAVED = OSCHF_TUNE_REG; - int32u DITHER_DIS_SAVED = DITHER_DIS_REG; + uint32_t OSC24M_BIASTRIM_SAVED = OSC24M_BIASTRIM_REG; + uint32_t OSCHF_TUNE_SAVED = OSCHF_TUNE_REG; + uint32_t DITHER_DIS_SAVED = DITHER_DIS_REG; //OSC24M_CTRL - reinitialized by halPowerUp() or similar //CPU_CLKSEL - reinitialized by halPowerUp() or similar //TMR1_CLK_SEL - reinitialized by halPowerUp() or similar //TMR2_CLK_SEL - reinitialized by halPowerUp() or similar - int32u PCTRACE_SEL_SAVED = PCTRACE_SEL_REG; + uint32_t PCTRACE_SEL_SAVED = PCTRACE_SEL_REG; //----RAM_CTRL - int32u MEM_PROT_0_SAVED = MEM_PROT_0_REG; - int32u MEM_PROT_1_SAVED = MEM_PROT_1_REG; - int32u MEM_PROT_2_SAVED = MEM_PROT_2_REG; - int32u MEM_PROT_3_SAVED = MEM_PROT_3_REG; - int32u MEM_PROT_4_SAVED = MEM_PROT_4_REG; - int32u MEM_PROT_5_SAVED = MEM_PROT_5_REG; - int32u MEM_PROT_6_SAVED = MEM_PROT_6_REG; - int32u MEM_PROT_7_SAVED = MEM_PROT_7_REG; - int32u MEM_PROT_EN_SAVED = MEM_PROT_EN_REG; + uint32_t MEM_PROT_0_SAVED = MEM_PROT_0_REG; + uint32_t MEM_PROT_1_SAVED = MEM_PROT_1_REG; + uint32_t MEM_PROT_2_SAVED = MEM_PROT_2_REG; + uint32_t MEM_PROT_3_SAVED = MEM_PROT_3_REG; + uint32_t MEM_PROT_4_SAVED = MEM_PROT_4_REG; + uint32_t MEM_PROT_5_SAVED = MEM_PROT_5_REG; + uint32_t MEM_PROT_6_SAVED = MEM_PROT_6_REG; + uint32_t MEM_PROT_7_SAVED = MEM_PROT_7_REG; + uint32_t MEM_PROT_EN_SAVED = MEM_PROT_EN_REG; //----AUX_ADC // reinitialized by halPowerUp() or similar //----CAL_ADC @@ -295,14 +295,14 @@ deepSleepCore: //----NVIC //ST_CSR - fixed, restored by cstartup when exiting deep sleep //ST_RVR - fixed, restored by cstartup when exiting deep sleep - int32u INT_CFGSET_SAVED = INT_CFGSET_REG; //mask against wake sources + uint32_t INT_CFGSET_SAVED = INT_CFGSET_REG; //mask against wake sources //INT_PENDSET - used below when overlapping interrupts and wake sources //NVIC_IPR_3to0 - fixed, restored by cstartup when exiting deep sleep //NVIC_IPR_7to4 - fixed, restored by cstartup when exiting deep sleep //NVIC_IPR_11to8 - fixed, restored by cstartup when exiting deep sleep //NVIC_IPR_15to12 - fixed, restored by cstartup when exiting deep sleep //NVIC_IPR_19to16 - fixed, restored by cstartup when exiting deep sleep - int32u SCS_VTOR_SAVED = SCS_VTOR_REG; + uint32_t SCS_VTOR_SAVED = SCS_VTOR_REG; //SCS_CCR - fixed, restored by cstartup when exiting deep sleep //SCS_SHPR_7to4 - fixed, restored by cstartup when exiting deep sleep //SCS_SHPR_11to8 - fixed, restored by cstartup when exiting deep sleep @@ -320,7 +320,7 @@ deepSleepCore: //up exactly which GPIO could have woken us up. //Reading the three IN registers is done separately to avoid warnings //about undefined order of volatile access. - int32u GPIO_IN_SAVED = GPIO_PAIN; + uint32_t GPIO_IN_SAVED = GPIO_PAIN; GPIO_IN_SAVED |= (GPIO_PBIN<<8); GPIO_IN_SAVED |= (GPIO_PCIN<<16); //reset the power up events by writing 1 to all bits. @@ -425,7 +425,7 @@ deepSleepCore: //only propagate across deep sleep the interrupts that are both //enabled and possible wake sources { - int32u wakeSourceInterruptMask = 0; + uint32_t wakeSourceInterruptMask = 0; if(GPIO_PBWAKE&PB0) { wakeSourceInterruptMask |= INT_IRQA; @@ -513,7 +513,7 @@ deepSleepCore: { //Use a local copy of WAKE_SEL to avoid warnings from the compiler //about order of volatile accesses - int32u wakeSel = WAKE_SEL; + uint32_t wakeSel = WAKE_SEL; //stall until a wake event or CSYSPWRUPREQ/ACK clears while( (CSYSPWRUPACK_STATUS) && (!(PWRUP_EVENT&wakeSel)) ) {} //if there was a wake event, allow CSYSPWRUPACK and skip sleep @@ -630,14 +630,14 @@ deepSleepCore: //Now that we're awake, normal interrupts are operational again //Take a snapshot of the new GPIO state and the EVENT register to //record our wake event - int32u GPIO_IN_NEW = GPIO_PAIN; + uint32_t GPIO_IN_NEW = GPIO_PAIN; GPIO_IN_NEW |= (GPIO_PBIN<<8); GPIO_IN_NEW |= (GPIO_PCIN<<16); //Only operate on power up events that are also wake events. Power //up events will always trigger like an interrupt flag, so we have //to check them against events that are enabled for waking. (This is //a two step process because we're accessing two volatile values.) - int32u powerUpEvents = PWRUP_EVENT; + uint32_t powerUpEvents = PWRUP_EVENT; powerUpEvents &= WAKE_SEL; halInternalWakeEvent |= ((GPIO_IN_SAVED^GPIO_IN_NEW)&gpioWakeSel); //PWRUP_SC1 is PB2 which is bit 10 @@ -845,7 +845,7 @@ deepSleepCore: } -void halSleepWithOptions(SleepModes sleepMode, int32u gpioWakeBitMask) +void halSleepWithOptions(SleepModes sleepMode, uint32_t gpioWakeBitMask) { //configure all GPIO wake sources GPIO_PAWAKE = (gpioWakeBitMask>>0)&0xFF; diff --git a/cpu/stm32w108/hal/micro/cortexm3/spmr.s79 b/cpu/stm32w108/hal/micro/cortexm3/spmr.s79 index 76360196c..7969b2e2e 100644 --- a/cpu/stm32w108/hal/micro/cortexm3/spmr.s79 +++ b/cpu/stm32w108/hal/micro/cortexm3/spmr.s79 @@ -35,7 +35,7 @@ __EXPORT__ _executeBarrierInstructions //------------------------------------------------------------------------------ -// int8u _readBasePri(void) +// uint8_t _readBasePri(void) // // Read and return the BASEPRI value. // @@ -50,7 +50,7 @@ _readBasePri: __CFI__(EndBlock cfiBlock0) //------------------------------------------------------------------------------ -// void _writeBasePri(int8u priority) +// void _writeBasePri(uint8_t priority) // // Write BASEPRI with the passed value to obtain the proper preemptive priority // group masking. Note that the value passed must have been left shifted by 3 @@ -68,7 +68,7 @@ _writeBasePri: __CFI__(EndBlock cfiBlock1) //------------------------------------------------------------------------------ -// int8u _disableBasePri(void) +// uint8_t _disableBasePri(void) // // Set BASEPRI to mask out interrupts but allow faults. It returns the value // BASEPRI had when it was called. diff --git a/cpu/stm32w108/hal/micro/cortexm3/stm32w108/board.h b/cpu/stm32w108/hal/micro/cortexm3/stm32w108/board.h index decca640f..aaf9de78d 100644 --- a/cpu/stm32w108/hal/micro/cortexm3/stm32w108/board.h +++ b/cpu/stm32w108/hal/micro/cortexm3/stm32w108/board.h @@ -84,9 +84,9 @@ typedef struct LedResourceStruct { /** Name of the LED as printed in the board */ char *name; /** GPIO port associated with the LED */ - int8u gpioPort; + uint8_t gpioPort; /** GPIO pin associated with the LED */ - int8u gpioPin; + uint8_t gpioPin; } LedResourceType; typedef LedResourceType InfraRedLedResourceType; @@ -98,9 +98,9 @@ typedef struct ButtonResourceStruct { /** Name of the button as printed in the board */ char *name; /** GPIO port associated with the button */ - int8u gpioPort; + uint8_t gpioPort; /** GPIO pin associated with the button */ - int8u gpioPin; + uint8_t gpioPin; } ButtonResourceType; /** @@ -110,7 +110,7 @@ typedef struct MemsResourceStruct { /** Name of the MEMS device */ char *name; /** Serial communication port associated with the MEMS */ - int8u scPort; + uint8_t scPort; } MemsResourceType; /** @@ -120,9 +120,9 @@ typedef struct TempSensorResourceStruct { /** Name of the temperature sensor device */ char *name; /** GPIO port associated with the sensor */ - int8u gpioPort; + uint8_t gpioPort; /** GPIO pin associated with the sensor */ - int8u gpioPin; + uint8_t gpioPin; /** Flag to indicate whether the ADC range extension bug fix is implemented */ boolean adcFix; } TempSensorResourceType; @@ -167,11 +167,11 @@ typedef struct BoardIOStruct { */ typedef struct BoardResourcesStruct { const char *name; - const int32u flags; + const uint32_t flags; /** Number of buttons */ - int8u buttons; + uint8_t buttons; /** Number of leds */ - int8u leds; + uint8_t leds; /** Board I/O description */ const BoardIOType *io; /** Board infrared led description */ @@ -202,7 +202,7 @@ extern BoardResourcesType const *boardDescription; /** Description buttons definition */ #define BUTTON_Sn(n) (PORTx_PIN(boardDescription->io->buttons[n].gpioPort, boardDescription->io->buttons[n].gpioPin)) #define BUTTON_Sn_WAKE_SOURCE(n) (1 << ((boardDescription->io->buttons[n].gpioPin) + (8 * (boardDescription->io->buttons[n].gpioPort >> 3)))) -#define BUTTON_INPUT_GPIO(port) *((volatile int32u *) (GPIO_PxIN_BASE + GPIO_Px_OFFSET * port)) +#define BUTTON_INPUT_GPIO(port) *((volatile uint32_t *) (GPIO_PxIN_BASE + GPIO_Px_OFFSET * port)) #define DUMMY_BUTTON 0xff #define BUTTON_S1 (boardDescription->buttons>0 ? BUTTON_Sn(0): DUMMY_BUTTON) diff --git a/cpu/stm32w108/hal/micro/cortexm3/stm32w108/crt_stm32w108.c b/cpu/stm32w108/hal/micro/cortexm3/stm32w108/crt-stm32w108.c similarity index 96% rename from cpu/stm32w108/hal/micro/cortexm3/stm32w108/crt_stm32w108.c rename to cpu/stm32w108/hal/micro/cortexm3/stm32w108/crt-stm32w108.c index f54d14803..a41820ec2 100644 --- a/cpu/stm32w108/hal/micro/cortexm3/stm32w108/crt_stm32w108.c +++ b/cpu/stm32w108/hal/micro/cortexm3/stm32w108/crt-stm32w108.c @@ -139,8 +139,8 @@ void (* const g_pfnVectors[])(void) = halDebugIsr, // 32 }; -static void setStackPointer(int32u address) __attribute__((noinline)); -static void setStackPointer(int32u address) +static void setStackPointer(uint32_t address) __attribute__((noinline)); +static void setStackPointer(uint32_t address) { // This code is needed to generate the instruction below // that GNU ASM is refusing to add @@ -148,7 +148,7 @@ static void setStackPointer(int32u address) asm(".short 0x4685"); } -static const int16u blOffset[] = { +static const uint16_t blOffset[] = { 0x0715 - 0x03ad - 0x68, 0x0719 - 0x03ad - 0x6C }; @@ -277,17 +277,17 @@ void Reset_Handler(void) } //USART bootloader software activation check - if ((*((int32u *)RAM_BOTTOM) == IAP_BOOTLOADER_APP_SWITCH_SIGNATURE) && (*((int8u *)(RAM_BOTTOM+4)) == IAP_BOOTLOADER_MODE_UART)){ - int8u cut = *(volatile int8u *) 0x08040798; - int16u offset = 0; + if ((*((uint32_t *)RAM_BOTTOM) == IAP_BOOTLOADER_APP_SWITCH_SIGNATURE) && (*((uint8_t *)(RAM_BOTTOM+4)) == IAP_BOOTLOADER_MODE_UART)){ + uint8_t cut = *(volatile uint8_t *) 0x08040798; + uint16_t offset = 0; typedef void (*EntryPoint)(void); offset = (halFixedAddressTable.baseTable.version == 3) ? blOffset[cut - 2] : 0; - *((int32u *)RAM_BOTTOM) = 0; + *((uint32_t *)RAM_BOTTOM) = 0; if (offset) { halInternalSwitchToXtal(); } - EntryPoint entryPoint = (EntryPoint)(*(int32u *)(FIB_BOTTOM+4) - offset); - setStackPointer(*(int32u *)FIB_BOTTOM); + EntryPoint entryPoint = (EntryPoint)(*(uint32_t *)(FIB_BOTTOM+4) - offset); + setStackPointer(*(uint32_t *)FIB_BOTTOM); entryPoint(); } diff --git a/cpu/stm32w108/hal/micro/cortexm3/stm32w108/low_level_init.c b/cpu/stm32w108/hal/micro/cortexm3/stm32w108/low-level-init.c similarity index 94% rename from cpu/stm32w108/hal/micro/cortexm3/stm32w108/low_level_init.c rename to cpu/stm32w108/hal/micro/cortexm3/stm32w108/low-level-init.c index 790ef608e..3903a4985 100644 --- a/cpu/stm32w108/hal/micro/cortexm3/stm32w108/low_level_init.c +++ b/cpu/stm32w108/hal/micro/cortexm3/stm32w108/low-level-init.c @@ -38,12 +38,12 @@ extern void halInternalSwitchToXtal(void); __interwork int __low_level_init(void); -static void setStackPointer(int32u address) +static void setStackPointer(uint32_t address) { asm("MOVS SP, r0"); } -static const int16u blOffset[] = { +static const uint16_t blOffset[] = { 0x0715 - 0x03ad - 0x68, 0x0719 - 0x03ad - 0x6C }; @@ -79,7 +79,7 @@ __interwork int __low_level_init(void) ////---- Always remap the vector table ----//// // We might be coming from a bootloader at the base of flash, or even in the // NULL_BTL case, the BAT/AAT will be at the beginning of the image - SCS_VTOR = (int32u)__vector_table; + SCS_VTOR = (uint32_t)__vector_table; ////---- Always Configure Interrupt Priorities ----//// //The STM32W support 5 bits of priority configuration. @@ -169,17 +169,17 @@ __interwork int __low_level_init(void) } //USART bootloader software activation check - if ((*((int32u *)RAM_BOTTOM) == IAP_BOOTLOADER_APP_SWITCH_SIGNATURE) && (*((int8u *)(RAM_BOTTOM+4)) == IAP_BOOTLOADER_MODE_UART)){ - int8u cut = *(volatile int8u *) 0x08040798; - int16u offset = 0; + if ((*((uint32_t *)RAM_BOTTOM) == IAP_BOOTLOADER_APP_SWITCH_SIGNATURE) && (*((uint8_t *)(RAM_BOTTOM+4)) == IAP_BOOTLOADER_MODE_UART)){ + uint8_t cut = *(volatile uint8_t *) 0x08040798; + uint16_t offset = 0; typedef void (*EntryPoint)(void); offset = (halFixedAddressTable.baseTable.version == 3) ? blOffset[cut - 2] : 0; - *((int32u *)RAM_BOTTOM) = 0; + *((uint32_t *)RAM_BOTTOM) = 0; if (offset) { halInternalSwitchToXtal(); } - EntryPoint entryPoint = (EntryPoint)(*(int32u *)(FIB_BOTTOM+4) - offset); - setStackPointer(*(int32u *)FIB_BOTTOM); + EntryPoint entryPoint = (EntryPoint)(*(uint32_t *)(FIB_BOTTOM+4) - offset); + setStackPointer(*(uint32_t *)FIB_BOTTOM); entryPoint(); } diff --git a/cpu/stm32w108/hal/micro/cortexm3/stm32w108/memmap.h b/cpu/stm32w108/hal/micro/cortexm3/stm32w108/memmap.h index f54cd3dd6..171eea204 100644 --- a/cpu/stm32w108/hal/micro/cortexm3/stm32w108/memmap.h +++ b/cpu/stm32w108/hal/micro/cortexm3/stm32w108/memmap.h @@ -46,12 +46,12 @@ #define FPEC_KEY2 0xCDEF89AB //magic key defined in hardware //Translation between page number and simee (word based) address -#define SIMEE_ADDR_TO_PAGE(x) ((int8u)(((int16u)(x)) >> 9)) -#define PAGE_TO_SIMEE_ADDR(x) (((int16u)(x)) << 9) +#define SIMEE_ADDR_TO_PAGE(x) ((uint8_t)(((uint16_t)(x)) >> 9)) +#define PAGE_TO_SIMEE_ADDR(x) (((uint16_t)(x)) << 9) //Translation between page number and code addresses, used by bootloaders -#define PROG_ADDR_TO_PAGE(x) ((int8u)((((int32u)(x))&MFB_ADDR_MASK) >> 10)) -#define PAGE_TO_PROG_ADDR(x) ((((int32u)(x)) << 10)|MFB_BOTTOM) +#define PROG_ADDR_TO_PAGE(x) ((uint8_t)((((uint32_t)(x))&MFB_ADDR_MASK) >> 10)) +#define PAGE_TO_PROG_ADDR(x) ((((uint32_t)(x)) << 10)|MFB_BOTTOM) #endif //__STM32W108_MEMMAP_H__ diff --git a/cpu/stm32w108/hal/micro/cortexm3/stm32w108/regs.h b/cpu/stm32w108/hal/micro/cortexm3/stm32w108/regs.h index aa0572be2..aab30182a 100644 --- a/cpu/stm32w108/hal/micro/cortexm3/stm32w108/regs.h +++ b/cpu/stm32w108/hal/micro/cortexm3/stm32w108/regs.h @@ -40,8 +40,8 @@ #define DATA_CM_HV_END (0x40000044u) #define DATA_CM_HV_SIZE (DATA_CM_HV_END - DATA_CM_HV_BASE + 1) -#define HV_SPARE *((volatile int32u *)0x40000000u) -#define HV_SPARE_REG *((volatile int32u *)0x40000000u) +#define HV_SPARE *((volatile uint32_t *)0x40000000u) +#define HV_SPARE_REG *((volatile uint32_t *)0x40000000u) #define HV_SPARE_ADDR (0x40000000u) #define HV_SPARE_RESET (0x00000000u) /* HV_SPARE field */ @@ -50,8 +50,8 @@ #define HV_SPARE_HV_SPARE_BIT (0) #define HV_SPARE_HV_SPARE_BITS (8) -#define EVENT_CTRL *((volatile int32u *)0x40000004u) -#define EVENT_CTRL_REG *((volatile int32u *)0x40000004u) +#define EVENT_CTRL *((volatile uint32_t *)0x40000004u) +#define EVENT_CTRL_REG *((volatile uint32_t *)0x40000004u) #define EVENT_CTRL_ADDR (0x40000004u) #define EVENT_CTRL_RESET (0x00000000u) /* LV_FREEZE field */ @@ -60,8 +60,8 @@ #define LV_FREEZE_BIT (1) #define LV_FREEZE_BITS (1) -#define SLEEPTMR_CLKEN *((volatile int32u *)0x40000008u) -#define SLEEPTMR_CLKEN_REG *((volatile int32u *)0x40000008u) +#define SLEEPTMR_CLKEN *((volatile uint32_t *)0x40000008u) +#define SLEEPTMR_CLKEN_REG *((volatile uint32_t *)0x40000008u) #define SLEEPTMR_CLKEN_ADDR (0x40000008u) #define SLEEPTMR_CLKEN_RESET (0x00000002u) /* SLEEPTMR_CLK10KEN field */ @@ -75,8 +75,8 @@ #define SLEEPTMR_CLK32KEN_BIT (0) #define SLEEPTMR_CLK32KEN_BITS (1) -#define CLKRC_TUNE *((volatile int32u *)0x4000000Cu) -#define CLKRC_TUNE_REG *((volatile int32u *)0x4000000Cu) +#define CLKRC_TUNE *((volatile uint32_t *)0x4000000Cu) +#define CLKRC_TUNE_REG *((volatile uint32_t *)0x4000000Cu) #define CLKRC_TUNE_ADDR (0x4000000Cu) #define CLKRC_TUNE_RESET (0x00000000u) /* CLKRC_TUNE_FIELD field */ @@ -85,8 +85,8 @@ #define CLKRC_TUNE_FIELD_BIT (0) #define CLKRC_TUNE_FIELD_BITS (4) -#define CLK1K_CAL *((volatile int32u *)0x40000010u) -#define CLK1K_CAL_REG *((volatile int32u *)0x40000010u) +#define CLK1K_CAL *((volatile uint32_t *)0x40000010u) +#define CLK1K_CAL_REG *((volatile uint32_t *)0x40000010u) #define CLK1K_CAL_ADDR (0x40000010u) #define CLK1K_CAL_RESET (0x00005000u) /* CLK1K_INTEGER field */ @@ -100,8 +100,8 @@ #define CLK1K_FRACTIONAL_BIT (0) #define CLK1K_FRACTIONAL_BITS (11) -#define REGEN_DSLEEP *((volatile int32u *)0x40000014u) -#define REGEN_DSLEEP_REG *((volatile int32u *)0x40000014u) +#define REGEN_DSLEEP *((volatile uint32_t *)0x40000014u) +#define REGEN_DSLEEP_REG *((volatile uint32_t *)0x40000014u) #define REGEN_DSLEEP_ADDR (0x40000014u) #define REGEN_DSLEEP_RESET (0x00000001u) /* REGEN_DSLEEP_FIELD field */ @@ -110,8 +110,8 @@ #define REGEN_DSLEEP_FIELD_BIT (0) #define REGEN_DSLEEP_FIELD_BITS (1) -#define VREG *((volatile int32u *)0x40000018u) -#define VREG_REG *((volatile int32u *)0x40000018u) +#define VREG *((volatile uint32_t *)0x40000018u) +#define VREG_REG *((volatile uint32_t *)0x40000018u) #define VREG_ADDR (0x40000018u) #define VREG_RESET (0x00000207u) /* VREF_EN field */ @@ -155,8 +155,8 @@ #define VREG_VREG_1V2_TRIM_BIT (0) #define VREG_VREG_1V2_TRIM_BITS (3) -#define WAKE_SEL *((volatile int32u *)0x40000020u) -#define WAKE_SEL_REG *((volatile int32u *)0x40000020u) +#define WAKE_SEL *((volatile uint32_t *)0x40000020u) +#define WAKE_SEL_REG *((volatile uint32_t *)0x40000020u) #define WAKE_SEL_ADDR (0x40000020u) #define WAKE_SEL_RESET (0x00000200u) /* WAKE_CSYSPWRUPREQ field */ @@ -210,8 +210,8 @@ #define GPIO_WAKE_BIT (0) #define GPIO_WAKE_BITS (1) -#define WAKE_CORE *((volatile int32u *)0x40000024u) -#define WAKE_CORE_REG *((volatile int32u *)0x40000024u) +#define WAKE_CORE *((volatile uint32_t *)0x40000024u) +#define WAKE_CORE_REG *((volatile uint32_t *)0x40000024u) #define WAKE_CORE_ADDR (0x40000024u) #define WAKE_CORE_RESET (0x00000000u) /* WAKE_CORE_FIELD field */ @@ -220,8 +220,8 @@ #define WAKE_CORE_FIELD_BIT (5) #define WAKE_CORE_FIELD_BITS (1) -#define PWRUP_EVENT *((volatile int32u *)0x40000028u) -#define PWRUP_EVENT_REG *((volatile int32u *)0x40000028u) +#define PWRUP_EVENT *((volatile uint32_t *)0x40000028u) +#define PWRUP_EVENT_REG *((volatile uint32_t *)0x40000028u) #define PWRUP_EVENT_ADDR (0x40000028u) #define PWRUP_EVENT_RESET (0x00000000u) /* PWRUP_CSYSPWRUPREQ field */ @@ -275,8 +275,8 @@ #define PWRUP_GPIO_BIT (0) #define PWRUP_GPIO_BITS (1) -#define RESET_EVENT *((volatile int32u *)0x4000002Cu) -#define RESET_EVENT_REG *((volatile int32u *)0x4000002Cu) +#define RESET_EVENT *((volatile uint32_t *)0x4000002Cu) +#define RESET_EVENT_REG *((volatile uint32_t *)0x4000002Cu) #define RESET_EVENT_ADDR (0x4000002Cu) #define RESET_EVENT_RESET (0x00000001u) /* RESET_CPULOCKUP field */ @@ -320,8 +320,8 @@ #define RESET_PWRHV_BIT (0) #define RESET_PWRHV_BITS (1) -#define DBG_MBOX *((volatile int32u *)0x40000030u) -#define DBG_MBOX_REG *((volatile int32u *)0x40000030u) +#define DBG_MBOX *((volatile uint32_t *)0x40000030u) +#define DBG_MBOX_REG *((volatile uint32_t *)0x40000030u) #define DBG_MBOX_ADDR (0x40000030u) #define DBG_MBOX_RESET (0x00000000u) /* DBG_MBOX field */ @@ -330,8 +330,8 @@ #define DBG_MBOX_DBG_MBOX_BIT (0) #define DBG_MBOX_DBG_MBOX_BITS (16) -#define CPWRUPREQ_STATUS *((volatile int32u *)0x40000034u) -#define CPWRUPREQ_STATUS_REG *((volatile int32u *)0x40000034u) +#define CPWRUPREQ_STATUS *((volatile uint32_t *)0x40000034u) +#define CPWRUPREQ_STATUS_REG *((volatile uint32_t *)0x40000034u) #define CPWRUPREQ_STATUS_ADDR (0x40000034u) #define CPWRUPREQ_STATUS_RESET (0x00000000u) /* CPWRUPREQ field */ @@ -340,8 +340,8 @@ #define CPWRUPREQ_STATUS_CPWRUPREQ_BIT (0) #define CPWRUPREQ_STATUS_CPWRUPREQ_BITS (1) -#define CSYSPWRUPREQ_STATUS *((volatile int32u *)0x40000038u) -#define CSYSPWRUPREQ_STATUS_REG *((volatile int32u *)0x40000038u) +#define CSYSPWRUPREQ_STATUS *((volatile uint32_t *)0x40000038u) +#define CSYSPWRUPREQ_STATUS_REG *((volatile uint32_t *)0x40000038u) #define CSYSPWRUPREQ_STATUS_ADDR (0x40000038u) #define CSYSPWRUPREQ_STATUS_RESET (0x00000000u) /* CSYSPWRUPREQ field */ @@ -350,8 +350,8 @@ #define CSYSPWRUPREQ_STATUS_CSYSPWRUPREQ_BIT (0) #define CSYSPWRUPREQ_STATUS_CSYSPWRUPREQ_BITS (1) -#define CSYSPWRUPACK_STATUS *((volatile int32u *)0x4000003Cu) -#define CSYSPWRUPACK_STATUS_REG *((volatile int32u *)0x4000003Cu) +#define CSYSPWRUPACK_STATUS *((volatile uint32_t *)0x4000003Cu) +#define CSYSPWRUPACK_STATUS_REG *((volatile uint32_t *)0x4000003Cu) #define CSYSPWRUPACK_STATUS_ADDR (0x4000003Cu) #define CSYSPWRUPACK_STATUS_RESET (0x00000000u) /* CSYSPWRUPACK field */ @@ -360,8 +360,8 @@ #define CSYSPWRUPACK_STATUS_CSYSPWRUPACK_BIT (0) #define CSYSPWRUPACK_STATUS_CSYSPWRUPACK_BITS (1) -#define CSYSPWRUPACK_INHIBIT *((volatile int32u *)0x40000040u) -#define CSYSPWRUPACK_INHIBIT_REG *((volatile int32u *)0x40000040u) +#define CSYSPWRUPACK_INHIBIT *((volatile uint32_t *)0x40000040u) +#define CSYSPWRUPACK_INHIBIT_REG *((volatile uint32_t *)0x40000040u) #define CSYSPWRUPACK_INHIBIT_ADDR (0x40000040u) #define CSYSPWRUPACK_INHIBIT_RESET (0x00000000u) /* CSYSPWRUPACK_INHIBIT field */ @@ -370,8 +370,8 @@ #define CSYSPWRUPACK_INHIBIT_CSYSPWRUPACK_INHIBIT_BIT (0) #define CSYSPWRUPACK_INHIBIT_CSYSPWRUPACK_INHIBIT_BITS (1) -#define OPT_ERR_MAINTAIN_WAKE *((volatile int32u *)0x40000044u) -#define OPT_ERR_MAINTAIN_WAKE_REG *((volatile int32u *)0x40000044u) +#define OPT_ERR_MAINTAIN_WAKE *((volatile uint32_t *)0x40000044u) +#define OPT_ERR_MAINTAIN_WAKE_REG *((volatile uint32_t *)0x40000044u) #define OPT_ERR_MAINTAIN_WAKE_ADDR (0x40000044u) #define OPT_ERR_MAINTAIN_WAKE_RESET (0x00000000u) /* OPT_ERR_MAINTAIN_WAKE field */ @@ -385,8 +385,8 @@ #define DATA_BASEBAND_END (0x40001114u) #define DATA_BASEBAND_SIZE (DATA_BASEBAND_END - DATA_BASEBAND_BASE + 1) -#define MOD_CAL_CTRL *((volatile int32u *)0x40001000u) -#define MOD_CAL_CTRL_REG *((volatile int32u *)0x40001000u) +#define MOD_CAL_CTRL *((volatile uint32_t *)0x40001000u) +#define MOD_CAL_CTRL_REG *((volatile uint32_t *)0x40001000u) #define MOD_CAL_CTRL_ADDR (0x40001000u) #define MOD_CAL_CTRL_RESET (0x00000000u) /* MOD_CAL_GO field */ @@ -405,8 +405,8 @@ #define MOD_CAL_CTRL_MOD_CAL_CYCLES_BIT (0) #define MOD_CAL_CTRL_MOD_CAL_CYCLES_BITS (2) -#define MOD_CAL_COUNT_H *((volatile int32u *)0x40001004u) -#define MOD_CAL_COUNT_H_REG *((volatile int32u *)0x40001004u) +#define MOD_CAL_COUNT_H *((volatile uint32_t *)0x40001004u) +#define MOD_CAL_COUNT_H_REG *((volatile uint32_t *)0x40001004u) #define MOD_CAL_COUNT_H_ADDR (0x40001004u) #define MOD_CAL_COUNT_H_RESET (0x00000000u) /* MOD_CAL_COUNT_H field */ @@ -415,8 +415,8 @@ #define MOD_CAL_COUNT_H_MOD_CAL_COUNT_H_BIT (0) #define MOD_CAL_COUNT_H_MOD_CAL_COUNT_H_BITS (8) -#define MOD_CAL_COUNT_L *((volatile int32u *)0x40001008u) -#define MOD_CAL_COUNT_L_REG *((volatile int32u *)0x40001008u) +#define MOD_CAL_COUNT_L *((volatile uint32_t *)0x40001008u) +#define MOD_CAL_COUNT_L_REG *((volatile uint32_t *)0x40001008u) #define MOD_CAL_COUNT_L_ADDR (0x40001008u) #define MOD_CAL_COUNT_L_RESET (0x00000000u) /* MOD_CAL_COUNT_L field */ @@ -425,8 +425,8 @@ #define MOD_CAL_COUNT_L_MOD_CAL_COUNT_L_BIT (0) #define MOD_CAL_COUNT_L_MOD_CAL_COUNT_L_BITS (16) -#define RSSI_ROLLING *((volatile int32u *)0x4000100Cu) -#define RSSI_ROLLING_REG *((volatile int32u *)0x4000100Cu) +#define RSSI_ROLLING *((volatile uint32_t *)0x4000100Cu) +#define RSSI_ROLLING_REG *((volatile uint32_t *)0x4000100Cu) #define RSSI_ROLLING_ADDR (0x4000100Cu) #define RSSI_ROLLING_RESET (0x00000000u) /* RSSI_ROLLING field */ @@ -435,8 +435,8 @@ #define RSSI_ROLLING_RSSI_ROLLING_BIT (0) #define RSSI_ROLLING_RSSI_ROLLING_BITS (14) -#define RSSI_PKT *((volatile int32u *)0x40001010u) -#define RSSI_PKT_REG *((volatile int32u *)0x40001010u) +#define RSSI_PKT *((volatile uint32_t *)0x40001010u) +#define RSSI_PKT_REG *((volatile uint32_t *)0x40001010u) #define RSSI_PKT_ADDR (0x40001010u) #define RSSI_PKT_RESET (0x00000000u) /* RSSI_PKT field */ @@ -445,8 +445,8 @@ #define RSSI_PKT_RSSI_PKT_BIT (0) #define RSSI_PKT_RSSI_PKT_BITS (8) -#define RX_ADC *((volatile int32u *)0x40001014u) -#define RX_ADC_REG *((volatile int32u *)0x40001014u) +#define RX_ADC *((volatile uint32_t *)0x40001014u) +#define RX_ADC_REG *((volatile uint32_t *)0x40001014u) #define RX_ADC_ADDR (0x40001014u) #define RX_ADC_RESET (0x00000024u) /* RX_ADC field */ @@ -455,8 +455,8 @@ #define RX_ADC_RX_ADC_BIT (0) #define RX_ADC_RX_ADC_BITS (7) -#define DEBUG_BB_MODE *((volatile int32u *)0x40001018u) -#define DEBUG_BB_MODE_REG *((volatile int32u *)0x40001018u) +#define DEBUG_BB_MODE *((volatile uint32_t *)0x40001018u) +#define DEBUG_BB_MODE_REG *((volatile uint32_t *)0x40001018u) #define DEBUG_BB_MODE_ADDR (0x40001018u) #define DEBUG_BB_MODE_RESET (0x00000000u) /* DEBUG_BB_MODE_EN field */ @@ -470,8 +470,8 @@ #define DEBUG_BB_MODE_DEBUG_BB_MODE_BIT (0) #define DEBUG_BB_MODE_DEBUG_BB_MODE_BITS (2) -#define BB_DEBUG *((volatile int32u *)0x4000101Cu) -#define BB_DEBUG_REG *((volatile int32u *)0x4000101Cu) +#define BB_DEBUG *((volatile uint32_t *)0x4000101Cu) +#define BB_DEBUG_REG *((volatile uint32_t *)0x4000101Cu) #define BB_DEBUG_ADDR (0x4000101Cu) #define BB_DEBUG_RESET (0x00000002u) /* SYNC_REG_EN field */ @@ -490,8 +490,8 @@ #define BB_DEBUG_BB_DEBUG_SEL_BIT (0) #define BB_DEBUG_BB_DEBUG_SEL_BITS (2) -#define BB_DEBUG_VIEW *((volatile int32u *)0x40001020u) -#define BB_DEBUG_VIEW_REG *((volatile int32u *)0x40001020u) +#define BB_DEBUG_VIEW *((volatile uint32_t *)0x40001020u) +#define BB_DEBUG_VIEW_REG *((volatile uint32_t *)0x40001020u) #define BB_DEBUG_VIEW_ADDR (0x40001020u) #define BB_DEBUG_VIEW_RESET (0x00000000u) /* BB_DEBUG_VIEW field */ @@ -500,8 +500,8 @@ #define BB_DEBUG_VIEW_BB_DEBUG_VIEW_BIT (0) #define BB_DEBUG_VIEW_BB_DEBUG_VIEW_BITS (16) -#define IF_FREQ *((volatile int32u *)0x40001024u) -#define IF_FREQ_REG *((volatile int32u *)0x40001024u) +#define IF_FREQ *((volatile uint32_t *)0x40001024u) +#define IF_FREQ_REG *((volatile uint32_t *)0x40001024u) #define IF_FREQ_ADDR (0x40001024u) #define IF_FREQ_RESET (0x00000155u) /* TIMING_CORR_EN field */ @@ -515,8 +515,8 @@ #define IF_FREQ_IF_FREQ_BIT (0) #define IF_FREQ_IF_FREQ_BITS (9) -#define MOD_EN *((volatile int32u *)0x40001028u) -#define MOD_EN_REG *((volatile int32u *)0x40001028u) +#define MOD_EN *((volatile uint32_t *)0x40001028u) +#define MOD_EN_REG *((volatile uint32_t *)0x40001028u) #define MOD_EN_ADDR (0x40001028u) #define MOD_EN_RESET (0x00000001u) /* MOD_EN field */ @@ -525,8 +525,8 @@ #define MOD_EN_MOD_EN_BIT (0) #define MOD_EN_MOD_EN_BITS (1) -#define PRESCALE_CTRL *((volatile int32u *)0x4000102Cu) -#define PRESCALE_CTRL_REG *((volatile int32u *)0x4000102Cu) +#define PRESCALE_CTRL *((volatile uint32_t *)0x4000102Cu) +#define PRESCALE_CTRL_REG *((volatile uint32_t *)0x4000102Cu) #define PRESCALE_CTRL_ADDR (0x4000102Cu) #define PRESCALE_CTRL_RESET (0x00000000u) /* PRESCALE_SET field */ @@ -540,8 +540,8 @@ #define PRESCALE_CTRL_PRESCALE_VAL_BIT (0) #define PRESCALE_CTRL_PRESCALE_VAL_BITS (3) -#define ADC_BYPASS_EN *((volatile int32u *)0x40001030u) -#define ADC_BYPASS_EN_REG *((volatile int32u *)0x40001030u) +#define ADC_BYPASS_EN *((volatile uint32_t *)0x40001030u) +#define ADC_BYPASS_EN_REG *((volatile uint32_t *)0x40001030u) #define ADC_BYPASS_EN_ADDR (0x40001030u) #define ADC_BYPASS_EN_RESET (0x00000000u) /* ADC_BYPASS_EN field */ @@ -550,8 +550,8 @@ #define ADC_BYPASS_EN_ADC_BYPASS_EN_BIT (0) #define ADC_BYPASS_EN_ADC_BYPASS_EN_BITS (1) -#define FIXED_CODE_EN *((volatile int32u *)0x40001034u) -#define FIXED_CODE_EN_REG *((volatile int32u *)0x40001034u) +#define FIXED_CODE_EN *((volatile uint32_t *)0x40001034u) +#define FIXED_CODE_EN_REG *((volatile uint32_t *)0x40001034u) #define FIXED_CODE_EN_ADDR (0x40001034u) #define FIXED_CODE_EN_RESET (0x00000000u) /* FIXED_CODE_EN field */ @@ -560,8 +560,8 @@ #define FIXED_CODE_EN_FIXED_CODE_EN_BIT (0) #define FIXED_CODE_EN_FIXED_CODE_EN_BITS (1) -#define FIXED_CODE_H *((volatile int32u *)0x40001038u) -#define FIXED_CODE_H_REG *((volatile int32u *)0x40001038u) +#define FIXED_CODE_H *((volatile uint32_t *)0x40001038u) +#define FIXED_CODE_H_REG *((volatile uint32_t *)0x40001038u) #define FIXED_CODE_H_ADDR (0x40001038u) #define FIXED_CODE_H_RESET (0x00000000u) /* FIXED_CODE_H field */ @@ -570,8 +570,8 @@ #define FIXED_CODE_H_FIXED_CODE_H_BIT (0) #define FIXED_CODE_H_FIXED_CODE_H_BITS (16) -#define FIXED_CODE_L *((volatile int32u *)0x4000103Cu) -#define FIXED_CODE_L_REG *((volatile int32u *)0x4000103Cu) +#define FIXED_CODE_L *((volatile uint32_t *)0x4000103Cu) +#define FIXED_CODE_L_REG *((volatile uint32_t *)0x4000103Cu) #define FIXED_CODE_L_ADDR (0x4000103Cu) #define FIXED_CODE_L_RESET (0x00000000u) /* FIXED_CODE_L field */ @@ -580,8 +580,8 @@ #define FIXED_CODE_L_FIXED_CODE_L_BIT (0) #define FIXED_CODE_L_FIXED_CODE_L_BITS (16) -#define FIXED_CODE_L_SHADOW *((volatile int32u *)0x40001040u) -#define FIXED_CODE_L_SHADOW_REG *((volatile int32u *)0x40001040u) +#define FIXED_CODE_L_SHADOW *((volatile uint32_t *)0x40001040u) +#define FIXED_CODE_L_SHADOW_REG *((volatile uint32_t *)0x40001040u) #define FIXED_CODE_L_SHADOW_ADDR (0x40001040u) #define FIXED_CODE_L_SHADOW_RESET (0x00000000u) /* FIXED_CODE_L_SHADOW field */ @@ -590,8 +590,8 @@ #define FIXED_CODE_L_SHADOW_FIXED_CODE_L_SHADOW_BIT (0) #define FIXED_CODE_L_SHADOW_FIXED_CODE_L_SHADOW_BITS (16) -#define RX_GAIN_CTRL *((volatile int32u *)0x40001044u) -#define RX_GAIN_CTRL_REG *((volatile int32u *)0x40001044u) +#define RX_GAIN_CTRL *((volatile uint32_t *)0x40001044u) +#define RX_GAIN_CTRL_REG *((volatile uint32_t *)0x40001044u) #define RX_GAIN_CTRL_ADDR (0x40001044u) #define RX_GAIN_CTRL_RESET (0x00000000u) /* RX_GAIN_MUX field */ @@ -620,8 +620,8 @@ #define RX_GAIN_CTRL_RX_IF_GAIN_TEST_BIT (0) #define RX_GAIN_CTRL_RX_IF_GAIN_TEST_BITS (4) -#define PD_DITHER_EN *((volatile int32u *)0x40001048u) -#define PD_DITHER_EN_REG *((volatile int32u *)0x40001048u) +#define PD_DITHER_EN *((volatile uint32_t *)0x40001048u) +#define PD_DITHER_EN_REG *((volatile uint32_t *)0x40001048u) #define PD_DITHER_EN_ADDR (0x40001048u) #define PD_DITHER_EN_RESET (0x00000001u) /* PD_DITHER_EN field */ @@ -630,8 +630,8 @@ #define PD_DITHER_EN_PD_DITHER_EN_BIT (0) #define PD_DITHER_EN_PD_DITHER_EN_BITS (1) -#define RX_ERR_THRESH *((volatile int32u *)0x4000104Cu) -#define RX_ERR_THRESH_REG *((volatile int32u *)0x4000104Cu) +#define RX_ERR_THRESH *((volatile uint32_t *)0x4000104Cu) +#define RX_ERR_THRESH_REG *((volatile uint32_t *)0x4000104Cu) #define RX_ERR_THRESH_ADDR (0x4000104Cu) #define RX_ERR_THRESH_RESET (0x00004608u) /* LPF_RX_ERR_COEFF field */ @@ -650,8 +650,8 @@ #define RX_ERR_THRESH_RX_ERR_THRESH_BIT (0) #define RX_ERR_THRESH_RX_ERR_THRESH_BITS (5) -#define CARRIER_THRESH *((volatile int32u *)0x40001050u) -#define CARRIER_THRESH_REG *((volatile int32u *)0x40001050u) +#define CARRIER_THRESH *((volatile uint32_t *)0x40001050u) +#define CARRIER_THRESH_REG *((volatile uint32_t *)0x40001050u) #define CARRIER_THRESH_ADDR (0x40001050u) #define CARRIER_THRESH_RESET (0x00002332u) /* CARRIER_SPIKE_THRESH field */ @@ -665,8 +665,8 @@ #define CARRIER_THRESH_CARRIER_THRESH_BIT (0) #define CARRIER_THRESH_CARRIER_THRESH_BITS (8) -#define RSSI_THRESH *((volatile int32u *)0x40001054u) -#define RSSI_THRESH_REG *((volatile int32u *)0x40001054u) +#define RSSI_THRESH *((volatile uint32_t *)0x40001054u) +#define RSSI_THRESH_REG *((volatile uint32_t *)0x40001054u) #define RSSI_THRESH_ADDR (0x40001054u) #define RSSI_THRESH_RESET (0x00000100u) /* RSSI_THRESH field */ @@ -675,8 +675,8 @@ #define RSSI_THRESH_RSSI_THRESH_BIT (0) #define RSSI_THRESH_RSSI_THRESH_BITS (16) -#define SYNTH_START *((volatile int32u *)0x40001058u) -#define SYNTH_START_REG *((volatile int32u *)0x40001058u) +#define SYNTH_START *((volatile uint32_t *)0x40001058u) +#define SYNTH_START_REG *((volatile uint32_t *)0x40001058u) #define SYNTH_START_ADDR (0x40001058u) #define SYNTH_START_RESET (0x00006464u) /* SYNTH_WARM_START field */ @@ -690,8 +690,8 @@ #define SYNTH_START_SYNTH_COLD_START_BIT (0) #define SYNTH_START_SYNTH_COLD_START_BITS (8) -#define IN_LOCK_EN *((volatile int32u *)0x4000105Cu) -#define IN_LOCK_EN_REG *((volatile int32u *)0x4000105Cu) +#define IN_LOCK_EN *((volatile uint32_t *)0x4000105Cu) +#define IN_LOCK_EN_REG *((volatile uint32_t *)0x4000105Cu) #define IN_LOCK_EN_ADDR (0x4000105Cu) #define IN_LOCK_EN_RESET (0x00000001u) /* IN_LOCK_EN field */ @@ -700,8 +700,8 @@ #define IN_LOCK_EN_IN_LOCK_EN_BIT (0) #define IN_LOCK_EN_IN_LOCK_EN_BITS (1) -#define DITHER_AMPLITUDE *((volatile int32u *)0x40001060u) -#define DITHER_AMPLITUDE_REG *((volatile int32u *)0x40001060u) +#define DITHER_AMPLITUDE *((volatile uint32_t *)0x40001060u) +#define DITHER_AMPLITUDE_REG *((volatile uint32_t *)0x40001060u) #define DITHER_AMPLITUDE_ADDR (0x40001060u) #define DITHER_AMPLITUDE_RESET (0x0000003Fu) /* DITHER_AMP field */ @@ -710,8 +710,8 @@ #define DITHER_AMPLITUDE_DITHER_AMP_BIT (0) #define DITHER_AMPLITUDE_DITHER_AMP_BITS (6) -#define TX_STEP_TIME *((volatile int32u *)0x40001064u) -#define TX_STEP_TIME_REG *((volatile int32u *)0x40001064u) +#define TX_STEP_TIME *((volatile uint32_t *)0x40001064u) +#define TX_STEP_TIME_REG *((volatile uint32_t *)0x40001064u) #define TX_STEP_TIME_ADDR (0x40001064u) #define TX_STEP_TIME_RESET (0x00000000u) /* TX_STEP_TIME field */ @@ -720,8 +720,8 @@ #define TX_STEP_TIME_TX_STEP_TIME_BIT (0) #define TX_STEP_TIME_TX_STEP_TIME_BITS (8) -#define GAIN_THRESH_MAX *((volatile int32u *)0x40001068u) -#define GAIN_THRESH_MAX_REG *((volatile int32u *)0x40001068u) +#define GAIN_THRESH_MAX *((volatile uint32_t *)0x40001068u) +#define GAIN_THRESH_MAX_REG *((volatile uint32_t *)0x40001068u) #define GAIN_THRESH_MAX_ADDR (0x40001068u) #define GAIN_THRESH_MAX_RESET (0x00000060u) /* GAIN_THRESH_MAX field */ @@ -730,8 +730,8 @@ #define GAIN_THRESH_MAX_GAIN_THRESH_MAX_BIT (0) #define GAIN_THRESH_MAX_GAIN_THRESH_MAX_BITS (8) -#define GAIN_THRESH_MID *((volatile int32u *)0x4000106Cu) -#define GAIN_THRESH_MID_REG *((volatile int32u *)0x4000106Cu) +#define GAIN_THRESH_MID *((volatile uint32_t *)0x4000106Cu) +#define GAIN_THRESH_MID_REG *((volatile uint32_t *)0x4000106Cu) #define GAIN_THRESH_MID_ADDR (0x4000106Cu) #define GAIN_THRESH_MID_RESET (0x00000030u) /* GAIN_THRESH_MID field */ @@ -740,8 +740,8 @@ #define GAIN_THRESH_MID_GAIN_THRESH_MID_BIT (0) #define GAIN_THRESH_MID_GAIN_THRESH_MID_BITS (8) -#define GAIN_THRESH_MIN *((volatile int32u *)0x40001070u) -#define GAIN_THRESH_MIN_REG *((volatile int32u *)0x40001070u) +#define GAIN_THRESH_MIN *((volatile uint32_t *)0x40001070u) +#define GAIN_THRESH_MIN_REG *((volatile uint32_t *)0x40001070u) #define GAIN_THRESH_MIN_ADDR (0x40001070u) #define GAIN_THRESH_MIN_RESET (0x00000018u) /* GAIN_THRESH_MIN field */ @@ -750,8 +750,8 @@ #define GAIN_THRESH_MIN_GAIN_THRESH_MIN_BIT (0) #define GAIN_THRESH_MIN_GAIN_THRESH_MIN_BITS (8) -#define GAIN_SETTING_0 *((volatile int32u *)0x40001074u) -#define GAIN_SETTING_0_REG *((volatile int32u *)0x40001074u) +#define GAIN_SETTING_0 *((volatile uint32_t *)0x40001074u) +#define GAIN_SETTING_0_REG *((volatile uint32_t *)0x40001074u) #define GAIN_SETTING_0_ADDR (0x40001074u) #define GAIN_SETTING_0_RESET (0x00000000u) /* RX_MIXER_GAIN_0 field */ @@ -770,8 +770,8 @@ #define GAIN_SETTING_0_RX_IF_GAIN_0_BIT (0) #define GAIN_SETTING_0_RX_IF_GAIN_0_BITS (4) -#define GAIN_SETTING_1 *((volatile int32u *)0x40001078u) -#define GAIN_SETTING_1_REG *((volatile int32u *)0x40001078u) +#define GAIN_SETTING_1 *((volatile uint32_t *)0x40001078u) +#define GAIN_SETTING_1_REG *((volatile uint32_t *)0x40001078u) #define GAIN_SETTING_1_ADDR (0x40001078u) #define GAIN_SETTING_1_RESET (0x00000010u) /* RX_MIXER_GAIN_1 field */ @@ -790,8 +790,8 @@ #define GAIN_SETTING_1_RX_IF_GAIN_1_BIT (0) #define GAIN_SETTING_1_RX_IF_GAIN_1_BITS (4) -#define GAIN_SETTING_2 *((volatile int32u *)0x4000107Cu) -#define GAIN_SETTING_2_REG *((volatile int32u *)0x4000107Cu) +#define GAIN_SETTING_2 *((volatile uint32_t *)0x4000107Cu) +#define GAIN_SETTING_2_REG *((volatile uint32_t *)0x4000107Cu) #define GAIN_SETTING_2_ADDR (0x4000107Cu) #define GAIN_SETTING_2_RESET (0x00000030u) /* RX_MIXER_GAIN_2 field */ @@ -810,8 +810,8 @@ #define GAIN_SETTING_2_RX_IF_GAIN_2_BIT (0) #define GAIN_SETTING_2_RX_IF_GAIN_2_BITS (4) -#define GAIN_SETTING_3 *((volatile int32u *)0x40001080u) -#define GAIN_SETTING_3_REG *((volatile int32u *)0x40001080u) +#define GAIN_SETTING_3 *((volatile uint32_t *)0x40001080u) +#define GAIN_SETTING_3_REG *((volatile uint32_t *)0x40001080u) #define GAIN_SETTING_3_ADDR (0x40001080u) #define GAIN_SETTING_3_RESET (0x00000031u) /* RX_MIXER_GAIN_3 field */ @@ -830,8 +830,8 @@ #define GAIN_SETTING_3_RX_IF_GAIN_3_BIT (0) #define GAIN_SETTING_3_RX_IF_GAIN_3_BITS (4) -#define GAIN_SETTING_4 *((volatile int32u *)0x40001084u) -#define GAIN_SETTING_4_REG *((volatile int32u *)0x40001084u) +#define GAIN_SETTING_4 *((volatile uint32_t *)0x40001084u) +#define GAIN_SETTING_4_REG *((volatile uint32_t *)0x40001084u) #define GAIN_SETTING_4_ADDR (0x40001084u) #define GAIN_SETTING_4_RESET (0x00000032u) /* RX_MIXER_GAIN_4 field */ @@ -850,8 +850,8 @@ #define GAIN_SETTING_4_RX_IF_GAIN_4_BIT (0) #define GAIN_SETTING_4_RX_IF_GAIN_4_BITS (4) -#define GAIN_SETTING_5 *((volatile int32u *)0x40001088u) -#define GAIN_SETTING_5_REG *((volatile int32u *)0x40001088u) +#define GAIN_SETTING_5 *((volatile uint32_t *)0x40001088u) +#define GAIN_SETTING_5_REG *((volatile uint32_t *)0x40001088u) #define GAIN_SETTING_5_ADDR (0x40001088u) #define GAIN_SETTING_5_RESET (0x00000033u) /* RX_MIXER_GAIN_5 field */ @@ -870,8 +870,8 @@ #define GAIN_SETTING_5_RX_IF_GAIN_5_BIT (0) #define GAIN_SETTING_5_RX_IF_GAIN_5_BITS (4) -#define GAIN_SETTING_6 *((volatile int32u *)0x4000108Cu) -#define GAIN_SETTING_6_REG *((volatile int32u *)0x4000108Cu) +#define GAIN_SETTING_6 *((volatile uint32_t *)0x4000108Cu) +#define GAIN_SETTING_6_REG *((volatile uint32_t *)0x4000108Cu) #define GAIN_SETTING_6_ADDR (0x4000108Cu) #define GAIN_SETTING_6_RESET (0x00000034u) /* RX_MIXER_GAIN_6 field */ @@ -890,8 +890,8 @@ #define GAIN_SETTING_6_RX_IF_GAIN_6_BIT (0) #define GAIN_SETTING_6_RX_IF_GAIN_6_BITS (4) -#define GAIN_SETTING_7 *((volatile int32u *)0x40001090u) -#define GAIN_SETTING_7_REG *((volatile int32u *)0x40001090u) +#define GAIN_SETTING_7 *((volatile uint32_t *)0x40001090u) +#define GAIN_SETTING_7_REG *((volatile uint32_t *)0x40001090u) #define GAIN_SETTING_7_ADDR (0x40001090u) #define GAIN_SETTING_7_RESET (0x00000035u) /* RX_MIXER_GAIN_7 field */ @@ -910,8 +910,8 @@ #define GAIN_SETTING_7_RX_IF_GAIN_7_BIT (0) #define GAIN_SETTING_7_RX_IF_GAIN_7_BITS (4) -#define GAIN_SETTING_8 *((volatile int32u *)0x40001094u) -#define GAIN_SETTING_8_REG *((volatile int32u *)0x40001094u) +#define GAIN_SETTING_8 *((volatile uint32_t *)0x40001094u) +#define GAIN_SETTING_8_REG *((volatile uint32_t *)0x40001094u) #define GAIN_SETTING_8_ADDR (0x40001094u) #define GAIN_SETTING_8_RESET (0x00000036u) /* RX_MIXER_GAIN_8 field */ @@ -930,8 +930,8 @@ #define GAIN_SETTING_8_RX_IF_GAIN_8_BIT (0) #define GAIN_SETTING_8_RX_IF_GAIN_8_BITS (4) -#define GAIN_SETTING_9 *((volatile int32u *)0x40001098u) -#define GAIN_SETTING_9_REG *((volatile int32u *)0x40001098u) +#define GAIN_SETTING_9 *((volatile uint32_t *)0x40001098u) +#define GAIN_SETTING_9_REG *((volatile uint32_t *)0x40001098u) #define GAIN_SETTING_9_ADDR (0x40001098u) #define GAIN_SETTING_9_RESET (0x00000076u) /* RX_MIXER_GAIN_9 field */ @@ -950,8 +950,8 @@ #define GAIN_SETTING_9_RX_IF_GAIN_9_BIT (0) #define GAIN_SETTING_9_RX_IF_GAIN_9_BITS (4) -#define GAIN_SETTING_10 *((volatile int32u *)0x4000109Cu) -#define GAIN_SETTING_10_REG *((volatile int32u *)0x4000109Cu) +#define GAIN_SETTING_10 *((volatile uint32_t *)0x4000109Cu) +#define GAIN_SETTING_10_REG *((volatile uint32_t *)0x4000109Cu) #define GAIN_SETTING_10_ADDR (0x4000109Cu) #define GAIN_SETTING_10_RESET (0x00000077u) /* RX_MIXER_GAIN_10 field */ @@ -970,8 +970,8 @@ #define GAIN_SETTING_10_RX_IF_GAIN_10_BIT (0) #define GAIN_SETTING_10_RX_IF_GAIN_10_BITS (4) -#define GAIN_SETTING_11 *((volatile int32u *)0x400010A0u) -#define GAIN_SETTING_11_REG *((volatile int32u *)0x400010A0u) +#define GAIN_SETTING_11 *((volatile uint32_t *)0x400010A0u) +#define GAIN_SETTING_11_REG *((volatile uint32_t *)0x400010A0u) #define GAIN_SETTING_11_ADDR (0x400010A0u) #define GAIN_SETTING_11_RESET (0x00000078u) /* RX_MIXER_GAIN_11 field */ @@ -990,8 +990,8 @@ #define GAIN_SETTING_11_RX_IF_GAIN_11_BIT (0) #define GAIN_SETTING_11_RX_IF_GAIN_11_BITS (4) -#define GAIN_CTRL_MIN_RF *((volatile int32u *)0x400010A4u) -#define GAIN_CTRL_MIN_RF_REG *((volatile int32u *)0x400010A4u) +#define GAIN_CTRL_MIN_RF *((volatile uint32_t *)0x400010A4u) +#define GAIN_CTRL_MIN_RF_REG *((volatile uint32_t *)0x400010A4u) #define GAIN_CTRL_MIN_RF_ADDR (0x400010A4u) #define GAIN_CTRL_MIN_RF_RESET (0x000000F0u) /* GAIN_CTRL_MIN_RF field */ @@ -1000,8 +1000,8 @@ #define GAIN_CTRL_MIN_RF_GAIN_CTRL_MIN_RF_BIT (0) #define GAIN_CTRL_MIN_RF_GAIN_CTRL_MIN_RF_BITS (9) -#define GAIN_CTRL_MAX_RF *((volatile int32u *)0x400010A8u) -#define GAIN_CTRL_MAX_RF_REG *((volatile int32u *)0x400010A8u) +#define GAIN_CTRL_MAX_RF *((volatile uint32_t *)0x400010A8u) +#define GAIN_CTRL_MAX_RF_REG *((volatile uint32_t *)0x400010A8u) #define GAIN_CTRL_MAX_RF_ADDR (0x400010A8u) #define GAIN_CTRL_MAX_RF_RESET (0x000000FCu) /* GAIN_CTRL_MAX_RF field */ @@ -1010,8 +1010,8 @@ #define GAIN_CTRL_MAX_RF_GAIN_CTRL_MAX_RF_BIT (0) #define GAIN_CTRL_MAX_RF_GAIN_CTRL_MAX_RF_BITS (9) -#define MIXER_GAIN_STEP *((volatile int32u *)0x400010ACu) -#define MIXER_GAIN_STEP_REG *((volatile int32u *)0x400010ACu) +#define MIXER_GAIN_STEP *((volatile uint32_t *)0x400010ACu) +#define MIXER_GAIN_STEP_REG *((volatile uint32_t *)0x400010ACu) #define MIXER_GAIN_STEP_ADDR (0x400010ACu) #define MIXER_GAIN_STEP_RESET (0x0000000Cu) /* MIXER_GAIN_STEP field */ @@ -1020,8 +1020,8 @@ #define MIXER_GAIN_STEP_MIXER_GAIN_STEP_BIT (0) #define MIXER_GAIN_STEP_MIXER_GAIN_STEP_BITS (4) -#define PREAMBLE_EVENT *((volatile int32u *)0x400010B0u) -#define PREAMBLE_EVENT_REG *((volatile int32u *)0x400010B0u) +#define PREAMBLE_EVENT *((volatile uint32_t *)0x400010B0u) +#define PREAMBLE_EVENT_REG *((volatile uint32_t *)0x400010B0u) #define PREAMBLE_EVENT_ADDR (0x400010B0u) #define PREAMBLE_EVENT_RESET (0x00005877u) /* PREAMBLE_CONFIRM_THRESH field */ @@ -1035,8 +1035,8 @@ #define PREAMBLE_EVENT_PREAMBLE_EVENT_THRESH_BIT (0) #define PREAMBLE_EVENT_PREAMBLE_EVENT_THRESH_BITS (8) -#define PREAMBLE_ABORT_THRESH *((volatile int32u *)0x400010B4u) -#define PREAMBLE_ABORT_THRESH_REG *((volatile int32u *)0x400010B4u) +#define PREAMBLE_ABORT_THRESH *((volatile uint32_t *)0x400010B4u) +#define PREAMBLE_ABORT_THRESH_REG *((volatile uint32_t *)0x400010B4u) #define PREAMBLE_ABORT_THRESH_ADDR (0x400010B4u) #define PREAMBLE_ABORT_THRESH_RESET (0x00000071u) /* PREAMBLE_ABORT_THRESH field */ @@ -1045,8 +1045,8 @@ #define PREAMBLE_ABORT_THRESH_PREAMBLE_ABORT_THRESH_BIT (0) #define PREAMBLE_ABORT_THRESH_PREAMBLE_ABORT_THRESH_BITS (8) -#define PREAMBLE_ACCEPT_WINDOW *((volatile int32u *)0x400010B8u) -#define PREAMBLE_ACCEPT_WINDOW_REG *((volatile int32u *)0x400010B8u) +#define PREAMBLE_ACCEPT_WINDOW *((volatile uint32_t *)0x400010B8u) +#define PREAMBLE_ACCEPT_WINDOW_REG *((volatile uint32_t *)0x400010B8u) #define PREAMBLE_ACCEPT_WINDOW_ADDR (0x400010B8u) #define PREAMBLE_ACCEPT_WINDOW_RESET (0x00000003u) /* PREAMBLE_ACCEPT_WINDOW field */ @@ -1055,8 +1055,8 @@ #define PREAMBLE_ACCEPT_WINDOW_PREAMBLE_ACCEPT_WINDOW_BIT (0) #define PREAMBLE_ACCEPT_WINDOW_PREAMBLE_ACCEPT_WINDOW_BITS (7) -#define CCA_MODE *((volatile int32u *)0x400010BCu) -#define CCA_MODE_REG *((volatile int32u *)0x400010BCu) +#define CCA_MODE *((volatile uint32_t *)0x400010BCu) +#define CCA_MODE_REG *((volatile uint32_t *)0x400010BCu) #define CCA_MODE_ADDR (0x400010BCu) #define CCA_MODE_RESET (0x00000000u) /* CCA_MODE field */ @@ -1065,8 +1065,8 @@ #define CCA_MODE_CCA_MODE_BIT (0) #define CCA_MODE_CCA_MODE_BITS (2) -#define TX_POWER_MAX *((volatile int32u *)0x400010C0u) -#define TX_POWER_MAX_REG *((volatile int32u *)0x400010C0u) +#define TX_POWER_MAX *((volatile uint32_t *)0x400010C0u) +#define TX_POWER_MAX_REG *((volatile uint32_t *)0x400010C0u) #define TX_POWER_MAX_ADDR (0x400010C0u) #define TX_POWER_MAX_RESET (0x00000000u) /* MANUAL_POWER field */ @@ -1080,8 +1080,8 @@ #define TX_POWER_MAX_TX_POWER_MAX_BIT (0) #define TX_POWER_MAX_TX_POWER_MAX_BITS (5) -#define SYNTH_FREQ_H *((volatile int32u *)0x400010C4u) -#define SYNTH_FREQ_H_REG *((volatile int32u *)0x400010C4u) +#define SYNTH_FREQ_H *((volatile uint32_t *)0x400010C4u) +#define SYNTH_FREQ_H_REG *((volatile uint32_t *)0x400010C4u) #define SYNTH_FREQ_H_ADDR (0x400010C4u) #define SYNTH_FREQ_H_RESET (0x00000003u) /* SYNTH_FREQ_H field */ @@ -1090,8 +1090,8 @@ #define SYNTH_FREQ_H_SYNTH_FREQ_H_BIT (0) #define SYNTH_FREQ_H_SYNTH_FREQ_H_BITS (2) -#define SYNTH_FREQ_L *((volatile int32u *)0x400010C8u) -#define SYNTH_FREQ_L_REG *((volatile int32u *)0x400010C8u) +#define SYNTH_FREQ_L *((volatile uint32_t *)0x400010C8u) +#define SYNTH_FREQ_L_REG *((volatile uint32_t *)0x400010C8u) #define SYNTH_FREQ_L_ADDR (0x400010C8u) #define SYNTH_FREQ_L_RESET (0x00003800u) /* SYNTH_FREQ_L field */ @@ -1100,8 +1100,8 @@ #define SYNTH_FREQ_L_SYNTH_FREQ_L_BIT (0) #define SYNTH_FREQ_L_SYNTH_FREQ_L_BITS (16) -#define RSSI_INST *((volatile int32u *)0x400010CCu) -#define RSSI_INST_REG *((volatile int32u *)0x400010CCu) +#define RSSI_INST *((volatile uint32_t *)0x400010CCu) +#define RSSI_INST_REG *((volatile uint32_t *)0x400010CCu) #define RSSI_INST_ADDR (0x400010CCu) #define RSSI_INST_RESET (0x00000000u) /* NEW_RSSI_INST field */ @@ -1115,8 +1115,8 @@ #define RSSI_INST_RSSI_INST_BIT (0) #define RSSI_INST_RSSI_INST_BITS (9) -#define FREQ_MEAS_CTRL1 *((volatile int32u *)0x400010D0u) -#define FREQ_MEAS_CTRL1_REG *((volatile int32u *)0x400010D0u) +#define FREQ_MEAS_CTRL1 *((volatile uint32_t *)0x400010D0u) +#define FREQ_MEAS_CTRL1_REG *((volatile uint32_t *)0x400010D0u) #define FREQ_MEAS_CTRL1_ADDR (0x400010D0u) #define FREQ_MEAS_CTRL1_RESET (0x00000160u) /* AUTO_TUNE_EN field */ @@ -1160,8 +1160,8 @@ #define FREQ_MEAS_CTRL1_TUNE_VCO_INIT_BIT (0) #define FREQ_MEAS_CTRL1_TUNE_VCO_INIT_BITS (6) -#define FREQ_MEAS_CTRL2 *((volatile int32u *)0x400010D4u) -#define FREQ_MEAS_CTRL2_REG *((volatile int32u *)0x400010D4u) +#define FREQ_MEAS_CTRL2 *((volatile uint32_t *)0x400010D4u) +#define FREQ_MEAS_CTRL2_REG *((volatile uint32_t *)0x400010D4u) #define FREQ_MEAS_CTRL2_ADDR (0x400010D4u) #define FREQ_MEAS_CTRL2_RESET (0x0000201Eu) /* FREQ_MEAS_TIMER field */ @@ -1175,8 +1175,8 @@ #define FREQ_MEAS_CTRL2_TARGET_PERIOD_BIT (0) #define FREQ_MEAS_CTRL2_TARGET_PERIOD_BITS (8) -#define FREQ_MEAS_SHIFT *((volatile int32u *)0x400010D8u) -#define FREQ_MEAS_SHIFT_REG *((volatile int32u *)0x400010D8u) +#define FREQ_MEAS_SHIFT *((volatile uint32_t *)0x400010D8u) +#define FREQ_MEAS_SHIFT_REG *((volatile uint32_t *)0x400010D8u) #define FREQ_MEAS_SHIFT_ADDR (0x400010D8u) #define FREQ_MEAS_SHIFT_RESET (0x00000035u) /* FREQ_MEAS_SHIFT field */ @@ -1185,8 +1185,8 @@ #define FREQ_MEAS_SHIFT_FREQ_MEAS_SHIFT_BIT (0) #define FREQ_MEAS_SHIFT_FREQ_MEAS_SHIFT_BITS (8) -#define FREQ_MEAS_STATUS1 *((volatile int32u *)0x400010DCu) -#define FREQ_MEAS_STATUS1_REG *((volatile int32u *)0x400010DCu) +#define FREQ_MEAS_STATUS1 *((volatile uint32_t *)0x400010DCu) +#define FREQ_MEAS_STATUS1_REG *((volatile uint32_t *)0x400010DCu) #define FREQ_MEAS_STATUS1_ADDR (0x400010DCu) #define FREQ_MEAS_STATUS1_RESET (0x00000000u) /* INVALID_EDGE field */ @@ -1215,8 +1215,8 @@ #define FREQ_MEAS_STATUS1_NEAREST_DIFF_BIT (0) #define FREQ_MEAS_STATUS1_NEAREST_DIFF_BITS (10) -#define FREQ_MEAS_STATUS2 *((volatile int32u *)0x400010E0u) -#define FREQ_MEAS_STATUS2_REG *((volatile int32u *)0x400010E0u) +#define FREQ_MEAS_STATUS2 *((volatile uint32_t *)0x400010E0u) +#define FREQ_MEAS_STATUS2_REG *((volatile uint32_t *)0x400010E0u) #define FREQ_MEAS_STATUS2_ADDR (0x400010E0u) #define FREQ_MEAS_STATUS2_RESET (0x00000000u) /* BEAT_TIMER field */ @@ -1230,8 +1230,8 @@ #define FREQ_MEAS_STATUS2_BEATS_BIT (0) #define FREQ_MEAS_STATUS2_BEATS_BITS (6) -#define FREQ_MEAS_STATUS3 *((volatile int32u *)0x400010E4u) -#define FREQ_MEAS_STATUS3_REG *((volatile int32u *)0x400010E4u) +#define FREQ_MEAS_STATUS3 *((volatile uint32_t *)0x400010E4u) +#define FREQ_MEAS_STATUS3_REG *((volatile uint32_t *)0x400010E4u) #define FREQ_MEAS_STATUS3_ADDR (0x400010E4u) #define FREQ_MEAS_STATUS3_RESET (0x00000020u) /* TUNE_VCO field */ @@ -1240,8 +1240,8 @@ #define FREQ_MEAS_STATUS3_TUNE_VCO_BIT (0) #define FREQ_MEAS_STATUS3_TUNE_VCO_BITS (6) -#define SCR_CTRL *((volatile int32u *)0x400010E8u) -#define SCR_CTRL_REG *((volatile int32u *)0x400010E8u) +#define SCR_CTRL *((volatile uint32_t *)0x400010E8u) +#define SCR_CTRL_REG *((volatile uint32_t *)0x400010E8u) #define SCR_CTRL_ADDR (0x400010E8u) #define SCR_CTRL_RESET (0x00000004u) /* SCR_RESET field */ @@ -1260,8 +1260,8 @@ #define SCR_CTRL_SCR_READ_BIT (0) #define SCR_CTRL_SCR_READ_BITS (1) -#define SCR_BUSY *((volatile int32u *)0x400010ECu) -#define SCR_BUSY_REG *((volatile int32u *)0x400010ECu) +#define SCR_BUSY *((volatile uint32_t *)0x400010ECu) +#define SCR_BUSY_REG *((volatile uint32_t *)0x400010ECu) #define SCR_BUSY_ADDR (0x400010ECu) #define SCR_BUSY_RESET (0x00000000u) /* SCR_BUSY field */ @@ -1270,8 +1270,8 @@ #define SCR_BUSY_SCR_BUSY_BIT (0) #define SCR_BUSY_SCR_BUSY_BITS (1) -#define SCR_ADDR *((volatile int32u *)0x400010F0u) -#define SCR_ADDR_REG *((volatile int32u *)0x400010F0u) +#define SCR_ADDR *((volatile uint32_t *)0x400010F0u) +#define SCR_ADDR_REG *((volatile uint32_t *)0x400010F0u) #define SCR_ADDR_ADDR (0x400010F0u) #define SCR_ADDR_RESET (0x00000000u) /* SCR_ADDR field */ @@ -1280,8 +1280,8 @@ #define SCR_ADDR_SCR_ADDR_BIT (0) #define SCR_ADDR_SCR_ADDR_BITS (8) -#define SCR_WRITE *((volatile int32u *)0x400010F4u) -#define SCR_WRITE_REG *((volatile int32u *)0x400010F4u) +#define SCR_WRITE *((volatile uint32_t *)0x400010F4u) +#define SCR_WRITE_REG *((volatile uint32_t *)0x400010F4u) #define SCR_WRITE_ADDR (0x400010F4u) #define SCR_WRITE_RESET (0x00000000u) /* SCR_WRITE field */ @@ -1290,8 +1290,8 @@ #define SCR_WRITE_SCR_WRITE_BIT (0) #define SCR_WRITE_SCR_WRITE_BITS (16) -#define SCR_READ *((volatile int32u *)0x400010F8u) -#define SCR_READ_REG *((volatile int32u *)0x400010F8u) +#define SCR_READ *((volatile uint32_t *)0x400010F8u) +#define SCR_READ_REG *((volatile uint32_t *)0x400010F8u) #define SCR_READ_ADDR (0x400010F8u) #define SCR_READ_RESET (0x00000000u) /* SCR_READ field */ @@ -1300,8 +1300,8 @@ #define SCR_READ_SCR_READ_BIT (0) #define SCR_READ_SCR_READ_BITS (16) -#define SYNTH_LOCK *((volatile int32u *)0x400010FCu) -#define SYNTH_LOCK_REG *((volatile int32u *)0x400010FCu) +#define SYNTH_LOCK *((volatile uint32_t *)0x400010FCu) +#define SYNTH_LOCK_REG *((volatile uint32_t *)0x400010FCu) #define SYNTH_LOCK_ADDR (0x400010FCu) #define SYNTH_LOCK_RESET (0x00000000u) /* IN_LOCK field */ @@ -1310,8 +1310,8 @@ #define SYNTH_LOCK_IN_LOCK_BIT (0) #define SYNTH_LOCK_IN_LOCK_BITS (1) -#define AN_CAL_STATUS *((volatile int32u *)0x40001100u) -#define AN_CAL_STATUS_REG *((volatile int32u *)0x40001100u) +#define AN_CAL_STATUS *((volatile uint32_t *)0x40001100u) +#define AN_CAL_STATUS_REG *((volatile uint32_t *)0x40001100u) #define AN_CAL_STATUS_ADDR (0x40001100u) #define AN_CAL_STATUS_RESET (0x00000000u) /* VCO_CTRL field */ @@ -1320,8 +1320,8 @@ #define AN_CAL_STATUS_VCO_CTRL_BIT (2) #define AN_CAL_STATUS_VCO_CTRL_BITS (2) -#define BIAS_CAL_STATUS *((volatile int32u *)0x40001104u) -#define BIAS_CAL_STATUS_REG *((volatile int32u *)0x40001104u) +#define BIAS_CAL_STATUS *((volatile uint32_t *)0x40001104u) +#define BIAS_CAL_STATUS_REG *((volatile uint32_t *)0x40001104u) #define BIAS_CAL_STATUS_ADDR (0x40001104u) #define BIAS_CAL_STATUS_RESET (0x00000000u) /* VCOMP field */ @@ -1335,8 +1335,8 @@ #define BIAS_CAL_STATUS_ICOMP_BIT (0) #define BIAS_CAL_STATUS_ICOMP_BITS (1) -#define ATEST_SEL *((volatile int32u *)0x40001108u) -#define ATEST_SEL_REG *((volatile int32u *)0x40001108u) +#define ATEST_SEL *((volatile uint32_t *)0x40001108u) +#define ATEST_SEL_REG *((volatile uint32_t *)0x40001108u) #define ATEST_SEL_ADDR (0x40001108u) #define ATEST_SEL_RESET (0x00000000u) /* ATEST_CTRL field */ @@ -1350,8 +1350,8 @@ #define ATEST_SEL_ATEST_SEL_BIT (0) #define ATEST_SEL_ATEST_SEL_BITS (5) -#define AN_EN_TEST *((volatile int32u *)0x4000110Cu) -#define AN_EN_TEST_REG *((volatile int32u *)0x4000110Cu) +#define AN_EN_TEST *((volatile uint32_t *)0x4000110Cu) +#define AN_EN_TEST_REG *((volatile uint32_t *)0x4000110Cu) #define AN_EN_TEST_ADDR (0x4000110Cu) #define AN_EN_TEST_RESET (0x00000000u) /* AN_TEST_MODE field */ @@ -1425,8 +1425,8 @@ #define AN_EN_TEST_BIAS_EN_BIT (0) #define AN_EN_TEST_BIAS_EN_BITS (1) -#define TUNE_FILTER_CTRL *((volatile int32u *)0x40001110u) -#define TUNE_FILTER_CTRL_REG *((volatile int32u *)0x40001110u) +#define TUNE_FILTER_CTRL *((volatile uint32_t *)0x40001110u) +#define TUNE_FILTER_CTRL_REG *((volatile uint32_t *)0x40001110u) #define TUNE_FILTER_CTRL_ADDR (0x40001110u) #define TUNE_FILTER_CTRL_RESET (0x00000000u) /* TUNE_FILTER_EN field */ @@ -1440,8 +1440,8 @@ #define TUNE_FILTER_CTRL_TUNE_FILTER_RESET_BIT (0) #define TUNE_FILTER_CTRL_TUNE_FILTER_RESET_BITS (1) -#define NOISE_EN *((volatile int32u *)0x40001114u) -#define NOISE_EN_REG *((volatile int32u *)0x40001114u) +#define NOISE_EN *((volatile uint32_t *)0x40001114u) +#define NOISE_EN_REG *((volatile uint32_t *)0x40001114u) #define NOISE_EN_ADDR (0x40001114u) #define NOISE_EN_RESET (0x00000000u) /* NOISE_EN field */ @@ -1455,8 +1455,8 @@ #define DATA_MAC_END (0x400020C8u) #define DATA_MAC_SIZE (DATA_MAC_END - DATA_MAC_BASE + 1) -#define MAC_RX_ST_ADDR_A *((volatile int32u *)0x40002000u) -#define MAC_RX_ST_ADDR_A_REG *((volatile int32u *)0x40002000u) +#define MAC_RX_ST_ADDR_A *((volatile uint32_t *)0x40002000u) +#define MAC_RX_ST_ADDR_A_REG *((volatile uint32_t *)0x40002000u) #define MAC_RX_ST_ADDR_A_ADDR (0x40002000u) #define MAC_RX_ST_ADDR_A_RESET (0x20000000u) /* MAC_RAM_OFFS field */ @@ -1470,8 +1470,8 @@ #define MAC_RX_ST_ADDR_A_MAC_RX_ST_ADDR_A_BIT (1) #define MAC_RX_ST_ADDR_A_MAC_RX_ST_ADDR_A_BITS (12) -#define MAC_RX_END_ADDR_A *((volatile int32u *)0x40002004u) -#define MAC_RX_END_ADDR_A_REG *((volatile int32u *)0x40002004u) +#define MAC_RX_END_ADDR_A *((volatile uint32_t *)0x40002004u) +#define MAC_RX_END_ADDR_A_REG *((volatile uint32_t *)0x40002004u) #define MAC_RX_END_ADDR_A_ADDR (0x40002004u) #define MAC_RX_END_ADDR_A_RESET (0x20000088u) /* MAC_RAM_OFFS field */ @@ -1485,8 +1485,8 @@ #define MAC_RX_END_ADDR_A_MAC_RX_END_ADDR_A_BIT (1) #define MAC_RX_END_ADDR_A_MAC_RX_END_ADDR_A_BITS (12) -#define MAC_RX_ST_ADDR_B *((volatile int32u *)0x40002008u) -#define MAC_RX_ST_ADDR_B_REG *((volatile int32u *)0x40002008u) +#define MAC_RX_ST_ADDR_B *((volatile uint32_t *)0x40002008u) +#define MAC_RX_ST_ADDR_B_REG *((volatile uint32_t *)0x40002008u) #define MAC_RX_ST_ADDR_B_ADDR (0x40002008u) #define MAC_RX_ST_ADDR_B_RESET (0x20000000u) /* MAC_RAM_OFFS field */ @@ -1500,8 +1500,8 @@ #define MAC_RX_ST_ADDR_B_MAC_RX_ST_ADDR_B_BIT (1) #define MAC_RX_ST_ADDR_B_MAC_RX_ST_ADDR_B_BITS (12) -#define MAC_RX_END_ADDR_B *((volatile int32u *)0x4000200Cu) -#define MAC_RX_END_ADDR_B_REG *((volatile int32u *)0x4000200Cu) +#define MAC_RX_END_ADDR_B *((volatile uint32_t *)0x4000200Cu) +#define MAC_RX_END_ADDR_B_REG *((volatile uint32_t *)0x4000200Cu) #define MAC_RX_END_ADDR_B_ADDR (0x4000200Cu) #define MAC_RX_END_ADDR_B_RESET (0x20000088u) /* MAC_RAM_OFFS field */ @@ -1515,8 +1515,8 @@ #define MAC_RX_END_ADDR_B_MAC_RX_END_ADDR_B_BIT (1) #define MAC_RX_END_ADDR_B_MAC_RX_END_ADDR_B_BITS (12) -#define MAC_TX_ST_ADDR_A *((volatile int32u *)0x40002010u) -#define MAC_TX_ST_ADDR_A_REG *((volatile int32u *)0x40002010u) +#define MAC_TX_ST_ADDR_A *((volatile uint32_t *)0x40002010u) +#define MAC_TX_ST_ADDR_A_REG *((volatile uint32_t *)0x40002010u) #define MAC_TX_ST_ADDR_A_ADDR (0x40002010u) #define MAC_TX_ST_ADDR_A_RESET (0x20000000u) /* MAC_RAM_OFFS field */ @@ -1530,8 +1530,8 @@ #define MAC_TX_ST_ADDR_A_MAC_TX_ST_ADDR_A_BIT (1) #define MAC_TX_ST_ADDR_A_MAC_TX_ST_ADDR_A_BITS (12) -#define MAC_TX_END_ADDR_A *((volatile int32u *)0x40002014u) -#define MAC_TX_END_ADDR_A_REG *((volatile int32u *)0x40002014u) +#define MAC_TX_END_ADDR_A *((volatile uint32_t *)0x40002014u) +#define MAC_TX_END_ADDR_A_REG *((volatile uint32_t *)0x40002014u) #define MAC_TX_END_ADDR_A_ADDR (0x40002014u) #define MAC_TX_END_ADDR_A_RESET (0x20000000u) /* MAC_RAM_OFFS field */ @@ -1545,8 +1545,8 @@ #define MAC_TX_END_ADDR_A_MAC_TX_END_ADDR_A_BIT (1) #define MAC_TX_END_ADDR_A_MAC_TX_END_ADDR_A_BITS (12) -#define MAC_TX_ST_ADDR_B *((volatile int32u *)0x40002018u) -#define MAC_TX_ST_ADDR_B_REG *((volatile int32u *)0x40002018u) +#define MAC_TX_ST_ADDR_B *((volatile uint32_t *)0x40002018u) +#define MAC_TX_ST_ADDR_B_REG *((volatile uint32_t *)0x40002018u) #define MAC_TX_ST_ADDR_B_ADDR (0x40002018u) #define MAC_TX_ST_ADDR_B_RESET (0x20000000u) /* MAC_RAM_OFFS field */ @@ -1560,8 +1560,8 @@ #define MAC_TX_ST_ADDR_B_MAC_TX_ST_ADDR_B_BIT (1) #define MAC_TX_ST_ADDR_B_MAC_TX_ST_ADDR_B_BITS (12) -#define MAC_TX_END_ADDR_B *((volatile int32u *)0x4000201Cu) -#define MAC_TX_END_ADDR_B_REG *((volatile int32u *)0x4000201Cu) +#define MAC_TX_END_ADDR_B *((volatile uint32_t *)0x4000201Cu) +#define MAC_TX_END_ADDR_B_REG *((volatile uint32_t *)0x4000201Cu) #define MAC_TX_END_ADDR_B_ADDR (0x4000201Cu) #define MAC_TX_END_ADDR_B_RESET (0x20000000u) /* MAC_RAM_OFFS field */ @@ -1575,8 +1575,8 @@ #define MAC_TX_END_ADDR_B_MAC_TX_END_ADDR_B_BIT (1) #define MAC_TX_END_ADDR_B_MAC_TX_END_ADDR_B_BITS (12) -#define RX_A_COUNT *((volatile int32u *)0x40002020u) -#define RX_A_COUNT_REG *((volatile int32u *)0x40002020u) +#define RX_A_COUNT *((volatile uint32_t *)0x40002020u) +#define RX_A_COUNT_REG *((volatile uint32_t *)0x40002020u) #define RX_A_COUNT_ADDR (0x40002020u) #define RX_A_COUNT_RESET (0x00000000u) /* RX_A_COUNT field */ @@ -1585,8 +1585,8 @@ #define RX_A_COUNT_RX_A_COUNT_BIT (0) #define RX_A_COUNT_RX_A_COUNT_BITS (11) -#define RX_B_COUNT *((volatile int32u *)0x40002024u) -#define RX_B_COUNT_REG *((volatile int32u *)0x40002024u) +#define RX_B_COUNT *((volatile uint32_t *)0x40002024u) +#define RX_B_COUNT_REG *((volatile uint32_t *)0x40002024u) #define RX_B_COUNT_ADDR (0x40002024u) #define RX_B_COUNT_RESET (0x00000000u) /* RX_B_COUNT field */ @@ -1595,8 +1595,8 @@ #define RX_B_COUNT_RX_B_COUNT_BIT (0) #define RX_B_COUNT_RX_B_COUNT_BITS (11) -#define TX_COUNT *((volatile int32u *)0x40002028u) -#define TX_COUNT_REG *((volatile int32u *)0x40002028u) +#define TX_COUNT *((volatile uint32_t *)0x40002028u) +#define TX_COUNT_REG *((volatile uint32_t *)0x40002028u) #define TX_COUNT_ADDR (0x40002028u) #define TX_COUNT_RESET (0x00000000u) /* TX_COUNT field */ @@ -1605,8 +1605,8 @@ #define TX_COUNT_TX_COUNT_BIT (0) #define TX_COUNT_TX_COUNT_BITS (11) -#define MAC_DMA_STATUS *((volatile int32u *)0x4000202Cu) -#define MAC_DMA_STATUS_REG *((volatile int32u *)0x4000202Cu) +#define MAC_DMA_STATUS *((volatile uint32_t *)0x4000202Cu) +#define MAC_DMA_STATUS_REG *((volatile uint32_t *)0x4000202Cu) #define MAC_DMA_STATUS_ADDR (0x4000202Cu) #define MAC_DMA_STATUS_RESET (0x00000000u) /* TX_ACTIVE_B field */ @@ -1630,8 +1630,8 @@ #define MAC_DMA_STATUS_RX_ACTIVE_A_BIT (0) #define MAC_DMA_STATUS_RX_ACTIVE_A_BITS (1) -#define MAC_DMA_CONFIG *((volatile int32u *)0x40002030u) -#define MAC_DMA_CONFIG_REG *((volatile int32u *)0x40002030u) +#define MAC_DMA_CONFIG *((volatile uint32_t *)0x40002030u) +#define MAC_DMA_CONFIG_REG *((volatile uint32_t *)0x40002030u) #define MAC_DMA_CONFIG_ADDR (0x40002030u) #define MAC_DMA_CONFIG_RESET (0x00000000u) /* TX_DMA_RESET field */ @@ -1665,8 +1665,8 @@ #define MAC_DMA_CONFIG_RX_LOAD_A_BIT (0) #define MAC_DMA_CONFIG_RX_LOAD_A_BITS (1) -#define MAC_TIMER *((volatile int32u *)0x40002038u) -#define MAC_TIMER_REG *((volatile int32u *)0x40002038u) +#define MAC_TIMER *((volatile uint32_t *)0x40002038u) +#define MAC_TIMER_REG *((volatile uint32_t *)0x40002038u) #define MAC_TIMER_ADDR (0x40002038u) #define MAC_TIMER_RESET (0x00000000u) /* MAC_TIMER field */ @@ -1675,8 +1675,8 @@ #define MAC_TIMER_MAC_TIMER_BIT (0) #define MAC_TIMER_MAC_TIMER_BITS (20) -#define MAC_TIMER_COMPARE_A_H *((volatile int32u *)0x40002040u) -#define MAC_TIMER_COMPARE_A_H_REG *((volatile int32u *)0x40002040u) +#define MAC_TIMER_COMPARE_A_H *((volatile uint32_t *)0x40002040u) +#define MAC_TIMER_COMPARE_A_H_REG *((volatile uint32_t *)0x40002040u) #define MAC_TIMER_COMPARE_A_H_ADDR (0x40002040u) #define MAC_TIMER_COMPARE_A_H_RESET (0x00000000u) /* MAC_COMPARE_A_H field */ @@ -1685,8 +1685,8 @@ #define MAC_TIMER_COMPARE_A_H_MAC_COMPARE_A_H_BIT (0) #define MAC_TIMER_COMPARE_A_H_MAC_COMPARE_A_H_BITS (4) -#define MAC_TIMER_COMPARE_A_L *((volatile int32u *)0x40002044u) -#define MAC_TIMER_COMPARE_A_L_REG *((volatile int32u *)0x40002044u) +#define MAC_TIMER_COMPARE_A_L *((volatile uint32_t *)0x40002044u) +#define MAC_TIMER_COMPARE_A_L_REG *((volatile uint32_t *)0x40002044u) #define MAC_TIMER_COMPARE_A_L_ADDR (0x40002044u) #define MAC_TIMER_COMPARE_A_L_RESET (0x00000000u) /* MAC_COMPARE_A_L field */ @@ -1695,8 +1695,8 @@ #define MAC_TIMER_COMPARE_A_L_MAC_COMPARE_A_L_BIT (0) #define MAC_TIMER_COMPARE_A_L_MAC_COMPARE_A_L_BITS (16) -#define MAC_TIMER_COMPARE_B_H *((volatile int32u *)0x40002048u) -#define MAC_TIMER_COMPARE_B_H_REG *((volatile int32u *)0x40002048u) +#define MAC_TIMER_COMPARE_B_H *((volatile uint32_t *)0x40002048u) +#define MAC_TIMER_COMPARE_B_H_REG *((volatile uint32_t *)0x40002048u) #define MAC_TIMER_COMPARE_B_H_ADDR (0x40002048u) #define MAC_TIMER_COMPARE_B_H_RESET (0x00000000u) /* MAC_COMPARE_B_H field */ @@ -1705,8 +1705,8 @@ #define MAC_TIMER_COMPARE_B_H_MAC_COMPARE_B_H_BIT (0) #define MAC_TIMER_COMPARE_B_H_MAC_COMPARE_B_H_BITS (4) -#define MAC_TIMER_COMPARE_B_L *((volatile int32u *)0x4000204Cu) -#define MAC_TIMER_COMPARE_B_L_REG *((volatile int32u *)0x4000204Cu) +#define MAC_TIMER_COMPARE_B_L *((volatile uint32_t *)0x4000204Cu) +#define MAC_TIMER_COMPARE_B_L_REG *((volatile uint32_t *)0x4000204Cu) #define MAC_TIMER_COMPARE_B_L_ADDR (0x4000204Cu) #define MAC_TIMER_COMPARE_B_L_RESET (0x00000000u) /* MAC_COMPARE_B_L field */ @@ -1715,8 +1715,8 @@ #define MAC_TIMER_COMPARE_B_L_MAC_COMPARE_B_L_BIT (0) #define MAC_TIMER_COMPARE_B_L_MAC_COMPARE_B_L_BITS (16) -#define MAC_TIMER_CAPTURE_H *((volatile int32u *)0x40002050u) -#define MAC_TIMER_CAPTURE_H_REG *((volatile int32u *)0x40002050u) +#define MAC_TIMER_CAPTURE_H *((volatile uint32_t *)0x40002050u) +#define MAC_TIMER_CAPTURE_H_REG *((volatile uint32_t *)0x40002050u) #define MAC_TIMER_CAPTURE_H_ADDR (0x40002050u) #define MAC_TIMER_CAPTURE_H_RESET (0x00000000u) /* MAC_SFD_CAPTURE_HIGH field */ @@ -1725,8 +1725,8 @@ #define MAC_TIMER_CAPTURE_H_MAC_SFD_CAPTURE_HIGH_BIT (0) #define MAC_TIMER_CAPTURE_H_MAC_SFD_CAPTURE_HIGH_BITS (4) -#define MAC_TIMER_CAPTURE_L *((volatile int32u *)0x40002054u) -#define MAC_TIMER_CAPTURE_L_REG *((volatile int32u *)0x40002054u) +#define MAC_TIMER_CAPTURE_L *((volatile uint32_t *)0x40002054u) +#define MAC_TIMER_CAPTURE_L_REG *((volatile uint32_t *)0x40002054u) #define MAC_TIMER_CAPTURE_L_ADDR (0x40002054u) #define MAC_TIMER_CAPTURE_L_RESET (0x00000000u) /* MAC_SFD_CAPTURE_LOW field */ @@ -1735,8 +1735,8 @@ #define MAC_TIMER_CAPTURE_L_MAC_SFD_CAPTURE_LOW_BIT (0) #define MAC_TIMER_CAPTURE_L_MAC_SFD_CAPTURE_LOW_BITS (16) -#define MAC_BO_TIMER *((volatile int32u *)0x40002058u) -#define MAC_BO_TIMER_REG *((volatile int32u *)0x40002058u) +#define MAC_BO_TIMER *((volatile uint32_t *)0x40002058u) +#define MAC_BO_TIMER_REG *((volatile uint32_t *)0x40002058u) #define MAC_BO_TIMER_ADDR (0x40002058u) #define MAC_BO_TIMER_RESET (0x00000000u) /* MAC_BO_TIMER field */ @@ -1745,8 +1745,8 @@ #define MAC_BO_TIMER_MAC_BO_TIMER_BIT (0) #define MAC_BO_TIMER_MAC_BO_TIMER_BITS (12) -#define MAC_BOP_TIMER *((volatile int32u *)0x4000205Cu) -#define MAC_BOP_TIMER_REG *((volatile int32u *)0x4000205Cu) +#define MAC_BOP_TIMER *((volatile uint32_t *)0x4000205Cu) +#define MAC_BOP_TIMER_REG *((volatile uint32_t *)0x4000205Cu) #define MAC_BOP_TIMER_ADDR (0x4000205Cu) #define MAC_BOP_TIMER_RESET (0x00000000u) /* MAC_BOP_TIMER field */ @@ -1755,8 +1755,8 @@ #define MAC_BOP_TIMER_MAC_BOP_TIMER_BIT (0) #define MAC_BOP_TIMER_MAC_BOP_TIMER_BITS (7) -#define MAC_TX_STROBE *((volatile int32u *)0x40002060u) -#define MAC_TX_STROBE_REG *((volatile int32u *)0x40002060u) +#define MAC_TX_STROBE *((volatile uint32_t *)0x40002060u) +#define MAC_TX_STROBE_REG *((volatile uint32_t *)0x40002060u) #define MAC_TX_STROBE_ADDR (0x40002060u) #define MAC_TX_STROBE_RESET (0x00000000u) /* AUTO_CRC_TX field */ @@ -1780,8 +1780,8 @@ #define MAC_TX_STROBE_START_TX_BIT (0) #define MAC_TX_STROBE_START_TX_BITS (1) -#define MAC_ACK_STROBE *((volatile int32u *)0x40002064u) -#define MAC_ACK_STROBE_REG *((volatile int32u *)0x40002064u) +#define MAC_ACK_STROBE *((volatile uint32_t *)0x40002064u) +#define MAC_ACK_STROBE_REG *((volatile uint32_t *)0x40002064u) #define MAC_ACK_STROBE_ADDR (0x40002064u) #define MAC_ACK_STROBE_RESET (0x00000000u) /* MANUAL_ACK field */ @@ -1795,8 +1795,8 @@ #define MAC_ACK_STROBE_FRAME_PENDING_BIT (0) #define MAC_ACK_STROBE_FRAME_PENDING_BITS (1) -#define MAC_STATUS *((volatile int32u *)0x40002068u) -#define MAC_STATUS_REG *((volatile int32u *)0x40002068u) +#define MAC_STATUS *((volatile uint32_t *)0x40002068u) +#define MAC_STATUS_REG *((volatile uint32_t *)0x40002068u) #define MAC_STATUS_ADDR (0x40002068u) #define MAC_STATUS_RESET (0x00000000u) /* RX_B_PEND_TX_ACK field */ @@ -1860,8 +1860,8 @@ #define MAC_STATUS_RX_CRC_PASS_BIT (0) #define MAC_STATUS_RX_CRC_PASS_BITS (1) -#define TX_CRC *((volatile int32u *)0x4000206Cu) -#define TX_CRC_REG *((volatile int32u *)0x4000206Cu) +#define TX_CRC *((volatile uint32_t *)0x4000206Cu) +#define TX_CRC_REG *((volatile uint32_t *)0x4000206Cu) #define TX_CRC_ADDR (0x4000206Cu) #define TX_CRC_RESET (0x00000000u) /* TX_CRC field */ @@ -1870,8 +1870,8 @@ #define TX_CRC_TX_CRC_BIT (0) #define TX_CRC_TX_CRC_BITS (16) -#define RX_CRC *((volatile int32u *)0x40002070u) -#define RX_CRC_REG *((volatile int32u *)0x40002070u) +#define RX_CRC *((volatile uint32_t *)0x40002070u) +#define RX_CRC_REG *((volatile uint32_t *)0x40002070u) #define RX_CRC_ADDR (0x40002070u) #define RX_CRC_RESET (0x00000000u) /* RX_CRC field */ @@ -1880,8 +1880,8 @@ #define RX_CRC_RX_CRC_BIT (0) #define RX_CRC_RX_CRC_BITS (16) -#define MAC_ACK_TO *((volatile int32u *)0x40002074u) -#define MAC_ACK_TO_REG *((volatile int32u *)0x40002074u) +#define MAC_ACK_TO *((volatile uint32_t *)0x40002074u) +#define MAC_ACK_TO_REG *((volatile uint32_t *)0x40002074u) #define MAC_ACK_TO_ADDR (0x40002074u) #define MAC_ACK_TO_RESET (0x00000300u) /* ACK_TO field */ @@ -1890,8 +1890,8 @@ #define MAC_ACK_TO_ACK_TO_BIT (0) #define MAC_ACK_TO_ACK_TO_BITS (14) -#define MAC_BOP_COMPARE *((volatile int32u *)0x40002078u) -#define MAC_BOP_COMPARE_REG *((volatile int32u *)0x40002078u) +#define MAC_BOP_COMPARE *((volatile uint32_t *)0x40002078u) +#define MAC_BOP_COMPARE_REG *((volatile uint32_t *)0x40002078u) #define MAC_BOP_COMPARE_ADDR (0x40002078u) #define MAC_BOP_COMPARE_RESET (0x00000014u) /* MAC_BOP_COMPARE field */ @@ -1900,8 +1900,8 @@ #define MAC_BOP_COMPARE_MAC_BOP_COMPARE_BIT (0) #define MAC_BOP_COMPARE_MAC_BOP_COMPARE_BITS (7) -#define MAC_TX_ACK_FRAME *((volatile int32u *)0x4000207Cu) -#define MAC_TX_ACK_FRAME_REG *((volatile int32u *)0x4000207Cu) +#define MAC_TX_ACK_FRAME *((volatile uint32_t *)0x4000207Cu) +#define MAC_TX_ACK_FRAME_REG *((volatile uint32_t *)0x4000207Cu) #define MAC_TX_ACK_FRAME_ADDR (0x4000207Cu) #define MAC_TX_ACK_FRAME_RESET (0x00000002u) /* ACK_SRC_AM field */ @@ -1950,8 +1950,8 @@ #define MAC_TX_ACK_FRAME_ACK_FRAME_T_BIT (0) #define MAC_TX_ACK_FRAME_ACK_FRAME_T_BITS (3) -#define MAC_CONFIG *((volatile int32u *)0x40002080u) -#define MAC_CONFIG_REG *((volatile int32u *)0x40002080u) +#define MAC_CONFIG *((volatile uint32_t *)0x40002080u) +#define MAC_CONFIG_REG *((volatile uint32_t *)0x40002080u) #define MAC_CONFIG_ADDR (0x40002080u) #define MAC_CONFIG_RESET (0x00000000u) /* RSSI_INST_EN field */ @@ -1970,8 +1970,8 @@ #define MAC_CONFIG_MAC_MODE_BIT (0) #define MAC_CONFIG_MAC_MODE_BITS (1) -#define MAC_RX_CONFIG *((volatile int32u *)0x40002084u) -#define MAC_RX_CONFIG_REG *((volatile int32u *)0x40002084u) +#define MAC_RX_CONFIG *((volatile uint32_t *)0x40002084u) +#define MAC_RX_CONFIG_REG *((volatile uint32_t *)0x40002084u) #define MAC_RX_CONFIG_ADDR (0x40002084u) #define MAC_RX_CONFIG_RESET (0x00000000u) /* AUTO_ACK field */ @@ -2015,8 +2015,8 @@ #define MAC_RX_CONFIG_MAC_RX_RST_BIT (0) #define MAC_RX_CONFIG_MAC_RX_RST_BITS (1) -#define MAC_TX_CONFIG *((volatile int32u *)0x40002088u) -#define MAC_TX_CONFIG_REG *((volatile int32u *)0x40002088u) +#define MAC_TX_CONFIG *((volatile uint32_t *)0x40002088u) +#define MAC_TX_CONFIG_REG *((volatile uint32_t *)0x40002088u) #define MAC_TX_CONFIG_ADDR (0x40002088u) #define MAC_TX_CONFIG_RESET (0x00000008u) /* SLOTTED field */ @@ -2045,8 +2045,8 @@ #define MAC_TX_CONFIG_WAIT_ACK_BIT (0) #define MAC_TX_CONFIG_WAIT_ACK_BITS (1) -#define MAC_TIMER_CTRL *((volatile int32u *)0x4000208Cu) -#define MAC_TIMER_CTRL_REG *((volatile int32u *)0x4000208Cu) +#define MAC_TIMER_CTRL *((volatile uint32_t *)0x4000208Cu) +#define MAC_TIMER_CTRL_REG *((volatile uint32_t *)0x4000208Cu) #define MAC_TIMER_CTRL_ADDR (0x4000208Cu) #define MAC_TIMER_CTRL_RESET (0x00000000u) /* COMP_A_SYNC field */ @@ -2085,8 +2085,8 @@ #define MAC_TIMER_CTRL_MAC_TIMER_EN_BIT (0) #define MAC_TIMER_CTRL_MAC_TIMER_EN_BITS (1) -#define PAN_ID *((volatile int32u *)0x40002090u) -#define PAN_ID_REG *((volatile int32u *)0x40002090u) +#define PAN_ID *((volatile uint32_t *)0x40002090u) +#define PAN_ID_REG *((volatile uint32_t *)0x40002090u) #define PAN_ID_ADDR (0x40002090u) #define PAN_ID_RESET (0x00000000u) /* PAN_ID field */ @@ -2095,8 +2095,8 @@ #define PAN_ID_PAN_ID_BIT (0) #define PAN_ID_PAN_ID_BITS (16) -#define SHORT_ADDR *((volatile int32u *)0x40002094u) -#define SHORT_ADDR_REG *((volatile int32u *)0x40002094u) +#define SHORT_ADDR *((volatile uint32_t *)0x40002094u) +#define SHORT_ADDR_REG *((volatile uint32_t *)0x40002094u) #define SHORT_ADDR_ADDR (0x40002094u) #define SHORT_ADDR_RESET (0x00000000u) /* SHORT_ADDR field */ @@ -2105,8 +2105,8 @@ #define SHORT_ADDR_SHORT_ADDR_BIT (0) #define SHORT_ADDR_SHORT_ADDR_BITS (16) -#define EXT_ADDR_0 *((volatile int32u *)0x40002098u) -#define EXT_ADDR_0_REG *((volatile int32u *)0x40002098u) +#define EXT_ADDR_0 *((volatile uint32_t *)0x40002098u) +#define EXT_ADDR_0_REG *((volatile uint32_t *)0x40002098u) #define EXT_ADDR_0_ADDR (0x40002098u) #define EXT_ADDR_0_RESET (0x00000000u) /* EXT_ADDR_0 field */ @@ -2115,8 +2115,8 @@ #define EXT_ADDR_0_EXT_ADDR_0_BIT (0) #define EXT_ADDR_0_EXT_ADDR_0_BITS (16) -#define EXT_ADDR_1 *((volatile int32u *)0x4000209Cu) -#define EXT_ADDR_1_REG *((volatile int32u *)0x4000209Cu) +#define EXT_ADDR_1 *((volatile uint32_t *)0x4000209Cu) +#define EXT_ADDR_1_REG *((volatile uint32_t *)0x4000209Cu) #define EXT_ADDR_1_ADDR (0x4000209Cu) #define EXT_ADDR_1_RESET (0x00000000u) /* EXT_ADDR_1 field */ @@ -2125,8 +2125,8 @@ #define EXT_ADDR_1_EXT_ADDR_1_BIT (0) #define EXT_ADDR_1_EXT_ADDR_1_BITS (16) -#define EXT_ADDR_2 *((volatile int32u *)0x400020A0u) -#define EXT_ADDR_2_REG *((volatile int32u *)0x400020A0u) +#define EXT_ADDR_2 *((volatile uint32_t *)0x400020A0u) +#define EXT_ADDR_2_REG *((volatile uint32_t *)0x400020A0u) #define EXT_ADDR_2_ADDR (0x400020A0u) #define EXT_ADDR_2_RESET (0x00000000u) /* EXT_ADDR_2 field */ @@ -2135,8 +2135,8 @@ #define EXT_ADDR_2_EXT_ADDR_2_BIT (0) #define EXT_ADDR_2_EXT_ADDR_2_BITS (16) -#define EXT_ADDR_3 *((volatile int32u *)0x400020A4u) -#define EXT_ADDR_3_REG *((volatile int32u *)0x400020A4u) +#define EXT_ADDR_3 *((volatile uint32_t *)0x400020A4u) +#define EXT_ADDR_3_REG *((volatile uint32_t *)0x400020A4u) #define EXT_ADDR_3_ADDR (0x400020A4u) #define EXT_ADDR_3_RESET (0x00000000u) /* EXT_ADDR_3 field */ @@ -2145,8 +2145,8 @@ #define EXT_ADDR_3_EXT_ADDR_3_BIT (0) #define EXT_ADDR_3_EXT_ADDR_3_BITS (16) -#define MAC_STATE *((volatile int32u *)0x400020A8u) -#define MAC_STATE_REG *((volatile int32u *)0x400020A8u) +#define MAC_STATE *((volatile uint32_t *)0x400020A8u) +#define MAC_STATE_REG *((volatile uint32_t *)0x400020A8u) #define MAC_STATE_ADDR (0x400020A8u) #define MAC_STATE_RESET (0x00000000u) /* SPY_STATE field */ @@ -2170,8 +2170,8 @@ #define MAC_STATE_TOP_STATE_BIT (0) #define MAC_STATE_TOP_STATE_BITS (2) -#define RX_STATE *((volatile int32u *)0x400020ACu) -#define RX_STATE_REG *((volatile int32u *)0x400020ACu) +#define RX_STATE *((volatile uint32_t *)0x400020ACu) +#define RX_STATE_REG *((volatile uint32_t *)0x400020ACu) #define RX_STATE_ADDR (0x400020ACu) #define RX_STATE_RESET (0x00000000u) /* RX_BUFFER_STATE field */ @@ -2185,8 +2185,8 @@ #define RX_STATE_RX_TOP_STATE_BIT (0) #define RX_STATE_RX_TOP_STATE_BITS (5) -#define TX_STATE *((volatile int32u *)0x400020B0u) -#define TX_STATE_REG *((volatile int32u *)0x400020B0u) +#define TX_STATE *((volatile uint32_t *)0x400020B0u) +#define TX_STATE_REG *((volatile uint32_t *)0x400020B0u) #define TX_STATE_ADDR (0x400020B0u) #define TX_STATE_RESET (0x00000000u) /* TX_BUFFER_STATE field */ @@ -2200,8 +2200,8 @@ #define TX_STATE_TX_TOP_STATE_BIT (0) #define TX_STATE_TX_TOP_STATE_BITS (4) -#define DMA_STATE *((volatile int32u *)0x400020B4u) -#define DMA_STATE_REG *((volatile int32u *)0x400020B4u) +#define DMA_STATE *((volatile uint32_t *)0x400020B4u) +#define DMA_STATE_REG *((volatile uint32_t *)0x400020B4u) #define DMA_STATE_ADDR (0x400020B4u) #define DMA_STATE_RESET (0x00000000u) /* DMA_RX_STATE field */ @@ -2215,8 +2215,8 @@ #define DMA_STATE_DMA_TX_STATE_BIT (0) #define DMA_STATE_DMA_TX_STATE_BITS (3) -#define MAC_DEBUG *((volatile int32u *)0x400020B8u) -#define MAC_DEBUG_REG *((volatile int32u *)0x400020B8u) +#define MAC_DEBUG *((volatile uint32_t *)0x400020B8u) +#define MAC_DEBUG_REG *((volatile uint32_t *)0x400020B8u) #define MAC_DEBUG_ADDR (0x400020B8u) #define MAC_DEBUG_RESET (0x00000000u) /* SW_DEBUG_OUT field */ @@ -2230,8 +2230,8 @@ #define MAC_DEBUG_MAC_DEBUG_MUX_BIT (0) #define MAC_DEBUG_MAC_DEBUG_MUX_BITS (5) -#define MAC_DEBUG_VIEW *((volatile int32u *)0x400020BCu) -#define MAC_DEBUG_VIEW_REG *((volatile int32u *)0x400020BCu) +#define MAC_DEBUG_VIEW *((volatile uint32_t *)0x400020BCu) +#define MAC_DEBUG_VIEW_REG *((volatile uint32_t *)0x400020BCu) #define MAC_DEBUG_VIEW_ADDR (0x400020BCu) #define MAC_DEBUG_VIEW_RESET (0x00000010u) /* MAC_DEBUG_VIEW field */ @@ -2240,8 +2240,8 @@ #define MAC_DEBUG_VIEW_MAC_DEBUG_VIEW_BIT (0) #define MAC_DEBUG_VIEW_MAC_DEBUG_VIEW_BITS (16) -#define MAC_RSSI_DELAY *((volatile int32u *)0x400020C0u) -#define MAC_RSSI_DELAY_REG *((volatile int32u *)0x400020C0u) +#define MAC_RSSI_DELAY *((volatile uint32_t *)0x400020C0u) +#define MAC_RSSI_DELAY_REG *((volatile uint32_t *)0x400020C0u) #define MAC_RSSI_DELAY_ADDR (0x400020C0u) #define MAC_RSSI_DELAY_RESET (0x00000000u) /* RSSI_INST_DELAY_OK field */ @@ -2255,8 +2255,8 @@ #define MAC_RSSI_DELAY_RSSI_INST_DELAY_BIT (0) #define MAC_RSSI_DELAY_RSSI_INST_DELAY_BITS (6) -#define PANID_COUNT *((volatile int32u *)0x400020C4u) -#define PANID_COUNT_REG *((volatile int32u *)0x400020C4u) +#define PANID_COUNT *((volatile uint32_t *)0x400020C4u) +#define PANID_COUNT_REG *((volatile uint32_t *)0x400020C4u) #define PANID_COUNT_ADDR (0x400020C4u) #define PANID_COUNT_RESET (0x00000000u) /* PANID_COUNT field */ @@ -2265,8 +2265,8 @@ #define PANID_COUNT_PANID_COUNT_BIT (0) #define PANID_COUNT_PANID_COUNT_BITS (16) -#define NONPAN_COUNT *((volatile int32u *)0x400020C8u) -#define NONPAN_COUNT_REG *((volatile int32u *)0x400020C8u) +#define NONPAN_COUNT *((volatile uint32_t *)0x400020C8u) +#define NONPAN_COUNT_REG *((volatile uint32_t *)0x400020C8u) #define NONPAN_COUNT_ADDR (0x400020C8u) #define NONPAN_COUNT_RESET (0x00000000u) /* NONPAN_COUNT field */ @@ -2280,8 +2280,8 @@ #define DATA_SECURITY_END (0x40003044u) #define DATA_SECURITY_SIZE (DATA_SECURITY_END - DATA_SECURITY_BASE + 1) -#define SECURITY_CONFIG *((volatile int32u *)0x40003000u) -#define SECURITY_CONFIG_REG *((volatile int32u *)0x40003000u) +#define SECURITY_CONFIG *((volatile uint32_t *)0x40003000u) +#define SECURITY_CONFIG_REG *((volatile uint32_t *)0x40003000u) #define SECURITY_CONFIG_ADDR (0x40003000u) #define SECURITY_CONFIG_RESET (0x00000000u) /* SEC_RST field */ @@ -2325,8 +2325,8 @@ #define SECURITY_CONFIG_START_AES_BIT (0) #define SECURITY_CONFIG_START_AES_BITS (1) -#define SECURITY_STATUS *((volatile int32u *)0x40003004u) -#define SECURITY_STATUS_REG *((volatile int32u *)0x40003004u) +#define SECURITY_STATUS *((volatile uint32_t *)0x40003004u) +#define SECURITY_STATUS_REG *((volatile uint32_t *)0x40003004u) #define SECURITY_STATUS_ADDR (0x40003004u) #define SECURITY_STATUS_RESET (0x00000000u) /* SEC_BUSY field */ @@ -2335,8 +2335,8 @@ #define SECURITY_STATUS_SEC_BUSY_BIT (0) #define SECURITY_STATUS_SEC_BUSY_BITS (1) -#define CBC_STATE_0 *((volatile int32u *)0x40003008u) -#define CBC_STATE_0_REG *((volatile int32u *)0x40003008u) +#define CBC_STATE_0 *((volatile uint32_t *)0x40003008u) +#define CBC_STATE_0_REG *((volatile uint32_t *)0x40003008u) #define CBC_STATE_0_ADDR (0x40003008u) #define CBC_STATE_0_RESET (0x00000000u) /* CBC_STATE field */ @@ -2345,8 +2345,8 @@ #define CBC_STATE_0_CBC_STATE_BIT (0) #define CBC_STATE_0_CBC_STATE_BITS (32) -#define CBC_STATE_1 *((volatile int32u *)0x4000300Cu) -#define CBC_STATE_1_REG *((volatile int32u *)0x4000300Cu) +#define CBC_STATE_1 *((volatile uint32_t *)0x4000300Cu) +#define CBC_STATE_1_REG *((volatile uint32_t *)0x4000300Cu) #define CBC_STATE_1_ADDR (0x4000300Cu) #define CBC_STATE_1_RESET (0x00000000u) /* CBC_STATE_1 field */ @@ -2355,8 +2355,8 @@ #define CBC_STATE_1_CBC_STATE_1_BIT (0) #define CBC_STATE_1_CBC_STATE_1_BITS (32) -#define CBC_STATE_2 *((volatile int32u *)0x40003010u) -#define CBC_STATE_2_REG *((volatile int32u *)0x40003010u) +#define CBC_STATE_2 *((volatile uint32_t *)0x40003010u) +#define CBC_STATE_2_REG *((volatile uint32_t *)0x40003010u) #define CBC_STATE_2_ADDR (0x40003010u) #define CBC_STATE_2_RESET (0x00000000u) /* CBC_STATE_2 field */ @@ -2365,8 +2365,8 @@ #define CBC_STATE_2_CBC_STATE_2_BIT (0) #define CBC_STATE_2_CBC_STATE_2_BITS (32) -#define CBC_STATE_3 *((volatile int32u *)0x40003014u) -#define CBC_STATE_3_REG *((volatile int32u *)0x40003014u) +#define CBC_STATE_3 *((volatile uint32_t *)0x40003014u) +#define CBC_STATE_3_REG *((volatile uint32_t *)0x40003014u) #define CBC_STATE_3_ADDR (0x40003014u) #define CBC_STATE_3_RESET (0x00000000u) /* CBC_STATE_3 field */ @@ -2375,8 +2375,8 @@ #define CBC_STATE_3_CBC_STATE_3_BIT (0) #define CBC_STATE_3_CBC_STATE_3_BITS (32) -#define PT *((volatile int32u *)0x40003028u) -#define PT_REG *((volatile int32u *)0x40003028u) +#define PT *((volatile uint32_t *)0x40003028u) +#define PT_REG *((volatile uint32_t *)0x40003028u) #define PT_ADDR (0x40003028u) #define PT_RESET (0x00000000u) /* PT field */ @@ -2385,8 +2385,8 @@ #define PT_PT_BIT (0) #define PT_PT_BITS (32) -#define CT *((volatile int32u *)0x40003030u) -#define CT_REG *((volatile int32u *)0x40003030u) +#define CT *((volatile uint32_t *)0x40003030u) +#define CT_REG *((volatile uint32_t *)0x40003030u) #define CT_ADDR (0x40003030u) #define CT_RESET (0x00000000u) /* CT field */ @@ -2395,8 +2395,8 @@ #define CT_CT_BIT (0) #define CT_CT_BITS (32) -#define KEY_0 *((volatile int32u *)0x40003038u) -#define KEY_0_REG *((volatile int32u *)0x40003038u) +#define KEY_0 *((volatile uint32_t *)0x40003038u) +#define KEY_0_REG *((volatile uint32_t *)0x40003038u) #define KEY_0_ADDR (0x40003038u) #define KEY_0_RESET (0x00000000u) /* KEY_O field */ @@ -2405,8 +2405,8 @@ #define KEY_0_KEY_O_BIT (0) #define KEY_0_KEY_O_BITS (32) -#define KEY_1 *((volatile int32u *)0x4000303Cu) -#define KEY_1_REG *((volatile int32u *)0x4000303Cu) +#define KEY_1 *((volatile uint32_t *)0x4000303Cu) +#define KEY_1_REG *((volatile uint32_t *)0x4000303Cu) #define KEY_1_ADDR (0x4000303Cu) #define KEY_1_RESET (0x00000000u) /* KEY_1 field */ @@ -2415,8 +2415,8 @@ #define KEY_1_KEY_1_BIT (0) #define KEY_1_KEY_1_BITS (32) -#define KEY_2 *((volatile int32u *)0x40003040u) -#define KEY_2_REG *((volatile int32u *)0x40003040u) +#define KEY_2 *((volatile uint32_t *)0x40003040u) +#define KEY_2_REG *((volatile uint32_t *)0x40003040u) #define KEY_2_ADDR (0x40003040u) #define KEY_2_RESET (0x00000000u) /* KEY_2 field */ @@ -2425,8 +2425,8 @@ #define KEY_2_KEY_2_BIT (0) #define KEY_2_KEY_2_BITS (32) -#define KEY_3 *((volatile int32u *)0x40003044u) -#define KEY_3_REG *((volatile int32u *)0x40003044u) +#define KEY_3 *((volatile uint32_t *)0x40003044u) +#define KEY_3_REG *((volatile uint32_t *)0x40003044u) #define KEY_3_ADDR (0x40003044u) #define KEY_3_RESET (0x00000000u) /* KEY_3 field */ @@ -2440,8 +2440,8 @@ #define BLOCK_CM_LV_END (0x40004034u) #define BLOCK_CM_LV_SIZE (BLOCK_CM_LV_END - BLOCK_CM_LV_BASE + 1) -#define SILICON_ID *((volatile int32u *)0x40004000u) -#define SILICON_ID_REG *((volatile int32u *)0x40004000u) +#define SILICON_ID *((volatile uint32_t *)0x40004000u) +#define SILICON_ID_REG *((volatile uint32_t *)0x40004000u) #define SILICON_ID_ADDR (0x40004000u) #define SILICON_ID_RESET (0x069A862Bu) /* HW_VERSION field */ @@ -2475,8 +2475,8 @@ #define SILICON_ID_ONE_BIT (0) #define SILICON_ID_ONE_BITS (1) -#define OSC24M_BIASTRIM *((volatile int32u *)0x40004004u) -#define OSC24M_BIASTRIM_REG *((volatile int32u *)0x40004004u) +#define OSC24M_BIASTRIM *((volatile uint32_t *)0x40004004u) +#define OSC24M_BIASTRIM_REG *((volatile uint32_t *)0x40004004u) #define OSC24M_BIASTRIM_ADDR (0x40004004u) #define OSC24M_BIASTRIM_RESET (0x0000000Fu) /* OSC24M_BIAS_TRIM field */ @@ -2485,8 +2485,8 @@ #define OSC24M_BIASTRIM_OSC24M_BIAS_TRIM_BIT (0) #define OSC24M_BIASTRIM_OSC24M_BIAS_TRIM_BITS (4) -#define OSCHF_TUNE *((volatile int32u *)0x40004008u) -#define OSCHF_TUNE_REG *((volatile int32u *)0x40004008u) +#define OSCHF_TUNE *((volatile uint32_t *)0x40004008u) +#define OSCHF_TUNE_REG *((volatile uint32_t *)0x40004008u) #define OSCHF_TUNE_ADDR (0x40004008u) #define OSCHF_TUNE_RESET (0x00000017u) /* OSCHF_TUNE_FIELD field */ @@ -2495,8 +2495,8 @@ #define OSCHF_TUNE_FIELD_BIT (0) #define OSCHF_TUNE_FIELD_BITS (5) -#define OSC24M_COMP *((volatile int32u *)0x4000400Cu) -#define OSC24M_COMP_REG *((volatile int32u *)0x4000400Cu) +#define OSC24M_COMP *((volatile uint32_t *)0x4000400Cu) +#define OSC24M_COMP_REG *((volatile uint32_t *)0x4000400Cu) #define OSC24M_COMP_ADDR (0x4000400Cu) #define OSC24M_COMP_RESET (0x00000000u) /* OSC24M_HI field */ @@ -2510,8 +2510,8 @@ #define OSC24M_LO_BIT (0) #define OSC24M_LO_BITS (1) -#define CLK_PERIODMODE *((volatile int32u *)0x40004010u) -#define CLK_PERIODMODE_REG *((volatile int32u *)0x40004010u) +#define CLK_PERIODMODE *((volatile uint32_t *)0x40004010u) +#define CLK_PERIODMODE_REG *((volatile uint32_t *)0x40004010u) #define CLK_PERIODMODE_ADDR (0x40004010u) #define CLK_PERIODMODE_RESET (0x00000000u) /* CLK_PERIODMODE_FIELD field */ @@ -2520,8 +2520,8 @@ #define CLK_PERIODMODE_FIELD_BIT (0) #define CLK_PERIODMODE_FIELD_BITS (2) -#define CLK_PERIOD *((volatile int32u *)0x40004014u) -#define CLK_PERIOD_REG *((volatile int32u *)0x40004014u) +#define CLK_PERIOD *((volatile uint32_t *)0x40004014u) +#define CLK_PERIOD_REG *((volatile uint32_t *)0x40004014u) #define CLK_PERIOD_ADDR (0x40004014u) #define CLK_PERIOD_RESET (0x00000000u) /* CLK_PERIOD_FIELD field */ @@ -2530,8 +2530,8 @@ #define CLK_PERIOD_FIELD_BIT (0) #define CLK_PERIOD_FIELD_BITS (16) -#define DITHER_DIS *((volatile int32u *)0x40004018u) -#define DITHER_DIS_REG *((volatile int32u *)0x40004018u) +#define DITHER_DIS *((volatile uint32_t *)0x40004018u) +#define DITHER_DIS_REG *((volatile uint32_t *)0x40004018u) #define DITHER_DIS_ADDR (0x40004018u) #define DITHER_DIS_RESET (0x00000000u) /* DITHER_DIS field */ @@ -2540,8 +2540,8 @@ #define DITHER_DIS_DITHER_DIS_BIT (0) #define DITHER_DIS_DITHER_DIS_BITS (1) -#define OSC24M_CTRL *((volatile int32u *)0x4000401Cu) -#define OSC24M_CTRL_REG *((volatile int32u *)0x4000401Cu) +#define OSC24M_CTRL *((volatile uint32_t *)0x4000401Cu) +#define OSC24M_CTRL_REG *((volatile uint32_t *)0x4000401Cu) #define OSC24M_CTRL_ADDR (0x4000401Cu) #define OSC24M_CTRL_RESET (0x00000000u) /* OSC24M_EN field */ @@ -2555,8 +2555,8 @@ #define OSC24M_CTRL_OSC24M_SEL_BIT (0) #define OSC24M_CTRL_OSC24M_SEL_BITS (1) -#define CPU_CLKSEL *((volatile int32u *)0x40004020u) -#define CPU_CLKSEL_REG *((volatile int32u *)0x40004020u) +#define CPU_CLKSEL *((volatile uint32_t *)0x40004020u) +#define CPU_CLKSEL_REG *((volatile uint32_t *)0x40004020u) #define CPU_CLKSEL_ADDR (0x40004020u) #define CPU_CLKSEL_RESET (0x00000000u) /* CPU_CLKSEL_FIELD field */ @@ -2565,8 +2565,8 @@ #define CPU_CLKSEL_FIELD_BIT (0) #define CPU_CLKSEL_FIELD_BITS (1) -#define BUS_FAULT *((volatile int32u *)0x40004024u) -#define BUS_FAULT_REG *((volatile int32u *)0x40004024u) +#define BUS_FAULT *((volatile uint32_t *)0x40004024u) +#define BUS_FAULT_REG *((volatile uint32_t *)0x40004024u) #define BUS_FAULT_ADDR (0x40004024u) #define BUS_FAULT_RESET (0x00000000u) /* WRONGSIZE field */ @@ -2590,8 +2590,8 @@ #define BUS_FAULT_MISSED_BIT (0) #define BUS_FAULT_MISSED_BITS (1) -#define PCTRACE_SEL *((volatile int32u *)0x40004028u) -#define PCTRACE_SEL_REG *((volatile int32u *)0x40004028u) +#define PCTRACE_SEL *((volatile uint32_t *)0x40004028u) +#define PCTRACE_SEL_REG *((volatile uint32_t *)0x40004028u) #define PCTRACE_SEL_ADDR (0x40004028u) #define PCTRACE_SEL_RESET (0x00000000u) /* PCTRACE_SEL_FIELD field */ @@ -2600,8 +2600,8 @@ #define PCTRACE_SEL_FIELD_BIT (0) #define PCTRACE_SEL_FIELD_BITS (1) -#define FPEC_CLKREQ *((volatile int32u *)0x4000402Cu) -#define FPEC_CLKREQ_REG *((volatile int32u *)0x4000402Cu) +#define FPEC_CLKREQ *((volatile uint32_t *)0x4000402Cu) +#define FPEC_CLKREQ_REG *((volatile uint32_t *)0x4000402Cu) #define FPEC_CLKREQ_ADDR (0x4000402Cu) #define FPEC_CLKREQ_RESET (0x00000000u) /* FPEC_CLKREQ_FIELD field */ @@ -2610,8 +2610,8 @@ #define FPEC_CLKREQ_FIELD_BIT (0) #define FPEC_CLKREQ_FIELD_BITS (1) -#define FPEC_CLKSTAT *((volatile int32u *)0x40004030u) -#define FPEC_CLKSTAT_REG *((volatile int32u *)0x40004030u) +#define FPEC_CLKSTAT *((volatile uint32_t *)0x40004030u) +#define FPEC_CLKSTAT_REG *((volatile uint32_t *)0x40004030u) #define FPEC_CLKSTAT_ADDR (0x40004030u) #define FPEC_CLKSTAT_RESET (0x00000000u) /* FPEC_CLKBSY field */ @@ -2625,8 +2625,8 @@ #define FPEC_CLKACK_BIT (0) #define FPEC_CLKACK_BITS (1) -#define LV_SPARE *((volatile int32u *)0x40004034u) -#define LV_SPARE_REG *((volatile int32u *)0x40004034u) +#define LV_SPARE *((volatile uint32_t *)0x40004034u) +#define LV_SPARE_REG *((volatile uint32_t *)0x40004034u) #define LV_SPARE_ADDR (0x40004034u) #define LV_SPARE_RESET (0x00000000u) /* LV_SPARE field */ @@ -2640,8 +2640,8 @@ #define DATA_RAM_CTRL_END (0x40005028u) #define DATA_RAM_CTRL_SIZE (DATA_RAM_CTRL_END - DATA_RAM_CTRL_BASE + 1) -#define MEM_PROT_0 *((volatile int32u *)0x40005000u) -#define MEM_PROT_0_REG *((volatile int32u *)0x40005000u) +#define MEM_PROT_0 *((volatile uint32_t *)0x40005000u) +#define MEM_PROT_0_REG *((volatile uint32_t *)0x40005000u) #define MEM_PROT_0_ADDR (0x40005000u) #define MEM_PROT_0_RESET (0x00000000u) /* MEM_PROT_0 field */ @@ -2650,8 +2650,8 @@ #define MEM_PROT_0_MEM_PROT_0_BIT (0) #define MEM_PROT_0_MEM_PROT_0_BITS (32) -#define MEM_PROT_1 *((volatile int32u *)0x40005004u) -#define MEM_PROT_1_REG *((volatile int32u *)0x40005004u) +#define MEM_PROT_1 *((volatile uint32_t *)0x40005004u) +#define MEM_PROT_1_REG *((volatile uint32_t *)0x40005004u) #define MEM_PROT_1_ADDR (0x40005004u) #define MEM_PROT_1_RESET (0x00000000u) /* MEM_PROT_1 field */ @@ -2660,8 +2660,8 @@ #define MEM_PROT_1_MEM_PROT_1_BIT (0) #define MEM_PROT_1_MEM_PROT_1_BITS (32) -#define MEM_PROT_2 *((volatile int32u *)0x40005008u) -#define MEM_PROT_2_REG *((volatile int32u *)0x40005008u) +#define MEM_PROT_2 *((volatile uint32_t *)0x40005008u) +#define MEM_PROT_2_REG *((volatile uint32_t *)0x40005008u) #define MEM_PROT_2_ADDR (0x40005008u) #define MEM_PROT_2_RESET (0x00000000u) /* MEM_PROT_2 field */ @@ -2670,8 +2670,8 @@ #define MEM_PROT_2_MEM_PROT_2_BIT (0) #define MEM_PROT_2_MEM_PROT_2_BITS (32) -#define MEM_PROT_3 *((volatile int32u *)0x4000500Cu) -#define MEM_PROT_3_REG *((volatile int32u *)0x4000500Cu) +#define MEM_PROT_3 *((volatile uint32_t *)0x4000500Cu) +#define MEM_PROT_3_REG *((volatile uint32_t *)0x4000500Cu) #define MEM_PROT_3_ADDR (0x4000500Cu) #define MEM_PROT_3_RESET (0x00000000u) /* MEM_PROT_3 field */ @@ -2680,8 +2680,8 @@ #define MEM_PROT_3_MEM_PROT_3_BIT (0) #define MEM_PROT_3_MEM_PROT_3_BITS (32) -#define MEM_PROT_4 *((volatile int32u *)0x40005010u) -#define MEM_PROT_4_REG *((volatile int32u *)0x40005010u) +#define MEM_PROT_4 *((volatile uint32_t *)0x40005010u) +#define MEM_PROT_4_REG *((volatile uint32_t *)0x40005010u) #define MEM_PROT_4_ADDR (0x40005010u) #define MEM_PROT_4_RESET (0x00000000u) /* MEM_PROT_4 field */ @@ -2690,8 +2690,8 @@ #define MEM_PROT_4_MEM_PROT_4_BIT (0) #define MEM_PROT_4_MEM_PROT_4_BITS (32) -#define MEM_PROT_5 *((volatile int32u *)0x40005014u) -#define MEM_PROT_5_REG *((volatile int32u *)0x40005014u) +#define MEM_PROT_5 *((volatile uint32_t *)0x40005014u) +#define MEM_PROT_5_REG *((volatile uint32_t *)0x40005014u) #define MEM_PROT_5_ADDR (0x40005014u) #define MEM_PROT_5_RESET (0x00000000u) /* MEM_PROT_5 field */ @@ -2700,8 +2700,8 @@ #define MEM_PROT_5_MEM_PROT_5_BIT (0) #define MEM_PROT_5_MEM_PROT_5_BITS (32) -#define MEM_PROT_6 *((volatile int32u *)0x40005018u) -#define MEM_PROT_6_REG *((volatile int32u *)0x40005018u) +#define MEM_PROT_6 *((volatile uint32_t *)0x40005018u) +#define MEM_PROT_6_REG *((volatile uint32_t *)0x40005018u) #define MEM_PROT_6_ADDR (0x40005018u) #define MEM_PROT_6_RESET (0x00000000u) /* MEM_PROT_6 field */ @@ -2710,8 +2710,8 @@ #define MEM_PROT_6_MEM_PROT_6_BIT (0) #define MEM_PROT_6_MEM_PROT_6_BITS (32) -#define MEM_PROT_7 *((volatile int32u *)0x4000501Cu) -#define MEM_PROT_7_REG *((volatile int32u *)0x4000501Cu) +#define MEM_PROT_7 *((volatile uint32_t *)0x4000501Cu) +#define MEM_PROT_7_REG *((volatile uint32_t *)0x4000501Cu) #define MEM_PROT_7_ADDR (0x4000501Cu) #define MEM_PROT_7_RESET (0x00000000u) /* MEM_PROT_7 field */ @@ -2720,8 +2720,8 @@ #define MEM_PROT_7_MEM_PROT_7_BIT (0) #define MEM_PROT_7_MEM_PROT_7_BITS (32) -#define DMA_PROT_ADDR *((volatile int32u *)0x40005020u) -#define DMA_PROT_ADDR_REG *((volatile int32u *)0x40005020u) +#define DMA_PROT_ADDR *((volatile uint32_t *)0x40005020u) +#define DMA_PROT_ADDR_REG *((volatile uint32_t *)0x40005020u) #define DMA_PROT_ADDR_ADDR (0x40005020u) #define DMA_PROT_ADDR_RESET (0x20000000u) /* DMA_PROT_OFFS field */ @@ -2735,8 +2735,8 @@ #define DMA_PROT_ADDR_DMA_PROT_ADDR_BIT (0) #define DMA_PROT_ADDR_DMA_PROT_ADDR_BITS (13) -#define DMA_PROT_CH *((volatile int32u *)0x40005024u) -#define DMA_PROT_CH_REG *((volatile int32u *)0x40005024u) +#define DMA_PROT_CH *((volatile uint32_t *)0x40005024u) +#define DMA_PROT_CH_REG *((volatile uint32_t *)0x40005024u) #define DMA_PROT_CH_ADDR (0x40005024u) #define DMA_PROT_CH_RESET (0x00000000u) /* DMA_PROT_CH field */ @@ -2745,8 +2745,8 @@ #define DMA_PROT_CH_DMA_PROT_CH_BIT (0) #define DMA_PROT_CH_DMA_PROT_CH_BITS (3) -#define MEM_PROT_EN *((volatile int32u *)0x40005028u) -#define MEM_PROT_EN_REG *((volatile int32u *)0x40005028u) +#define MEM_PROT_EN *((volatile uint32_t *)0x40005028u) +#define MEM_PROT_EN_REG *((volatile uint32_t *)0x40005028u) #define MEM_PROT_EN_ADDR (0x40005028u) #define MEM_PROT_EN_RESET (0x00000000u) /* FORCE_PROT field */ @@ -2770,8 +2770,8 @@ #define DATA_SLOW_TIMERS_END (0x40006024u) #define DATA_SLOW_TIMERS_SIZE (DATA_SLOW_TIMERS_END - DATA_SLOW_TIMERS_BASE + 1) -#define WDOG_CFG *((volatile int32u *)0x40006000u) -#define WDOG_CFG_REG *((volatile int32u *)0x40006000u) +#define WDOG_CFG *((volatile uint32_t *)0x40006000u) +#define WDOG_CFG_REG *((volatile uint32_t *)0x40006000u) #define WDOG_CFG_ADDR (0x40006000u) #define WDOG_CFG_RESET (0x00000002u) /* WDOG_DISABLE field */ @@ -2785,8 +2785,8 @@ #define WDOG_ENABLE_BIT (0) #define WDOG_ENABLE_BITS (1) -#define WDOG_KEY *((volatile int32u *)0x40006004u) -#define WDOG_KEY_REG *((volatile int32u *)0x40006004u) +#define WDOG_KEY *((volatile uint32_t *)0x40006004u) +#define WDOG_KEY_REG *((volatile uint32_t *)0x40006004u) #define WDOG_KEY_ADDR (0x40006004u) #define WDOG_KEY_RESET (0x00000000u) /* WDOG_KEY_FIELD field */ @@ -2795,13 +2795,13 @@ #define WDOG_KEY_FIELD_BIT (0) #define WDOG_KEY_FIELD_BITS (16) -#define WDOG_RESET *((volatile int32u *)0x40006008u) -#define WDOG_RESET_REG *((volatile int32u *)0x40006008u) +#define WDOG_RESET *((volatile uint32_t *)0x40006008u) +#define WDOG_RESET_REG *((volatile uint32_t *)0x40006008u) #define WDOG_RESET_ADDR (0x40006008u) #define WDOG_RESET_RESET (0x00000000u) -#define SLEEPTMR_CFG *((volatile int32u *)0x4000600Cu) -#define SLEEPTMR_CFG_REG *((volatile int32u *)0x4000600Cu) +#define SLEEPTMR_CFG *((volatile uint32_t *)0x4000600Cu) +#define SLEEPTMR_CFG_REG *((volatile uint32_t *)0x4000600Cu) #define SLEEPTMR_CFG_ADDR (0x4000600Cu) #define SLEEPTMR_CFG_RESET (0x00000400u) /* SLEEPTMR_REVERSE field */ @@ -2830,8 +2830,8 @@ #define SLEEPTMR_CLKSEL_BIT (0) #define SLEEPTMR_CLKSEL_BITS (1) -#define SLEEPTMR_CNTH *((volatile int32u *)0x40006010u) -#define SLEEPTMR_CNTH_REG *((volatile int32u *)0x40006010u) +#define SLEEPTMR_CNTH *((volatile uint32_t *)0x40006010u) +#define SLEEPTMR_CNTH_REG *((volatile uint32_t *)0x40006010u) #define SLEEPTMR_CNTH_ADDR (0x40006010u) #define SLEEPTMR_CNTH_RESET (0x00000000u) /* SLEEPTMR_CNTH_FIELD field */ @@ -2840,8 +2840,8 @@ #define SLEEPTMR_CNTH_FIELD_BIT (0) #define SLEEPTMR_CNTH_FIELD_BITS (16) -#define SLEEPTMR_CNTL *((volatile int32u *)0x40006014u) -#define SLEEPTMR_CNTL_REG *((volatile int32u *)0x40006014u) +#define SLEEPTMR_CNTL *((volatile uint32_t *)0x40006014u) +#define SLEEPTMR_CNTL_REG *((volatile uint32_t *)0x40006014u) #define SLEEPTMR_CNTL_ADDR (0x40006014u) #define SLEEPTMR_CNTL_RESET (0x00000000u) /* SLEEPTMR_CNTL_FIELD field */ @@ -2850,8 +2850,8 @@ #define SLEEPTMR_CNTL_FIELD_BIT (0) #define SLEEPTMR_CNTL_FIELD_BITS (16) -#define SLEEPTMR_CMPAH *((volatile int32u *)0x40006018u) -#define SLEEPTMR_CMPAH_REG *((volatile int32u *)0x40006018u) +#define SLEEPTMR_CMPAH *((volatile uint32_t *)0x40006018u) +#define SLEEPTMR_CMPAH_REG *((volatile uint32_t *)0x40006018u) #define SLEEPTMR_CMPAH_ADDR (0x40006018u) #define SLEEPTMR_CMPAH_RESET (0x0000FFFFu) /* SLEEPTMR_CMPAH_FIELD field */ @@ -2860,8 +2860,8 @@ #define SLEEPTMR_CMPAH_FIELD_BIT (0) #define SLEEPTMR_CMPAH_FIELD_BITS (16) -#define SLEEPTMR_CMPAL *((volatile int32u *)0x4000601Cu) -#define SLEEPTMR_CMPAL_REG *((volatile int32u *)0x4000601Cu) +#define SLEEPTMR_CMPAL *((volatile uint32_t *)0x4000601Cu) +#define SLEEPTMR_CMPAL_REG *((volatile uint32_t *)0x4000601Cu) #define SLEEPTMR_CMPAL_ADDR (0x4000601Cu) #define SLEEPTMR_CMPAL_RESET (0x0000FFFFu) /* SLEEPTMR_CMPAL_FIELD field */ @@ -2870,8 +2870,8 @@ #define SLEEPTMR_CMPAL_FIELD_BIT (0) #define SLEEPTMR_CMPAL_FIELD_BITS (16) -#define SLEEPTMR_CMPBH *((volatile int32u *)0x40006020u) -#define SLEEPTMR_CMPBH_REG *((volatile int32u *)0x40006020u) +#define SLEEPTMR_CMPBH *((volatile uint32_t *)0x40006020u) +#define SLEEPTMR_CMPBH_REG *((volatile uint32_t *)0x40006020u) #define SLEEPTMR_CMPBH_ADDR (0x40006020u) #define SLEEPTMR_CMPBH_RESET (0x0000FFFFu) /* SLEEPTMR_CMPBH_FIELD field */ @@ -2880,8 +2880,8 @@ #define SLEEPTMR_CMPBH_FIELD_BIT (0) #define SLEEPTMR_CMPBH_FIELD_BITS (16) -#define SLEEPTMR_CMPBL *((volatile int32u *)0x40006024u) -#define SLEEPTMR_CMPBL_REG *((volatile int32u *)0x40006024u) +#define SLEEPTMR_CMPBL *((volatile uint32_t *)0x40006024u) +#define SLEEPTMR_CMPBL_REG *((volatile uint32_t *)0x40006024u) #define SLEEPTMR_CMPBL_ADDR (0x40006024u) #define SLEEPTMR_CMPBL_RESET (0x0000FFFFu) /* SLEEPTMR_CMPBL_FIELD field */ @@ -2895,8 +2895,8 @@ #define DATA_CAL_ADC_END (0x40007004u) #define DATA_CAL_ADC_SIZE (DATA_CAL_ADC_END - DATA_CAL_ADC_BASE + 1) -#define CAL_ADC_DATA *((volatile int32u *)0x40007000u) -#define CAL_ADC_DATA_REG *((volatile int32u *)0x40007000u) +#define CAL_ADC_DATA *((volatile uint32_t *)0x40007000u) +#define CAL_ADC_DATA_REG *((volatile uint32_t *)0x40007000u) #define CAL_ADC_DATA_ADDR (0x40007000u) #define CAL_ADC_DATA_RESET (0x00000000u) /* CAL_ADC_DATA field */ @@ -2905,8 +2905,8 @@ #define CAL_ADC_DATA_CAL_ADC_DATA_BIT (0) #define CAL_ADC_DATA_CAL_ADC_DATA_BITS (16) -#define CAL_ADC_CONFIG *((volatile int32u *)0x40007004u) -#define CAL_ADC_CONFIG_REG *((volatile int32u *)0x40007004u) +#define CAL_ADC_CONFIG *((volatile uint32_t *)0x40007004u) +#define CAL_ADC_CONFIG_REG *((volatile uint32_t *)0x40007004u) #define CAL_ADC_CONFIG_ADDR (0x40007004u) #define CAL_ADC_CONFIG_RESET (0x00000000u) /* CAL_ADC_RATE field */ @@ -2940,8 +2940,8 @@ #define DATA_FLASH_CONTROL_END (0x40008084u) #define DATA_FLASH_CONTROL_SIZE (DATA_FLASH_CONTROL_END - DATA_FLASH_CONTROL_BASE + 1) -#define FLASH_ACCESS *((volatile int32u *)0x40008000u) -#define FLASH_ACCESS_REG *((volatile int32u *)0x40008000u) +#define FLASH_ACCESS *((volatile uint32_t *)0x40008000u) +#define FLASH_ACCESS_REG *((volatile uint32_t *)0x40008000u) #define FLASH_ACCESS_ADDR (0x40008000u) #define FLASH_ACCESS_RESET (0x00000031u) /* PREFETCH_STATUS field */ @@ -2965,8 +2965,8 @@ #define FLASH_ACCESS_CODE_LATENCY_BIT (0) #define FLASH_ACCESS_CODE_LATENCY_BITS (3) -#define FPEC_KEY *((volatile int32u *)0x40008004u) -#define FPEC_KEY_REG *((volatile int32u *)0x40008004u) +#define FPEC_KEY *((volatile uint32_t *)0x40008004u) +#define FPEC_KEY_REG *((volatile uint32_t *)0x40008004u) #define FPEC_KEY_ADDR (0x40008004u) #define FPEC_KEY_RESET (0x00000000u) /* FKEYR field */ @@ -2975,8 +2975,8 @@ #define FPEC_KEY_FKEYR_BIT (0) #define FPEC_KEY_FKEYR_BITS (32) -#define OPT_KEY *((volatile int32u *)0x40008008u) -#define OPT_KEY_REG *((volatile int32u *)0x40008008u) +#define OPT_KEY *((volatile uint32_t *)0x40008008u) +#define OPT_KEY_REG *((volatile uint32_t *)0x40008008u) #define OPT_KEY_ADDR (0x40008008u) #define OPT_KEY_RESET (0x00000000u) /* OPTKEYR field */ @@ -2985,8 +2985,8 @@ #define OPT_KEY_OPTKEYR_BIT (0) #define OPT_KEY_OPTKEYR_BITS (32) -#define FLASH_STATUS *((volatile int32u *)0x4000800Cu) -#define FLASH_STATUS_REG *((volatile int32u *)0x4000800Cu) +#define FLASH_STATUS *((volatile uint32_t *)0x4000800Cu) +#define FLASH_STATUS_REG *((volatile uint32_t *)0x4000800Cu) #define FLASH_STATUS_ADDR (0x4000800Cu) #define FLASH_STATUS_RESET (0x00000000u) /* EOP field */ @@ -3020,8 +3020,8 @@ #define FLASH_STATUS_FLA_BSY_BIT (0) #define FLASH_STATUS_FLA_BSY_BITS (1) -#define FLASH_CTRL *((volatile int32u *)0x40008010u) -#define FLASH_CTRL_REG *((volatile int32u *)0x40008010u) +#define FLASH_CTRL *((volatile uint32_t *)0x40008010u) +#define FLASH_CTRL_REG *((volatile uint32_t *)0x40008010u) #define FLASH_CTRL_ADDR (0x40008010u) #define FLASH_CTRL_RESET (0x00000080u) /* EOPIE field */ @@ -3090,8 +3090,8 @@ #define FLASH_CTRL_PROG_BIT (0) #define FLASH_CTRL_PROG_BITS (1) -#define FLASH_ADDR *((volatile int32u *)0x40008014u) -#define FLASH_ADDR_REG *((volatile int32u *)0x40008014u) +#define FLASH_ADDR *((volatile uint32_t *)0x40008014u) +#define FLASH_ADDR_REG *((volatile uint32_t *)0x40008014u) #define FLASH_ADDR_ADDR (0x40008014u) #define FLASH_ADDR_RESET (0x00000000u) /* FAR field */ @@ -3100,8 +3100,8 @@ #define FLASH_ADDR_FAR_BIT (0) #define FLASH_ADDR_FAR_BITS (32) -#define OPT_BYTE *((volatile int32u *)0x4000801Cu) -#define OPT_BYTE_REG *((volatile int32u *)0x4000801Cu) +#define OPT_BYTE *((volatile uint32_t *)0x4000801Cu) +#define OPT_BYTE_REG *((volatile uint32_t *)0x4000801Cu) #define OPT_BYTE_ADDR (0x4000801Cu) #define OPT_BYTE_RESET (0xFBFFFFFEu) /* RSVD field */ @@ -3125,8 +3125,8 @@ #define OPT_BYTE_OPT_ERR_BIT (0) #define OPT_BYTE_OPT_ERR_BITS (1) -#define WRPROT *((volatile int32u *)0x40008020u) -#define WRPROT_REG *((volatile int32u *)0x40008020u) +#define WRPROT *((volatile uint32_t *)0x40008020u) +#define WRPROT_REG *((volatile uint32_t *)0x40008020u) #define WRPROT_ADDR (0x40008020u) #define WRPROT_RESET (0xFFFFFFFFu) /* WRP field */ @@ -3135,8 +3135,8 @@ #define WRPROT_WRP_BIT (0) #define WRPROT_WRP_BITS (32) -#define FLASH_TEST_CTRL *((volatile int32u *)0x40008080u) -#define FLASH_TEST_CTRL_REG *((volatile int32u *)0x40008080u) +#define FLASH_TEST_CTRL *((volatile uint32_t *)0x40008080u) +#define FLASH_TEST_CTRL_REG *((volatile uint32_t *)0x40008080u) #define FLASH_TEST_CTRL_ADDR (0x40008080u) #define FLASH_TEST_CTRL_RESET (0x00000000u) /* TMR field */ @@ -3200,8 +3200,8 @@ #define FLASH_TEST_CTRL_SW_EN_BIT (0) #define FLASH_TEST_CTRL_SW_EN_BITS (1) -#define FLASH_DATA0 *((volatile int32u *)0x40008084u) -#define FLASH_DATA0_REG *((volatile int32u *)0x40008084u) +#define FLASH_DATA0 *((volatile uint32_t *)0x40008084u) +#define FLASH_DATA0_REG *((volatile uint32_t *)0x40008084u) #define FLASH_DATA0_ADDR (0x40008084u) #define FLASH_DATA0_RESET (0xFFFFFFFFu) /* FDR0 field */ @@ -3215,8 +3215,8 @@ #define DATA_EMU_REGS_END (0x40009000u) #define DATA_EMU_REGS_SIZE (DATA_EMU_REGS_END - DATA_EMU_REGS_BASE + 1) -#define I_AM_AN_EMULATOR *((volatile int32u *)0x40009000u) -#define I_AM_AN_EMULATOR_REG *((volatile int32u *)0x40009000u) +#define I_AM_AN_EMULATOR *((volatile uint32_t *)0x40009000u) +#define I_AM_AN_EMULATOR_REG *((volatile uint32_t *)0x40009000u) #define I_AM_AN_EMULATOR_ADDR (0x40009000u) #define I_AM_AN_EMULATOR_RESET (0x00000000u) /* I_AM_AN_EMULATOR field */ @@ -3230,8 +3230,8 @@ #define BLOCK_INTERRUPTS_END (0x4000A86Cu) #define BLOCK_INTERRUPTS_SIZE (BLOCK_INTERRUPTS_END - BLOCK_INTERRUPTS_BASE + 1) -#define MAC_RX_INT_SRC *((volatile int32u *)0x4000A000u) -#define MAC_RX_INT_SRC_REG *((volatile int32u *)0x4000A000u) +#define MAC_RX_INT_SRC *((volatile uint32_t *)0x4000A000u) +#define MAC_RX_INT_SRC_REG *((volatile uint32_t *)0x4000A000u) #define MAC_RX_INT_SRC_ADDR (0x4000A000u) #define MAC_RX_INT_SRC_RESET (0x00000000u) /* TX_B_ACK_ERR_SRC field */ @@ -3315,8 +3315,8 @@ #define MAC_RX_INT_SRC_RX_FRAME_SRC_BIT (0) #define MAC_RX_INT_SRC_RX_FRAME_SRC_BITS (1) -#define MAC_TX_INT_SRC *((volatile int32u *)0x4000A004u) -#define MAC_TX_INT_SRC_REG *((volatile int32u *)0x4000A004u) +#define MAC_TX_INT_SRC *((volatile uint32_t *)0x4000A004u) +#define MAC_TX_INT_SRC_REG *((volatile uint32_t *)0x4000A004u) #define MAC_TX_INT_SRC_ADDR (0x4000A004u) #define MAC_TX_INT_SRC_RESET (0x00000000u) /* RX_B_ACK_SRC field */ @@ -3380,8 +3380,8 @@ #define MAC_TX_INT_SRC_TX_COMPLETE_SRC_BIT (0) #define MAC_TX_INT_SRC_TX_COMPLETE_SRC_BITS (1) -#define MAC_TIMER_INT_SRC *((volatile int32u *)0x4000A008u) -#define MAC_TIMER_INT_SRC_REG *((volatile int32u *)0x4000A008u) +#define MAC_TIMER_INT_SRC *((volatile uint32_t *)0x4000A008u) +#define MAC_TIMER_INT_SRC_REG *((volatile uint32_t *)0x4000A008u) #define MAC_TIMER_INT_SRC_ADDR (0x4000A008u) #define MAC_TIMER_INT_SRC_RESET (0x00000000u) /* TIMER_COMP_B_SRC field */ @@ -3400,8 +3400,8 @@ #define MAC_TIMER_INT_SRC_TIMER_WRAP_SRC_BIT (0) #define MAC_TIMER_INT_SRC_TIMER_WRAP_SRC_BITS (1) -#define BB_INT_SRC *((volatile int32u *)0x4000A00Cu) -#define BB_INT_SRC_REG *((volatile int32u *)0x4000A00Cu) +#define BB_INT_SRC *((volatile uint32_t *)0x4000A00Cu) +#define BB_INT_SRC_REG *((volatile uint32_t *)0x4000A00Cu) #define BB_INT_SRC_ADDR (0x4000A00Cu) #define BB_INT_SRC_RESET (0x00000000u) /* RSSI_INT_SRC field */ @@ -3415,8 +3415,8 @@ #define BB_INT_SRC_BASEBAND_INT_SRC_BIT (0) #define BB_INT_SRC_BASEBAND_INT_SRC_BITS (1) -#define SEC_INT_SRC *((volatile int32u *)0x4000A010u) -#define SEC_INT_SRC_REG *((volatile int32u *)0x4000A010u) +#define SEC_INT_SRC *((volatile uint32_t *)0x4000A010u) +#define SEC_INT_SRC_REG *((volatile uint32_t *)0x4000A010u) #define SEC_INT_SRC_ADDR (0x4000A010u) #define SEC_INT_SRC_RESET (0x00000000u) /* CT_WORD_VALID_SRC field */ @@ -3435,8 +3435,8 @@ #define SEC_INT_SRC_ENC_COMPLETE_SRC_BIT (0) #define SEC_INT_SRC_ENC_COMPLETE_SRC_BITS (1) -#define INT_SLEEPTMRFLAG *((volatile int32u *)0x4000A014u) -#define INT_SLEEPTMRFLAG_REG *((volatile int32u *)0x4000A014u) +#define INT_SLEEPTMRFLAG *((volatile uint32_t *)0x4000A014u) +#define INT_SLEEPTMRFLAG_REG *((volatile uint32_t *)0x4000A014u) #define INT_SLEEPTMRFLAG_ADDR (0x4000A014u) #define INT_SLEEPTMRFLAG_RESET (0x00000000u) /* INT_SLEEPTMRCMPB field */ @@ -3455,8 +3455,8 @@ #define INT_SLEEPTMRWRAP_BIT (0) #define INT_SLEEPTMRWRAP_BITS (1) -#define INT_MGMTFLAG *((volatile int32u *)0x4000A018u) -#define INT_MGMTFLAG_REG *((volatile int32u *)0x4000A018u) +#define INT_MGMTFLAG *((volatile uint32_t *)0x4000A018u) +#define INT_MGMTFLAG_REG *((volatile uint32_t *)0x4000A018u) #define INT_MGMTFLAG_ADDR (0x4000A018u) #define INT_MGMTFLAG_RESET (0x00000000u) /* INT_MGMTDMAPROT field */ @@ -3485,8 +3485,8 @@ #define INT_MGMTOSC24MLO_BIT (0) #define INT_MGMTOSC24MLO_BITS (1) -#define INT_NMIFLAG *((volatile int32u *)0x4000A01Cu) -#define INT_NMIFLAG_REG *((volatile int32u *)0x4000A01Cu) +#define INT_NMIFLAG *((volatile uint32_t *)0x4000A01Cu) +#define INT_NMIFLAG_REG *((volatile uint32_t *)0x4000A01Cu) #define INT_NMIFLAG_ADDR (0x4000A01Cu) #define INT_NMIFLAG_RESET (0x00000000u) /* INT_NMICLK24M field */ @@ -3500,8 +3500,8 @@ #define INT_NMIWDOG_BIT (0) #define INT_NMIWDOG_BITS (1) -#define INT_SLEEPTMRFORCE *((volatile int32u *)0x4000A020u) -#define INT_SLEEPTMRFORCE_REG *((volatile int32u *)0x4000A020u) +#define INT_SLEEPTMRFORCE *((volatile uint32_t *)0x4000A020u) +#define INT_SLEEPTMRFORCE_REG *((volatile uint32_t *)0x4000A020u) #define INT_SLEEPTMRFORCE_ADDR (0x4000A020u) #define INT_SLEEPTMRFORCE_RESET (0x00000000u) /* INT_SLEEPTMRCMPB field */ @@ -3520,8 +3520,8 @@ #define INT_SLEEPTMRWRAP_BIT (0) #define INT_SLEEPTMRWRAP_BITS (1) -#define TEST_FORCE_ALL_INT *((volatile int32u *)0x4000A024u) -#define TEST_FORCE_ALL_INT_REG *((volatile int32u *)0x4000A024u) +#define TEST_FORCE_ALL_INT *((volatile uint32_t *)0x4000A024u) +#define TEST_FORCE_ALL_INT_REG *((volatile uint32_t *)0x4000A024u) #define TEST_FORCE_ALL_INT_ADDR (0x4000A024u) #define TEST_FORCE_ALL_INT_RESET (0x00000000u) /* FORCE_ALL_INT field */ @@ -3530,8 +3530,8 @@ #define TEST_FORCE_ALL_INT_FORCE_ALL_INT_BIT (0) #define TEST_FORCE_ALL_INT_FORCE_ALL_INT_BITS (1) -#define MAC_RX_INT_MASK *((volatile int32u *)0x4000A040u) -#define MAC_RX_INT_MASK_REG *((volatile int32u *)0x4000A040u) +#define MAC_RX_INT_MASK *((volatile uint32_t *)0x4000A040u) +#define MAC_RX_INT_MASK_REG *((volatile uint32_t *)0x4000A040u) #define MAC_RX_INT_MASK_ADDR (0x4000A040u) #define MAC_RX_INT_MASK_RESET (0x00000000u) /* TX_B_ACK_ERR_MSK field */ @@ -3615,8 +3615,8 @@ #define MAC_RX_INT_MASK_RX_FRAME_MSK_BIT (0) #define MAC_RX_INT_MASK_RX_FRAME_MSK_BITS (1) -#define MAC_TX_INT_MASK *((volatile int32u *)0x4000A044u) -#define MAC_TX_INT_MASK_REG *((volatile int32u *)0x4000A044u) +#define MAC_TX_INT_MASK *((volatile uint32_t *)0x4000A044u) +#define MAC_TX_INT_MASK_REG *((volatile uint32_t *)0x4000A044u) #define MAC_TX_INT_MASK_ADDR (0x4000A044u) #define MAC_TX_INT_MASK_RESET (0x00000000u) /* RX_B_ACK_MSK field */ @@ -3680,8 +3680,8 @@ #define MAC_TX_INT_MASK_TX_COMPLETE_MSK_BIT (0) #define MAC_TX_INT_MASK_TX_COMPLETE_MSK_BITS (1) -#define MAC_TIMER_INT_MASK *((volatile int32u *)0x4000A048u) -#define MAC_TIMER_INT_MASK_REG *((volatile int32u *)0x4000A048u) +#define MAC_TIMER_INT_MASK *((volatile uint32_t *)0x4000A048u) +#define MAC_TIMER_INT_MASK_REG *((volatile uint32_t *)0x4000A048u) #define MAC_TIMER_INT_MASK_ADDR (0x4000A048u) #define MAC_TIMER_INT_MASK_RESET (0x00000000u) /* TIMER_COMP_B_MSK field */ @@ -3700,8 +3700,8 @@ #define MAC_TIMER_INT_MASK_TIMER_WRAP_MSK_BIT (0) #define MAC_TIMER_INT_MASK_TIMER_WRAP_MSK_BITS (1) -#define BB_INT_MASK *((volatile int32u *)0x4000A04Cu) -#define BB_INT_MASK_REG *((volatile int32u *)0x4000A04Cu) +#define BB_INT_MASK *((volatile uint32_t *)0x4000A04Cu) +#define BB_INT_MASK_REG *((volatile uint32_t *)0x4000A04Cu) #define BB_INT_MASK_ADDR (0x4000A04Cu) #define BB_INT_MASK_RESET (0x00000000u) /* RSSI_INT_MSK field */ @@ -3715,8 +3715,8 @@ #define BB_INT_MASK_BASEBAND_INT_MSK_BIT (0) #define BB_INT_MASK_BASEBAND_INT_MSK_BITS (1) -#define SEC_INT_MASK *((volatile int32u *)0x4000A050u) -#define SEC_INT_MASK_REG *((volatile int32u *)0x4000A050u) +#define SEC_INT_MASK *((volatile uint32_t *)0x4000A050u) +#define SEC_INT_MASK_REG *((volatile uint32_t *)0x4000A050u) #define SEC_INT_MASK_ADDR (0x4000A050u) #define SEC_INT_MASK_RESET (0x00000000u) /* CT_WORD_VALID_MSK field */ @@ -3735,8 +3735,8 @@ #define SEC_INT_MASK_ENC_COMPLETE_MSK_BIT (0) #define SEC_INT_MASK_ENC_COMPLETE_MSK_BITS (1) -#define INT_SLEEPTMRCFG *((volatile int32u *)0x4000A054u) -#define INT_SLEEPTMRCFG_REG *((volatile int32u *)0x4000A054u) +#define INT_SLEEPTMRCFG *((volatile uint32_t *)0x4000A054u) +#define INT_SLEEPTMRCFG_REG *((volatile uint32_t *)0x4000A054u) #define INT_SLEEPTMRCFG_ADDR (0x4000A054u) #define INT_SLEEPTMRCFG_RESET (0x00000000u) /* INT_SLEEPTMRCMPB field */ @@ -3755,8 +3755,8 @@ #define INT_SLEEPTMRWRAP_BIT (0) #define INT_SLEEPTMRWRAP_BITS (1) -#define INT_MGMTCFG *((volatile int32u *)0x4000A058u) -#define INT_MGMTCFG_REG *((volatile int32u *)0x4000A058u) +#define INT_MGMTCFG *((volatile uint32_t *)0x4000A058u) +#define INT_MGMTCFG_REG *((volatile uint32_t *)0x4000A058u) #define INT_MGMTCFG_ADDR (0x4000A058u) #define INT_MGMTCFG_RESET (0x00000000u) /* INT_MGMTDMAPROT field */ @@ -3785,8 +3785,8 @@ #define INT_MGMTOSC24MLO_BIT (0) #define INT_MGMTOSC24MLO_BITS (1) -#define INT_TIM1FLAG *((volatile int32u *)0x4000A800u) -#define INT_TIM1FLAG_REG *((volatile int32u *)0x4000A800u) +#define INT_TIM1FLAG *((volatile uint32_t *)0x4000A800u) +#define INT_TIM1FLAG_REG *((volatile uint32_t *)0x4000A800u) #define INT_TIM1FLAG_ADDR (0x4000A800u) #define INT_TIM1FLAG_RESET (0x00000000u) /* INT_TIMRSVD field */ @@ -3825,8 +3825,8 @@ #define INT_TIMUIF_BIT (0) #define INT_TIMUIF_BITS (1) -#define INT_TIM2FLAG *((volatile int32u *)0x4000A804u) -#define INT_TIM2FLAG_REG *((volatile int32u *)0x4000A804u) +#define INT_TIM2FLAG *((volatile uint32_t *)0x4000A804u) +#define INT_TIM2FLAG_REG *((volatile uint32_t *)0x4000A804u) #define INT_TIM2FLAG_ADDR (0x4000A804u) #define INT_TIM2FLAG_RESET (0x00000000u) /* INT_TIMRSVD field */ @@ -3865,8 +3865,8 @@ #define INT_TIMUIF_BIT (0) #define INT_TIMUIF_BITS (1) -#define INT_SC1FLAG *((volatile int32u *)0x4000A808u) -#define INT_SC1FLAG_REG *((volatile int32u *)0x4000A808u) +#define INT_SC1FLAG *((volatile uint32_t *)0x4000A808u) +#define INT_SC1FLAG_REG *((volatile uint32_t *)0x4000A808u) #define INT_SC1FLAG_ADDR (0x4000A808u) #define INT_SC1FLAG_RESET (0x00000000u) /* INT_SC1PARERR field */ @@ -3945,8 +3945,8 @@ #define INT_SCRXVAL_BIT (0) #define INT_SCRXVAL_BITS (1) -#define INT_SC2FLAG *((volatile int32u *)0x4000A80Cu) -#define INT_SC2FLAG_REG *((volatile int32u *)0x4000A80Cu) +#define INT_SC2FLAG *((volatile uint32_t *)0x4000A80Cu) +#define INT_SC2FLAG_REG *((volatile uint32_t *)0x4000A80Cu) #define INT_SC2FLAG_ADDR (0x4000A80Cu) #define INT_SC2FLAG_RESET (0x00000000u) /* INT_SCTXULDB field */ @@ -4015,8 +4015,8 @@ #define INT_SCRXVAL_BIT (0) #define INT_SCRXVAL_BITS (1) -#define INT_ADCFLAG *((volatile int32u *)0x4000A810u) -#define INT_ADCFLAG_REG *((volatile int32u *)0x4000A810u) +#define INT_ADCFLAG *((volatile uint32_t *)0x4000A810u) +#define INT_ADCFLAG_REG *((volatile uint32_t *)0x4000A810u) #define INT_ADCFLAG_ADDR (0x4000A810u) #define INT_ADCFLAG_RESET (0x00000000u) /* INT_ADCOVF field */ @@ -4045,8 +4045,8 @@ #define INT_ADCFLAGRSVD_BIT (0) #define INT_ADCFLAGRSVD_BITS (1) -#define INT_GPIOFLAG *((volatile int32u *)0x4000A814u) -#define INT_GPIOFLAG_REG *((volatile int32u *)0x4000A814u) +#define INT_GPIOFLAG *((volatile uint32_t *)0x4000A814u) +#define INT_GPIOFLAG_REG *((volatile uint32_t *)0x4000A814u) #define INT_GPIOFLAG_ADDR (0x4000A814u) #define INT_GPIOFLAG_RESET (0x00000000u) /* INT_IRQDFLAG field */ @@ -4070,8 +4070,8 @@ #define INT_IRQAFLAG_BIT (0) #define INT_IRQAFLAG_BITS (1) -#define INT_TIM1MISS *((volatile int32u *)0x4000A818u) -#define INT_TIM1MISS_REG *((volatile int32u *)0x4000A818u) +#define INT_TIM1MISS *((volatile uint32_t *)0x4000A818u) +#define INT_TIM1MISS_REG *((volatile uint32_t *)0x4000A818u) #define INT_TIM1MISS_ADDR (0x4000A818u) #define INT_TIM1MISS_RESET (0x00000000u) /* INT_TIMMISSCC4IF field */ @@ -4100,8 +4100,8 @@ #define INT_TIMMISSRSVD_BIT (0) #define INT_TIMMISSRSVD_BITS (7) -#define INT_TIM2MISS *((volatile int32u *)0x4000A81Cu) -#define INT_TIM2MISS_REG *((volatile int32u *)0x4000A81Cu) +#define INT_TIM2MISS *((volatile uint32_t *)0x4000A81Cu) +#define INT_TIM2MISS_REG *((volatile uint32_t *)0x4000A81Cu) #define INT_TIM2MISS_ADDR (0x4000A81Cu) #define INT_TIM2MISS_RESET (0x00000000u) /* INT_TIMMISSCC4IF field */ @@ -4130,8 +4130,8 @@ #define INT_TIMMISSRSVD_BIT (0) #define INT_TIMMISSRSVD_BITS (7) -#define INT_MISS *((volatile int32u *)0x4000A820u) -#define INT_MISS_REG *((volatile int32u *)0x4000A820u) +#define INT_MISS *((volatile uint32_t *)0x4000A820u) +#define INT_MISS_REG *((volatile uint32_t *)0x4000A820u) #define INT_MISS_ADDR (0x4000A820u) #define INT_MISS_RESET (0x00000000u) /* INT_MISSIRQD field */ @@ -4205,8 +4205,8 @@ #define INT_MISSMGMT_BIT (2) #define INT_MISSMGMT_BITS (1) -#define INT_TIM1CFG *((volatile int32u *)0x4000A840u) -#define INT_TIM1CFG_REG *((volatile int32u *)0x4000A840u) +#define INT_TIM1CFG *((volatile uint32_t *)0x4000A840u) +#define INT_TIM1CFG_REG *((volatile uint32_t *)0x4000A840u) #define INT_TIM1CFG_ADDR (0x4000A840u) #define INT_TIM1CFG_RESET (0x00000000u) /* INT_TIMTIF field */ @@ -4240,8 +4240,8 @@ #define INT_TIMUIF_BIT (0) #define INT_TIMUIF_BITS (1) -#define INT_TIM2CFG *((volatile int32u *)0x4000A844u) -#define INT_TIM2CFG_REG *((volatile int32u *)0x4000A844u) +#define INT_TIM2CFG *((volatile uint32_t *)0x4000A844u) +#define INT_TIM2CFG_REG *((volatile uint32_t *)0x4000A844u) #define INT_TIM2CFG_ADDR (0x4000A844u) #define INT_TIM2CFG_RESET (0x00000000u) /* INT_TIMTIF field */ @@ -4275,8 +4275,8 @@ #define INT_TIMUIF_BIT (0) #define INT_TIMUIF_BITS (1) -#define INT_SC1CFG *((volatile int32u *)0x4000A848u) -#define INT_SC1CFG_REG *((volatile int32u *)0x4000A848u) +#define INT_SC1CFG *((volatile uint32_t *)0x4000A848u) +#define INT_SC1CFG_REG *((volatile uint32_t *)0x4000A848u) #define INT_SC1CFG_ADDR (0x4000A848u) #define INT_SC1CFG_RESET (0x00000000u) /* INT_SC1PARERR field */ @@ -4355,8 +4355,8 @@ #define INT_SCRXVAL_BIT (0) #define INT_SCRXVAL_BITS (1) -#define INT_SC2CFG *((volatile int32u *)0x4000A84Cu) -#define INT_SC2CFG_REG *((volatile int32u *)0x4000A84Cu) +#define INT_SC2CFG *((volatile uint32_t *)0x4000A84Cu) +#define INT_SC2CFG_REG *((volatile uint32_t *)0x4000A84Cu) #define INT_SC2CFG_ADDR (0x4000A84Cu) #define INT_SC2CFG_RESET (0x00000000u) /* INT_SCTXULDB field */ @@ -4425,8 +4425,8 @@ #define INT_SCRXVAL_BIT (0) #define INT_SCRXVAL_BITS (1) -#define INT_ADCCFG *((volatile int32u *)0x4000A850u) -#define INT_ADCCFG_REG *((volatile int32u *)0x4000A850u) +#define INT_ADCCFG *((volatile uint32_t *)0x4000A850u) +#define INT_ADCCFG_REG *((volatile uint32_t *)0x4000A850u) #define INT_ADCCFG_ADDR (0x4000A850u) #define INT_ADCCFG_RESET (0x00000000u) /* INT_ADCOVF field */ @@ -4455,8 +4455,8 @@ #define INT_ADCCFGRSVD_BIT (0) #define INT_ADCCFGRSVD_BITS (1) -#define SC1_INTMODE *((volatile int32u *)0x4000A854u) -#define SC1_INTMODE_REG *((volatile int32u *)0x4000A854u) +#define SC1_INTMODE *((volatile uint32_t *)0x4000A854u) +#define SC1_INTMODE_REG *((volatile uint32_t *)0x4000A854u) #define SC1_INTMODE_ADDR (0x4000A854u) #define SC1_INTMODE_RESET (0x00000000u) /* SC_TXIDLELEVEL field */ @@ -4475,8 +4475,8 @@ #define SC_RXVALLEVEL_BIT (0) #define SC_RXVALLEVEL_BITS (1) -#define SC2_INTMODE *((volatile int32u *)0x4000A858u) -#define SC2_INTMODE_REG *((volatile int32u *)0x4000A858u) +#define SC2_INTMODE *((volatile uint32_t *)0x4000A858u) +#define SC2_INTMODE_REG *((volatile uint32_t *)0x4000A858u) #define SC2_INTMODE_ADDR (0x4000A858u) #define SC2_INTMODE_RESET (0x00000000u) /* SC_TXIDLELEVEL field */ @@ -4495,8 +4495,8 @@ #define SC_RXVALLEVEL_BIT (0) #define SC_RXVALLEVEL_BITS (1) -#define GPIO_INTCFGA *((volatile int32u *)0x4000A860u) -#define GPIO_INTCFGA_REG *((volatile int32u *)0x4000A860u) +#define GPIO_INTCFGA *((volatile uint32_t *)0x4000A860u) +#define GPIO_INTCFGA_REG *((volatile uint32_t *)0x4000A860u) #define GPIO_INTCFGA_ADDR (0x4000A860u) #define GPIO_INTCFGA_RESET (0x00000000u) /* GPIO_INTFILT field */ @@ -4510,8 +4510,8 @@ #define GPIO_INTMOD_BIT (5) #define GPIO_INTMOD_BITS (3) -#define GPIO_INTCFGB *((volatile int32u *)0x4000A864u) -#define GPIO_INTCFGB_REG *((volatile int32u *)0x4000A864u) +#define GPIO_INTCFGB *((volatile uint32_t *)0x4000A864u) +#define GPIO_INTCFGB_REG *((volatile uint32_t *)0x4000A864u) #define GPIO_INTCFGB_ADDR (0x4000A864u) #define GPIO_INTCFGB_RESET (0x00000000u) /* GPIO_INTFILT field */ @@ -4525,8 +4525,8 @@ #define GPIO_INTMOD_BIT (5) #define GPIO_INTMOD_BITS (3) -#define GPIO_INTCFGC *((volatile int32u *)0x4000A868u) -#define GPIO_INTCFGC_REG *((volatile int32u *)0x4000A868u) +#define GPIO_INTCFGC *((volatile uint32_t *)0x4000A868u) +#define GPIO_INTCFGC_REG *((volatile uint32_t *)0x4000A868u) #define GPIO_INTCFGC_ADDR (0x4000A868u) #define GPIO_INTCFGC_RESET (0x00000000u) /* GPIO_INTFILT field */ @@ -4540,8 +4540,8 @@ #define GPIO_INTMOD_BIT (5) #define GPIO_INTMOD_BITS (3) -#define GPIO_INTCFGD *((volatile int32u *)0x4000A86Cu) -#define GPIO_INTCFGD_REG *((volatile int32u *)0x4000A86Cu) +#define GPIO_INTCFGD *((volatile uint32_t *)0x4000A86Cu) +#define GPIO_INTCFGD_REG *((volatile uint32_t *)0x4000A86Cu) #define GPIO_INTCFGD_ADDR (0x4000A86Cu) #define GPIO_INTCFGD_RESET (0x00000000u) /* GPIO_INTFILT field */ @@ -4560,8 +4560,8 @@ #define BLOCK_GPIO_END (0x4000BC1Cu) #define BLOCK_GPIO_SIZE (BLOCK_GPIO_END - BLOCK_GPIO_BASE + 1) -#define GPIO_PACFGL *((volatile int32u *)0x4000B000u) -#define GPIO_PACFGL_REG *((volatile int32u *)0x4000B000u) +#define GPIO_PACFGL *((volatile uint32_t *)0x4000B000u) +#define GPIO_PACFGL_REG *((volatile uint32_t *)0x4000B000u) #define GPIO_PACFGL_ADDR (0x4000B000u) #define GPIO_PACFGL_RESET (0x00004444u) /* PA3_CFG field */ @@ -4593,8 +4593,8 @@ #define GPIOCFG_IN (0x4u) #define GPIOCFG_IN_PUD (0x8u) -#define GPIO_PACFGH *((volatile int32u *)0x4000B004u) -#define GPIO_PACFGH_REG *((volatile int32u *)0x4000B004u) +#define GPIO_PACFGH *((volatile uint32_t *)0x4000B004u) +#define GPIO_PACFGH_REG *((volatile uint32_t *)0x4000B004u) #define GPIO_PACFGH_ADDR (0x4000B004u) #define GPIO_PACFGH_RESET (0x00004444u) /* PA7_CFG field */ @@ -4618,8 +4618,8 @@ #define PA4_CFG_BIT (0) #define PA4_CFG_BITS (4) -#define GPIO_PAIN *((volatile int32u *)0x4000B008u) -#define GPIO_PAIN_REG *((volatile int32u *)0x4000B008u) +#define GPIO_PAIN *((volatile uint32_t *)0x4000B008u) +#define GPIO_PAIN_REG *((volatile uint32_t *)0x4000B008u) #define GPIO_PAIN_ADDR (0x4000B008u) #define GPIO_PAIN_RESET (0x00000000u) /* PA7 field */ @@ -4663,8 +4663,8 @@ #define PA0_BIT (0) #define PA0_BITS (1) -#define GPIO_PAOUT *((volatile int32u *)0x4000B00Cu) -#define GPIO_PAOUT_REG *((volatile int32u *)0x4000B00Cu) +#define GPIO_PAOUT *((volatile uint32_t *)0x4000B00Cu) +#define GPIO_PAOUT_REG *((volatile uint32_t *)0x4000B00Cu) #define GPIO_PAOUT_ADDR (0x4000B00Cu) #define GPIO_PAOUT_RESET (0x00000000u) /* PA7 field */ @@ -4711,8 +4711,8 @@ #define GPIOOUT_PULLUP (0x1u) #define GPIOOUT_PULLDOWN (0x0u) -#define GPIO_PASET *((volatile int32u *)0x4000B010u) -#define GPIO_PASET_REG *((volatile int32u *)0x4000B010u) +#define GPIO_PASET *((volatile uint32_t *)0x4000B010u) +#define GPIO_PASET_REG *((volatile uint32_t *)0x4000B010u) #define GPIO_PASET_ADDR (0x4000B010u) #define GPIO_PASET_RESET (0x00000000u) /* GPIO_PXSETRSVD field */ @@ -4761,8 +4761,8 @@ #define PA0_BIT (0) #define PA0_BITS (1) -#define GPIO_PACLR *((volatile int32u *)0x4000B014u) -#define GPIO_PACLR_REG *((volatile int32u *)0x4000B014u) +#define GPIO_PACLR *((volatile uint32_t *)0x4000B014u) +#define GPIO_PACLR_REG *((volatile uint32_t *)0x4000B014u) #define GPIO_PACLR_ADDR (0x4000B014u) #define GPIO_PACLR_RESET (0x00000000u) /* PA7 field */ @@ -4806,8 +4806,8 @@ #define PA0_BIT (0) #define PA0_BITS (1) -#define GPIO_PBCFGL *((volatile int32u *)0x4000B400u) -#define GPIO_PBCFGL_REG *((volatile int32u *)0x4000B400u) +#define GPIO_PBCFGL *((volatile uint32_t *)0x4000B400u) +#define GPIO_PBCFGL_REG *((volatile uint32_t *)0x4000B400u) #define GPIO_PBCFGL_ADDR (0x4000B400u) #define GPIO_PBCFGL_RESET (0x00004444u) /* PB3_CFG field */ @@ -4831,8 +4831,8 @@ #define PB0_CFG_BIT (0) #define PB0_CFG_BITS (4) -#define GPIO_PBCFGH *((volatile int32u *)0x4000B404u) -#define GPIO_PBCFGH_REG *((volatile int32u *)0x4000B404u) +#define GPIO_PBCFGH *((volatile uint32_t *)0x4000B404u) +#define GPIO_PBCFGH_REG *((volatile uint32_t *)0x4000B404u) #define GPIO_PBCFGH_ADDR (0x4000B404u) #define GPIO_PBCFGH_RESET (0x00004444u) /* PB7_CFG field */ @@ -4856,8 +4856,8 @@ #define PB4_CFG_BIT (0) #define PB4_CFG_BITS (4) -#define GPIO_PBIN *((volatile int32u *)0x4000B408u) -#define GPIO_PBIN_REG *((volatile int32u *)0x4000B408u) +#define GPIO_PBIN *((volatile uint32_t *)0x4000B408u) +#define GPIO_PBIN_REG *((volatile uint32_t *)0x4000B408u) #define GPIO_PBIN_ADDR (0x4000B408u) #define GPIO_PBIN_RESET (0x00000000u) /* PB7 field */ @@ -4901,8 +4901,8 @@ #define PB0_BIT (0) #define PB0_BITS (1) -#define GPIO_PBOUT *((volatile int32u *)0x4000B40Cu) -#define GPIO_PBOUT_REG *((volatile int32u *)0x4000B40Cu) +#define GPIO_PBOUT *((volatile uint32_t *)0x4000B40Cu) +#define GPIO_PBOUT_REG *((volatile uint32_t *)0x4000B40Cu) #define GPIO_PBOUT_ADDR (0x4000B40Cu) #define GPIO_PBOUT_RESET (0x00000000u) /* PB7 field */ @@ -4946,8 +4946,8 @@ #define PB0_BIT (0) #define PB0_BITS (1) -#define GPIO_PBSET *((volatile int32u *)0x4000B410u) -#define GPIO_PBSET_REG *((volatile int32u *)0x4000B410u) +#define GPIO_PBSET *((volatile uint32_t *)0x4000B410u) +#define GPIO_PBSET_REG *((volatile uint32_t *)0x4000B410u) #define GPIO_PBSET_ADDR (0x4000B410u) #define GPIO_PBSET_RESET (0x00000000u) /* GPIO_PXSETRSVD field */ @@ -4996,8 +4996,8 @@ #define PB0_BIT (0) #define PB0_BITS (1) -#define GPIO_PBCLR *((volatile int32u *)0x4000B414u) -#define GPIO_PBCLR_REG *((volatile int32u *)0x4000B414u) +#define GPIO_PBCLR *((volatile uint32_t *)0x4000B414u) +#define GPIO_PBCLR_REG *((volatile uint32_t *)0x4000B414u) #define GPIO_PBCLR_ADDR (0x4000B414u) #define GPIO_PBCLR_RESET (0x00000000u) /* PB7 field */ @@ -5041,8 +5041,8 @@ #define PB0_BIT (0) #define PB0_BITS (1) -#define GPIO_PCCFGL *((volatile int32u *)0x4000B800u) -#define GPIO_PCCFGL_REG *((volatile int32u *)0x4000B800u) +#define GPIO_PCCFGL *((volatile uint32_t *)0x4000B800u) +#define GPIO_PCCFGL_REG *((volatile uint32_t *)0x4000B800u) #define GPIO_PCCFGL_ADDR (0x4000B800u) #define GPIO_PCCFGL_RESET (0x00004444u) /* PC3_CFG field */ @@ -5066,8 +5066,8 @@ #define PC0_CFG_BIT (0) #define PC0_CFG_BITS (4) -#define GPIO_PCCFGH *((volatile int32u *)0x4000B804u) -#define GPIO_PCCFGH_REG *((volatile int32u *)0x4000B804u) +#define GPIO_PCCFGH *((volatile uint32_t *)0x4000B804u) +#define GPIO_PCCFGH_REG *((volatile uint32_t *)0x4000B804u) #define GPIO_PCCFGH_ADDR (0x4000B804u) #define GPIO_PCCFGH_RESET (0x00004444u) /* PC7_CFG field */ @@ -5091,8 +5091,8 @@ #define PC4_CFG_BIT (0) #define PC4_CFG_BITS (4) -#define GPIO_PCIN *((volatile int32u *)0x4000B808u) -#define GPIO_PCIN_REG *((volatile int32u *)0x4000B808u) +#define GPIO_PCIN *((volatile uint32_t *)0x4000B808u) +#define GPIO_PCIN_REG *((volatile uint32_t *)0x4000B808u) #define GPIO_PCIN_ADDR (0x4000B808u) #define GPIO_PCIN_RESET (0x00000000u) /* PC7 field */ @@ -5136,8 +5136,8 @@ #define PC0_BIT (0) #define PC0_BITS (1) -#define GPIO_PCOUT *((volatile int32u *)0x4000B80Cu) -#define GPIO_PCOUT_REG *((volatile int32u *)0x4000B80Cu) +#define GPIO_PCOUT *((volatile uint32_t *)0x4000B80Cu) +#define GPIO_PCOUT_REG *((volatile uint32_t *)0x4000B80Cu) #define GPIO_PCOUT_ADDR (0x4000B80Cu) #define GPIO_PCOUT_RESET (0x00000000u) /* PC7 field */ @@ -5181,8 +5181,8 @@ #define PC0_BIT (0) #define PC0_BITS (1) -#define GPIO_PCSET *((volatile int32u *)0x4000B810u) -#define GPIO_PCSET_REG *((volatile int32u *)0x4000B810u) +#define GPIO_PCSET *((volatile uint32_t *)0x4000B810u) +#define GPIO_PCSET_REG *((volatile uint32_t *)0x4000B810u) #define GPIO_PCSET_ADDR (0x4000B810u) #define GPIO_PCSET_RESET (0x00000000u) /* GPIO_PXSETRSVD field */ @@ -5231,8 +5231,8 @@ #define PC0_BIT (0) #define PC0_BITS (1) -#define GPIO_PCCLR *((volatile int32u *)0x4000B814u) -#define GPIO_PCCLR_REG *((volatile int32u *)0x4000B814u) +#define GPIO_PCCLR *((volatile uint32_t *)0x4000B814u) +#define GPIO_PCCLR_REG *((volatile uint32_t *)0x4000B814u) #define GPIO_PCCLR_ADDR (0x4000B814u) #define GPIO_PCCLR_RESET (0x00000000u) /* PC7 field */ @@ -5276,8 +5276,8 @@ #define PC0_BIT (0) #define PC0_BITS (1) -#define GPIO_DBGCFG *((volatile int32u *)0x4000BC00u) -#define GPIO_DBGCFG_REG *((volatile int32u *)0x4000BC00u) +#define GPIO_DBGCFG *((volatile uint32_t *)0x4000BC00u) +#define GPIO_DBGCFG_REG *((volatile uint32_t *)0x4000BC00u) #define GPIO_DBGCFG_ADDR (0x4000BC00u) #define GPIO_DBGCFG_RESET (0x00000010u) /* GPIO_DEBUGDIS field */ @@ -5296,8 +5296,8 @@ #define GPIO_DBGCFGRSVD_BIT (3) #define GPIO_DBGCFGRSVD_BITS (1) -#define GPIO_DBGSTAT *((volatile int32u *)0x4000BC04u) -#define GPIO_DBGSTAT_REG *((volatile int32u *)0x4000BC04u) +#define GPIO_DBGSTAT *((volatile uint32_t *)0x4000BC04u) +#define GPIO_DBGSTAT_REG *((volatile uint32_t *)0x4000BC04u) #define GPIO_DBGSTAT_ADDR (0x4000BC04u) #define GPIO_DBGSTAT_RESET (0x00000000u) /* GPIO_BOOTMODE field */ @@ -5316,8 +5316,8 @@ #define GPIO_SWEN_BIT (0) #define GPIO_SWEN_BITS (1) -#define GPIO_PAWAKE *((volatile int32u *)0x4000BC08u) -#define GPIO_PAWAKE_REG *((volatile int32u *)0x4000BC08u) +#define GPIO_PAWAKE *((volatile uint32_t *)0x4000BC08u) +#define GPIO_PAWAKE_REG *((volatile uint32_t *)0x4000BC08u) #define GPIO_PAWAKE_ADDR (0x4000BC08u) #define GPIO_PAWAKE_RESET (0x00000000u) /* PA7 field */ @@ -5361,8 +5361,8 @@ #define PA0_BIT (0) #define PA0_BITS (1) -#define GPIO_PBWAKE *((volatile int32u *)0x4000BC0Cu) -#define GPIO_PBWAKE_REG *((volatile int32u *)0x4000BC0Cu) +#define GPIO_PBWAKE *((volatile uint32_t *)0x4000BC0Cu) +#define GPIO_PBWAKE_REG *((volatile uint32_t *)0x4000BC0Cu) #define GPIO_PBWAKE_ADDR (0x4000BC0Cu) #define GPIO_PBWAKE_RESET (0x00000000u) /* PB7 field */ @@ -5406,8 +5406,8 @@ #define PB0_BIT (0) #define PB0_BITS (1) -#define GPIO_PCWAKE *((volatile int32u *)0x4000BC10u) -#define GPIO_PCWAKE_REG *((volatile int32u *)0x4000BC10u) +#define GPIO_PCWAKE *((volatile uint32_t *)0x4000BC10u) +#define GPIO_PCWAKE_REG *((volatile uint32_t *)0x4000BC10u) #define GPIO_PCWAKE_ADDR (0x4000BC10u) #define GPIO_PCWAKE_RESET (0x00000000u) /* PC7 field */ @@ -5451,8 +5451,8 @@ #define PC0_BIT (0) #define PC0_BITS (1) -#define GPIO_IRQCSEL *((volatile int32u *)0x4000BC14u) -#define GPIO_IRQCSEL_REG *((volatile int32u *)0x4000BC14u) +#define GPIO_IRQCSEL *((volatile uint32_t *)0x4000BC14u) +#define GPIO_IRQCSEL_REG *((volatile uint32_t *)0x4000BC14u) #define GPIO_IRQCSEL_ADDR (0x4000BC14u) #define GPIO_IRQCSEL_RESET (0x0000000Fu) /* SEL_GPIO field */ @@ -5461,8 +5461,8 @@ #define SEL_GPIO_BIT (0) #define SEL_GPIO_BITS (5) -#define GPIO_IRQDSEL *((volatile int32u *)0x4000BC18u) -#define GPIO_IRQDSEL_REG *((volatile int32u *)0x4000BC18u) +#define GPIO_IRQDSEL *((volatile uint32_t *)0x4000BC18u) +#define GPIO_IRQDSEL_REG *((volatile uint32_t *)0x4000BC18u) #define GPIO_IRQDSEL_ADDR (0x4000BC18u) #define GPIO_IRQDSEL_RESET (0x00000010u) /* SEL_GPIO field */ @@ -5471,8 +5471,8 @@ #define SEL_GPIO_BIT (0) #define SEL_GPIO_BITS (5) -#define GPIO_WAKEFILT *((volatile int32u *)0x4000BC1Cu) -#define GPIO_WAKEFILT_REG *((volatile int32u *)0x4000BC1Cu) +#define GPIO_WAKEFILT *((volatile uint32_t *)0x4000BC1Cu) +#define GPIO_WAKEFILT_REG *((volatile uint32_t *)0x4000BC1Cu) #define GPIO_WAKEFILT_ADDR (0x4000BC1Cu) #define GPIO_WAKEFILT_RESET (0x00000000u) /* IRQD_WAKE_FILTER field */ @@ -5501,8 +5501,8 @@ #define BLOCK_SERIAL_END (0x4000C870u) #define BLOCK_SERIAL_SIZE (BLOCK_SERIAL_END - BLOCK_SERIAL_BASE + 1) -#define SC2_RXBEGA *((volatile int32u *)0x4000C000u) -#define SC2_RXBEGA_REG *((volatile int32u *)0x4000C000u) +#define SC2_RXBEGA *((volatile uint32_t *)0x4000C000u) +#define SC2_RXBEGA_REG *((volatile uint32_t *)0x4000C000u) #define SC2_RXBEGA_ADDR (0x4000C000u) #define SC2_RXBEGA_RESET (0x20000000u) /* FIXED field */ @@ -5516,8 +5516,8 @@ #define SC_RXBEGA_BIT (0) #define SC_RXBEGA_BITS (13) -#define SC2_RXENDA *((volatile int32u *)0x4000C004u) -#define SC2_RXENDA_REG *((volatile int32u *)0x4000C004u) +#define SC2_RXENDA *((volatile uint32_t *)0x4000C004u) +#define SC2_RXENDA_REG *((volatile uint32_t *)0x4000C004u) #define SC2_RXENDA_ADDR (0x4000C004u) #define SC2_RXENDA_RESET (0x20000000u) /* FIXED field */ @@ -5531,8 +5531,8 @@ #define SC_RXENDA_BIT (0) #define SC_RXENDA_BITS (13) -#define SC2_RXBEGB *((volatile int32u *)0x4000C008u) -#define SC2_RXBEGB_REG *((volatile int32u *)0x4000C008u) +#define SC2_RXBEGB *((volatile uint32_t *)0x4000C008u) +#define SC2_RXBEGB_REG *((volatile uint32_t *)0x4000C008u) #define SC2_RXBEGB_ADDR (0x4000C008u) #define SC2_RXBEGB_RESET (0x20000000u) /* FIXED field */ @@ -5546,8 +5546,8 @@ #define SC_RXBEGB_BIT (0) #define SC_RXBEGB_BITS (13) -#define SC2_RXENDB *((volatile int32u *)0x4000C00Cu) -#define SC2_RXENDB_REG *((volatile int32u *)0x4000C00Cu) +#define SC2_RXENDB *((volatile uint32_t *)0x4000C00Cu) +#define SC2_RXENDB_REG *((volatile uint32_t *)0x4000C00Cu) #define SC2_RXENDB_ADDR (0x4000C00Cu) #define SC2_RXENDB_RESET (0x20000000u) /* FIXED field */ @@ -5561,8 +5561,8 @@ #define SC_RXENDB_BIT (0) #define SC_RXENDB_BITS (13) -#define SC2_TXBEGA *((volatile int32u *)0x4000C010u) -#define SC2_TXBEGA_REG *((volatile int32u *)0x4000C010u) +#define SC2_TXBEGA *((volatile uint32_t *)0x4000C010u) +#define SC2_TXBEGA_REG *((volatile uint32_t *)0x4000C010u) #define SC2_TXBEGA_ADDR (0x4000C010u) #define SC2_TXBEGA_RESET (0x20000000u) /* FIXED field */ @@ -5576,8 +5576,8 @@ #define SC_TXBEGA_BIT (0) #define SC_TXBEGA_BITS (13) -#define SC2_TXENDA *((volatile int32u *)0x4000C014u) -#define SC2_TXENDA_REG *((volatile int32u *)0x4000C014u) +#define SC2_TXENDA *((volatile uint32_t *)0x4000C014u) +#define SC2_TXENDA_REG *((volatile uint32_t *)0x4000C014u) #define SC2_TXENDA_ADDR (0x4000C014u) #define SC2_TXENDA_RESET (0x20000000u) /* FIXED field */ @@ -5591,8 +5591,8 @@ #define SC_TXENDA_BIT (0) #define SC_TXENDA_BITS (13) -#define SC2_TXBEGB *((volatile int32u *)0x4000C018u) -#define SC2_TXBEGB_REG *((volatile int32u *)0x4000C018u) +#define SC2_TXBEGB *((volatile uint32_t *)0x4000C018u) +#define SC2_TXBEGB_REG *((volatile uint32_t *)0x4000C018u) #define SC2_TXBEGB_ADDR (0x4000C018u) #define SC2_TXBEGB_RESET (0x20000000u) /* FIXED field */ @@ -5606,8 +5606,8 @@ #define SC_TXBEGB_BIT (0) #define SC_TXBEGB_BITS (13) -#define SC2_TXENDB *((volatile int32u *)0x4000C01Cu) -#define SC2_TXENDB_REG *((volatile int32u *)0x4000C01Cu) +#define SC2_TXENDB *((volatile uint32_t *)0x4000C01Cu) +#define SC2_TXENDB_REG *((volatile uint32_t *)0x4000C01Cu) #define SC2_TXENDB_ADDR (0x4000C01Cu) #define SC2_TXENDB_RESET (0x20000000u) /* FIXED field */ @@ -5621,8 +5621,8 @@ #define SC_TXENDB_BIT (0) #define SC_TXENDB_BITS (13) -#define SC2_RXCNTA *((volatile int32u *)0x4000C020u) -#define SC2_RXCNTA_REG *((volatile int32u *)0x4000C020u) +#define SC2_RXCNTA *((volatile uint32_t *)0x4000C020u) +#define SC2_RXCNTA_REG *((volatile uint32_t *)0x4000C020u) #define SC2_RXCNTA_ADDR (0x4000C020u) #define SC2_RXCNTA_RESET (0x00000000u) /* SC_RXCNTA field */ @@ -5631,8 +5631,8 @@ #define SC_RXCNTA_BIT (0) #define SC_RXCNTA_BITS (13) -#define SC2_RXCNTB *((volatile int32u *)0x4000C024u) -#define SC2_RXCNTB_REG *((volatile int32u *)0x4000C024u) +#define SC2_RXCNTB *((volatile uint32_t *)0x4000C024u) +#define SC2_RXCNTB_REG *((volatile uint32_t *)0x4000C024u) #define SC2_RXCNTB_ADDR (0x4000C024u) #define SC2_RXCNTB_RESET (0x00000000u) /* SC_RXCNTB field */ @@ -5641,8 +5641,8 @@ #define SC_RXCNTB_BIT (0) #define SC_RXCNTB_BITS (13) -#define SC2_TXCNT *((volatile int32u *)0x4000C028u) -#define SC2_TXCNT_REG *((volatile int32u *)0x4000C028u) +#define SC2_TXCNT *((volatile uint32_t *)0x4000C028u) +#define SC2_TXCNT_REG *((volatile uint32_t *)0x4000C028u) #define SC2_TXCNT_ADDR (0x4000C028u) #define SC2_TXCNT_RESET (0x00000000u) /* SC_TXCNT field */ @@ -5651,8 +5651,8 @@ #define SC_TXCNT_BIT (0) #define SC_TXCNT_BITS (13) -#define SC2_DMASTAT *((volatile int32u *)0x4000C02Cu) -#define SC2_DMASTAT_REG *((volatile int32u *)0x4000C02Cu) +#define SC2_DMASTAT *((volatile uint32_t *)0x4000C02Cu) +#define SC2_DMASTAT_REG *((volatile uint32_t *)0x4000C02Cu) #define SC2_DMASTAT_ADDR (0x4000C02Cu) #define SC2_DMASTAT_RESET (0x00000000u) /* SC_RXSSEL field */ @@ -5691,8 +5691,8 @@ #define SC_RXACTA_BIT (0) #define SC_RXACTA_BITS (1) -#define SC2_DMACTRL *((volatile int32u *)0x4000C030u) -#define SC2_DMACTRL_REG *((volatile int32u *)0x4000C030u) +#define SC2_DMACTRL *((volatile uint32_t *)0x4000C030u) +#define SC2_DMACTRL_REG *((volatile uint32_t *)0x4000C030u) #define SC2_DMACTRL_ADDR (0x4000C030u) #define SC2_DMACTRL_RESET (0x00000000u) /* SC_TXDMARST field */ @@ -5726,8 +5726,8 @@ #define SC_RXLODA_BIT (0) #define SC_RXLODA_BITS (1) -#define SC2_RXERRA *((volatile int32u *)0x4000C034u) -#define SC2_RXERRA_REG *((volatile int32u *)0x4000C034u) +#define SC2_RXERRA *((volatile uint32_t *)0x4000C034u) +#define SC2_RXERRA_REG *((volatile uint32_t *)0x4000C034u) #define SC2_RXERRA_ADDR (0x4000C034u) #define SC2_RXERRA_RESET (0x00000000u) /* SC_RXERRA field */ @@ -5736,8 +5736,8 @@ #define SC_RXERRA_BIT (0) #define SC_RXERRA_BITS (13) -#define SC2_RXERRB *((volatile int32u *)0x4000C038u) -#define SC2_RXERRB_REG *((volatile int32u *)0x4000C038u) +#define SC2_RXERRB *((volatile uint32_t *)0x4000C038u) +#define SC2_RXERRB_REG *((volatile uint32_t *)0x4000C038u) #define SC2_RXERRB_ADDR (0x4000C038u) #define SC2_RXERRB_RESET (0x00000000u) /* SC_RXERRB field */ @@ -5746,8 +5746,8 @@ #define SC_RXERRB_BIT (0) #define SC_RXERRB_BITS (13) -#define SC2_DATA *((volatile int32u *)0x4000C03Cu) -#define SC2_DATA_REG *((volatile int32u *)0x4000C03Cu) +#define SC2_DATA *((volatile uint32_t *)0x4000C03Cu) +#define SC2_DATA_REG *((volatile uint32_t *)0x4000C03Cu) #define SC2_DATA_ADDR (0x4000C03Cu) #define SC2_DATA_RESET (0x00000000u) /* SC_DATA field */ @@ -5756,8 +5756,8 @@ #define SC_DATA_BIT (0) #define SC_DATA_BITS (8) -#define SC2_SPISTAT *((volatile int32u *)0x4000C040u) -#define SC2_SPISTAT_REG *((volatile int32u *)0x4000C040u) +#define SC2_SPISTAT *((volatile uint32_t *)0x4000C040u) +#define SC2_SPISTAT_REG *((volatile uint32_t *)0x4000C040u) #define SC2_SPISTAT_ADDR (0x4000C040u) #define SC2_SPISTAT_RESET (0x00000000u) /* SC_SPITXIDLE field */ @@ -5781,8 +5781,8 @@ #define SC_SPIRXOVF_BIT (0) #define SC_SPIRXOVF_BITS (1) -#define SC2_TWISTAT *((volatile int32u *)0x4000C044u) -#define SC2_TWISTAT_REG *((volatile int32u *)0x4000C044u) +#define SC2_TWISTAT *((volatile uint32_t *)0x4000C044u) +#define SC2_TWISTAT_REG *((volatile uint32_t *)0x4000C044u) #define SC2_TWISTAT_ADDR (0x4000C044u) #define SC2_TWISTAT_RESET (0x00000000u) /* SC_TWICMDFIN field */ @@ -5806,8 +5806,8 @@ #define SC_TWIRXNAK_BIT (0) #define SC_TWIRXNAK_BITS (1) -#define SC2_TWICTRL1 *((volatile int32u *)0x4000C04Cu) -#define SC2_TWICTRL1_REG *((volatile int32u *)0x4000C04Cu) +#define SC2_TWICTRL1 *((volatile uint32_t *)0x4000C04Cu) +#define SC2_TWICTRL1_REG *((volatile uint32_t *)0x4000C04Cu) #define SC2_TWICTRL1_ADDR (0x4000C04Cu) #define SC2_TWICTRL1_RESET (0x00000000u) /* SC_TWISTOP field */ @@ -5831,8 +5831,8 @@ #define SC_TWIRECV_BIT (0) #define SC_TWIRECV_BITS (1) -#define SC2_TWICTRL2 *((volatile int32u *)0x4000C050u) -#define SC2_TWICTRL2_REG *((volatile int32u *)0x4000C050u) +#define SC2_TWICTRL2 *((volatile uint32_t *)0x4000C050u) +#define SC2_TWICTRL2_REG *((volatile uint32_t *)0x4000C050u) #define SC2_TWICTRL2_ADDR (0x4000C050u) #define SC2_TWICTRL2_RESET (0x00000000u) /* SC_TWIACK field */ @@ -5841,8 +5841,8 @@ #define SC_TWIACK_BIT (0) #define SC_TWIACK_BITS (1) -#define SC2_MODE *((volatile int32u *)0x4000C054u) -#define SC2_MODE_REG *((volatile int32u *)0x4000C054u) +#define SC2_MODE *((volatile uint32_t *)0x4000C054u) +#define SC2_MODE_REG *((volatile uint32_t *)0x4000C054u) #define SC2_MODE_ADDR (0x4000C054u) #define SC2_MODE_RESET (0x00000000u) /* SC_MODE field */ @@ -5855,8 +5855,8 @@ #define SC2_MODE_SPI (2) #define SC2_MODE_I2C (3) -#define SC2_SPICFG *((volatile int32u *)0x4000C058u) -#define SC2_SPICFG_REG *((volatile int32u *)0x4000C058u) +#define SC2_SPICFG *((volatile uint32_t *)0x4000C058u) +#define SC2_SPICFG_REG *((volatile uint32_t *)0x4000C058u) #define SC2_SPICFG_ADDR (0x4000C058u) #define SC2_SPICFG_RESET (0x00000000u) /* SC_SPIRXDRV field */ @@ -5890,8 +5890,8 @@ #define SC_SPIPOL_BIT (0) #define SC_SPIPOL_BITS (1) -#define SC2_RATELIN *((volatile int32u *)0x4000C060u) -#define SC2_RATELIN_REG *((volatile int32u *)0x4000C060u) +#define SC2_RATELIN *((volatile uint32_t *)0x4000C060u) +#define SC2_RATELIN_REG *((volatile uint32_t *)0x4000C060u) #define SC2_RATELIN_ADDR (0x4000C060u) #define SC2_RATELIN_RESET (0x00000000u) /* SC_RATELIN field */ @@ -5900,8 +5900,8 @@ #define SC_RATELIN_BIT (0) #define SC_RATELIN_BITS (4) -#define SC2_RATEEXP *((volatile int32u *)0x4000C064u) -#define SC2_RATEEXP_REG *((volatile int32u *)0x4000C064u) +#define SC2_RATEEXP *((volatile uint32_t *)0x4000C064u) +#define SC2_RATEEXP_REG *((volatile uint32_t *)0x4000C064u) #define SC2_RATEEXP_ADDR (0x4000C064u) #define SC2_RATEEXP_RESET (0x00000000u) /* SC_RATEEXP field */ @@ -5910,8 +5910,8 @@ #define SC_RATEEXP_BIT (0) #define SC_RATEEXP_BITS (4) -#define SC2_RXCNTSAVED *((volatile int32u *)0x4000C070u) -#define SC2_RXCNTSAVED_REG *((volatile int32u *)0x4000C070u) +#define SC2_RXCNTSAVED *((volatile uint32_t *)0x4000C070u) +#define SC2_RXCNTSAVED_REG *((volatile uint32_t *)0x4000C070u) #define SC2_RXCNTSAVED_ADDR (0x4000C070u) #define SC2_RXCNTSAVED_RESET (0x00000000u) /* SC_RXCNTSAVED field */ @@ -5920,8 +5920,8 @@ #define SC_RXCNTSAVED_BIT (0) #define SC_RXCNTSAVED_BITS (13) -#define SC1_RXBEGA *((volatile int32u *)0x4000C800u) -#define SC1_RXBEGA_REG *((volatile int32u *)0x4000C800u) +#define SC1_RXBEGA *((volatile uint32_t *)0x4000C800u) +#define SC1_RXBEGA_REG *((volatile uint32_t *)0x4000C800u) #define SC1_RXBEGA_ADDR (0x4000C800u) #define SC1_RXBEGA_RESET (0x20000000u) /* FIXED field */ @@ -5935,8 +5935,8 @@ #define SC_RXBEGA_BIT (0) #define SC_RXBEGA_BITS (13) -#define SC1_RXENDA *((volatile int32u *)0x4000C804u) -#define SC1_RXENDA_REG *((volatile int32u *)0x4000C804u) +#define SC1_RXENDA *((volatile uint32_t *)0x4000C804u) +#define SC1_RXENDA_REG *((volatile uint32_t *)0x4000C804u) #define SC1_RXENDA_ADDR (0x4000C804u) #define SC1_RXENDA_RESET (0x20000000u) /* FIXED field */ @@ -5950,8 +5950,8 @@ #define SC_RXENDA_BIT (0) #define SC_RXENDA_BITS (13) -#define SC1_RXBEGB *((volatile int32u *)0x4000C808u) -#define SC1_RXBEGB_REG *((volatile int32u *)0x4000C808u) +#define SC1_RXBEGB *((volatile uint32_t *)0x4000C808u) +#define SC1_RXBEGB_REG *((volatile uint32_t *)0x4000C808u) #define SC1_RXBEGB_ADDR (0x4000C808u) #define SC1_RXBEGB_RESET (0x20000000u) /* FIXED field */ @@ -5965,8 +5965,8 @@ #define SC_RXBEGB_BIT (0) #define SC_RXBEGB_BITS (13) -#define SC1_RXENDB *((volatile int32u *)0x4000C80Cu) -#define SC1_RXENDB_REG *((volatile int32u *)0x4000C80Cu) +#define SC1_RXENDB *((volatile uint32_t *)0x4000C80Cu) +#define SC1_RXENDB_REG *((volatile uint32_t *)0x4000C80Cu) #define SC1_RXENDB_ADDR (0x4000C80Cu) #define SC1_RXENDB_RESET (0x20000000u) /* FIXED field */ @@ -5980,8 +5980,8 @@ #define SC_RXENDB_BIT (0) #define SC_RXENDB_BITS (13) -#define SC1_TXBEGA *((volatile int32u *)0x4000C810u) -#define SC1_TXBEGA_REG *((volatile int32u *)0x4000C810u) +#define SC1_TXBEGA *((volatile uint32_t *)0x4000C810u) +#define SC1_TXBEGA_REG *((volatile uint32_t *)0x4000C810u) #define SC1_TXBEGA_ADDR (0x4000C810u) #define SC1_TXBEGA_RESET (0x20000000u) /* FIXED field */ @@ -5995,8 +5995,8 @@ #define SC_TXBEGA_BIT (0) #define SC_TXBEGA_BITS (13) -#define SC1_TXENDA *((volatile int32u *)0x4000C814u) -#define SC1_TXENDA_REG *((volatile int32u *)0x4000C814u) +#define SC1_TXENDA *((volatile uint32_t *)0x4000C814u) +#define SC1_TXENDA_REG *((volatile uint32_t *)0x4000C814u) #define SC1_TXENDA_ADDR (0x4000C814u) #define SC1_TXENDA_RESET (0x20000000u) /* FIXED field */ @@ -6010,8 +6010,8 @@ #define SC_TXENDA_BIT (0) #define SC_TXENDA_BITS (13) -#define SC1_TXBEGB *((volatile int32u *)0x4000C818u) -#define SC1_TXBEGB_REG *((volatile int32u *)0x4000C818u) +#define SC1_TXBEGB *((volatile uint32_t *)0x4000C818u) +#define SC1_TXBEGB_REG *((volatile uint32_t *)0x4000C818u) #define SC1_TXBEGB_ADDR (0x4000C818u) #define SC1_TXBEGB_RESET (0x20000000u) /* FIXED field */ @@ -6025,8 +6025,8 @@ #define SC_TXBEGB_BIT (0) #define SC_TXBEGB_BITS (13) -#define SC1_TXENDB *((volatile int32u *)0x4000C81Cu) -#define SC1_TXENDB_REG *((volatile int32u *)0x4000C81Cu) +#define SC1_TXENDB *((volatile uint32_t *)0x4000C81Cu) +#define SC1_TXENDB_REG *((volatile uint32_t *)0x4000C81Cu) #define SC1_TXENDB_ADDR (0x4000C81Cu) #define SC1_TXENDB_RESET (0x20000000u) /* FIXED field */ @@ -6040,8 +6040,8 @@ #define SC_TXENDB_BIT (0) #define SC_TXENDB_BITS (13) -#define SC1_RXCNTA *((volatile int32u *)0x4000C820u) -#define SC1_RXCNTA_REG *((volatile int32u *)0x4000C820u) +#define SC1_RXCNTA *((volatile uint32_t *)0x4000C820u) +#define SC1_RXCNTA_REG *((volatile uint32_t *)0x4000C820u) #define SC1_RXCNTA_ADDR (0x4000C820u) #define SC1_RXCNTA_RESET (0x00000000u) /* SC_RXCNTA field */ @@ -6050,8 +6050,8 @@ #define SC_RXCNTA_BIT (0) #define SC_RXCNTA_BITS (13) -#define SC1_RXCNTB *((volatile int32u *)0x4000C824u) -#define SC1_RXCNTB_REG *((volatile int32u *)0x4000C824u) +#define SC1_RXCNTB *((volatile uint32_t *)0x4000C824u) +#define SC1_RXCNTB_REG *((volatile uint32_t *)0x4000C824u) #define SC1_RXCNTB_ADDR (0x4000C824u) #define SC1_RXCNTB_RESET (0x00000000u) /* SC_RXCNTB field */ @@ -6060,8 +6060,8 @@ #define SC_RXCNTB_BIT (0) #define SC_RXCNTB_BITS (13) -#define SC1_TXCNT *((volatile int32u *)0x4000C828u) -#define SC1_TXCNT_REG *((volatile int32u *)0x4000C828u) +#define SC1_TXCNT *((volatile uint32_t *)0x4000C828u) +#define SC1_TXCNT_REG *((volatile uint32_t *)0x4000C828u) #define SC1_TXCNT_ADDR (0x4000C828u) #define SC1_TXCNT_RESET (0x00000000u) /* SC_TXCNT field */ @@ -6070,8 +6070,8 @@ #define SC_TXCNT_BIT (0) #define SC_TXCNT_BITS (13) -#define SC1_DMASTAT *((volatile int32u *)0x4000C82Cu) -#define SC1_DMASTAT_REG *((volatile int32u *)0x4000C82Cu) +#define SC1_DMASTAT *((volatile uint32_t *)0x4000C82Cu) +#define SC1_DMASTAT_REG *((volatile uint32_t *)0x4000C82Cu) #define SC1_DMASTAT_ADDR (0x4000C82Cu) #define SC1_DMASTAT_RESET (0x00000000u) /* SC_RXSSEL field */ @@ -6130,8 +6130,8 @@ #define SC_RXACTA_BIT (0) #define SC_RXACTA_BITS (1) -#define SC1_DMACTRL *((volatile int32u *)0x4000C830u) -#define SC1_DMACTRL_REG *((volatile int32u *)0x4000C830u) +#define SC1_DMACTRL *((volatile uint32_t *)0x4000C830u) +#define SC1_DMACTRL_REG *((volatile uint32_t *)0x4000C830u) #define SC1_DMACTRL_ADDR (0x4000C830u) #define SC1_DMACTRL_RESET (0x00000000u) /* SC_TXDMARST field */ @@ -6165,8 +6165,8 @@ #define SC_RXLODA_BIT (0) #define SC_RXLODA_BITS (1) -#define SC1_RXERRA *((volatile int32u *)0x4000C834u) -#define SC1_RXERRA_REG *((volatile int32u *)0x4000C834u) +#define SC1_RXERRA *((volatile uint32_t *)0x4000C834u) +#define SC1_RXERRA_REG *((volatile uint32_t *)0x4000C834u) #define SC1_RXERRA_ADDR (0x4000C834u) #define SC1_RXERRA_RESET (0x00000000u) /* SC_RXERRA field */ @@ -6175,8 +6175,8 @@ #define SC_RXERRA_BIT (0) #define SC_RXERRA_BITS (13) -#define SC1_RXERRB *((volatile int32u *)0x4000C838u) -#define SC1_RXERRB_REG *((volatile int32u *)0x4000C838u) +#define SC1_RXERRB *((volatile uint32_t *)0x4000C838u) +#define SC1_RXERRB_REG *((volatile uint32_t *)0x4000C838u) #define SC1_RXERRB_ADDR (0x4000C838u) #define SC1_RXERRB_RESET (0x00000000u) /* SC_RXERRB field */ @@ -6185,8 +6185,8 @@ #define SC_RXERRB_BIT (0) #define SC_RXERRB_BITS (13) -#define SC1_DATA *((volatile int32u *)0x4000C83Cu) -#define SC1_DATA_REG *((volatile int32u *)0x4000C83Cu) +#define SC1_DATA *((volatile uint32_t *)0x4000C83Cu) +#define SC1_DATA_REG *((volatile uint32_t *)0x4000C83Cu) #define SC1_DATA_ADDR (0x4000C83Cu) #define SC1_DATA_RESET (0x00000000u) /* SC_DATA field */ @@ -6195,8 +6195,8 @@ #define SC_DATA_BIT (0) #define SC_DATA_BITS (8) -#define SC1_SPISTAT *((volatile int32u *)0x4000C840u) -#define SC1_SPISTAT_REG *((volatile int32u *)0x4000C840u) +#define SC1_SPISTAT *((volatile uint32_t *)0x4000C840u) +#define SC1_SPISTAT_REG *((volatile uint32_t *)0x4000C840u) #define SC1_SPISTAT_ADDR (0x4000C840u) #define SC1_SPISTAT_RESET (0x00000000u) /* SC_SPITXIDLE field */ @@ -6220,8 +6220,8 @@ #define SC_SPIRXOVF_BIT (0) #define SC_SPIRXOVF_BITS (1) -#define SC1_TWISTAT *((volatile int32u *)0x4000C844u) -#define SC1_TWISTAT_REG *((volatile int32u *)0x4000C844u) +#define SC1_TWISTAT *((volatile uint32_t *)0x4000C844u) +#define SC1_TWISTAT_REG *((volatile uint32_t *)0x4000C844u) #define SC1_TWISTAT_ADDR (0x4000C844u) #define SC1_TWISTAT_RESET (0x00000000u) /* SC_TWICMDFIN field */ @@ -6245,8 +6245,8 @@ #define SC_TWIRXNAK_BIT (0) #define SC_TWIRXNAK_BITS (1) -#define SC1_UARTSTAT *((volatile int32u *)0x4000C848u) -#define SC1_UARTSTAT_REG *((volatile int32u *)0x4000C848u) +#define SC1_UARTSTAT *((volatile uint32_t *)0x4000C848u) +#define SC1_UARTSTAT_REG *((volatile uint32_t *)0x4000C848u) #define SC1_UARTSTAT_ADDR (0x4000C848u) #define SC1_UARTSTAT_RESET (0x00000040u) /* SC_UARTTXIDLE field */ @@ -6285,8 +6285,8 @@ #define SC_UARTCTS_BIT (0) #define SC_UARTCTS_BITS (1) -#define SC1_TWICTRL1 *((volatile int32u *)0x4000C84Cu) -#define SC1_TWICTRL1_REG *((volatile int32u *)0x4000C84Cu) +#define SC1_TWICTRL1 *((volatile uint32_t *)0x4000C84Cu) +#define SC1_TWICTRL1_REG *((volatile uint32_t *)0x4000C84Cu) #define SC1_TWICTRL1_ADDR (0x4000C84Cu) #define SC1_TWICTRL1_RESET (0x00000000u) /* SC_TWISTOP field */ @@ -6310,8 +6310,8 @@ #define SC_TWIRECV_BIT (0) #define SC_TWIRECV_BITS (1) -#define SC1_TWICTRL2 *((volatile int32u *)0x4000C850u) -#define SC1_TWICTRL2_REG *((volatile int32u *)0x4000C850u) +#define SC1_TWICTRL2 *((volatile uint32_t *)0x4000C850u) +#define SC1_TWICTRL2_REG *((volatile uint32_t *)0x4000C850u) #define SC1_TWICTRL2_ADDR (0x4000C850u) #define SC1_TWICTRL2_RESET (0x00000000u) /* SC_TWIACK field */ @@ -6320,8 +6320,8 @@ #define SC_TWIACK_BIT (0) #define SC_TWIACK_BITS (1) -#define SC1_MODE *((volatile int32u *)0x4000C854u) -#define SC1_MODE_REG *((volatile int32u *)0x4000C854u) +#define SC1_MODE *((volatile uint32_t *)0x4000C854u) +#define SC1_MODE_REG *((volatile uint32_t *)0x4000C854u) #define SC1_MODE_ADDR (0x4000C854u) #define SC1_MODE_RESET (0x00000000u) /* SC_MODE field */ @@ -6335,8 +6335,8 @@ #define SC1_MODE_SPI (2) #define SC1_MODE_I2C (3) -#define SC1_SPICFG *((volatile int32u *)0x4000C858u) -#define SC1_SPICFG_REG *((volatile int32u *)0x4000C858u) +#define SC1_SPICFG *((volatile uint32_t *)0x4000C858u) +#define SC1_SPICFG_REG *((volatile uint32_t *)0x4000C858u) #define SC1_SPICFG_ADDR (0x4000C858u) #define SC1_SPICFG_RESET (0x00000000u) /* SC_SPIRXDRV field */ @@ -6370,8 +6370,8 @@ #define SC_SPIPOL_BIT (0) #define SC_SPIPOL_BITS (1) -#define SC1_UARTCFG *((volatile int32u *)0x4000C85Cu) -#define SC1_UARTCFG_REG *((volatile int32u *)0x4000C85Cu) +#define SC1_UARTCFG *((volatile uint32_t *)0x4000C85Cu) +#define SC1_UARTCFG_REG *((volatile uint32_t *)0x4000C85Cu) #define SC1_UARTCFG_ADDR (0x4000C85Cu) #define SC1_UARTCFG_RESET (0x00000000u) /* SC_UARTAUTO field */ @@ -6410,8 +6410,8 @@ #define SC_UARTRTS_BIT (0) #define SC_UARTRTS_BITS (1) -#define SC1_RATELIN *((volatile int32u *)0x4000C860u) -#define SC1_RATELIN_REG *((volatile int32u *)0x4000C860u) +#define SC1_RATELIN *((volatile uint32_t *)0x4000C860u) +#define SC1_RATELIN_REG *((volatile uint32_t *)0x4000C860u) #define SC1_RATELIN_ADDR (0x4000C860u) #define SC1_RATELIN_RESET (0x00000000u) /* SC_RATELIN field */ @@ -6420,8 +6420,8 @@ #define SC_RATELIN_BIT (0) #define SC_RATELIN_BITS (4) -#define SC1_RATEEXP *((volatile int32u *)0x4000C864u) -#define SC1_RATEEXP_REG *((volatile int32u *)0x4000C864u) +#define SC1_RATEEXP *((volatile uint32_t *)0x4000C864u) +#define SC1_RATEEXP_REG *((volatile uint32_t *)0x4000C864u) #define SC1_RATEEXP_ADDR (0x4000C864u) #define SC1_RATEEXP_RESET (0x00000000u) /* SC_RATEEXP field */ @@ -6430,8 +6430,8 @@ #define SC_RATEEXP_BIT (0) #define SC_RATEEXP_BITS (4) -#define SC1_UARTPER *((volatile int32u *)0x4000C868u) -#define SC1_UARTPER_REG *((volatile int32u *)0x4000C868u) +#define SC1_UARTPER *((volatile uint32_t *)0x4000C868u) +#define SC1_UARTPER_REG *((volatile uint32_t *)0x4000C868u) #define SC1_UARTPER_ADDR (0x4000C868u) #define SC1_UARTPER_RESET (0x00000000u) /* SC_UARTPER field */ @@ -6440,8 +6440,8 @@ #define SC_UARTPER_BIT (0) #define SC_UARTPER_BITS (16) -#define SC1_UARTFRAC *((volatile int32u *)0x4000C86Cu) -#define SC1_UARTFRAC_REG *((volatile int32u *)0x4000C86Cu) +#define SC1_UARTFRAC *((volatile uint32_t *)0x4000C86Cu) +#define SC1_UARTFRAC_REG *((volatile uint32_t *)0x4000C86Cu) #define SC1_UARTFRAC_ADDR (0x4000C86Cu) #define SC1_UARTFRAC_RESET (0x00000000u) /* SC_UARTFRAC field */ @@ -6450,8 +6450,8 @@ #define SC_UARTFRAC_BIT (0) #define SC_UARTFRAC_BITS (1) -#define SC1_RXCNTSAVED *((volatile int32u *)0x4000C870u) -#define SC1_RXCNTSAVED_REG *((volatile int32u *)0x4000C870u) +#define SC1_RXCNTSAVED *((volatile uint32_t *)0x4000C870u) +#define SC1_RXCNTSAVED_REG *((volatile uint32_t *)0x4000C870u) #define SC1_RXCNTSAVED_ADDR (0x4000C870u) #define SC1_RXCNTSAVED_RESET (0x00000000u) /* SC_RXCNTSAVED field */ @@ -6465,8 +6465,8 @@ #define BLOCK_ADC_END (0x4000D024u) #define BLOCK_ADC_SIZE (BLOCK_ADC_END - BLOCK_ADC_BASE + 1) -#define ADC_DATA *((volatile int32u *)0x4000D000u) -#define ADC_DATA_REG *((volatile int32u *)0x4000D000u) +#define ADC_DATA *((volatile uint32_t *)0x4000D000u) +#define ADC_DATA_REG *((volatile uint32_t *)0x4000D000u) #define ADC_DATA_ADDR (0x4000D000u) #define ADC_DATA_RESET (0x00000000u) /* ADC_DATA_FIELD field */ @@ -6475,8 +6475,8 @@ #define ADC_DATA_FIELD_BIT (0) #define ADC_DATA_FIELD_BITS (16) -#define ADC_CFG *((volatile int32u *)0x4000D004u) -#define ADC_CFG_REG *((volatile int32u *)0x4000D004u) +#define ADC_CFG *((volatile uint32_t *)0x4000D004u) +#define ADC_CFG_REG *((volatile uint32_t *)0x4000D004u) #define ADC_CFG_ADDR (0x4000D004u) #define ADC_CFG_RESET (0x00001800u) /* ADC_PERIOD field */ @@ -6520,8 +6520,8 @@ #define ADC_ENABLE_BIT (0) #define ADC_ENABLE_BITS (1) -#define ADC_OFFSET *((volatile int32u *)0x4000D008u) -#define ADC_OFFSET_REG *((volatile int32u *)0x4000D008u) +#define ADC_OFFSET *((volatile uint32_t *)0x4000D008u) +#define ADC_OFFSET_REG *((volatile uint32_t *)0x4000D008u) #define ADC_OFFSET_ADDR (0x4000D008u) #define ADC_OFFSET_RESET (0x00000000u) /* ADC_OFFSET_FIELD field */ @@ -6530,8 +6530,8 @@ #define ADC_OFFSET_FIELD_BIT (0) #define ADC_OFFSET_FIELD_BITS (16) -#define ADC_GAIN *((volatile int32u *)0x4000D00Cu) -#define ADC_GAIN_REG *((volatile int32u *)0x4000D00Cu) +#define ADC_GAIN *((volatile uint32_t *)0x4000D00Cu) +#define ADC_GAIN_REG *((volatile uint32_t *)0x4000D00Cu) #define ADC_GAIN_ADDR (0x4000D00Cu) #define ADC_GAIN_RESET (0x00008000u) /* ADC_GAIN_FIELD field */ @@ -6540,8 +6540,8 @@ #define ADC_GAIN_FIELD_BIT (0) #define ADC_GAIN_FIELD_BITS (16) -#define ADC_DMACFG *((volatile int32u *)0x4000D010u) -#define ADC_DMACFG_REG *((volatile int32u *)0x4000D010u) +#define ADC_DMACFG *((volatile uint32_t *)0x4000D010u) +#define ADC_DMACFG_REG *((volatile uint32_t *)0x4000D010u) #define ADC_DMACFG_ADDR (0x4000D010u) #define ADC_DMACFG_RESET (0x00000000u) /* ADC_DMARST field */ @@ -6560,8 +6560,8 @@ #define ADC_DMALOAD_BIT (0) #define ADC_DMALOAD_BITS (1) -#define ADC_DMASTAT *((volatile int32u *)0x4000D014u) -#define ADC_DMASTAT_REG *((volatile int32u *)0x4000D014u) +#define ADC_DMASTAT *((volatile uint32_t *)0x4000D014u) +#define ADC_DMASTAT_REG *((volatile uint32_t *)0x4000D014u) #define ADC_DMASTAT_ADDR (0x4000D014u) #define ADC_DMASTAT_RESET (0x00000000u) /* ADC_DMAOVF field */ @@ -6575,8 +6575,8 @@ #define ADC_DMAACT_BIT (0) #define ADC_DMAACT_BITS (1) -#define ADC_DMABEG *((volatile int32u *)0x4000D018u) -#define ADC_DMABEG_REG *((volatile int32u *)0x4000D018u) +#define ADC_DMABEG *((volatile uint32_t *)0x4000D018u) +#define ADC_DMABEG_REG *((volatile uint32_t *)0x4000D018u) #define ADC_DMABEG_ADDR (0x4000D018u) #define ADC_DMABEG_RESET (0x20000000u) /* ADC_DMABEG_FIXED field */ @@ -6590,8 +6590,8 @@ #define ADC_DMABEG_FIELD_BIT (0) #define ADC_DMABEG_FIELD_BITS (13) -#define ADC_DMASIZE *((volatile int32u *)0x4000D01Cu) -#define ADC_DMASIZE_REG *((volatile int32u *)0x4000D01Cu) +#define ADC_DMASIZE *((volatile uint32_t *)0x4000D01Cu) +#define ADC_DMASIZE_REG *((volatile uint32_t *)0x4000D01Cu) #define ADC_DMASIZE_ADDR (0x4000D01Cu) #define ADC_DMASIZE_RESET (0x00000000u) /* ADC_DMASIZE_FIELD field */ @@ -6600,8 +6600,8 @@ #define ADC_DMASIZE_FIELD_BIT (0) #define ADC_DMASIZE_FIELD_BITS (12) -#define ADC_DMACUR *((volatile int32u *)0x4000D020u) -#define ADC_DMACUR_REG *((volatile int32u *)0x4000D020u) +#define ADC_DMACUR *((volatile uint32_t *)0x4000D020u) +#define ADC_DMACUR_REG *((volatile uint32_t *)0x4000D020u) #define ADC_DMACUR_ADDR (0x4000D020u) #define ADC_DMACUR_RESET (0x20000000u) /* ADC_DMACUR_FIXED field */ @@ -6615,8 +6615,8 @@ #define ADC_DMACUR_FIELD_BIT (0) #define ADC_DMACUR_FIELD_BITS (13) -#define ADC_DMACNT *((volatile int32u *)0x4000D024u) -#define ADC_DMACNT_REG *((volatile int32u *)0x4000D024u) +#define ADC_DMACNT *((volatile uint32_t *)0x4000D024u) +#define ADC_DMACNT_REG *((volatile uint32_t *)0x4000D024u) #define ADC_DMACNT_ADDR (0x4000D024u) #define ADC_DMACNT_RESET (0x00000000u) /* ADC_DMACNT_FIELD field */ @@ -6630,8 +6630,8 @@ #define BLOCK_TIM1_END (0x4000E050u) #define BLOCK_TIM1_SIZE (BLOCK_TIM1_END - BLOCK_TIM1_BASE + 1) -#define TIM1_CR1 *((volatile int32u *)0x4000E000u) -#define TIM1_CR1_REG *((volatile int32u *)0x4000E000u) +#define TIM1_CR1 *((volatile uint32_t *)0x4000E000u) +#define TIM1_CR1_REG *((volatile uint32_t *)0x4000E000u) #define TIM1_CR1_ADDR (0x4000E000u) #define TIM1_CR1_RESET (0x00000000u) /* TIM_ARBE field */ @@ -6670,8 +6670,8 @@ #define TIM_CEN_BIT (0) #define TIM_CEN_BITS (1) -#define TIM1_CR2 *((volatile int32u *)0x4000E004u) -#define TIM1_CR2_REG *((volatile int32u *)0x4000E004u) +#define TIM1_CR2 *((volatile uint32_t *)0x4000E004u) +#define TIM1_CR2_REG *((volatile uint32_t *)0x4000E004u) #define TIM1_CR2_ADDR (0x4000E004u) #define TIM1_CR2_RESET (0x00000000u) /* TIM_TI1S field */ @@ -6685,8 +6685,8 @@ #define TIM_MMS_BIT (4) #define TIM_MMS_BITS (3) -#define TIM1_SMCR *((volatile int32u *)0x4000E008u) -#define TIM1_SMCR_REG *((volatile int32u *)0x4000E008u) +#define TIM1_SMCR *((volatile uint32_t *)0x4000E008u) +#define TIM1_SMCR_REG *((volatile uint32_t *)0x4000E008u) #define TIM1_SMCR_ADDR (0x4000E008u) #define TIM1_SMCR_RESET (0x00000000u) /* TIM_ETP field */ @@ -6725,8 +6725,8 @@ #define TIM_SMS_BIT (0) #define TIM_SMS_BITS (3) -#define TMR1_DIER *((volatile int32u *)0x4000E00Cu) -#define TMR1_DIER_REG *((volatile int32u *)0x4000E00Cu) +#define TMR1_DIER *((volatile uint32_t *)0x4000E00Cu) +#define TMR1_DIER_REG *((volatile uint32_t *)0x4000E00Cu) #define TMR1_DIER_ADDR (0x4000E00Cu) #define TMR1_DIER_RESET (0x00000000u) /* TIE field */ @@ -6760,8 +6760,8 @@ #define TMR1_DIER_UIE_BIT (0) #define TMR1_DIER_UIE_BITS (1) -#define TMR1_SR *((volatile int32u *)0x4000E010u) -#define TMR1_SR_REG *((volatile int32u *)0x4000E010u) +#define TMR1_SR *((volatile uint32_t *)0x4000E010u) +#define TMR1_SR_REG *((volatile uint32_t *)0x4000E010u) #define TMR1_SR_ADDR (0x4000E010u) #define TMR1_SR_RESET (0x00000000u) /* CC4OF field */ @@ -6815,8 +6815,8 @@ #define TMR1_SR_UIF_BIT (0) #define TMR1_SR_UIF_BITS (1) -#define TIM1_EGR *((volatile int32u *)0x4000E014u) -#define TIM1_EGR_REG *((volatile int32u *)0x4000E014u) +#define TIM1_EGR *((volatile uint32_t *)0x4000E014u) +#define TIM1_EGR_REG *((volatile uint32_t *)0x4000E014u) #define TIM1_EGR_ADDR (0x4000E014u) #define TIM1_EGR_RESET (0x00000000u) /* TIM_TG field */ @@ -6850,8 +6850,8 @@ #define TIM_UG_BIT (0) #define TIM_UG_BITS (1) -#define TIM1_CCMR1 *((volatile int32u *)0x4000E018u) -#define TIM1_CCMR1_REG *((volatile int32u *)0x4000E018u) +#define TIM1_CCMR1 *((volatile uint32_t *)0x4000E018u) +#define TIM1_CCMR1_REG *((volatile uint32_t *)0x4000E018u) #define TIM1_CCMR1_ADDR (0x4000E018u) #define TIM1_CCMR1_RESET (0x00000000u) /* TIM_IC2F field */ @@ -6925,8 +6925,8 @@ #define TIM_CC1S_BIT (0) #define TIM_CC1S_BITS (2) -#define TIM1_CCMR2 *((volatile int32u *)0x4000E01Cu) -#define TIM1_CCMR2_REG *((volatile int32u *)0x4000E01Cu) +#define TIM1_CCMR2 *((volatile uint32_t *)0x4000E01Cu) +#define TIM1_CCMR2_REG *((volatile uint32_t *)0x4000E01Cu) #define TIM1_CCMR2_ADDR (0x4000E01Cu) #define TIM1_CCMR2_RESET (0x00000000u) /* TIM_IC4F field */ @@ -7000,8 +7000,8 @@ #define TIM_CC3S_BIT (0) #define TIM_CC3S_BITS (2) -#define TIM1_CCER *((volatile int32u *)0x4000E020u) -#define TIM1_CCER_REG *((volatile int32u *)0x4000E020u) +#define TIM1_CCER *((volatile uint32_t *)0x4000E020u) +#define TIM1_CCER_REG *((volatile uint32_t *)0x4000E020u) #define TIM1_CCER_ADDR (0x4000E020u) #define TIM1_CCER_RESET (0x00000000u) /* TIM_CC4P field */ @@ -7045,8 +7045,8 @@ #define TIM_CC1E_BIT (0) #define TIM_CC1E_BITS (1) -#define TIM1_CNT *((volatile int32u *)0x4000E024u) -#define TIM1_CNT_REG *((volatile int32u *)0x4000E024u) +#define TIM1_CNT *((volatile uint32_t *)0x4000E024u) +#define TIM1_CNT_REG *((volatile uint32_t *)0x4000E024u) #define TIM1_CNT_ADDR (0x4000E024u) #define TIM1_CNT_RESET (0x00000000u) /* TIM_CNT field */ @@ -7055,8 +7055,8 @@ #define TIM_CNT_BIT (0) #define TIM_CNT_BITS (16) -#define TIM1_PSC *((volatile int32u *)0x4000E028u) -#define TIM1_PSC_REG *((volatile int32u *)0x4000E028u) +#define TIM1_PSC *((volatile uint32_t *)0x4000E028u) +#define TIM1_PSC_REG *((volatile uint32_t *)0x4000E028u) #define TIM1_PSC_ADDR (0x4000E028u) #define TIM1_PSC_RESET (0x00000000u) /* TIM_PSC field */ @@ -7065,8 +7065,8 @@ #define TIM_PSC_BIT (0) #define TIM_PSC_BITS (4) -#define TIM1_ARR *((volatile int32u *)0x4000E02Cu) -#define TIM1_ARR_REG *((volatile int32u *)0x4000E02Cu) +#define TIM1_ARR *((volatile uint32_t *)0x4000E02Cu) +#define TIM1_ARR_REG *((volatile uint32_t *)0x4000E02Cu) #define TIM1_ARR_ADDR (0x4000E02Cu) #define TIM1_ARR_RESET (0x0000FFFFu) /* TIM_ARR field */ @@ -7075,8 +7075,8 @@ #define TIM_ARR_BIT (0) #define TIM_ARR_BITS (16) -#define TIM1_CCR1 *((volatile int32u *)0x4000E034u) -#define TIM1_CCR1_REG *((volatile int32u *)0x4000E034u) +#define TIM1_CCR1 *((volatile uint32_t *)0x4000E034u) +#define TIM1_CCR1_REG *((volatile uint32_t *)0x4000E034u) #define TIM1_CCR1_ADDR (0x4000E034u) #define TIM1_CCR1_RESET (0x00000000u) /* TIM_CCR field */ @@ -7085,8 +7085,8 @@ #define TIM_CCR_BIT (0) #define TIM_CCR_BITS (16) -#define TIM1_CCR2 *((volatile int32u *)0x4000E038u) -#define TIM1_CCR2_REG *((volatile int32u *)0x4000E038u) +#define TIM1_CCR2 *((volatile uint32_t *)0x4000E038u) +#define TIM1_CCR2_REG *((volatile uint32_t *)0x4000E038u) #define TIM1_CCR2_ADDR (0x4000E038u) #define TIM1_CCR2_RESET (0x00000000u) /* TIM_CCR field */ @@ -7095,8 +7095,8 @@ #define TIM_CCR_BIT (0) #define TIM_CCR_BITS (16) -#define TIM1_CCR3 *((volatile int32u *)0x4000E03Cu) -#define TIM1_CCR3_REG *((volatile int32u *)0x4000E03Cu) +#define TIM1_CCR3 *((volatile uint32_t *)0x4000E03Cu) +#define TIM1_CCR3_REG *((volatile uint32_t *)0x4000E03Cu) #define TIM1_CCR3_ADDR (0x4000E03Cu) #define TIM1_CCR3_RESET (0x00000000u) /* TIM_CCR field */ @@ -7105,8 +7105,8 @@ #define TIM_CCR_BIT (0) #define TIM_CCR_BITS (16) -#define TIM1_CCR4 *((volatile int32u *)0x4000E040u) -#define TIM1_CCR4_REG *((volatile int32u *)0x4000E040u) +#define TIM1_CCR4 *((volatile uint32_t *)0x4000E040u) +#define TIM1_CCR4_REG *((volatile uint32_t *)0x4000E040u) #define TIM1_CCR4_ADDR (0x4000E040u) #define TIM1_CCR4_RESET (0x00000000u) /* TIM_CCR field */ @@ -7115,8 +7115,8 @@ #define TIM_CCR_BIT (0) #define TIM_CCR_BITS (16) -#define TIM1_OR *((volatile int32u *)0x4000E050u) -#define TIM1_OR_REG *((volatile int32u *)0x4000E050u) +#define TIM1_OR *((volatile uint32_t *)0x4000E050u) +#define TIM1_OR_REG *((volatile uint32_t *)0x4000E050u) #define TIM1_OR_ADDR (0x4000E050u) #define TIM1_OR_RESET (0x00000000u) /* TIM_ORRSVD field */ @@ -7140,8 +7140,8 @@ #define BLOCK_TIM2_END (0x4000F050u) #define BLOCK_TIM2_SIZE (BLOCK_TIM2_END - BLOCK_TIM2_BASE + 1) -#define TIM2_CR1 *((volatile int32u *)0x4000F000u) -#define TIM2_CR1_REG *((volatile int32u *)0x4000F000u) +#define TIM2_CR1 *((volatile uint32_t *)0x4000F000u) +#define TIM2_CR1_REG *((volatile uint32_t *)0x4000F000u) #define TIM2_CR1_ADDR (0x4000F000u) #define TIM2_CR1_RESET (0x00000000u) /* TIM_ARBE field */ @@ -7180,8 +7180,8 @@ #define TIM_CEN_BIT (0) #define TIM_CEN_BITS (1) -#define TIM2_CR2 *((volatile int32u *)0x4000F004u) -#define TIM2_CR2_REG *((volatile int32u *)0x4000F004u) +#define TIM2_CR2 *((volatile uint32_t *)0x4000F004u) +#define TIM2_CR2_REG *((volatile uint32_t *)0x4000F004u) #define TIM2_CR2_ADDR (0x4000F004u) #define TIM2_CR2_RESET (0x00000000u) /* TIM_TI1S field */ @@ -7195,8 +7195,8 @@ #define TIM_MMS_BIT (4) #define TIM_MMS_BITS (3) -#define TIM2_SMCR *((volatile int32u *)0x4000F008u) -#define TIM2_SMCR_REG *((volatile int32u *)0x4000F008u) +#define TIM2_SMCR *((volatile uint32_t *)0x4000F008u) +#define TIM2_SMCR_REG *((volatile uint32_t *)0x4000F008u) #define TIM2_SMCR_ADDR (0x4000F008u) #define TIM2_SMCR_RESET (0x00000000u) /* TIM_ETP field */ @@ -7235,8 +7235,8 @@ #define TIM_SMS_BIT (0) #define TIM_SMS_BITS (3) -#define TMR2_DIER *((volatile int32u *)0x4000F00Cu) -#define TMR2_DIER_REG *((volatile int32u *)0x4000F00Cu) +#define TMR2_DIER *((volatile uint32_t *)0x4000F00Cu) +#define TMR2_DIER_REG *((volatile uint32_t *)0x4000F00Cu) #define TMR2_DIER_ADDR (0x4000F00Cu) #define TMR2_DIER_RESET (0x00000000u) /* TIE field */ @@ -7270,8 +7270,8 @@ #define TMR2_DIER_UIE_BIT (0) #define TMR2_DIER_UIE_BITS (1) -#define TMR2_SR *((volatile int32u *)0x4000F010u) -#define TMR2_SR_REG *((volatile int32u *)0x4000F010u) +#define TMR2_SR *((volatile uint32_t *)0x4000F010u) +#define TMR2_SR_REG *((volatile uint32_t *)0x4000F010u) #define TMR2_SR_ADDR (0x4000F010u) #define TMR2_SR_RESET (0x00000000u) /* CC4OF field */ @@ -7325,8 +7325,8 @@ #define TMR2_SR_UIF_BIT (0) #define TMR2_SR_UIF_BITS (1) -#define TIM2_EGR *((volatile int32u *)0x4000F014u) -#define TIM2_EGR_REG *((volatile int32u *)0x4000F014u) +#define TIM2_EGR *((volatile uint32_t *)0x4000F014u) +#define TIM2_EGR_REG *((volatile uint32_t *)0x4000F014u) #define TIM2_EGR_ADDR (0x4000F014u) #define TIM2_EGR_RESET (0x00000000u) /* TIM_TG field */ @@ -7360,8 +7360,8 @@ #define TIM_UG_BIT (0) #define TIM_UG_BITS (1) -#define TIM2_CCMR1 *((volatile int32u *)0x4000F018u) -#define TIM2_CCMR1_REG *((volatile int32u *)0x4000F018u) +#define TIM2_CCMR1 *((volatile uint32_t *)0x4000F018u) +#define TIM2_CCMR1_REG *((volatile uint32_t *)0x4000F018u) #define TIM2_CCMR1_ADDR (0x4000F018u) #define TIM2_CCMR1_RESET (0x00000000u) /* TIM_IC2F field */ @@ -7435,8 +7435,8 @@ #define TIM_CC1S_BIT (0) #define TIM_CC1S_BITS (2) -#define TIM2_CCMR2 *((volatile int32u *)0x4000F01Cu) -#define TIM2_CCMR2_REG *((volatile int32u *)0x4000F01Cu) +#define TIM2_CCMR2 *((volatile uint32_t *)0x4000F01Cu) +#define TIM2_CCMR2_REG *((volatile uint32_t *)0x4000F01Cu) #define TIM2_CCMR2_ADDR (0x4000F01Cu) #define TIM2_CCMR2_RESET (0x00000000u) /* TIM_IC4F field */ @@ -7510,8 +7510,8 @@ #define TIM_CC3S_BIT (0) #define TIM_CC3S_BITS (2) -#define TIM2_CCER *((volatile int32u *)0x4000F020u) -#define TIM2_CCER_REG *((volatile int32u *)0x4000F020u) +#define TIM2_CCER *((volatile uint32_t *)0x4000F020u) +#define TIM2_CCER_REG *((volatile uint32_t *)0x4000F020u) #define TIM2_CCER_ADDR (0x4000F020u) #define TIM2_CCER_RESET (0x00000000u) /* TIM_CC4P field */ @@ -7555,8 +7555,8 @@ #define TIM_CC1E_BIT (0) #define TIM_CC1E_BITS (1) -#define TIM2_CNT *((volatile int32u *)0x4000F024u) -#define TIM2_CNT_REG *((volatile int32u *)0x4000F024u) +#define TIM2_CNT *((volatile uint32_t *)0x4000F024u) +#define TIM2_CNT_REG *((volatile uint32_t *)0x4000F024u) #define TIM2_CNT_ADDR (0x4000F024u) #define TIM2_CNT_RESET (0x00000000u) /* TIM_CNT field */ @@ -7565,8 +7565,8 @@ #define TIM_CNT_BIT (0) #define TIM_CNT_BITS (16) -#define TIM2_PSC *((volatile int32u *)0x4000F028u) -#define TIM2_PSC_REG *((volatile int32u *)0x4000F028u) +#define TIM2_PSC *((volatile uint32_t *)0x4000F028u) +#define TIM2_PSC_REG *((volatile uint32_t *)0x4000F028u) #define TIM2_PSC_ADDR (0x4000F028u) #define TIM2_PSC_RESET (0x00000000u) /* TIM_PSC field */ @@ -7575,8 +7575,8 @@ #define TIM_PSC_BIT (0) #define TIM_PSC_BITS (4) -#define TIM2_ARR *((volatile int32u *)0x4000F02Cu) -#define TIM2_ARR_REG *((volatile int32u *)0x4000F02Cu) +#define TIM2_ARR *((volatile uint32_t *)0x4000F02Cu) +#define TIM2_ARR_REG *((volatile uint32_t *)0x4000F02Cu) #define TIM2_ARR_ADDR (0x4000F02Cu) #define TIM2_ARR_RESET (0x0000FFFFu) /* TIM_ARR field */ @@ -7585,8 +7585,8 @@ #define TIM_ARR_BIT (0) #define TIM_ARR_BITS (16) -#define TIM2_CCR1 *((volatile int32u *)0x4000F034u) -#define TIM2_CCR1_REG *((volatile int32u *)0x4000F034u) +#define TIM2_CCR1 *((volatile uint32_t *)0x4000F034u) +#define TIM2_CCR1_REG *((volatile uint32_t *)0x4000F034u) #define TIM2_CCR1_ADDR (0x4000F034u) #define TIM2_CCR1_RESET (0x00000000u) /* TIM_CCR field */ @@ -7595,8 +7595,8 @@ #define TIM_CCR_BIT (0) #define TIM_CCR_BITS (16) -#define TIM2_CCR2 *((volatile int32u *)0x4000F038u) -#define TIM2_CCR2_REG *((volatile int32u *)0x4000F038u) +#define TIM2_CCR2 *((volatile uint32_t *)0x4000F038u) +#define TIM2_CCR2_REG *((volatile uint32_t *)0x4000F038u) #define TIM2_CCR2_ADDR (0x4000F038u) #define TIM2_CCR2_RESET (0x00000000u) /* TIM_CCR field */ @@ -7605,8 +7605,8 @@ #define TIM_CCR_BIT (0) #define TIM_CCR_BITS (16) -#define TIM2_CCR3 *((volatile int32u *)0x4000F03Cu) -#define TIM2_CCR3_REG *((volatile int32u *)0x4000F03Cu) +#define TIM2_CCR3 *((volatile uint32_t *)0x4000F03Cu) +#define TIM2_CCR3_REG *((volatile uint32_t *)0x4000F03Cu) #define TIM2_CCR3_ADDR (0x4000F03Cu) #define TIM2_CCR3_RESET (0x00000000u) /* TIM_CCR field */ @@ -7615,8 +7615,8 @@ #define TIM_CCR_BIT (0) #define TIM_CCR_BITS (16) -#define TIM2_CCR4 *((volatile int32u *)0x4000F040u) -#define TIM2_CCR4_REG *((volatile int32u *)0x4000F040u) +#define TIM2_CCR4 *((volatile uint32_t *)0x4000F040u) +#define TIM2_CCR4_REG *((volatile uint32_t *)0x4000F040u) #define TIM2_CCR4_ADDR (0x4000F040u) #define TIM2_CCR4_RESET (0x00000000u) /* TIM_CCR field */ @@ -7625,8 +7625,8 @@ #define TIM_CCR_BIT (0) #define TIM_CCR_BITS (16) -#define TIM2_OR *((volatile int32u *)0x4000F050u) -#define TIM2_OR_REG *((volatile int32u *)0x4000F050u) +#define TIM2_OR *((volatile uint32_t *)0x4000F050u) +#define TIM2_OR_REG *((volatile uint32_t *)0x4000F050u) #define TIM2_OR_ADDR (0x4000F050u) #define TIM2_OR_RESET (0x00000000u) /* TIM_REMAPC4 field */ @@ -7680,8 +7680,8 @@ #define DATA_ITM_END (0xE0000FFFu) #define DATA_ITM_SIZE (DATA_ITM_END - DATA_ITM_BASE + 1) -#define ITM_SP0 *((volatile int32u *)0xE0000000u) -#define ITM_SP0_REG *((volatile int32u *)0xE0000000u) +#define ITM_SP0 *((volatile uint32_t *)0xE0000000u) +#define ITM_SP0_REG *((volatile uint32_t *)0xE0000000u) #define ITM_SP0_ADDR (0xE0000000u) #define ITM_SP0_RESET (0x00000000u) /* FIFOREADY field */ @@ -7695,8 +7695,8 @@ #define ITM_SP0_STIMULUS_BIT (0) #define ITM_SP0_STIMULUS_BITS (32) -#define ITM_SP1 *((volatile int32u *)0xE0000004u) -#define ITM_SP1_REG *((volatile int32u *)0xE0000004u) +#define ITM_SP1 *((volatile uint32_t *)0xE0000004u) +#define ITM_SP1_REG *((volatile uint32_t *)0xE0000004u) #define ITM_SP1_ADDR (0xE0000004u) #define ITM_SP1_RESET (0x00000000u) /* FIFOREADY field */ @@ -7710,8 +7710,8 @@ #define ITM_SP1_STIMULUS_BIT (0) #define ITM_SP1_STIMULUS_BITS (32) -#define ITM_SP2 *((volatile int32u *)0xE0000008u) -#define ITM_SP2_REG *((volatile int32u *)0xE0000008u) +#define ITM_SP2 *((volatile uint32_t *)0xE0000008u) +#define ITM_SP2_REG *((volatile uint32_t *)0xE0000008u) #define ITM_SP2_ADDR (0xE0000008u) #define ITM_SP2_RESET (0x00000000u) /* FIFOREADY field */ @@ -7725,8 +7725,8 @@ #define ITM_SP2_STIMULUS_BIT (0) #define ITM_SP2_STIMULUS_BITS (32) -#define ITM_SP3 *((volatile int32u *)0xE000000Cu) -#define ITM_SP3_REG *((volatile int32u *)0xE000000Cu) +#define ITM_SP3 *((volatile uint32_t *)0xE000000Cu) +#define ITM_SP3_REG *((volatile uint32_t *)0xE000000Cu) #define ITM_SP3_ADDR (0xE000000Cu) #define ITM_SP3_RESET (0x00000000u) /* FIFOREADY field */ @@ -7740,8 +7740,8 @@ #define ITM_SP3_STIMULUS_BIT (0) #define ITM_SP3_STIMULUS_BITS (32) -#define ITM_SP4 *((volatile int32u *)0xE0000010u) -#define ITM_SP4_REG *((volatile int32u *)0xE0000010u) +#define ITM_SP4 *((volatile uint32_t *)0xE0000010u) +#define ITM_SP4_REG *((volatile uint32_t *)0xE0000010u) #define ITM_SP4_ADDR (0xE0000010u) #define ITM_SP4_RESET (0x00000000u) /* FIFOREADY field */ @@ -7755,8 +7755,8 @@ #define ITM_SP4_STIMULUS_BIT (0) #define ITM_SP4_STIMULUS_BITS (32) -#define ITM_SP5 *((volatile int32u *)0xE0000014u) -#define ITM_SP5_REG *((volatile int32u *)0xE0000014u) +#define ITM_SP5 *((volatile uint32_t *)0xE0000014u) +#define ITM_SP5_REG *((volatile uint32_t *)0xE0000014u) #define ITM_SP5_ADDR (0xE0000014u) #define ITM_SP5_RESET (0x00000000u) /* FIFOREADY field */ @@ -7770,8 +7770,8 @@ #define ITM_SP5_STIMULUS_BIT (0) #define ITM_SP5_STIMULUS_BITS (32) -#define ITM_SP6 *((volatile int32u *)0xE0000018u) -#define ITM_SP6_REG *((volatile int32u *)0xE0000018u) +#define ITM_SP6 *((volatile uint32_t *)0xE0000018u) +#define ITM_SP6_REG *((volatile uint32_t *)0xE0000018u) #define ITM_SP6_ADDR (0xE0000018u) #define ITM_SP6_RESET (0x00000000u) /* FIFOREADY field */ @@ -7785,8 +7785,8 @@ #define ITM_SP6_STIMULUS_BIT (0) #define ITM_SP6_STIMULUS_BITS (32) -#define ITM_SP7 *((volatile int32u *)0xE000001Cu) -#define ITM_SP7_REG *((volatile int32u *)0xE000001Cu) +#define ITM_SP7 *((volatile uint32_t *)0xE000001Cu) +#define ITM_SP7_REG *((volatile uint32_t *)0xE000001Cu) #define ITM_SP7_ADDR (0xE000001Cu) #define ITM_SP7_RESET (0x00000000u) /* FIFOREADY field */ @@ -7800,8 +7800,8 @@ #define ITM_SP7_STIMULUS_BIT (0) #define ITM_SP7_STIMULUS_BITS (32) -#define ITM_SP8 *((volatile int32u *)0xE0000020u) -#define ITM_SP8_REG *((volatile int32u *)0xE0000020u) +#define ITM_SP8 *((volatile uint32_t *)0xE0000020u) +#define ITM_SP8_REG *((volatile uint32_t *)0xE0000020u) #define ITM_SP8_ADDR (0xE0000020u) #define ITM_SP8_RESET (0x00000000u) /* FIFOREADY field */ @@ -7815,8 +7815,8 @@ #define ITM_SP8_STIMULUS_BIT (0) #define ITM_SP8_STIMULUS_BITS (32) -#define ITM_SP9 *((volatile int32u *)0xE0000024u) -#define ITM_SP9_REG *((volatile int32u *)0xE0000024u) +#define ITM_SP9 *((volatile uint32_t *)0xE0000024u) +#define ITM_SP9_REG *((volatile uint32_t *)0xE0000024u) #define ITM_SP9_ADDR (0xE0000024u) #define ITM_SP9_RESET (0x00000000u) /* FIFOREADY field */ @@ -7830,8 +7830,8 @@ #define ITM_SP9_STIMULUS_BIT (0) #define ITM_SP9_STIMULUS_BITS (32) -#define ITM_SP10 *((volatile int32u *)0xE0000028u) -#define ITM_SP10_REG *((volatile int32u *)0xE0000028u) +#define ITM_SP10 *((volatile uint32_t *)0xE0000028u) +#define ITM_SP10_REG *((volatile uint32_t *)0xE0000028u) #define ITM_SP10_ADDR (0xE0000028u) #define ITM_SP10_RESET (0x00000000u) /* FIFOREADY field */ @@ -7845,8 +7845,8 @@ #define ITM_SP10_STIMULUS_BIT (0) #define ITM_SP10_STIMULUS_BITS (32) -#define ITM_SP11 *((volatile int32u *)0xE000002Cu) -#define ITM_SP11_REG *((volatile int32u *)0xE000002Cu) +#define ITM_SP11 *((volatile uint32_t *)0xE000002Cu) +#define ITM_SP11_REG *((volatile uint32_t *)0xE000002Cu) #define ITM_SP11_ADDR (0xE000002Cu) #define ITM_SP11_RESET (0x00000000u) /* FIFOREADY field */ @@ -7860,8 +7860,8 @@ #define ITM_SP11_STIMULUS_BIT (0) #define ITM_SP11_STIMULUS_BITS (32) -#define ITM_SP12 *((volatile int32u *)0xE0000030u) -#define ITM_SP12_REG *((volatile int32u *)0xE0000030u) +#define ITM_SP12 *((volatile uint32_t *)0xE0000030u) +#define ITM_SP12_REG *((volatile uint32_t *)0xE0000030u) #define ITM_SP12_ADDR (0xE0000030u) #define ITM_SP12_RESET (0x00000000u) /* FIFOREADY field */ @@ -7875,8 +7875,8 @@ #define ITM_SP12_STIMULUS_BIT (0) #define ITM_SP12_STIMULUS_BITS (32) -#define ITM_SP13 *((volatile int32u *)0xE0000034u) -#define ITM_SP13_REG *((volatile int32u *)0xE0000034u) +#define ITM_SP13 *((volatile uint32_t *)0xE0000034u) +#define ITM_SP13_REG *((volatile uint32_t *)0xE0000034u) #define ITM_SP13_ADDR (0xE0000034u) #define ITM_SP13_RESET (0x00000000u) /* FIFOREADY field */ @@ -7890,8 +7890,8 @@ #define ITM_SP13_STIMULUS_BIT (0) #define ITM_SP13_STIMULUS_BITS (32) -#define ITM_SP14 *((volatile int32u *)0xE0000038u) -#define ITM_SP14_REG *((volatile int32u *)0xE0000038u) +#define ITM_SP14 *((volatile uint32_t *)0xE0000038u) +#define ITM_SP14_REG *((volatile uint32_t *)0xE0000038u) #define ITM_SP14_ADDR (0xE0000038u) #define ITM_SP14_RESET (0x00000000u) /* FIFOREADY field */ @@ -7905,8 +7905,8 @@ #define ITM_SP14_STIMULUS_BIT (0) #define ITM_SP14_STIMULUS_BITS (32) -#define ITM_SP15 *((volatile int32u *)0xE000003Cu) -#define ITM_SP15_REG *((volatile int32u *)0xE000003Cu) +#define ITM_SP15 *((volatile uint32_t *)0xE000003Cu) +#define ITM_SP15_REG *((volatile uint32_t *)0xE000003Cu) #define ITM_SP15_ADDR (0xE000003Cu) #define ITM_SP15_RESET (0x00000000u) /* FIFOREADY field */ @@ -7920,8 +7920,8 @@ #define ITM_SP15_STIMULUS_BIT (0) #define ITM_SP15_STIMULUS_BITS (32) -#define ITM_SP16 *((volatile int32u *)0xE0000040u) -#define ITM_SP16_REG *((volatile int32u *)0xE0000040u) +#define ITM_SP16 *((volatile uint32_t *)0xE0000040u) +#define ITM_SP16_REG *((volatile uint32_t *)0xE0000040u) #define ITM_SP16_ADDR (0xE0000040u) #define ITM_SP16_RESET (0x00000000u) /* FIFOREADY field */ @@ -7935,8 +7935,8 @@ #define ITM_SP16_STIMULUS_BIT (0) #define ITM_SP16_STIMULUS_BITS (32) -#define ITM_SP17 *((volatile int32u *)0xE0000044u) -#define ITM_SP17_REG *((volatile int32u *)0xE0000044u) +#define ITM_SP17 *((volatile uint32_t *)0xE0000044u) +#define ITM_SP17_REG *((volatile uint32_t *)0xE0000044u) #define ITM_SP17_ADDR (0xE0000044u) #define ITM_SP17_RESET (0x00000000u) /* FIFOREADY field */ @@ -7950,8 +7950,8 @@ #define ITM_SP17_STIMULUS_BIT (0) #define ITM_SP17_STIMULUS_BITS (32) -#define ITM_SP18 *((volatile int32u *)0xE0000048u) -#define ITM_SP18_REG *((volatile int32u *)0xE0000048u) +#define ITM_SP18 *((volatile uint32_t *)0xE0000048u) +#define ITM_SP18_REG *((volatile uint32_t *)0xE0000048u) #define ITM_SP18_ADDR (0xE0000048u) #define ITM_SP18_RESET (0x00000000u) /* FIFOREADY field */ @@ -7965,8 +7965,8 @@ #define ITM_SP18_STIMULUS_BIT (0) #define ITM_SP18_STIMULUS_BITS (32) -#define ITM_SP19 *((volatile int32u *)0xE000004Cu) -#define ITM_SP19_REG *((volatile int32u *)0xE000004Cu) +#define ITM_SP19 *((volatile uint32_t *)0xE000004Cu) +#define ITM_SP19_REG *((volatile uint32_t *)0xE000004Cu) #define ITM_SP19_ADDR (0xE000004Cu) #define ITM_SP19_RESET (0x00000000u) /* FIFOREADY field */ @@ -7980,8 +7980,8 @@ #define ITM_SP19_STIMULUS_BIT (0) #define ITM_SP19_STIMULUS_BITS (32) -#define ITM_SP20 *((volatile int32u *)0xE0000050u) -#define ITM_SP20_REG *((volatile int32u *)0xE0000050u) +#define ITM_SP20 *((volatile uint32_t *)0xE0000050u) +#define ITM_SP20_REG *((volatile uint32_t *)0xE0000050u) #define ITM_SP20_ADDR (0xE0000050u) #define ITM_SP20_RESET (0x00000000u) /* FIFOREADY field */ @@ -7995,8 +7995,8 @@ #define ITM_SP20_STIMULUS_BIT (0) #define ITM_SP20_STIMULUS_BITS (32) -#define ITM_SP21 *((volatile int32u *)0xE0000054u) -#define ITM_SP21_REG *((volatile int32u *)0xE0000054u) +#define ITM_SP21 *((volatile uint32_t *)0xE0000054u) +#define ITM_SP21_REG *((volatile uint32_t *)0xE0000054u) #define ITM_SP21_ADDR (0xE0000054u) #define ITM_SP21_RESET (0x00000000u) /* FIFOREADY field */ @@ -8010,8 +8010,8 @@ #define ITM_SP21_STIMULUS_BIT (0) #define ITM_SP21_STIMULUS_BITS (32) -#define ITM_SP22 *((volatile int32u *)0xE0000058u) -#define ITM_SP22_REG *((volatile int32u *)0xE0000058u) +#define ITM_SP22 *((volatile uint32_t *)0xE0000058u) +#define ITM_SP22_REG *((volatile uint32_t *)0xE0000058u) #define ITM_SP22_ADDR (0xE0000058u) #define ITM_SP22_RESET (0x00000000u) /* FIFOREADY field */ @@ -8025,8 +8025,8 @@ #define ITM_SP22_STIMULUS_BIT (0) #define ITM_SP22_STIMULUS_BITS (32) -#define ITM_SP23 *((volatile int32u *)0xE000005Cu) -#define ITM_SP23_REG *((volatile int32u *)0xE000005Cu) +#define ITM_SP23 *((volatile uint32_t *)0xE000005Cu) +#define ITM_SP23_REG *((volatile uint32_t *)0xE000005Cu) #define ITM_SP23_ADDR (0xE000005Cu) #define ITM_SP23_RESET (0x00000000u) /* FIFOREADY field */ @@ -8040,8 +8040,8 @@ #define ITM_SP23_STIMULUS_BIT (0) #define ITM_SP23_STIMULUS_BITS (32) -#define ITM_SP24 *((volatile int32u *)0xE0000060u) -#define ITM_SP24_REG *((volatile int32u *)0xE0000060u) +#define ITM_SP24 *((volatile uint32_t *)0xE0000060u) +#define ITM_SP24_REG *((volatile uint32_t *)0xE0000060u) #define ITM_SP24_ADDR (0xE0000060u) #define ITM_SP24_RESET (0x00000000u) /* FIFOREADY field */ @@ -8055,8 +8055,8 @@ #define ITM_SP24_STIMULUS_BIT (0) #define ITM_SP24_STIMULUS_BITS (32) -#define ITM_SP25 *((volatile int32u *)0xE0000064u) -#define ITM_SP25_REG *((volatile int32u *)0xE0000064u) +#define ITM_SP25 *((volatile uint32_t *)0xE0000064u) +#define ITM_SP25_REG *((volatile uint32_t *)0xE0000064u) #define ITM_SP25_ADDR (0xE0000064u) #define ITM_SP25_RESET (0x00000000u) /* FIFOREADY field */ @@ -8070,8 +8070,8 @@ #define ITM_SP25_STIMULUS_BIT (0) #define ITM_SP25_STIMULUS_BITS (32) -#define ITM_SP26 *((volatile int32u *)0xE0000068u) -#define ITM_SP26_REG *((volatile int32u *)0xE0000068u) +#define ITM_SP26 *((volatile uint32_t *)0xE0000068u) +#define ITM_SP26_REG *((volatile uint32_t *)0xE0000068u) #define ITM_SP26_ADDR (0xE0000068u) #define ITM_SP26_RESET (0x00000000u) /* FIFOREADY field */ @@ -8085,8 +8085,8 @@ #define ITM_SP26_STIMULUS_BIT (0) #define ITM_SP26_STIMULUS_BITS (32) -#define ITM_SP27 *((volatile int32u *)0xE000006Cu) -#define ITM_SP27_REG *((volatile int32u *)0xE000006Cu) +#define ITM_SP27 *((volatile uint32_t *)0xE000006Cu) +#define ITM_SP27_REG *((volatile uint32_t *)0xE000006Cu) #define ITM_SP27_ADDR (0xE000006Cu) #define ITM_SP27_RESET (0x00000000u) /* FIFOREADY field */ @@ -8100,8 +8100,8 @@ #define ITM_SP27_STIMULUS_BIT (0) #define ITM_SP27_STIMULUS_BITS (32) -#define ITM_SP28 *((volatile int32u *)0xE0000070u) -#define ITM_SP28_REG *((volatile int32u *)0xE0000070u) +#define ITM_SP28 *((volatile uint32_t *)0xE0000070u) +#define ITM_SP28_REG *((volatile uint32_t *)0xE0000070u) #define ITM_SP28_ADDR (0xE0000070u) #define ITM_SP28_RESET (0x00000000u) /* FIFOREADY field */ @@ -8115,8 +8115,8 @@ #define ITM_SP28_STIMULUS_BIT (0) #define ITM_SP28_STIMULUS_BITS (32) -#define ITM_SP29 *((volatile int32u *)0xE0000074u) -#define ITM_SP29_REG *((volatile int32u *)0xE0000074u) +#define ITM_SP29 *((volatile uint32_t *)0xE0000074u) +#define ITM_SP29_REG *((volatile uint32_t *)0xE0000074u) #define ITM_SP29_ADDR (0xE0000074u) #define ITM_SP29_RESET (0x00000000u) /* FIFOREADY field */ @@ -8130,8 +8130,8 @@ #define ITM_SP29_STIMULUS_BIT (0) #define ITM_SP29_STIMULUS_BITS (32) -#define ITM_SP30 *((volatile int32u *)0xE0000078u) -#define ITM_SP30_REG *((volatile int32u *)0xE0000078u) +#define ITM_SP30 *((volatile uint32_t *)0xE0000078u) +#define ITM_SP30_REG *((volatile uint32_t *)0xE0000078u) #define ITM_SP30_ADDR (0xE0000078u) #define ITM_SP30_RESET (0x00000000u) /* FIFOREADY field */ @@ -8145,8 +8145,8 @@ #define ITM_SP30_STIMULUS_BIT (0) #define ITM_SP30_STIMULUS_BITS (32) -#define ITM_SP31 *((volatile int32u *)0xE000007Cu) -#define ITM_SP31_REG *((volatile int32u *)0xE000007Cu) +#define ITM_SP31 *((volatile uint32_t *)0xE000007Cu) +#define ITM_SP31_REG *((volatile uint32_t *)0xE000007Cu) #define ITM_SP31_ADDR (0xE000007Cu) #define ITM_SP31_RESET (0x00000000u) /* FIFOREADY field */ @@ -8160,8 +8160,8 @@ #define ITM_SP31_STIMULUS_BIT (0) #define ITM_SP31_STIMULUS_BITS (32) -#define ITM_TER *((volatile int32u *)0xE0000E00u) -#define ITM_TER_REG *((volatile int32u *)0xE0000E00u) +#define ITM_TER *((volatile uint32_t *)0xE0000E00u) +#define ITM_TER_REG *((volatile uint32_t *)0xE0000E00u) #define ITM_TER_ADDR (0xE0000E00u) #define ITM_TER_RESET (0x00000000u) /* STIMENA field */ @@ -8170,8 +8170,8 @@ #define ITM_TER_STIMENA_BIT (0) #define ITM_TER_STIMENA_BITS (32) -#define ITM_TPR *((volatile int32u *)0xE0000E40u) -#define ITM_TPR_REG *((volatile int32u *)0xE0000E40u) +#define ITM_TPR *((volatile uint32_t *)0xE0000E40u) +#define ITM_TPR_REG *((volatile uint32_t *)0xE0000E40u) #define ITM_TPR_ADDR (0xE0000E40u) #define ITM_TPR_RESET (0x00000000u) /* PRIVMASK field */ @@ -8180,8 +8180,8 @@ #define ITM_TPR_PRIVMASK_BIT (0) #define ITM_TPR_PRIVMASK_BITS (4) -#define ITM_TCR *((volatile int32u *)0xE0000E80u) -#define ITM_TCR_REG *((volatile int32u *)0xE0000E80u) +#define ITM_TCR *((volatile uint32_t *)0xE0000E80u) +#define ITM_TCR_REG *((volatile uint32_t *)0xE0000E80u) #define ITM_TCR_ADDR (0xE0000E80u) #define ITM_TCR_RESET (0x00000000u) /* BUSY field */ @@ -8225,8 +8225,8 @@ #define ITM_TCR_ITMEN_BIT (0) #define ITM_TCR_ITMEN_BITS (1) -#define ITM_IW *((volatile int32u *)0xE0000EF8u) -#define ITM_IW_REG *((volatile int32u *)0xE0000EF8u) +#define ITM_IW *((volatile uint32_t *)0xE0000EF8u) +#define ITM_IW_REG *((volatile uint32_t *)0xE0000EF8u) #define ITM_IW_ADDR (0xE0000EF8u) #define ITM_IW_RESET (0x00000000u) /* ATVALIDM field */ @@ -8235,8 +8235,8 @@ #define ITM_IW_ATVALIDM_BIT (0) #define ITM_IW_ATVALIDM_BITS (1) -#define ITM_IR *((volatile int32u *)0xE0000EFCu) -#define ITM_IR_REG *((volatile int32u *)0xE0000EFCu) +#define ITM_IR *((volatile uint32_t *)0xE0000EFCu) +#define ITM_IR_REG *((volatile uint32_t *)0xE0000EFCu) #define ITM_IR_ADDR (0xE0000EFCu) #define ITM_IR_RESET (0x00000000u) /* ATREADYM field */ @@ -8245,8 +8245,8 @@ #define ITM_IR_ATREADYM_BIT (0) #define ITM_IR_ATREADYM_BITS (1) -#define ITM_IMC *((volatile int32u *)0xE0000F00u) -#define ITM_IMC_REG *((volatile int32u *)0xE0000F00u) +#define ITM_IMC *((volatile uint32_t *)0xE0000F00u) +#define ITM_IMC_REG *((volatile uint32_t *)0xE0000F00u) #define ITM_IMC_ADDR (0xE0000F00u) #define ITM_IMC_RESET (0x00000000u) /* INTEGRATION field */ @@ -8255,8 +8255,8 @@ #define ITM_IMC_INTEGRATION_BIT (0) #define ITM_IMC_INTEGRATION_BITS (1) -#define ITM_LA *((volatile int32u *)0xE0000FB0u) -#define ITM_LA_REG *((volatile int32u *)0xE0000FB0u) +#define ITM_LA *((volatile uint32_t *)0xE0000FB0u) +#define ITM_LA_REG *((volatile uint32_t *)0xE0000FB0u) #define ITM_LA_ADDR (0xE0000FB0u) #define ITM_LA_RESET (0x00000000u) /* LOCKACC field */ @@ -8265,8 +8265,8 @@ #define ITM_LA_LOCKACC_BIT (0) #define ITM_LA_LOCKACC_BITS (32) -#define ITM_LS *((volatile int32u *)0xE0000FB4u) -#define ITM_LS_REG *((volatile int32u *)0xE0000FB4u) +#define ITM_LS *((volatile uint32_t *)0xE0000FB4u) +#define ITM_LS_REG *((volatile uint32_t *)0xE0000FB4u) #define ITM_LS_ADDR (0xE0000FB4u) #define ITM_LS_RESET (0x00000000u) /* BYTEACC field */ @@ -8285,8 +8285,8 @@ #define ITM_LS_PRESENT_BIT (0) #define ITM_LS_PRESENT_BITS (1) -#define ITM_PERIPHID4 *((volatile int32u *)0xE0000FD0u) -#define ITM_PERIPHID4_REG *((volatile int32u *)0xE0000FD0u) +#define ITM_PERIPHID4 *((volatile uint32_t *)0xE0000FD0u) +#define ITM_PERIPHID4_REG *((volatile uint32_t *)0xE0000FD0u) #define ITM_PERIPHID4_ADDR (0xE0000FD0u) #define ITM_PERIPHID4_RESET (0x00000004u) /* PERIPHID field */ @@ -8295,8 +8295,8 @@ #define ITM_PERIPHID4_PERIPHID_BIT (0) #define ITM_PERIPHID4_PERIPHID_BITS (32) -#define ITM_PERIPHID5 *((volatile int32u *)0xE0000FD4u) -#define ITM_PERIPHID5_REG *((volatile int32u *)0xE0000FD4u) +#define ITM_PERIPHID5 *((volatile uint32_t *)0xE0000FD4u) +#define ITM_PERIPHID5_REG *((volatile uint32_t *)0xE0000FD4u) #define ITM_PERIPHID5_ADDR (0xE0000FD4u) #define ITM_PERIPHID5_RESET (0x00000000u) /* PERIPHID field */ @@ -8305,8 +8305,8 @@ #define ITM_PERIPHID5_PERIPHID_BIT (0) #define ITM_PERIPHID5_PERIPHID_BITS (32) -#define ITM_PERIPHID6 *((volatile int32u *)0xE0000FD8u) -#define ITM_PERIPHID6_REG *((volatile int32u *)0xE0000FD8u) +#define ITM_PERIPHID6 *((volatile uint32_t *)0xE0000FD8u) +#define ITM_PERIPHID6_REG *((volatile uint32_t *)0xE0000FD8u) #define ITM_PERIPHID6_ADDR (0xE0000FD8u) #define ITM_PERIPHID6_RESET (0x00000000u) /* PERIPHID field */ @@ -8315,8 +8315,8 @@ #define ITM_PERIPHID6_PERIPHID_BIT (0) #define ITM_PERIPHID6_PERIPHID_BITS (32) -#define ITM_PERIPHID7 *((volatile int32u *)0xE0000FDCu) -#define ITM_PERIPHID7_REG *((volatile int32u *)0xE0000FDCu) +#define ITM_PERIPHID7 *((volatile uint32_t *)0xE0000FDCu) +#define ITM_PERIPHID7_REG *((volatile uint32_t *)0xE0000FDCu) #define ITM_PERIPHID7_ADDR (0xE0000FDCu) #define ITM_PERIPHID7_RESET (0x00000000u) /* PERIPHID field */ @@ -8325,8 +8325,8 @@ #define ITM_PERIPHID7_PERIPHID_BIT (0) #define ITM_PERIPHID7_PERIPHID_BITS (32) -#define ITM_PERIPHID0 *((volatile int32u *)0xE0000FE0u) -#define ITM_PERIPHID0_REG *((volatile int32u *)0xE0000FE0u) +#define ITM_PERIPHID0 *((volatile uint32_t *)0xE0000FE0u) +#define ITM_PERIPHID0_REG *((volatile uint32_t *)0xE0000FE0u) #define ITM_PERIPHID0_ADDR (0xE0000FE0u) #define ITM_PERIPHID0_RESET (0x00000001u) /* PERIPHID field */ @@ -8335,8 +8335,8 @@ #define ITM_PERIPHID0_PERIPHID_BIT (0) #define ITM_PERIPHID0_PERIPHID_BITS (32) -#define ITM_PERIPHID1 *((volatile int32u *)0xE0000FE4u) -#define ITM_PERIPHID1_REG *((volatile int32u *)0xE0000FE4u) +#define ITM_PERIPHID1 *((volatile uint32_t *)0xE0000FE4u) +#define ITM_PERIPHID1_REG *((volatile uint32_t *)0xE0000FE4u) #define ITM_PERIPHID1_ADDR (0xE0000FE4u) #define ITM_PERIPHID1_RESET (0x000000B0u) /* PERIPHID field */ @@ -8345,8 +8345,8 @@ #define ITM_PERIPHID1_PERIPHID_BIT (0) #define ITM_PERIPHID1_PERIPHID_BITS (32) -#define ITM_PERIPHID2 *((volatile int32u *)0xE0000FE8u) -#define ITM_PERIPHID2_REG *((volatile int32u *)0xE0000FE8u) +#define ITM_PERIPHID2 *((volatile uint32_t *)0xE0000FE8u) +#define ITM_PERIPHID2_REG *((volatile uint32_t *)0xE0000FE8u) #define ITM_PERIPHID2_ADDR (0xE0000FE8u) #define ITM_PERIPHID2_RESET (0x0000001Bu) /* PERIPHID field */ @@ -8355,8 +8355,8 @@ #define ITM_PERIPHID2_PERIPHID_BIT (0) #define ITM_PERIPHID2_PERIPHID_BITS (32) -#define ITM_PERIPHID3 *((volatile int32u *)0xE0000FECu) -#define ITM_PERIPHID3_REG *((volatile int32u *)0xE0000FECu) +#define ITM_PERIPHID3 *((volatile uint32_t *)0xE0000FECu) +#define ITM_PERIPHID3_REG *((volatile uint32_t *)0xE0000FECu) #define ITM_PERIPHID3_ADDR (0xE0000FECu) #define ITM_PERIPHID3_RESET (0x00000000u) /* PERIPHID field */ @@ -8365,8 +8365,8 @@ #define ITM_PERIPHID3_PERIPHID_BIT (0) #define ITM_PERIPHID3_PERIPHID_BITS (32) -#define ITM_CELLID0 *((volatile int32u *)0xE0000FF0u) -#define ITM_CELLID0_REG *((volatile int32u *)0xE0000FF0u) +#define ITM_CELLID0 *((volatile uint32_t *)0xE0000FF0u) +#define ITM_CELLID0_REG *((volatile uint32_t *)0xE0000FF0u) #define ITM_CELLID0_ADDR (0xE0000FF0u) #define ITM_CELLID0_RESET (0x0000000Du) /* PERIPHID field */ @@ -8375,8 +8375,8 @@ #define ITM_CELLID0_PERIPHID_BIT (0) #define ITM_CELLID0_PERIPHID_BITS (32) -#define ITM_CELLID1 *((volatile int32u *)0xE0000FF4u) -#define ITM_CELLID1_REG *((volatile int32u *)0xE0000FF4u) +#define ITM_CELLID1 *((volatile uint32_t *)0xE0000FF4u) +#define ITM_CELLID1_REG *((volatile uint32_t *)0xE0000FF4u) #define ITM_CELLID1_ADDR (0xE0000FF4u) #define ITM_CELLID1_RESET (0x000000E0u) /* PERIPHID field */ @@ -8385,8 +8385,8 @@ #define ITM_CELLID1_PERIPHID_BIT (0) #define ITM_CELLID1_PERIPHID_BITS (32) -#define ITM_CELLID2 *((volatile int32u *)0xE0000FF8u) -#define ITM_CELLID2_REG *((volatile int32u *)0xE0000FF8u) +#define ITM_CELLID2 *((volatile uint32_t *)0xE0000FF8u) +#define ITM_CELLID2_REG *((volatile uint32_t *)0xE0000FF8u) #define ITM_CELLID2_ADDR (0xE0000FF8u) #define ITM_CELLID2_RESET (0x00000005u) /* PERIPHID field */ @@ -8395,8 +8395,8 @@ #define ITM_CELLID2_PERIPHID_BIT (0) #define ITM_CELLID2_PERIPHID_BITS (32) -#define ITM_CELLID3 *((volatile int32u *)0xE0000FFCu) -#define ITM_CELLID3_REG *((volatile int32u *)0xE0000FFCu) +#define ITM_CELLID3 *((volatile uint32_t *)0xE0000FFCu) +#define ITM_CELLID3_REG *((volatile uint32_t *)0xE0000FFCu) #define ITM_CELLID3_ADDR (0xE0000FFCu) #define ITM_CELLID3_RESET (0x000000B1u) /* PERIPHID field */ @@ -8410,8 +8410,8 @@ #define DATA_DWT_END (0xE0001FFFu) #define DATA_DWT_SIZE (DATA_DWT_END - DATA_DWT_BASE + 1) -#define DWT_CTRL *((volatile int32u *)0xE0001000u) -#define DWT_CTRL_REG *((volatile int32u *)0xE0001000u) +#define DWT_CTRL *((volatile uint32_t *)0xE0001000u) +#define DWT_CTRL_REG *((volatile uint32_t *)0xE0001000u) #define DWT_CTRL_ADDR (0xE0001000u) #define DWT_CTRL_RESET (0x40000000u) /* NUMCOMP field */ @@ -8485,8 +8485,8 @@ #define DWT_CTRL_CYCCNTENA_BIT (0) #define DWT_CTRL_CYCCNTENA_BITS (1) -#define DWT_CYCCNT *((volatile int32u *)0xE0001004u) -#define DWT_CYCCNT_REG *((volatile int32u *)0xE0001004u) +#define DWT_CYCCNT *((volatile uint32_t *)0xE0001004u) +#define DWT_CYCCNT_REG *((volatile uint32_t *)0xE0001004u) #define DWT_CYCCNT_ADDR (0xE0001004u) #define DWT_CYCCNT_RESET (0x00000000u) /* CYCCNT field */ @@ -8495,8 +8495,8 @@ #define DWT_CYCCNT_CYCCNT_BIT (0) #define DWT_CYCCNT_CYCCNT_BITS (32) -#define DWT_CPICNT *((volatile int32u *)0xE0001008u) -#define DWT_CPICNT_REG *((volatile int32u *)0xE0001008u) +#define DWT_CPICNT *((volatile uint32_t *)0xE0001008u) +#define DWT_CPICNT_REG *((volatile uint32_t *)0xE0001008u) #define DWT_CPICNT_ADDR (0xE0001008u) #define DWT_CPICNT_RESET (0x00000000u) /* CPICNT field */ @@ -8505,8 +8505,8 @@ #define DWT_CPICNT_CPICNT_BIT (0) #define DWT_CPICNT_CPICNT_BITS (8) -#define DWT_EXCCNT *((volatile int32u *)0xE000100Cu) -#define DWT_EXCCNT_REG *((volatile int32u *)0xE000100Cu) +#define DWT_EXCCNT *((volatile uint32_t *)0xE000100Cu) +#define DWT_EXCCNT_REG *((volatile uint32_t *)0xE000100Cu) #define DWT_EXCCNT_ADDR (0xE000100Cu) #define DWT_EXCCNT_RESET (0x00000000u) /* EXCCNT field */ @@ -8515,8 +8515,8 @@ #define DWT_EXCCNT_EXCCNT_BIT (0) #define DWT_EXCCNT_EXCCNT_BITS (8) -#define DWT_SLEEPCNT *((volatile int32u *)0xE0001010u) -#define DWT_SLEEPCNT_REG *((volatile int32u *)0xE0001010u) +#define DWT_SLEEPCNT *((volatile uint32_t *)0xE0001010u) +#define DWT_SLEEPCNT_REG *((volatile uint32_t *)0xE0001010u) #define DWT_SLEEPCNT_ADDR (0xE0001010u) #define DWT_SLEEPCNT_RESET (0x00000000u) /* SLEEPCNT field */ @@ -8525,8 +8525,8 @@ #define DWT_SLEEPCNT_SLEEPCNT_BIT (0) #define DWT_SLEEPCNT_SLEEPCNT_BITS (8) -#define DWT_LSUCNT *((volatile int32u *)0xE0001014u) -#define DWT_LSUCNT_REG *((volatile int32u *)0xE0001014u) +#define DWT_LSUCNT *((volatile uint32_t *)0xE0001014u) +#define DWT_LSUCNT_REG *((volatile uint32_t *)0xE0001014u) #define DWT_LSUCNT_ADDR (0xE0001014u) #define DWT_LSUCNT_RESET (0x00000000u) /* CPICNT field */ @@ -8535,8 +8535,8 @@ #define DWT_LSUCNT_CPICNT_BIT (0) #define DWT_LSUCNT_CPICNT_BITS (8) -#define DWT_FOLDCNT *((volatile int32u *)0xE0001018u) -#define DWT_FOLDCNT_REG *((volatile int32u *)0xE0001018u) +#define DWT_FOLDCNT *((volatile uint32_t *)0xE0001018u) +#define DWT_FOLDCNT_REG *((volatile uint32_t *)0xE0001018u) #define DWT_FOLDCNT_ADDR (0xE0001018u) #define DWT_FOLDCNT_RESET (0x00000000u) /* CPICNT field */ @@ -8545,8 +8545,8 @@ #define DWT_FOLDCNT_CPICNT_BIT (0) #define DWT_FOLDCNT_CPICNT_BITS (8) -#define DWT_PCSR *((volatile int32u *)0xE000101Cu) -#define DWT_PCSR_REG *((volatile int32u *)0xE000101Cu) +#define DWT_PCSR *((volatile uint32_t *)0xE000101Cu) +#define DWT_PCSR_REG *((volatile uint32_t *)0xE000101Cu) #define DWT_PCSR_ADDR (0xE000101Cu) #define DWT_PCSR_RESET (0x00000000u) /* EIASAMPLE field */ @@ -8555,8 +8555,8 @@ #define DWT_PCSR_EIASAMPLE_BIT (0) #define DWT_PCSR_EIASAMPLE_BITS (32) -#define DWT_COMP0 *((volatile int32u *)0xE0001020u) -#define DWT_COMP0_REG *((volatile int32u *)0xE0001020u) +#define DWT_COMP0 *((volatile uint32_t *)0xE0001020u) +#define DWT_COMP0_REG *((volatile uint32_t *)0xE0001020u) #define DWT_COMP0_ADDR (0xE0001020u) #define DWT_COMP0_RESET (0x00000000u) /* COMP0 field */ @@ -8565,8 +8565,8 @@ #define DWT_COMP0_COMP0_BIT (0) #define DWT_COMP0_COMP0_BITS (32) -#define DWT_MASK0 *((volatile int32u *)0xE0001024u) -#define DWT_MASK0_REG *((volatile int32u *)0xE0001024u) +#define DWT_MASK0 *((volatile uint32_t *)0xE0001024u) +#define DWT_MASK0_REG *((volatile uint32_t *)0xE0001024u) #define DWT_MASK0_ADDR (0xE0001024u) #define DWT_MASK0_RESET (0x00000000u) /* MASK0 field */ @@ -8575,8 +8575,8 @@ #define DWT_MASK0_MASK0_BIT (0) #define DWT_MASK0_MASK0_BITS (5) -#define DWT_FUNCTION0 *((volatile int32u *)0xE0001028u) -#define DWT_FUNCTION0_REG *((volatile int32u *)0xE0001028u) +#define DWT_FUNCTION0 *((volatile uint32_t *)0xE0001028u) +#define DWT_FUNCTION0_REG *((volatile uint32_t *)0xE0001028u) #define DWT_FUNCTION0_ADDR (0xE0001028u) #define DWT_FUNCTION0_RESET (0x00000000u) /* MATCHED field */ @@ -8600,8 +8600,8 @@ #define DWT_FUNCTION0_FUNCTION_BIT (0) #define DWT_FUNCTION0_FUNCTION_BITS (4) -#define DWT_COMP1 *((volatile int32u *)0xE0001030u) -#define DWT_COMP1_REG *((volatile int32u *)0xE0001030u) +#define DWT_COMP1 *((volatile uint32_t *)0xE0001030u) +#define DWT_COMP1_REG *((volatile uint32_t *)0xE0001030u) #define DWT_COMP1_ADDR (0xE0001030u) #define DWT_COMP1_RESET (0x00000000u) /* COMP1 field */ @@ -8610,8 +8610,8 @@ #define DWT_COMP1_COMP1_BIT (0) #define DWT_COMP1_COMP1_BITS (32) -#define DWT_MASK1 *((volatile int32u *)0xE0001034u) -#define DWT_MASK1_REG *((volatile int32u *)0xE0001034u) +#define DWT_MASK1 *((volatile uint32_t *)0xE0001034u) +#define DWT_MASK1_REG *((volatile uint32_t *)0xE0001034u) #define DWT_MASK1_ADDR (0xE0001034u) #define DWT_MASK1_RESET (0x00000000u) /* MASK1 field */ @@ -8620,8 +8620,8 @@ #define DWT_MASK1_MASK1_BIT (0) #define DWT_MASK1_MASK1_BITS (5) -#define DWT_FUNCTION1 *((volatile int32u *)0xE0001038u) -#define DWT_FUNCTION1_REG *((volatile int32u *)0xE0001038u) +#define DWT_FUNCTION1 *((volatile uint32_t *)0xE0001038u) +#define DWT_FUNCTION1_REG *((volatile uint32_t *)0xE0001038u) #define DWT_FUNCTION1_ADDR (0xE0001038u) #define DWT_FUNCTION1_RESET (0x00000200u) /* MATCHED field */ @@ -8665,8 +8665,8 @@ #define DWT_FUNCTION1_FUNCTION_BIT (0) #define DWT_FUNCTION1_FUNCTION_BITS (4) -#define DWT_COMP2 *((volatile int32u *)0xE0001040u) -#define DWT_COMP2_REG *((volatile int32u *)0xE0001040u) +#define DWT_COMP2 *((volatile uint32_t *)0xE0001040u) +#define DWT_COMP2_REG *((volatile uint32_t *)0xE0001040u) #define DWT_COMP2_ADDR (0xE0001040u) #define DWT_COMP2_RESET (0x00000000u) /* COMP2 field */ @@ -8675,8 +8675,8 @@ #define DWT_COMP2_COMP2_BIT (0) #define DWT_COMP2_COMP2_BITS (32) -#define DWT_MASK2 *((volatile int32u *)0xE0001044u) -#define DWT_MASK2_REG *((volatile int32u *)0xE0001044u) +#define DWT_MASK2 *((volatile uint32_t *)0xE0001044u) +#define DWT_MASK2_REG *((volatile uint32_t *)0xE0001044u) #define DWT_MASK2_ADDR (0xE0001044u) #define DWT_MASK2_RESET (0x00000000u) /* MASK2 field */ @@ -8685,8 +8685,8 @@ #define DWT_MASK2_MASK2_BIT (0) #define DWT_MASK2_MASK2_BITS (5) -#define DWT_FUNCTION2 *((volatile int32u *)0xE0001048u) -#define DWT_FUNCTION2_REG *((volatile int32u *)0xE0001048u) +#define DWT_FUNCTION2 *((volatile uint32_t *)0xE0001048u) +#define DWT_FUNCTION2_REG *((volatile uint32_t *)0xE0001048u) #define DWT_FUNCTION2_ADDR (0xE0001048u) #define DWT_FUNCTION2_RESET (0x00000000u) /* MATCHED field */ @@ -8705,8 +8705,8 @@ #define DWT_FUNCTION2_FUNCTION_BIT (0) #define DWT_FUNCTION2_FUNCTION_BITS (4) -#define DWT_COMP3 *((volatile int32u *)0xE0001050u) -#define DWT_COMP3_REG *((volatile int32u *)0xE0001050u) +#define DWT_COMP3 *((volatile uint32_t *)0xE0001050u) +#define DWT_COMP3_REG *((volatile uint32_t *)0xE0001050u) #define DWT_COMP3_ADDR (0xE0001050u) #define DWT_COMP3_RESET (0x00000000u) /* COMP3 field */ @@ -8715,8 +8715,8 @@ #define DWT_COMP3_COMP3_BIT (0) #define DWT_COMP3_COMP3_BITS (32) -#define DWT_MASK3 *((volatile int32u *)0xE0001054u) -#define DWT_MASK3_REG *((volatile int32u *)0xE0001054u) +#define DWT_MASK3 *((volatile uint32_t *)0xE0001054u) +#define DWT_MASK3_REG *((volatile uint32_t *)0xE0001054u) #define DWT_MASK3_ADDR (0xE0001054u) #define DWT_MASK3_RESET (0x00000000u) /* MASK3 field */ @@ -8725,8 +8725,8 @@ #define DWT_MASK3_MASK3_BIT (0) #define DWT_MASK3_MASK3_BITS (5) -#define DWT_FUNCTION3 *((volatile int32u *)0xE0001058u) -#define DWT_FUNCTION3_REG *((volatile int32u *)0xE0001058u) +#define DWT_FUNCTION3 *((volatile uint32_t *)0xE0001058u) +#define DWT_FUNCTION3_REG *((volatile uint32_t *)0xE0001058u) #define DWT_FUNCTION3_ADDR (0xE0001058u) #define DWT_FUNCTION3_RESET (0x00000000u) /* MATCHED field */ @@ -8745,8 +8745,8 @@ #define DWT_FUNCTION3_FUNCTION_BIT (0) #define DWT_FUNCTION3_FUNCTION_BITS (4) -#define DWT_PERIPHID4 *((volatile int32u *)0xE0001FD0u) -#define DWT_PERIPHID4_REG *((volatile int32u *)0xE0001FD0u) +#define DWT_PERIPHID4 *((volatile uint32_t *)0xE0001FD0u) +#define DWT_PERIPHID4_REG *((volatile uint32_t *)0xE0001FD0u) #define DWT_PERIPHID4_ADDR (0xE0001FD0u) #define DWT_PERIPHID4_RESET (0x00000004u) /* PERIPHID field */ @@ -8755,8 +8755,8 @@ #define DWT_PERIPHID4_PERIPHID_BIT (0) #define DWT_PERIPHID4_PERIPHID_BITS (32) -#define DWT_PERIPHID5 *((volatile int32u *)0xE0001FD4u) -#define DWT_PERIPHID5_REG *((volatile int32u *)0xE0001FD4u) +#define DWT_PERIPHID5 *((volatile uint32_t *)0xE0001FD4u) +#define DWT_PERIPHID5_REG *((volatile uint32_t *)0xE0001FD4u) #define DWT_PERIPHID5_ADDR (0xE0001FD4u) #define DWT_PERIPHID5_RESET (0x00000000u) /* PERIPHID field */ @@ -8765,8 +8765,8 @@ #define DWT_PERIPHID5_PERIPHID_BIT (0) #define DWT_PERIPHID5_PERIPHID_BITS (32) -#define DWT_PERIPHID6 *((volatile int32u *)0xE0001FD8u) -#define DWT_PERIPHID6_REG *((volatile int32u *)0xE0001FD8u) +#define DWT_PERIPHID6 *((volatile uint32_t *)0xE0001FD8u) +#define DWT_PERIPHID6_REG *((volatile uint32_t *)0xE0001FD8u) #define DWT_PERIPHID6_ADDR (0xE0001FD8u) #define DWT_PERIPHID6_RESET (0x00000000u) /* PERIPHID field */ @@ -8775,8 +8775,8 @@ #define DWT_PERIPHID6_PERIPHID_BIT (0) #define DWT_PERIPHID6_PERIPHID_BITS (32) -#define DWT_PERIPHID7 *((volatile int32u *)0xE0001FDCu) -#define DWT_PERIPHID7_REG *((volatile int32u *)0xE0001FDCu) +#define DWT_PERIPHID7 *((volatile uint32_t *)0xE0001FDCu) +#define DWT_PERIPHID7_REG *((volatile uint32_t *)0xE0001FDCu) #define DWT_PERIPHID7_ADDR (0xE0001FDCu) #define DWT_PERIPHID7_RESET (0x00000000u) /* PERIPHID field */ @@ -8785,8 +8785,8 @@ #define DWT_PERIPHID7_PERIPHID_BIT (0) #define DWT_PERIPHID7_PERIPHID_BITS (32) -#define DWT_PERIPHID0 *((volatile int32u *)0xE0001FE0u) -#define DWT_PERIPHID0_REG *((volatile int32u *)0xE0001FE0u) +#define DWT_PERIPHID0 *((volatile uint32_t *)0xE0001FE0u) +#define DWT_PERIPHID0_REG *((volatile uint32_t *)0xE0001FE0u) #define DWT_PERIPHID0_ADDR (0xE0001FE0u) #define DWT_PERIPHID0_RESET (0x00000002u) /* PERIPHID field */ @@ -8795,8 +8795,8 @@ #define DWT_PERIPHID0_PERIPHID_BIT (0) #define DWT_PERIPHID0_PERIPHID_BITS (32) -#define DWT_PERIPHID1 *((volatile int32u *)0xE0001FE4u) -#define DWT_PERIPHID1_REG *((volatile int32u *)0xE0001FE4u) +#define DWT_PERIPHID1 *((volatile uint32_t *)0xE0001FE4u) +#define DWT_PERIPHID1_REG *((volatile uint32_t *)0xE0001FE4u) #define DWT_PERIPHID1_ADDR (0xE0001FE4u) #define DWT_PERIPHID1_RESET (0x00000000u) /* PERIPHID field */ @@ -8805,8 +8805,8 @@ #define DWT_PERIPHID1_PERIPHID_BIT (0) #define DWT_PERIPHID1_PERIPHID_BITS (32) -#define DWT_PERIPHID2 *((volatile int32u *)0xE0001FE8u) -#define DWT_PERIPHID2_REG *((volatile int32u *)0xE0001FE8u) +#define DWT_PERIPHID2 *((volatile uint32_t *)0xE0001FE8u) +#define DWT_PERIPHID2_REG *((volatile uint32_t *)0xE0001FE8u) #define DWT_PERIPHID2_ADDR (0xE0001FE8u) #define DWT_PERIPHID2_RESET (0x0000001Bu) /* PERIPHID field */ @@ -8815,8 +8815,8 @@ #define DWT_PERIPHID2_PERIPHID_BIT (0) #define DWT_PERIPHID2_PERIPHID_BITS (32) -#define DWT_PERIPHID3 *((volatile int32u *)0xE0001FECu) -#define DWT_PERIPHID3_REG *((volatile int32u *)0xE0001FECu) +#define DWT_PERIPHID3 *((volatile uint32_t *)0xE0001FECu) +#define DWT_PERIPHID3_REG *((volatile uint32_t *)0xE0001FECu) #define DWT_PERIPHID3_ADDR (0xE0001FECu) #define DWT_PERIPHID3_RESET (0x00000000u) /* PERIPHID field */ @@ -8825,8 +8825,8 @@ #define DWT_PERIPHID3_PERIPHID_BIT (0) #define DWT_PERIPHID3_PERIPHID_BITS (32) -#define DWT_CELLID0 *((volatile int32u *)0xE0001FF0u) -#define DWT_CELLID0_REG *((volatile int32u *)0xE0001FF0u) +#define DWT_CELLID0 *((volatile uint32_t *)0xE0001FF0u) +#define DWT_CELLID0_REG *((volatile uint32_t *)0xE0001FF0u) #define DWT_CELLID0_ADDR (0xE0001FF0u) #define DWT_CELLID0_RESET (0x0000000Du) /* CELLID field */ @@ -8835,8 +8835,8 @@ #define DWT_CELLID0_CELLID_BIT (0) #define DWT_CELLID0_CELLID_BITS (32) -#define DWT_CELLID1 *((volatile int32u *)0xE0001FF4u) -#define DWT_CELLID1_REG *((volatile int32u *)0xE0001FF4u) +#define DWT_CELLID1 *((volatile uint32_t *)0xE0001FF4u) +#define DWT_CELLID1_REG *((volatile uint32_t *)0xE0001FF4u) #define DWT_CELLID1_ADDR (0xE0001FF4u) #define DWT_CELLID1_RESET (0x000000E0u) /* CELLID field */ @@ -8845,8 +8845,8 @@ #define DWT_CELLID1_CELLID_BIT (0) #define DWT_CELLID1_CELLID_BITS (32) -#define DWT_CELLID2 *((volatile int32u *)0xE0001FF8u) -#define DWT_CELLID2_REG *((volatile int32u *)0xE0001FF8u) +#define DWT_CELLID2 *((volatile uint32_t *)0xE0001FF8u) +#define DWT_CELLID2_REG *((volatile uint32_t *)0xE0001FF8u) #define DWT_CELLID2_ADDR (0xE0001FF8u) #define DWT_CELLID2_RESET (0x00000005u) /* CELLID field */ @@ -8855,8 +8855,8 @@ #define DWT_CELLID2_CELLID_BIT (0) #define DWT_CELLID2_CELLID_BITS (32) -#define DWT_CELLID3 *((volatile int32u *)0xE0001FFCu) -#define DWT_CELLID3_REG *((volatile int32u *)0xE0001FFCu) +#define DWT_CELLID3 *((volatile uint32_t *)0xE0001FFCu) +#define DWT_CELLID3_REG *((volatile uint32_t *)0xE0001FFCu) #define DWT_CELLID3_ADDR (0xE0001FFCu) #define DWT_CELLID3_RESET (0x000000B1u) /* CELLID field */ @@ -8870,8 +8870,8 @@ #define DATA_FPB_END (0xE0002FFFu) #define DATA_FPB_SIZE (DATA_FPB_END - DATA_FPB_BASE + 1) -#define FPB_CTRL *((volatile int32u *)0xE0002000u) -#define FPB_CTRL_REG *((volatile int32u *)0xE0002000u) +#define FPB_CTRL *((volatile uint32_t *)0xE0002000u) +#define FPB_CTRL_REG *((volatile uint32_t *)0xE0002000u) #define FPB_CTRL_ADDR (0xE0002000u) #define FPB_CTRL_RESET (0x00000000u) /* NUM_LIT field */ @@ -8895,8 +8895,8 @@ #define FPB_CTRL_enable_BIT (0) #define FPB_CTRL_enable_BITS (1) -#define FPB_REMAP *((volatile int32u *)0xE0002004u) -#define FPB_REMAP_REG *((volatile int32u *)0xE0002004u) +#define FPB_REMAP *((volatile uint32_t *)0xE0002004u) +#define FPB_REMAP_REG *((volatile uint32_t *)0xE0002004u) #define FPB_REMAP_ADDR (0xE0002004u) #define FPB_REMAP_RESET (0x20000000u) /* REMAP field */ @@ -8905,8 +8905,8 @@ #define FPB_REMAP_REMAP_BIT (5) #define FPB_REMAP_REMAP_BITS (24) -#define FPB_COMP0 *((volatile int32u *)0xE0002008u) -#define FPB_COMP0_REG *((volatile int32u *)0xE0002008u) +#define FPB_COMP0 *((volatile uint32_t *)0xE0002008u) +#define FPB_COMP0_REG *((volatile uint32_t *)0xE0002008u) #define FPB_COMP0_ADDR (0xE0002008u) #define FPB_COMP0_RESET (0x00000000u) /* REPLACE field */ @@ -8925,8 +8925,8 @@ #define FPB_COMP0_enable_BIT (0) #define FPB_COMP0_enable_BITS (1) -#define FPB_COMP1 *((volatile int32u *)0xE000200Cu) -#define FPB_COMP1_REG *((volatile int32u *)0xE000200Cu) +#define FPB_COMP1 *((volatile uint32_t *)0xE000200Cu) +#define FPB_COMP1_REG *((volatile uint32_t *)0xE000200Cu) #define FPB_COMP1_ADDR (0xE000200Cu) #define FPB_COMP1_RESET (0x00000000u) /* REPLACE field */ @@ -8945,8 +8945,8 @@ #define FPB_COMP1_enable_BIT (0) #define FPB_COMP1_enable_BITS (1) -#define FPB_COMP2 *((volatile int32u *)0xE0002010u) -#define FPB_COMP2_REG *((volatile int32u *)0xE0002010u) +#define FPB_COMP2 *((volatile uint32_t *)0xE0002010u) +#define FPB_COMP2_REG *((volatile uint32_t *)0xE0002010u) #define FPB_COMP2_ADDR (0xE0002010u) #define FPB_COMP2_RESET (0x00000000u) /* REPLACE field */ @@ -8965,8 +8965,8 @@ #define FPB_COMP2_enable_BIT (0) #define FPB_COMP2_enable_BITS (1) -#define FPB_COMP3 *((volatile int32u *)0xE0002014u) -#define FPB_COMP3_REG *((volatile int32u *)0xE0002014u) +#define FPB_COMP3 *((volatile uint32_t *)0xE0002014u) +#define FPB_COMP3_REG *((volatile uint32_t *)0xE0002014u) #define FPB_COMP3_ADDR (0xE0002014u) #define FPB_COMP3_RESET (0x00000000u) /* REPLACE field */ @@ -8985,8 +8985,8 @@ #define FPB_COMP3_enable_BIT (0) #define FPB_COMP3_enable_BITS (1) -#define FPB_COMP4 *((volatile int32u *)0xE0002018u) -#define FPB_COMP4_REG *((volatile int32u *)0xE0002018u) +#define FPB_COMP4 *((volatile uint32_t *)0xE0002018u) +#define FPB_COMP4_REG *((volatile uint32_t *)0xE0002018u) #define FPB_COMP4_ADDR (0xE0002018u) #define FPB_COMP4_RESET (0x00000000u) /* REPLACE field */ @@ -9005,8 +9005,8 @@ #define FPB_COMP4_enable_BIT (0) #define FPB_COMP4_enable_BITS (1) -#define FPB_COMP5 *((volatile int32u *)0xE000201Cu) -#define FPB_COMP5_REG *((volatile int32u *)0xE000201Cu) +#define FPB_COMP5 *((volatile uint32_t *)0xE000201Cu) +#define FPB_COMP5_REG *((volatile uint32_t *)0xE000201Cu) #define FPB_COMP5_ADDR (0xE000201Cu) #define FPB_COMP5_RESET (0x00000000u) /* REPLACE field */ @@ -9025,8 +9025,8 @@ #define FPB_COMP5_enable_BIT (0) #define FPB_COMP5_enable_BITS (1) -#define FPB_COMP6 *((volatile int32u *)0xE0002020u) -#define FPB_COMP6_REG *((volatile int32u *)0xE0002020u) +#define FPB_COMP6 *((volatile uint32_t *)0xE0002020u) +#define FPB_COMP6_REG *((volatile uint32_t *)0xE0002020u) #define FPB_COMP6_ADDR (0xE0002020u) #define FPB_COMP6_RESET (0x00000000u) /* REPLACE field */ @@ -9045,8 +9045,8 @@ #define FPB_COMP6_enable_BIT (0) #define FPB_COMP6_enable_BITS (1) -#define FPB_COMP7 *((volatile int32u *)0xE0002024u) -#define FPB_COMP7_REG *((volatile int32u *)0xE0002024u) +#define FPB_COMP7 *((volatile uint32_t *)0xE0002024u) +#define FPB_COMP7_REG *((volatile uint32_t *)0xE0002024u) #define FPB_COMP7_ADDR (0xE0002024u) #define FPB_COMP7_RESET (0x00000000u) /* REPLACE field */ @@ -9065,8 +9065,8 @@ #define FPB_COMP7_enable_BIT (0) #define FPB_COMP7_enable_BITS (1) -#define FPB_PERIPHID4 *((volatile int32u *)0xE0002FD0u) -#define FPB_PERIPHID4_REG *((volatile int32u *)0xE0002FD0u) +#define FPB_PERIPHID4 *((volatile uint32_t *)0xE0002FD0u) +#define FPB_PERIPHID4_REG *((volatile uint32_t *)0xE0002FD0u) #define FPB_PERIPHID4_ADDR (0xE0002FD0u) #define FPB_PERIPHID4_RESET (0x00000004u) /* PERIPHID field */ @@ -9075,8 +9075,8 @@ #define FPB_PERIPHID4_PERIPHID_BIT (0) #define FPB_PERIPHID4_PERIPHID_BITS (32) -#define FPB_PERIPHID5 *((volatile int32u *)0xE0002FD4u) -#define FPB_PERIPHID5_REG *((volatile int32u *)0xE0002FD4u) +#define FPB_PERIPHID5 *((volatile uint32_t *)0xE0002FD4u) +#define FPB_PERIPHID5_REG *((volatile uint32_t *)0xE0002FD4u) #define FPB_PERIPHID5_ADDR (0xE0002FD4u) #define FPB_PERIPHID5_RESET (0x00000000u) /* PERIPHID field */ @@ -9085,8 +9085,8 @@ #define FPB_PERIPHID5_PERIPHID_BIT (0) #define FPB_PERIPHID5_PERIPHID_BITS (32) -#define FPB_PERIPHID6 *((volatile int32u *)0xE0002FD8u) -#define FPB_PERIPHID6_REG *((volatile int32u *)0xE0002FD8u) +#define FPB_PERIPHID6 *((volatile uint32_t *)0xE0002FD8u) +#define FPB_PERIPHID6_REG *((volatile uint32_t *)0xE0002FD8u) #define FPB_PERIPHID6_ADDR (0xE0002FD8u) #define FPB_PERIPHID6_RESET (0x00000000u) /* PERIPHID field */ @@ -9095,8 +9095,8 @@ #define FPB_PERIPHID6_PERIPHID_BIT (0) #define FPB_PERIPHID6_PERIPHID_BITS (32) -#define FPB_PERIPHID7 *((volatile int32u *)0xE0002FDCu) -#define FPB_PERIPHID7_REG *((volatile int32u *)0xE0002FDCu) +#define FPB_PERIPHID7 *((volatile uint32_t *)0xE0002FDCu) +#define FPB_PERIPHID7_REG *((volatile uint32_t *)0xE0002FDCu) #define FPB_PERIPHID7_ADDR (0xE0002FDCu) #define FPB_PERIPHID7_RESET (0x00000000u) /* PERIPHID field */ @@ -9105,8 +9105,8 @@ #define FPB_PERIPHID7_PERIPHID_BIT (0) #define FPB_PERIPHID7_PERIPHID_BITS (32) -#define FPB_PERIPHID0 *((volatile int32u *)0xE0002FE0u) -#define FPB_PERIPHID0_REG *((volatile int32u *)0xE0002FE0u) +#define FPB_PERIPHID0 *((volatile uint32_t *)0xE0002FE0u) +#define FPB_PERIPHID0_REG *((volatile uint32_t *)0xE0002FE0u) #define FPB_PERIPHID0_ADDR (0xE0002FE0u) #define FPB_PERIPHID0_RESET (0x00000003u) /* PERIPHID field */ @@ -9115,8 +9115,8 @@ #define FPB_PERIPHID0_PERIPHID_BIT (0) #define FPB_PERIPHID0_PERIPHID_BITS (32) -#define FPB_PERIPHID1 *((volatile int32u *)0xE0002FE4u) -#define FPB_PERIPHID1_REG *((volatile int32u *)0xE0002FE4u) +#define FPB_PERIPHID1 *((volatile uint32_t *)0xE0002FE4u) +#define FPB_PERIPHID1_REG *((volatile uint32_t *)0xE0002FE4u) #define FPB_PERIPHID1_ADDR (0xE0002FE4u) #define FPB_PERIPHID1_RESET (0x000000B0u) /* PERIPHID field */ @@ -9125,8 +9125,8 @@ #define FPB_PERIPHID1_PERIPHID_BIT (0) #define FPB_PERIPHID1_PERIPHID_BITS (32) -#define FPB_PERIPHID2 *((volatile int32u *)0xE0002FE8u) -#define FPB_PERIPHID2_REG *((volatile int32u *)0xE0002FE8u) +#define FPB_PERIPHID2 *((volatile uint32_t *)0xE0002FE8u) +#define FPB_PERIPHID2_REG *((volatile uint32_t *)0xE0002FE8u) #define FPB_PERIPHID2_ADDR (0xE0002FE8u) #define FPB_PERIPHID2_RESET (0x0000000Bu) /* PERIPHID field */ @@ -9135,8 +9135,8 @@ #define FPB_PERIPHID2_PERIPHID_BIT (0) #define FPB_PERIPHID2_PERIPHID_BITS (32) -#define FPB_PERIPHID3 *((volatile int32u *)0xE0002FECu) -#define FPB_PERIPHID3_REG *((volatile int32u *)0xE0002FECu) +#define FPB_PERIPHID3 *((volatile uint32_t *)0xE0002FECu) +#define FPB_PERIPHID3_REG *((volatile uint32_t *)0xE0002FECu) #define FPB_PERIPHID3_ADDR (0xE0002FECu) #define FPB_PERIPHID3_RESET (0x00000000u) /* PERIPHID field */ @@ -9145,8 +9145,8 @@ #define FPB_PERIPHID3_PERIPHID_BIT (0) #define FPB_PERIPHID3_PERIPHID_BITS (32) -#define FPB_CELLID0 *((volatile int32u *)0xE0002FF0u) -#define FPB_CELLID0_REG *((volatile int32u *)0xE0002FF0u) +#define FPB_CELLID0 *((volatile uint32_t *)0xE0002FF0u) +#define FPB_CELLID0_REG *((volatile uint32_t *)0xE0002FF0u) #define FPB_CELLID0_ADDR (0xE0002FF0u) #define FPB_CELLID0_RESET (0x0000000Du) /* CELLID field */ @@ -9155,8 +9155,8 @@ #define FPB_CELLID0_CELLID_BIT (0) #define FPB_CELLID0_CELLID_BITS (32) -#define FPB_CELLID1 *((volatile int32u *)0xE0002FF4u) -#define FPB_CELLID1_REG *((volatile int32u *)0xE0002FF4u) +#define FPB_CELLID1 *((volatile uint32_t *)0xE0002FF4u) +#define FPB_CELLID1_REG *((volatile uint32_t *)0xE0002FF4u) #define FPB_CELLID1_ADDR (0xE0002FF4u) #define FPB_CELLID1_RESET (0x000000E0u) /* CELLID field */ @@ -9165,8 +9165,8 @@ #define FPB_CELLID1_CELLID_BIT (0) #define FPB_CELLID1_CELLID_BITS (32) -#define FPB_CELLID2 *((volatile int32u *)0xE0002FF8u) -#define FPB_CELLID2_REG *((volatile int32u *)0xE0002FF8u) +#define FPB_CELLID2 *((volatile uint32_t *)0xE0002FF8u) +#define FPB_CELLID2_REG *((volatile uint32_t *)0xE0002FF8u) #define FPB_CELLID2_ADDR (0xE0002FF8u) #define FPB_CELLID2_RESET (0x00000005u) /* CELLID field */ @@ -9175,8 +9175,8 @@ #define FPB_CELLID2_CELLID_BIT (0) #define FPB_CELLID2_CELLID_BITS (32) -#define FPB_CELLID3 *((volatile int32u *)0xE0002FFCu) -#define FPB_CELLID3_REG *((volatile int32u *)0xE0002FFCu) +#define FPB_CELLID3 *((volatile uint32_t *)0xE0002FFCu) +#define FPB_CELLID3_REG *((volatile uint32_t *)0xE0002FFCu) #define FPB_CELLID3_ADDR (0xE0002FFCu) #define FPB_CELLID3_RESET (0x000000B1u) /* CELLID field */ @@ -9190,13 +9190,13 @@ #define BLOCK_NVIC_END (0xE000EFFFu) #define BLOCK_NVIC_SIZE (BLOCK_NVIC_END - BLOCK_NVIC_BASE + 1) -#define NVIC_MCR *((volatile int32u *)0xE000E000u) -#define NVIC_MCR_REG *((volatile int32u *)0xE000E000u) +#define NVIC_MCR *((volatile uint32_t *)0xE000E000u) +#define NVIC_MCR_REG *((volatile uint32_t *)0xE000E000u) #define NVIC_MCR_ADDR (0xE000E000u) #define NVIC_MCR_RESET (0x00000000u) -#define NVIC_ICTR *((volatile int32u *)0xE000E004u) -#define NVIC_ICTR_REG *((volatile int32u *)0xE000E004u) +#define NVIC_ICTR *((volatile uint32_t *)0xE000E004u) +#define NVIC_ICTR_REG *((volatile uint32_t *)0xE000E004u) #define NVIC_ICTR_ADDR (0xE000E004u) #define NVIC_ICTR_RESET (0x00000000u) /* INTLINESNUM field */ @@ -9205,8 +9205,8 @@ #define NVIC_ICTR_INTLINESNUM_BIT (0) #define NVIC_ICTR_INTLINESNUM_BITS (5) -#define ST_CSR *((volatile int32u *)0xE000E010u) -#define ST_CSR_REG *((volatile int32u *)0xE000E010u) +#define ST_CSR *((volatile uint32_t *)0xE000E010u) +#define ST_CSR_REG *((volatile uint32_t *)0xE000E010u) #define ST_CSR_ADDR (0xE000E010u) #define ST_CSR_RESET (0x00000000u) /* COUNTFLAG field */ @@ -9230,8 +9230,8 @@ #define ST_CSR_ENABLE_BIT (0) #define ST_CSR_ENABLE_BITS (1) -#define ST_RVR *((volatile int32u *)0xE000E014u) -#define ST_RVR_REG *((volatile int32u *)0xE000E014u) +#define ST_RVR *((volatile uint32_t *)0xE000E014u) +#define ST_RVR_REG *((volatile uint32_t *)0xE000E014u) #define ST_RVR_ADDR (0xE000E014u) #define ST_RVR_RESET (0x00000000u) /* RELOAD field */ @@ -9240,8 +9240,8 @@ #define ST_RVR_RELOAD_BIT (0) #define ST_RVR_RELOAD_BITS (24) -#define ST_CVR *((volatile int32u *)0xE000E018u) -#define ST_CVR_REG *((volatile int32u *)0xE000E018u) +#define ST_CVR *((volatile uint32_t *)0xE000E018u) +#define ST_CVR_REG *((volatile uint32_t *)0xE000E018u) #define ST_CVR_ADDR (0xE000E018u) #define ST_CVR_RESET (0x00000000u) /* CURRENT field */ @@ -9250,8 +9250,8 @@ #define ST_CVR_CURRENT_BIT (0) #define ST_CVR_CURRENT_BITS (32) -#define ST_CALVR *((volatile int32u *)0xE000E01Cu) -#define ST_CALVR_REG *((volatile int32u *)0xE000E01Cu) +#define ST_CALVR *((volatile uint32_t *)0xE000E01Cu) +#define ST_CALVR_REG *((volatile uint32_t *)0xE000E01Cu) #define ST_CALVR_ADDR (0xE000E01Cu) #define ST_CALVR_RESET (0x00000000u) /* NOREF field */ @@ -9270,8 +9270,8 @@ #define ST_CALVR_TENMS_BIT (0) #define ST_CALVR_TENMS_BITS (24) -#define INT_CFGSET *((volatile int32u *)0xE000E100u) -#define INT_CFGSET_REG *((volatile int32u *)0xE000E100u) +#define INT_CFGSET *((volatile uint32_t *)0xE000E100u) +#define INT_CFGSET_REG *((volatile uint32_t *)0xE000E100u) #define INT_CFGSET_ADDR (0xE000E100u) #define INT_CFGSET_RESET (0x00000000u) /* INT_DEBUG field */ @@ -9360,8 +9360,8 @@ #define INT_TIM1_BIT (0) #define INT_TIM1_BITS (1) -#define INT_CFGCLR *((volatile int32u *)0xE000E180u) -#define INT_CFGCLR_REG *((volatile int32u *)0xE000E180u) +#define INT_CFGCLR *((volatile uint32_t *)0xE000E180u) +#define INT_CFGCLR_REG *((volatile uint32_t *)0xE000E180u) #define INT_CFGCLR_ADDR (0xE000E180u) #define INT_CFGCLR_RESET (0x00000000u) /* INT_DEBUG field */ @@ -9450,8 +9450,8 @@ #define INT_TIM1_BIT (0) #define INT_TIM1_BITS (1) -#define INT_PENDSET *((volatile int32u *)0xE000E200u) -#define INT_PENDSET_REG *((volatile int32u *)0xE000E200u) +#define INT_PENDSET *((volatile uint32_t *)0xE000E200u) +#define INT_PENDSET_REG *((volatile uint32_t *)0xE000E200u) #define INT_PENDSET_ADDR (0xE000E200u) #define INT_PENDSET_RESET (0x00000000u) /* INT_DEBUG field */ @@ -9540,8 +9540,8 @@ #define INT_TIM1_BIT (0) #define INT_TIM1_BITS (1) -#define INT_PENDCLR *((volatile int32u *)0xE000E280u) -#define INT_PENDCLR_REG *((volatile int32u *)0xE000E280u) +#define INT_PENDCLR *((volatile uint32_t *)0xE000E280u) +#define INT_PENDCLR_REG *((volatile uint32_t *)0xE000E280u) #define INT_PENDCLR_ADDR (0xE000E280u) #define INT_PENDCLR_RESET (0x00000000u) /* INT_DEBUG field */ @@ -9630,8 +9630,8 @@ #define INT_TIM1_BIT (0) #define INT_TIM1_BITS (1) -#define INT_ACTIVE *((volatile int32u *)0xE000E300u) -#define INT_ACTIVE_REG *((volatile int32u *)0xE000E300u) +#define INT_ACTIVE *((volatile uint32_t *)0xE000E300u) +#define INT_ACTIVE_REG *((volatile uint32_t *)0xE000E300u) #define INT_ACTIVE_ADDR (0xE000E300u) #define INT_ACTIVE_RESET (0x00000000u) /* INT_DEBUG field */ @@ -9720,8 +9720,8 @@ #define INT_TIM1_BIT (0) #define INT_TIM1_BITS (1) -#define NVIC_IPR_3to0 *((volatile int32u *)0xE000E400u) -#define NVIC_IPR_3to0_REG *((volatile int32u *)0xE000E400u) +#define NVIC_IPR_3to0 *((volatile uint32_t *)0xE000E400u) +#define NVIC_IPR_3to0_REG *((volatile uint32_t *)0xE000E400u) #define NVIC_IPR_3to0_ADDR (0xE000E400u) #define NVIC_IPR_3to0_RESET (0x00000000u) /* PRI_3 field */ @@ -9745,8 +9745,8 @@ #define NVIC_IPR_3to0_PRI_0_BIT (0) #define NVIC_IPR_3to0_PRI_0_BITS (8) -#define NVIC_IPR_7to4 *((volatile int32u *)0xE000E404u) -#define NVIC_IPR_7to4_REG *((volatile int32u *)0xE000E404u) +#define NVIC_IPR_7to4 *((volatile uint32_t *)0xE000E404u) +#define NVIC_IPR_7to4_REG *((volatile uint32_t *)0xE000E404u) #define NVIC_IPR_7to4_ADDR (0xE000E404u) #define NVIC_IPR_7to4_RESET (0x00000000u) /* PRI_7 field */ @@ -9770,8 +9770,8 @@ #define NVIC_IPR_7to4_PRI_4_BIT (0) #define NVIC_IPR_7to4_PRI_4_BITS (8) -#define NVIC_IPR_11to8 *((volatile int32u *)0xE000E408u) -#define NVIC_IPR_11to8_REG *((volatile int32u *)0xE000E408u) +#define NVIC_IPR_11to8 *((volatile uint32_t *)0xE000E408u) +#define NVIC_IPR_11to8_REG *((volatile uint32_t *)0xE000E408u) #define NVIC_IPR_11to8_ADDR (0xE000E408u) #define NVIC_IPR_11to8_RESET (0x00000000u) /* PRI_11 field */ @@ -9795,8 +9795,8 @@ #define NVIC_IPR_11to8_PRI_8_BIT (0) #define NVIC_IPR_11to8_PRI_8_BITS (8) -#define NVIC_IPR_15to12 *((volatile int32u *)0xE000E40Cu) -#define NVIC_IPR_15to12_REG *((volatile int32u *)0xE000E40Cu) +#define NVIC_IPR_15to12 *((volatile uint32_t *)0xE000E40Cu) +#define NVIC_IPR_15to12_REG *((volatile uint32_t *)0xE000E40Cu) #define NVIC_IPR_15to12_ADDR (0xE000E40Cu) #define NVIC_IPR_15to12_RESET (0x00000000u) /* PRI_15 field */ @@ -9820,8 +9820,8 @@ #define NVIC_IPR_15to12_PRI_12_BIT (0) #define NVIC_IPR_15to12_PRI_12_BITS (8) -#define NVIC_IPR_19to16 *((volatile int32u *)0xE000E410u) -#define NVIC_IPR_19to16_REG *((volatile int32u *)0xE000E410u) +#define NVIC_IPR_19to16 *((volatile uint32_t *)0xE000E410u) +#define NVIC_IPR_19to16_REG *((volatile uint32_t *)0xE000E410u) #define NVIC_IPR_19to16_ADDR (0xE000E410u) #define NVIC_IPR_19to16_RESET (0x00000000u) /* PRI_19 field */ @@ -9845,8 +9845,8 @@ #define NVIC_IPR_19to16_PRI_16_BIT (0) #define NVIC_IPR_19to16_PRI_16_BITS (8) -#define SCS_CPUID *((volatile int32u *)0xE000ED00u) -#define SCS_CPUID_REG *((volatile int32u *)0xE000ED00u) +#define SCS_CPUID *((volatile uint32_t *)0xE000ED00u) +#define SCS_CPUID_REG *((volatile uint32_t *)0xE000ED00u) #define SCS_CPUID_ADDR (0xE000ED00u) #define SCS_CPUID_RESET (0x411FC231u) /* IMPLEMENTER field */ @@ -9875,8 +9875,8 @@ #define SCS_CPUID_REVISION_BIT (0) #define SCS_CPUID_REVISION_BITS (4) -#define SCS_ICSR *((volatile int32u *)0xE000ED04u) -#define SCS_ICSR_REG *((volatile int32u *)0xE000ED04u) +#define SCS_ICSR *((volatile uint32_t *)0xE000ED04u) +#define SCS_ICSR_REG *((volatile uint32_t *)0xE000ED04u) #define SCS_ICSR_ADDR (0xE000ED04u) #define SCS_ICSR_RESET (0x00000000u) /* NMIPENDSET field */ @@ -9930,8 +9930,8 @@ #define SCS_ICSR_VECACTIVE_BIT (0) #define SCS_ICSR_VECACTIVE_BITS (9) -#define SCS_VTOR *((volatile int32u *)0xE000ED08u) -#define SCS_VTOR_REG *((volatile int32u *)0xE000ED08u) +#define SCS_VTOR *((volatile uint32_t *)0xE000ED08u) +#define SCS_VTOR_REG *((volatile uint32_t *)0xE000ED08u) #define SCS_VTOR_ADDR (0xE000ED08u) #define SCS_VTOR_RESET (0x00000000u) /* TBLBASE field */ @@ -9945,8 +9945,8 @@ #define SCS_VTOR_TBLOFF_BIT (8) #define SCS_VTOR_TBLOFF_BITS (21) -#define SCS_AIRCR *((volatile int32u *)0xE000ED0Cu) -#define SCS_AIRCR_REG *((volatile int32u *)0xE000ED0Cu) +#define SCS_AIRCR *((volatile uint32_t *)0xE000ED0Cu) +#define SCS_AIRCR_REG *((volatile uint32_t *)0xE000ED0Cu) #define SCS_AIRCR_ADDR (0xE000ED0Cu) #define SCS_AIRCR_RESET (0x00000000u) /* VECTKEYSTAT field */ @@ -9985,8 +9985,8 @@ #define SCS_AIRCR_VECTRESET_BIT (0) #define SCS_AIRCR_VECTRESET_BITS (1) -#define SCS_SCR *((volatile int32u *)0xE000ED10u) -#define SCS_SCR_REG *((volatile int32u *)0xE000ED10u) +#define SCS_SCR *((volatile uint32_t *)0xE000ED10u) +#define SCS_SCR_REG *((volatile uint32_t *)0xE000ED10u) #define SCS_SCR_ADDR (0xE000ED10u) #define SCS_SCR_RESET (0x00000000u) /* SEVONPEND field */ @@ -10005,8 +10005,8 @@ #define SCS_SCR_SLEEPONEXIT_BIT (1) #define SCS_SCR_SLEEPONEXIT_BITS (1) -#define SCS_CCR *((volatile int32u *)0xE000ED14u) -#define SCS_CCR_REG *((volatile int32u *)0xE000ED14u) +#define SCS_CCR *((volatile uint32_t *)0xE000ED14u) +#define SCS_CCR_REG *((volatile uint32_t *)0xE000ED14u) #define SCS_CCR_ADDR (0xE000ED14u) #define SCS_CCR_RESET (0x00000000u) /* STKALIGN field */ @@ -10040,8 +10040,8 @@ #define SCS_CCR_NONBASETHRDENA_BIT (0) #define SCS_CCR_NONBASETHRDENA_BITS (1) -#define SCS_SHPR_7to4 *((volatile int32u *)0xE000ED18u) -#define SCS_SHPR_7to4_REG *((volatile int32u *)0xE000ED18u) +#define SCS_SHPR_7to4 *((volatile uint32_t *)0xE000ED18u) +#define SCS_SHPR_7to4_REG *((volatile uint32_t *)0xE000ED18u) #define SCS_SHPR_7to4_ADDR (0xE000ED18u) #define SCS_SHPR_7to4_RESET (0x00000000u) /* PRI_7 field */ @@ -10065,8 +10065,8 @@ #define SCS_SHPR_7to4_PRI_4_BIT (0) #define SCS_SHPR_7to4_PRI_4_BITS (8) -#define SCS_SHPR_11to8 *((volatile int32u *)0xE000ED1Cu) -#define SCS_SHPR_11to8_REG *((volatile int32u *)0xE000ED1Cu) +#define SCS_SHPR_11to8 *((volatile uint32_t *)0xE000ED1Cu) +#define SCS_SHPR_11to8_REG *((volatile uint32_t *)0xE000ED1Cu) #define SCS_SHPR_11to8_ADDR (0xE000ED1Cu) #define SCS_SHPR_11to8_RESET (0x00000000u) /* PRI_11 field */ @@ -10090,8 +10090,8 @@ #define SCS_SHPR_11to8_PRI_8_BIT (0) #define SCS_SHPR_11to8_PRI_8_BITS (8) -#define SCS_SHPR_15to12 *((volatile int32u *)0xE000ED20u) -#define SCS_SHPR_15to12_REG *((volatile int32u *)0xE000ED20u) +#define SCS_SHPR_15to12 *((volatile uint32_t *)0xE000ED20u) +#define SCS_SHPR_15to12_REG *((volatile uint32_t *)0xE000ED20u) #define SCS_SHPR_15to12_ADDR (0xE000ED20u) #define SCS_SHPR_15to12_RESET (0x00000000u) /* PRI_15 field */ @@ -10115,8 +10115,8 @@ #define SCS_SHPR_15to12_PRI_12_BIT (0) #define SCS_SHPR_15to12_PRI_12_BITS (8) -#define SCS_SHCSR *((volatile int32u *)0xE000ED24u) -#define SCS_SHCSR_REG *((volatile int32u *)0xE000ED24u) +#define SCS_SHCSR *((volatile uint32_t *)0xE000ED24u) +#define SCS_SHCSR_REG *((volatile uint32_t *)0xE000ED24u) #define SCS_SHCSR_ADDR (0xE000ED24u) #define SCS_SHCSR_RESET (0x00000000u) /* USGFAULTENA field */ @@ -10190,8 +10190,8 @@ #define SCS_SHCSR_MEMFAULTACT_BIT (0) #define SCS_SHCSR_MEMFAULTACT_BITS (1) -#define SCS_CFSR *((volatile int32u *)0xE000ED28u) -#define SCS_CFSR_REG *((volatile int32u *)0xE000ED28u) +#define SCS_CFSR *((volatile uint32_t *)0xE000ED28u) +#define SCS_CFSR_REG *((volatile uint32_t *)0xE000ED28u) #define SCS_CFSR_ADDR (0xE000ED28u) #define SCS_CFSR_RESET (0x00000000u) /* DIVBYZERO field */ @@ -10280,8 +10280,8 @@ #define SCS_CFSR_IACCVIOL_BIT (0) #define SCS_CFSR_IACCVIOL_BITS (1) -#define SCS_HFSR *((volatile int32u *)0xE000ED2Cu) -#define SCS_HFSR_REG *((volatile int32u *)0xE000ED2Cu) +#define SCS_HFSR *((volatile uint32_t *)0xE000ED2Cu) +#define SCS_HFSR_REG *((volatile uint32_t *)0xE000ED2Cu) #define SCS_HFSR_ADDR (0xE000ED2Cu) #define SCS_HFSR_RESET (0x00000000u) /* DEBUGEVT field */ @@ -10300,8 +10300,8 @@ #define SCS_HFSR_VECTTBL_BIT (1) #define SCS_HFSR_VECTTBL_BITS (1) -#define SCS_DFSR *((volatile int32u *)0xE000ED30u) -#define SCS_DFSR_REG *((volatile int32u *)0xE000ED30u) +#define SCS_DFSR *((volatile uint32_t *)0xE000ED30u) +#define SCS_DFSR_REG *((volatile uint32_t *)0xE000ED30u) #define SCS_DFSR_ADDR (0xE000ED30u) #define SCS_DFSR_RESET (0x00000000u) /* EXTERNAL field */ @@ -10330,8 +10330,8 @@ #define SCS_DFSR_HALTED_BIT (0) #define SCS_DFSR_HALTED_BITS (1) -#define SCS_MMAR *((volatile int32u *)0xE000ED34u) -#define SCS_MMAR_REG *((volatile int32u *)0xE000ED34u) +#define SCS_MMAR *((volatile uint32_t *)0xE000ED34u) +#define SCS_MMAR_REG *((volatile uint32_t *)0xE000ED34u) #define SCS_MMAR_ADDR (0xE000ED34u) #define SCS_MMAR_RESET (0x00000000u) /* ADDRESS field */ @@ -10340,8 +10340,8 @@ #define SCS_MMAR_ADDRESS_BIT (0) #define SCS_MMAR_ADDRESS_BITS (32) -#define SCS_BFAR *((volatile int32u *)0xE000ED38u) -#define SCS_BFAR_REG *((volatile int32u *)0xE000ED38u) +#define SCS_BFAR *((volatile uint32_t *)0xE000ED38u) +#define SCS_BFAR_REG *((volatile uint32_t *)0xE000ED38u) #define SCS_BFAR_ADDR (0xE000ED38u) #define SCS_BFAR_RESET (0x00000000u) /* ADDRESS field */ @@ -10350,8 +10350,8 @@ #define SCS_BFAR_ADDRESS_BIT (0) #define SCS_BFAR_ADDRESS_BITS (32) -#define SCS_AFSR *((volatile int32u *)0xE000ED3Cu) -#define SCS_AFSR_REG *((volatile int32u *)0xE000ED3Cu) +#define SCS_AFSR *((volatile uint32_t *)0xE000ED3Cu) +#define SCS_AFSR_REG *((volatile uint32_t *)0xE000ED3Cu) #define SCS_AFSR_ADDR (0xE000ED3Cu) #define SCS_AFSR_RESET (0x00000000u) /* WRONGSIZE field */ @@ -10375,8 +10375,8 @@ #define SCS_AFSR_MISSED_BIT (0) #define SCS_AFSR_MISSED_BITS (1) -#define SCS_PFR0 *((volatile int32u *)0xE000ED40u) -#define SCS_PFR0_REG *((volatile int32u *)0xE000ED40u) +#define SCS_PFR0 *((volatile uint32_t *)0xE000ED40u) +#define SCS_PFR0_REG *((volatile uint32_t *)0xE000ED40u) #define SCS_PFR0_ADDR (0xE000ED40u) #define SCS_PFR0_RESET (0x00000030u) /* FEATURE field */ @@ -10385,8 +10385,8 @@ #define SCS_PFR0_FEATURE_BIT (0) #define SCS_PFR0_FEATURE_BITS (32) -#define SCS_PFR1 *((volatile int32u *)0xE000ED44u) -#define SCS_PFR1_REG *((volatile int32u *)0xE000ED44u) +#define SCS_PFR1 *((volatile uint32_t *)0xE000ED44u) +#define SCS_PFR1_REG *((volatile uint32_t *)0xE000ED44u) #define SCS_PFR1_ADDR (0xE000ED44u) #define SCS_PFR1_RESET (0x00000200u) /* FEATURE field */ @@ -10395,8 +10395,8 @@ #define SCS_PFR1_FEATURE_BIT (0) #define SCS_PFR1_FEATURE_BITS (32) -#define SCS_DFR0 *((volatile int32u *)0xE000ED48u) -#define SCS_DFR0_REG *((volatile int32u *)0xE000ED48u) +#define SCS_DFR0 *((volatile uint32_t *)0xE000ED48u) +#define SCS_DFR0_REG *((volatile uint32_t *)0xE000ED48u) #define SCS_DFR0_ADDR (0xE000ED48u) #define SCS_DFR0_RESET (0x00100000u) /* FEATURE field */ @@ -10405,8 +10405,8 @@ #define SCS_DFR0_FEATURE_BIT (0) #define SCS_DFR0_FEATURE_BITS (32) -#define SCS_AFR0 *((volatile int32u *)0xE000ED4Cu) -#define SCS_AFR0_REG *((volatile int32u *)0xE000ED4Cu) +#define SCS_AFR0 *((volatile uint32_t *)0xE000ED4Cu) +#define SCS_AFR0_REG *((volatile uint32_t *)0xE000ED4Cu) #define SCS_AFR0_ADDR (0xE000ED4Cu) #define SCS_AFR0_RESET (0x00000000u) /* FEATURE field */ @@ -10415,8 +10415,8 @@ #define SCS_AFR0_FEATURE_BIT (0) #define SCS_AFR0_FEATURE_BITS (32) -#define SCS_MMFR0 *((volatile int32u *)0xE000ED50u) -#define SCS_MMFR0_REG *((volatile int32u *)0xE000ED50u) +#define SCS_MMFR0 *((volatile uint32_t *)0xE000ED50u) +#define SCS_MMFR0_REG *((volatile uint32_t *)0xE000ED50u) #define SCS_MMFR0_ADDR (0xE000ED50u) #define SCS_MMFR0_RESET (0x00000030u) /* FEATURE field */ @@ -10425,8 +10425,8 @@ #define SCS_MMFR0_FEATURE_BIT (0) #define SCS_MMFR0_FEATURE_BITS (32) -#define SCS_MMFR1 *((volatile int32u *)0xE000ED54u) -#define SCS_MMFR1_REG *((volatile int32u *)0xE000ED54u) +#define SCS_MMFR1 *((volatile uint32_t *)0xE000ED54u) +#define SCS_MMFR1_REG *((volatile uint32_t *)0xE000ED54u) #define SCS_MMFR1_ADDR (0xE000ED54u) #define SCS_MMFR1_RESET (0x00000000u) /* FEATURE field */ @@ -10435,8 +10435,8 @@ #define SCS_MMFR1_FEATURE_BIT (0) #define SCS_MMFR1_FEATURE_BITS (32) -#define SCS_MMFR2 *((volatile int32u *)0xE000ED58u) -#define SCS_MMFR2_REG *((volatile int32u *)0xE000ED58u) +#define SCS_MMFR2 *((volatile uint32_t *)0xE000ED58u) +#define SCS_MMFR2_REG *((volatile uint32_t *)0xE000ED58u) #define SCS_MMFR2_ADDR (0xE000ED58u) #define SCS_MMFR2_RESET (0x00000000u) /* FEATURE field */ @@ -10445,8 +10445,8 @@ #define SCS_MMFR2_FEATURE_BIT (0) #define SCS_MMFR2_FEATURE_BITS (32) -#define SCS_MMFR3 *((volatile int32u *)0xE000ED5Cu) -#define SCS_MMFR3_REG *((volatile int32u *)0xE000ED5Cu) +#define SCS_MMFR3 *((volatile uint32_t *)0xE000ED5Cu) +#define SCS_MMFR3_REG *((volatile uint32_t *)0xE000ED5Cu) #define SCS_MMFR3_ADDR (0xE000ED5Cu) #define SCS_MMFR3_RESET (0x00000000u) /* FEATURE field */ @@ -10455,8 +10455,8 @@ #define SCS_MMFR3_FEATURE_BIT (0) #define SCS_MMFR3_FEATURE_BITS (32) -#define SCS_ISAFR0 *((volatile int32u *)0xE000ED60u) -#define SCS_ISAFR0_REG *((volatile int32u *)0xE000ED60u) +#define SCS_ISAFR0 *((volatile uint32_t *)0xE000ED60u) +#define SCS_ISAFR0_REG *((volatile uint32_t *)0xE000ED60u) #define SCS_ISAFR0_ADDR (0xE000ED60u) #define SCS_ISAFR0_RESET (0x01141110u) /* FEATURE field */ @@ -10465,8 +10465,8 @@ #define SCS_ISAFR0_FEATURE_BIT (0) #define SCS_ISAFR0_FEATURE_BITS (32) -#define SCS_ISAFR1 *((volatile int32u *)0xE000ED64u) -#define SCS_ISAFR1_REG *((volatile int32u *)0xE000ED64u) +#define SCS_ISAFR1 *((volatile uint32_t *)0xE000ED64u) +#define SCS_ISAFR1_REG *((volatile uint32_t *)0xE000ED64u) #define SCS_ISAFR1_ADDR (0xE000ED64u) #define SCS_ISAFR1_RESET (0x02111000u) /* FEATURE field */ @@ -10475,8 +10475,8 @@ #define SCS_ISAFR1_FEATURE_BIT (0) #define SCS_ISAFR1_FEATURE_BITS (32) -#define SCS_ISAFR2 *((volatile int32u *)0xE000ED68u) -#define SCS_ISAFR2_REG *((volatile int32u *)0xE000ED68u) +#define SCS_ISAFR2 *((volatile uint32_t *)0xE000ED68u) +#define SCS_ISAFR2_REG *((volatile uint32_t *)0xE000ED68u) #define SCS_ISAFR2_ADDR (0xE000ED68u) #define SCS_ISAFR2_RESET (0x21112231u) /* FEATURE field */ @@ -10485,8 +10485,8 @@ #define SCS_ISAFR2_FEATURE_BIT (0) #define SCS_ISAFR2_FEATURE_BITS (32) -#define SCS_ISAFR3 *((volatile int32u *)0xE000ED6Cu) -#define SCS_ISAFR3_REG *((volatile int32u *)0xE000ED6Cu) +#define SCS_ISAFR3 *((volatile uint32_t *)0xE000ED6Cu) +#define SCS_ISAFR3_REG *((volatile uint32_t *)0xE000ED6Cu) #define SCS_ISAFR3_ADDR (0xE000ED6Cu) #define SCS_ISAFR3_RESET (0x11111110u) /* FEATURE field */ @@ -10495,8 +10495,8 @@ #define SCS_ISAFR3_FEATURE_BIT (0) #define SCS_ISAFR3_FEATURE_BITS (32) -#define SCS_ISAFR4 *((volatile int32u *)0xE000ED70u) -#define SCS_ISAFR4_REG *((volatile int32u *)0xE000ED70u) +#define SCS_ISAFR4 *((volatile uint32_t *)0xE000ED70u) +#define SCS_ISAFR4_REG *((volatile uint32_t *)0xE000ED70u) #define SCS_ISAFR4_ADDR (0xE000ED70u) #define SCS_ISAFR4_RESET (0x01310102u) /* FEATURE field */ @@ -10505,8 +10505,8 @@ #define SCS_ISAFR4_FEATURE_BIT (0) #define SCS_ISAFR4_FEATURE_BITS (32) -#define MPU_TYPE *((volatile int32u *)0xE000ED90u) -#define MPU_TYPE_REG *((volatile int32u *)0xE000ED90u) +#define MPU_TYPE *((volatile uint32_t *)0xE000ED90u) +#define MPU_TYPE_REG *((volatile uint32_t *)0xE000ED90u) #define MPU_TYPE_ADDR (0xE000ED90u) #define MPU_TYPE_RESET (0x00000800u) /* IREGION field */ @@ -10520,8 +10520,8 @@ #define MPU_TYPE_DREGION_BIT (8) #define MPU_TYPE_DREGION_BITS (8) -#define MPU_CTRL *((volatile int32u *)0xE000ED94u) -#define MPU_CTRL_REG *((volatile int32u *)0xE000ED94u) +#define MPU_CTRL *((volatile uint32_t *)0xE000ED94u) +#define MPU_CTRL_REG *((volatile uint32_t *)0xE000ED94u) #define MPU_CTRL_ADDR (0xE000ED94u) #define MPU_CTRL_RESET (0x00000000u) /* PRIVDEFENA field */ @@ -10540,8 +10540,8 @@ #define MPU_CTRL_ENABLE_BIT (0) #define MPU_CTRL_ENABLE_BITS (1) -#define MPU_REGION *((volatile int32u *)0xE000ED98u) -#define MPU_REGION_REG *((volatile int32u *)0xE000ED98u) +#define MPU_REGION *((volatile uint32_t *)0xE000ED98u) +#define MPU_REGION_REG *((volatile uint32_t *)0xE000ED98u) #define MPU_REGION_ADDR (0xE000ED98u) #define MPU_REGION_RESET (0x00000000u) /* REGION field */ @@ -10550,8 +10550,8 @@ #define MPU_REGION_REGION_BIT (0) #define MPU_REGION_REGION_BITS (8) -#define MPU_BASE *((volatile int32u *)0xE000ED9Cu) -#define MPU_BASE_REG *((volatile int32u *)0xE000ED9Cu) +#define MPU_BASE *((volatile uint32_t *)0xE000ED9Cu) +#define MPU_BASE_REG *((volatile uint32_t *)0xE000ED9Cu) #define MPU_BASE_ADDR (0xE000ED9Cu) #define MPU_BASE_RESET (0x00000000u) /* ADDRESS field */ @@ -10570,8 +10570,8 @@ #define MPU_BASE_REGION_BIT (0) #define MPU_BASE_REGION_BITS (4) -#define MPU_ATTR *((volatile int32u *)0xE000EDA0u) -#define MPU_ATTR_REG *((volatile int32u *)0xE000EDA0u) +#define MPU_ATTR *((volatile uint32_t *)0xE000EDA0u) +#define MPU_ATTR_REG *((volatile uint32_t *)0xE000EDA0u) #define MPU_ATTR_ADDR (0xE000EDA0u) #define MPU_ATTR_RESET (0x00000000u) /* XN field */ @@ -10620,8 +10620,8 @@ #define MPU_ATTR_ENABLE_BIT (0) #define MPU_ATTR_ENABLE_BITS (1) -#define MPU_BASE1 *((volatile int32u *)0xE000EDA4u) -#define MPU_BASE1_REG *((volatile int32u *)0xE000EDA4u) +#define MPU_BASE1 *((volatile uint32_t *)0xE000EDA4u) +#define MPU_BASE1_REG *((volatile uint32_t *)0xE000EDA4u) #define MPU_BASE1_ADDR (0xE000EDA4u) #define MPU_BASE1_RESET (0x00000000u) /* ADDRESS field */ @@ -10640,8 +10640,8 @@ #define MPU_BASE1_REGION_BIT (0) #define MPU_BASE1_REGION_BITS (4) -#define MPU_ATTR1 *((volatile int32u *)0xE000EDA8u) -#define MPU_ATTR1_REG *((volatile int32u *)0xE000EDA8u) +#define MPU_ATTR1 *((volatile uint32_t *)0xE000EDA8u) +#define MPU_ATTR1_REG *((volatile uint32_t *)0xE000EDA8u) #define MPU_ATTR1_ADDR (0xE000EDA8u) #define MPU_ATTR1_RESET (0x00000000u) /* XN field */ @@ -10690,8 +10690,8 @@ #define MPU_ATTR1_ENABLE_BIT (0) #define MPU_ATTR1_ENABLE_BITS (1) -#define MPU_BASE2 *((volatile int32u *)0xE000EDACu) -#define MPU_BASE2_REG *((volatile int32u *)0xE000EDACu) +#define MPU_BASE2 *((volatile uint32_t *)0xE000EDACu) +#define MPU_BASE2_REG *((volatile uint32_t *)0xE000EDACu) #define MPU_BASE2_ADDR (0xE000EDACu) #define MPU_BASE2_RESET (0x00000000u) /* ADDRESS field */ @@ -10710,8 +10710,8 @@ #define MPU_BASE2_REGION_BIT (0) #define MPU_BASE2_REGION_BITS (4) -#define MPU_ATTR2 *((volatile int32u *)0xE000EDB0u) -#define MPU_ATTR2_REG *((volatile int32u *)0xE000EDB0u) +#define MPU_ATTR2 *((volatile uint32_t *)0xE000EDB0u) +#define MPU_ATTR2_REG *((volatile uint32_t *)0xE000EDB0u) #define MPU_ATTR2_ADDR (0xE000EDB0u) #define MPU_ATTR2_RESET (0x00000000u) /* XN field */ @@ -10760,8 +10760,8 @@ #define MPU_ATTR2_ENABLE_BIT (0) #define MPU_ATTR2_ENABLE_BITS (2) -#define MPU_BASE3 *((volatile int32u *)0xE000EDB4u) -#define MPU_BASE3_REG *((volatile int32u *)0xE000EDB4u) +#define MPU_BASE3 *((volatile uint32_t *)0xE000EDB4u) +#define MPU_BASE3_REG *((volatile uint32_t *)0xE000EDB4u) #define MPU_BASE3_ADDR (0xE000EDB4u) #define MPU_BASE3_RESET (0x00000000u) /* ADDRESS field */ @@ -10780,8 +10780,8 @@ #define MPU_BASE3_REGION_BIT (0) #define MPU_BASE3_REGION_BITS (4) -#define MPU_ATTR3 *((volatile int32u *)0xE000EDBCu) -#define MPU_ATTR3_REG *((volatile int32u *)0xE000EDBCu) +#define MPU_ATTR3 *((volatile uint32_t *)0xE000EDBCu) +#define MPU_ATTR3_REG *((volatile uint32_t *)0xE000EDBCu) #define MPU_ATTR3_ADDR (0xE000EDBCu) #define MPU_ATTR3_RESET (0x00000000u) /* XN field */ @@ -10830,8 +10830,8 @@ #define MPU_ATTR3_ENABLE_BIT (0) #define MPU_ATTR3_ENABLE_BITS (2) -#define DEBUG_HCSR *((volatile int32u *)0xE000EDF0u) -#define DEBUG_HCSR_REG *((volatile int32u *)0xE000EDF0u) +#define DEBUG_HCSR *((volatile uint32_t *)0xE000EDF0u) +#define DEBUG_HCSR_REG *((volatile uint32_t *)0xE000EDF0u) #define DEBUG_HCSR_ADDR (0xE000EDF0u) #define DEBUG_HCSR_RESET (0x00000000u) /* S_RESET_ST field */ @@ -10895,8 +10895,8 @@ #define DEBUG_HCSR_C_DEBUGEN_BIT (0) #define DEBUG_HCSR_C_DEBUGEN_BITS (1) -#define DEBUG_CRSR *((volatile int32u *)0xE000EDF4u) -#define DEBUG_CRSR_REG *((volatile int32u *)0xE000EDF4u) +#define DEBUG_CRSR *((volatile uint32_t *)0xE000EDF4u) +#define DEBUG_CRSR_REG *((volatile uint32_t *)0xE000EDF4u) #define DEBUG_CRSR_ADDR (0xE000EDF4u) #define DEBUG_CRSR_RESET (0x00000000u) /* REGWnR field */ @@ -10910,8 +10910,8 @@ #define DEBUG_CRSR_REGSEL_BIT (0) #define DEBUG_CRSR_REGSEL_BITS (5) -#define DEBUG_CRDR *((volatile int32u *)0xE000EDF8u) -#define DEBUG_CRDR_REG *((volatile int32u *)0xE000EDF8u) +#define DEBUG_CRDR *((volatile uint32_t *)0xE000EDF8u) +#define DEBUG_CRDR_REG *((volatile uint32_t *)0xE000EDF8u) #define DEBUG_CRDR_ADDR (0xE000EDF8u) #define DEBUG_CRDR_RESET (0x00000000u) /* DBGTMP field */ @@ -10920,8 +10920,8 @@ #define DEBUG_CRDR_DBGTMP_BIT (0) #define DEBUG_CRDR_DBGTMP_BITS (32) -#define DEBUG_EMCR *((volatile int32u *)0xE000EDFCu) -#define DEBUG_EMCR_REG *((volatile int32u *)0xE000EDFCu) +#define DEBUG_EMCR *((volatile uint32_t *)0xE000EDFCu) +#define DEBUG_EMCR_REG *((volatile uint32_t *)0xE000EDFCu) #define DEBUG_EMCR_ADDR (0xE000EDFCu) #define DEBUG_EMCR_RESET (0x00000000u) /* TRCENA field */ @@ -10990,8 +10990,8 @@ #define DEBUG_EMCR_VC_CORERESET_BIT (0) #define DEBUG_EMCR_VC_CORERESET_BITS (1) -#define NVIC_STIR *((volatile int32u *)0xE000EF00u) -#define NVIC_STIR_REG *((volatile int32u *)0xE000EF00u) +#define NVIC_STIR *((volatile uint32_t *)0xE000EF00u) +#define NVIC_STIR_REG *((volatile uint32_t *)0xE000EF00u) #define NVIC_STIR_ADDR (0xE000EF00u) #define NVIC_STIR_RESET (0x00000000u) /* INTID field */ @@ -11000,8 +11000,8 @@ #define NVIC_STIR_INTID_BIT (0) #define NVIC_STIR_INTID_BITS (10) -#define NVIC_PERIPHID4 *((volatile int32u *)0xE000EFD0u) -#define NVIC_PERIPHID4_REG *((volatile int32u *)0xE000EFD0u) +#define NVIC_PERIPHID4 *((volatile uint32_t *)0xE000EFD0u) +#define NVIC_PERIPHID4_REG *((volatile uint32_t *)0xE000EFD0u) #define NVIC_PERIPHID4_ADDR (0xE000EFD0u) #define NVIC_PERIPHID4_RESET (0x00000004u) /* PERIPHID field */ @@ -11010,8 +11010,8 @@ #define NVIC_PERIPHID4_PERIPHID_BIT (0) #define NVIC_PERIPHID4_PERIPHID_BITS (32) -#define NVIC_PERIPHID5 *((volatile int32u *)0xE000EFD4u) -#define NVIC_PERIPHID5_REG *((volatile int32u *)0xE000EFD4u) +#define NVIC_PERIPHID5 *((volatile uint32_t *)0xE000EFD4u) +#define NVIC_PERIPHID5_REG *((volatile uint32_t *)0xE000EFD4u) #define NVIC_PERIPHID5_ADDR (0xE000EFD4u) #define NVIC_PERIPHID5_RESET (0x00000000u) /* PERIPHID field */ @@ -11020,8 +11020,8 @@ #define NVIC_PERIPHID5_PERIPHID_BIT (0) #define NVIC_PERIPHID5_PERIPHID_BITS (32) -#define NVIC_PERIPHID6 *((volatile int32u *)0xE000EFD8u) -#define NVIC_PERIPHID6_REG *((volatile int32u *)0xE000EFD8u) +#define NVIC_PERIPHID6 *((volatile uint32_t *)0xE000EFD8u) +#define NVIC_PERIPHID6_REG *((volatile uint32_t *)0xE000EFD8u) #define NVIC_PERIPHID6_ADDR (0xE000EFD8u) #define NVIC_PERIPHID6_RESET (0x00000000u) /* PERIPHID field */ @@ -11030,8 +11030,8 @@ #define NVIC_PERIPHID6_PERIPHID_BIT (0) #define NVIC_PERIPHID6_PERIPHID_BITS (32) -#define NVIC_PERIPHID7 *((volatile int32u *)0xE000EFDCu) -#define NVIC_PERIPHID7_REG *((volatile int32u *)0xE000EFDCu) +#define NVIC_PERIPHID7 *((volatile uint32_t *)0xE000EFDCu) +#define NVIC_PERIPHID7_REG *((volatile uint32_t *)0xE000EFDCu) #define NVIC_PERIPHID7_ADDR (0xE000EFDCu) #define NVIC_PERIPHID7_RESET (0x00000000u) /* PERIPHID field */ @@ -11040,8 +11040,8 @@ #define NVIC_PERIPHID7_PERIPHID_BIT (0) #define NVIC_PERIPHID7_PERIPHID_BITS (32) -#define NVIC_PERIPHID0 *((volatile int32u *)0xE000EFE0u) -#define NVIC_PERIPHID0_REG *((volatile int32u *)0xE000EFE0u) +#define NVIC_PERIPHID0 *((volatile uint32_t *)0xE000EFE0u) +#define NVIC_PERIPHID0_REG *((volatile uint32_t *)0xE000EFE0u) #define NVIC_PERIPHID0_ADDR (0xE000EFE0u) #define NVIC_PERIPHID0_RESET (0x00000000u) /* PERIPHID field */ @@ -11050,8 +11050,8 @@ #define NVIC_PERIPHID0_PERIPHID_BIT (0) #define NVIC_PERIPHID0_PERIPHID_BITS (32) -#define NVIC_PERIPHID1 *((volatile int32u *)0xE000EFE4u) -#define NVIC_PERIPHID1_REG *((volatile int32u *)0xE000EFE4u) +#define NVIC_PERIPHID1 *((volatile uint32_t *)0xE000EFE4u) +#define NVIC_PERIPHID1_REG *((volatile uint32_t *)0xE000EFE4u) #define NVIC_PERIPHID1_ADDR (0xE000EFE4u) #define NVIC_PERIPHID1_RESET (0x000000B0u) /* PERIPHID field */ @@ -11060,8 +11060,8 @@ #define NVIC_PERIPHID1_PERIPHID_BIT (0) #define NVIC_PERIPHID1_PERIPHID_BITS (32) -#define NVIC_PERIPHID2 *((volatile int32u *)0xE000EFE8u) -#define NVIC_PERIPHID2_REG *((volatile int32u *)0xE000EFE8u) +#define NVIC_PERIPHID2 *((volatile uint32_t *)0xE000EFE8u) +#define NVIC_PERIPHID2_REG *((volatile uint32_t *)0xE000EFE8u) #define NVIC_PERIPHID2_ADDR (0xE000EFE8u) #define NVIC_PERIPHID2_RESET (0x0000001Bu) /* PERIPHID field */ @@ -11070,8 +11070,8 @@ #define NVIC_PERIPHID2_PERIPHID_BIT (0) #define NVIC_PERIPHID2_PERIPHID_BITS (32) -#define NVIC_PERIPHID3 *((volatile int32u *)0xE000EFECu) -#define NVIC_PERIPHID3_REG *((volatile int32u *)0xE000EFECu) +#define NVIC_PERIPHID3 *((volatile uint32_t *)0xE000EFECu) +#define NVIC_PERIPHID3_REG *((volatile uint32_t *)0xE000EFECu) #define NVIC_PERIPHID3_ADDR (0xE000EFECu) #define NVIC_PERIPHID3_RESET (0x00000000u) /* PERIPHID field */ @@ -11080,8 +11080,8 @@ #define NVIC_PERIPHID3_PERIPHID_BIT (0) #define NVIC_PERIPHID3_PERIPHID_BITS (32) -#define NVIC_PCELLID0 *((volatile int32u *)0xE000EFF0u) -#define NVIC_PCELLID0_REG *((volatile int32u *)0xE000EFF0u) +#define NVIC_PCELLID0 *((volatile uint32_t *)0xE000EFF0u) +#define NVIC_PCELLID0_REG *((volatile uint32_t *)0xE000EFF0u) #define NVIC_PCELLID0_ADDR (0xE000EFF0u) #define NVIC_PCELLID0_RESET (0x0000000Du) /* PCELLID field */ @@ -11090,8 +11090,8 @@ #define NVIC_PCELLID0_PCELLID_BIT (0) #define NVIC_PCELLID0_PCELLID_BITS (32) -#define NVIC_PCELLID1 *((volatile int32u *)0xE000EFF4u) -#define NVIC_PCELLID1_REG *((volatile int32u *)0xE000EFF4u) +#define NVIC_PCELLID1 *((volatile uint32_t *)0xE000EFF4u) +#define NVIC_PCELLID1_REG *((volatile uint32_t *)0xE000EFF4u) #define NVIC_PCELLID1_ADDR (0xE000EFF4u) #define NVIC_PCELLID1_RESET (0x000000E0u) /* PCELLID field */ @@ -11100,8 +11100,8 @@ #define NVIC_PCELLID1_PCELLID_BIT (0) #define NVIC_PCELLID1_PCELLID_BITS (32) -#define NVIC_PCELLID2 *((volatile int32u *)0xE000EFF8u) -#define NVIC_PCELLID2_REG *((volatile int32u *)0xE000EFF8u) +#define NVIC_PCELLID2 *((volatile uint32_t *)0xE000EFF8u) +#define NVIC_PCELLID2_REG *((volatile uint32_t *)0xE000EFF8u) #define NVIC_PCELLID2_ADDR (0xE000EFF8u) #define NVIC_PCELLID2_RESET (0x00000005u) /* PCELLID field */ @@ -11110,8 +11110,8 @@ #define NVIC_PCELLID2_PCELLID_BIT (0) #define NVIC_PCELLID2_PCELLID_BITS (32) -#define NVIC_PCELLID3 *((volatile int32u *)0xE000EFFCu) -#define NVIC_PCELLID3_REG *((volatile int32u *)0xE000EFFCu) +#define NVIC_PCELLID3 *((volatile uint32_t *)0xE000EFFCu) +#define NVIC_PCELLID3_REG *((volatile uint32_t *)0xE000EFFCu) #define NVIC_PCELLID3_ADDR (0xE000EFFCu) #define NVIC_PCELLID3_RESET (0x000000B1u) /* PCELLID field */ @@ -11125,8 +11125,8 @@ #define DATA_TPIU_END (0xE0040EF8u) #define DATA_TPIU_SIZE (DATA_TPIU_END - DATA_TPIU_BASE + 1) -#define TPIU_SPS *((volatile int32u *)0xE0040000u) -#define TPIU_SPS_REG *((volatile int32u *)0xE0040000u) +#define TPIU_SPS *((volatile uint32_t *)0xE0040000u) +#define TPIU_SPS_REG *((volatile uint32_t *)0xE0040000u) #define TPIU_SPS_ADDR (0xE0040000u) #define TPIU_SPS_RESET (0x00000000u) /* SPS_04 field */ @@ -11150,8 +11150,8 @@ #define TPIU_SPS_SPS_01_BIT (0) #define TPIU_SPS_SPS_01_BITS (1) -#define TPIU_CPS *((volatile int32u *)0xE0040004u) -#define TPIU_CPS_REG *((volatile int32u *)0xE0040004u) +#define TPIU_CPS *((volatile uint32_t *)0xE0040004u) +#define TPIU_CPS_REG *((volatile uint32_t *)0xE0040004u) #define TPIU_CPS_ADDR (0xE0040004u) #define TPIU_CPS_RESET (0x00000001u) /* CPS_04 field */ @@ -11175,8 +11175,8 @@ #define TPIU_CPS_CPS_01_BIT (0) #define TPIU_CPS_CPS_01_BITS (1) -#define TPIU_COSD *((volatile int32u *)0xE0040010u) -#define TPIU_COSD_REG *((volatile int32u *)0xE0040010u) +#define TPIU_COSD *((volatile uint32_t *)0xE0040010u) +#define TPIU_COSD_REG *((volatile uint32_t *)0xE0040010u) #define TPIU_COSD_ADDR (0xE0040010u) #define TPIU_COSD_RESET (0x00000000u) /* PRESCALER field */ @@ -11185,8 +11185,8 @@ #define TPIU_COSD_PRESCALER_BIT (0) #define TPIU_COSD_PRESCALER_BITS (13) -#define TPIU_SPP *((volatile int32u *)0xE00400F0u) -#define TPIU_SPP_REG *((volatile int32u *)0xE00400F0u) +#define TPIU_SPP *((volatile uint32_t *)0xE00400F0u) +#define TPIU_SPP_REG *((volatile uint32_t *)0xE00400F0u) #define TPIU_SPP_ADDR (0xE00400F0u) #define TPIU_SPP_RESET (0x00000001u) /* PROTOCOL field */ @@ -11195,8 +11195,8 @@ #define TPIU_SPP_PROTOCOL_BIT (0) #define TPIU_SPP_PROTOCOL_BITS (2) -#define TPIU_FFS *((volatile int32u *)0xE0040300u) -#define TPIU_FFS_REG *((volatile int32u *)0xE0040300u) +#define TPIU_FFS *((volatile uint32_t *)0xE0040300u) +#define TPIU_FFS_REG *((volatile uint32_t *)0xE0040300u) #define TPIU_FFS_ADDR (0xE0040300u) #define TPIU_FFS_RESET (0x00000008u) /* FTNONSTOP field */ @@ -11220,8 +11220,8 @@ #define TPIU_FFS_FLINPROG_BIT (0) #define TPIU_FFS_FLINPROG_BITS (1) -#define TPIU_FFC *((volatile int32u *)0xE0040304u) -#define TPIU_FFC_REG *((volatile int32u *)0xE0040304u) +#define TPIU_FFC *((volatile uint32_t *)0xE0040304u) +#define TPIU_FFC_REG *((volatile uint32_t *)0xE0040304u) #define TPIU_FFC_ADDR (0xE0040304u) #define TPIU_FFC_RESET (0x00000102u) /* TRIGIN field */ @@ -11235,8 +11235,8 @@ #define TPIU_FFC_ENFCONT_BIT (1) #define TPIU_FFC_ENFCONT_BITS (1) -#define TPIU_FSC *((volatile int32u *)0xE0040308u) -#define TPIU_FSC_REG *((volatile int32u *)0xE0040308u) +#define TPIU_FSC *((volatile uint32_t *)0xE0040308u) +#define TPIU_FSC_REG *((volatile uint32_t *)0xE0040308u) #define TPIU_FSC_ADDR (0xE0040308u) #define TPIU_FSC_RESET (0x00000000u) /* FSC field */ @@ -11245,8 +11245,8 @@ #define TPIU_FSC_FSC_BIT (0) #define TPIU_FSC_FSC_BITS (32) -#define TPIU_ITATBCTR2 *((volatile int32u *)0xE0040EF0u) -#define TPIU_ITATBCTR2_REG *((volatile int32u *)0xE0040EF0u) +#define TPIU_ITATBCTR2 *((volatile uint32_t *)0xE0040EF0u) +#define TPIU_ITATBCTR2_REG *((volatile uint32_t *)0xE0040EF0u) #define TPIU_ITATBCTR2_ADDR (0xE0040EF0u) #define TPIU_ITATBCTR2_RESET (0x00000000u) /* ATREADY1 field */ @@ -11255,8 +11255,8 @@ #define TPIU_ITATBCTR2_ATREADY1_BIT (0) #define TPIU_ITATBCTR2_ATREADY1_BITS (1) -#define TPIU_ITATBCTR0 *((volatile int32u *)0xE0040EF8u) -#define TPIU_ITATBCTR0_REG *((volatile int32u *)0xE0040EF8u) +#define TPIU_ITATBCTR0 *((volatile uint32_t *)0xE0040EF8u) +#define TPIU_ITATBCTR0_REG *((volatile uint32_t *)0xE0040EF8u) #define TPIU_ITATBCTR0_ADDR (0xE0040EF8u) #define TPIU_ITATBCTR0_RESET (0x00000000u) /* ATREADY1 field */ @@ -11275,8 +11275,8 @@ #define DATA_ROM_TAB_END (0xE00FFFFFu) #define DATA_ROM_TAB_SIZE (DATA_ROM_TAB_END - DATA_ROM_TAB_BASE + 1) -#define ROM_SCS *((volatile int32u *)0xE00FF000u) -#define ROM_SCS_REG *((volatile int32u *)0xE00FF000u) +#define ROM_SCS *((volatile uint32_t *)0xE00FF000u) +#define ROM_SCS_REG *((volatile uint32_t *)0xE00FF000u) #define ROM_SCS_ADDR (0xE00FF000u) #define ROM_SCS_RESET (0xFFF0F003u) /* ADDR_OFF field */ @@ -11295,8 +11295,8 @@ #define ROM_SCS_ENTRY_PRES_BIT (0) #define ROM_SCS_ENTRY_PRES_BITS (1) -#define ROM_DWT *((volatile int32u *)0xE00FF004u) -#define ROM_DWT_REG *((volatile int32u *)0xE00FF004u) +#define ROM_DWT *((volatile uint32_t *)0xE00FF004u) +#define ROM_DWT_REG *((volatile uint32_t *)0xE00FF004u) #define ROM_DWT_ADDR (0xE00FF004u) #define ROM_DWT_RESET (0xFFF02003u) /* ADDR_OFF field */ @@ -11315,8 +11315,8 @@ #define ROM_DWT_ENTRY_PRES_BIT (0) #define ROM_DWT_ENTRY_PRES_BITS (1) -#define ROM_FPB *((volatile int32u *)0xE00FF008u) -#define ROM_FPB_REG *((volatile int32u *)0xE00FF008u) +#define ROM_FPB *((volatile uint32_t *)0xE00FF008u) +#define ROM_FPB_REG *((volatile uint32_t *)0xE00FF008u) #define ROM_FPB_ADDR (0xE00FF008u) #define ROM_FPB_RESET (0xFFF03003u) /* ADDR_OFF field */ @@ -11335,8 +11335,8 @@ #define ROM_FPB_ENTRY_PRES_BIT (0) #define ROM_FPB_ENTRY_PRES_BITS (1) -#define ROM_ITM *((volatile int32u *)0xE00FF00Cu) -#define ROM_ITM_REG *((volatile int32u *)0xE00FF00Cu) +#define ROM_ITM *((volatile uint32_t *)0xE00FF00Cu) +#define ROM_ITM_REG *((volatile uint32_t *)0xE00FF00Cu) #define ROM_ITM_ADDR (0xE00FF00Cu) #define ROM_ITM_RESET (0xFFF01003u) /* ADDR_OFF field */ @@ -11355,8 +11355,8 @@ #define ROM_ITM_ENTRY_PRES_BIT (0) #define ROM_ITM_ENTRY_PRES_BITS (1) -#define ROM_TPIU *((volatile int32u *)0xE00FF010u) -#define ROM_TPIU_REG *((volatile int32u *)0xE00FF010u) +#define ROM_TPIU *((volatile uint32_t *)0xE00FF010u) +#define ROM_TPIU_REG *((volatile uint32_t *)0xE00FF010u) #define ROM_TPIU_ADDR (0xE00FF010u) #define ROM_TPIU_RESET (0xFFF0F003u) /* ADDR_OFF field */ @@ -11375,8 +11375,8 @@ #define ROM_TPIU_ENTRY_PRES_BIT (0) #define ROM_TPIU_ENTRY_PRES_BITS (1) -#define ROM_ETM *((volatile int32u *)0xE00FF014u) -#define ROM_ETM_REG *((volatile int32u *)0xE00FF014u) +#define ROM_ETM *((volatile uint32_t *)0xE00FF014u) +#define ROM_ETM_REG *((volatile uint32_t *)0xE00FF014u) #define ROM_ETM_ADDR (0xE00FF014u) #define ROM_ETM_RESET (0xFFF0F002u) /* ADDR_OFF field */ @@ -11395,8 +11395,8 @@ #define ROM_ETM_ENTRY_PRES_BIT (0) #define ROM_ETM_ENTRY_PRES_BITS (1) -#define ROM_END *((volatile int32u *)0xE00FF018u) -#define ROM_END_REG *((volatile int32u *)0xE00FF018u) +#define ROM_END *((volatile uint32_t *)0xE00FF018u) +#define ROM_END_REG *((volatile uint32_t *)0xE00FF018u) #define ROM_END_ADDR (0xE00FF018u) #define ROM_END_RESET (0x00000000u) /* END field */ @@ -11405,8 +11405,8 @@ #define ROM_END_END_BIT (0) #define ROM_END_END_BITS (32) -#define ROM_MEMTYPE *((volatile int32u *)0xE00FFFCCu) -#define ROM_MEMTYPE_REG *((volatile int32u *)0xE00FFFCCu) +#define ROM_MEMTYPE *((volatile uint32_t *)0xE00FFFCCu) +#define ROM_MEMTYPE_REG *((volatile uint32_t *)0xE00FFFCCu) #define ROM_MEMTYPE_ADDR (0xE00FFFCCu) #define ROM_MEMTYPE_RESET (0x00000001u) /* MEMTYPE field */ @@ -11415,8 +11415,8 @@ #define ROM_MEMTYPE_MEMTYPE_BIT (0) #define ROM_MEMTYPE_MEMTYPE_BITS (1) -#define ROM_PID4 *((volatile int32u *)0xE00FFFD0u) -#define ROM_PID4_REG *((volatile int32u *)0xE00FFFD0u) +#define ROM_PID4 *((volatile uint32_t *)0xE00FFFD0u) +#define ROM_PID4_REG *((volatile uint32_t *)0xE00FFFD0u) #define ROM_PID4_ADDR (0xE00FFFD0u) #define ROM_PID4_RESET (0x00000000u) /* PID field */ @@ -11425,8 +11425,8 @@ #define ROM_PID4_PID_BIT (0) #define ROM_PID4_PID_BITS (4) -#define ROM_PID5 *((volatile int32u *)0xE00FFFD4u) -#define ROM_PID5_REG *((volatile int32u *)0xE00FFFD4u) +#define ROM_PID5 *((volatile uint32_t *)0xE00FFFD4u) +#define ROM_PID5_REG *((volatile uint32_t *)0xE00FFFD4u) #define ROM_PID5_ADDR (0xE00FFFD4u) #define ROM_PID5_RESET (0x00000000u) /* PID field */ @@ -11435,8 +11435,8 @@ #define ROM_PID5_PID_BIT (0) #define ROM_PID5_PID_BITS (4) -#define ROM_PID6 *((volatile int32u *)0xE00FFFD8u) -#define ROM_PID6_REG *((volatile int32u *)0xE00FFFD8u) +#define ROM_PID6 *((volatile uint32_t *)0xE00FFFD8u) +#define ROM_PID6_REG *((volatile uint32_t *)0xE00FFFD8u) #define ROM_PID6_ADDR (0xE00FFFD8u) #define ROM_PID6_RESET (0x00000000u) /* PID field */ @@ -11445,8 +11445,8 @@ #define ROM_PID6_PID_BIT (0) #define ROM_PID6_PID_BITS (4) -#define ROM_PID7 *((volatile int32u *)0xE00FFFDCu) -#define ROM_PID7_REG *((volatile int32u *)0xE00FFFDCu) +#define ROM_PID7 *((volatile uint32_t *)0xE00FFFDCu) +#define ROM_PID7_REG *((volatile uint32_t *)0xE00FFFDCu) #define ROM_PID7_ADDR (0xE00FFFDCu) #define ROM_PID7_RESET (0x00000000u) /* PID field */ @@ -11455,8 +11455,8 @@ #define ROM_PID7_PID_BIT (0) #define ROM_PID7_PID_BITS (4) -#define ROM_PID0 *((volatile int32u *)0xE00FFFE0u) -#define ROM_PID0_REG *((volatile int32u *)0xE00FFFE0u) +#define ROM_PID0 *((volatile uint32_t *)0xE00FFFE0u) +#define ROM_PID0_REG *((volatile uint32_t *)0xE00FFFE0u) #define ROM_PID0_ADDR (0xE00FFFE0u) #define ROM_PID0_RESET (0x00000000u) /* PID field */ @@ -11465,8 +11465,8 @@ #define ROM_PID0_PID_BIT (0) #define ROM_PID0_PID_BITS (4) -#define ROM_PID1 *((volatile int32u *)0xE00FFFE4u) -#define ROM_PID1_REG *((volatile int32u *)0xE00FFFE4u) +#define ROM_PID1 *((volatile uint32_t *)0xE00FFFE4u) +#define ROM_PID1_REG *((volatile uint32_t *)0xE00FFFE4u) #define ROM_PID1_ADDR (0xE00FFFE4u) #define ROM_PID1_RESET (0x00000000u) /* PID field */ @@ -11475,8 +11475,8 @@ #define ROM_PID1_PID_BIT (0) #define ROM_PID1_PID_BITS (4) -#define ROM_PID2 *((volatile int32u *)0xE00FFFE8u) -#define ROM_PID2_REG *((volatile int32u *)0xE00FFFE8u) +#define ROM_PID2 *((volatile uint32_t *)0xE00FFFE8u) +#define ROM_PID2_REG *((volatile uint32_t *)0xE00FFFE8u) #define ROM_PID2_ADDR (0xE00FFFE8u) #define ROM_PID2_RESET (0x00000000u) /* PID field */ @@ -11485,8 +11485,8 @@ #define ROM_PID2_PID_BIT (0) #define ROM_PID2_PID_BITS (4) -#define ROM_PID3 *((volatile int32u *)0xE00FFFECu) -#define ROM_PID3_REG *((volatile int32u *)0xE00FFFECu) +#define ROM_PID3 *((volatile uint32_t *)0xE00FFFECu) +#define ROM_PID3_REG *((volatile uint32_t *)0xE00FFFECu) #define ROM_PID3_ADDR (0xE00FFFECu) #define ROM_PID3_RESET (0x00000000u) /* PID field */ @@ -11495,8 +11495,8 @@ #define ROM_PID3_PID_BIT (0) #define ROM_PID3_PID_BITS (4) -#define ROM_CID0 *((volatile int32u *)0xE00FFFF0u) -#define ROM_CID0_REG *((volatile int32u *)0xE00FFFF0u) +#define ROM_CID0 *((volatile uint32_t *)0xE00FFFF0u) +#define ROM_CID0_REG *((volatile uint32_t *)0xE00FFFF0u) #define ROM_CID0_ADDR (0xE00FFFF0u) #define ROM_CID0_RESET (0x0000000Du) /* CID field */ @@ -11505,8 +11505,8 @@ #define ROM_CID0_CID_BIT (0) #define ROM_CID0_CID_BITS (8) -#define ROM_CID1 *((volatile int32u *)0xE00FFFF4u) -#define ROM_CID1_REG *((volatile int32u *)0xE00FFFF4u) +#define ROM_CID1 *((volatile uint32_t *)0xE00FFFF4u) +#define ROM_CID1_REG *((volatile uint32_t *)0xE00FFFF4u) #define ROM_CID1_ADDR (0xE00FFFF4u) #define ROM_CID1_RESET (0x00000010u) /* CID field */ @@ -11515,8 +11515,8 @@ #define ROM_CID1_CID_BIT (0) #define ROM_CID1_CID_BITS (8) -#define ROM_CID2 *((volatile int32u *)0xE00FFFF8u) -#define ROM_CID2_REG *((volatile int32u *)0xE00FFFF8u) +#define ROM_CID2 *((volatile uint32_t *)0xE00FFFF8u) +#define ROM_CID2_REG *((volatile uint32_t *)0xE00FFFF8u) #define ROM_CID2_ADDR (0xE00FFFF8u) #define ROM_CID2_RESET (0x00000005u) /* CID field */ @@ -11525,8 +11525,8 @@ #define ROM_CID2_CID_BIT (0) #define ROM_CID2_CID_BITS (8) -#define ROM_CID3 *((volatile int32u *)0xE00FFFFCu) -#define ROM_CID3_REG *((volatile int32u *)0xE00FFFFCu) +#define ROM_CID3 *((volatile uint32_t *)0xE00FFFFCu) +#define ROM_CID3_REG *((volatile uint32_t *)0xE00FFFFCu) #define ROM_CID3_ADDR (0xE00FFFFCu) #define ROM_CID3_RESET (0x000000B1u) /* CID field */ diff --git a/cpu/stm32w108/hal/micro/cortexm3/stm32w108/stm32w108_type.h b/cpu/stm32w108/hal/micro/cortexm3/stm32w108/stm32w108-type.h similarity index 98% rename from cpu/stm32w108/hal/micro/cortexm3/stm32w108/stm32w108_type.h rename to cpu/stm32w108/hal/micro/cortexm3/stm32w108/stm32w108-type.h index bddd90f34..30e11dd69 100644 --- a/cpu/stm32w108/hal/micro/cortexm3/stm32w108/stm32w108_type.h +++ b/cpu/stm32w108/hal/micro/cortexm3/stm32w108/stm32w108-type.h @@ -1,5 +1,5 @@ /******************** (C) COPYRIGHT 2007 STMicroelectronics ******************** -* File Name : stm32w108_type.h +* File Name : stm32w108-type.h * Author : MCD Application Team * Version : V1.0 * Date : 10/08/2009 diff --git a/cpu/stm32w108/hal/micro/cortexm3/system-timer.c b/cpu/stm32w108/hal/micro/cortexm3/system-timer.c index 1f9b1f533..46c350694 100644 --- a/cpu/stm32w108/hal/micro/cortexm3/system-timer.c +++ b/cpu/stm32w108/hal/micro/cortexm3/system-timer.c @@ -32,14 +32,14 @@ static boolean sleepTimerInterruptOccurred = FALSE; * a single clock tick occurs every 0.9769625 milliseconds, and a rollover * of the 16-bit timer occurs every 64 seconds. */ -int16u halCommonGetInt16uMillisecondTick(void) +uint16_t halCommonGetInt16uMillisecondTick(void) { - return (int16u)halCommonGetInt32uMillisecondTick(); + return (uint16_t)halCommonGetInt32uMillisecondTick(); } -int16u halCommonGetInt16uQuarterSecondTick(void) +uint16_t halCommonGetInt16uQuarterSecondTick(void) { - return (int16u)(halCommonGetInt32uMillisecondTick() >> 8); + return (uint16_t)(halCommonGetInt32uMillisecondTick() >> 8); } /** @@ -47,9 +47,9 @@ int16u halCommonGetInt16uQuarterSecondTick(void) * a single clock tick occurs every 0.9769625 milliseconds, and a rollover * of the 32-bit timer occurs approximately every 48.5 days. */ -int32u halCommonGetInt32uMillisecondTick(void) +uint32_t halCommonGetInt32uMillisecondTick(void) { - int32u time; + uint32_t time; time = SLEEPTMR_CNTH<<16; time |= SLEEPTMR_CNTL; @@ -71,13 +71,13 @@ void halSleepTimerIsr(void) #define CONVERT_TICKS_TO_QS(x) ((x) >> 8) #define TIMER_MAX_QS 0x1000000 // = 4194304 seconds * 4 = 16777216 static StStatus internalSleepForQs(boolean useGpioWakeMask, - int32u *duration, - int32u gpioWakeBitMask) + uint32_t *duration, + uint32_t gpioWakeBitMask) { StStatus status = ST_SUCCESS; - int32u sleepOverflowCount; - int32u remainder; - int32u startCount; + uint32_t sleepOverflowCount; + uint32_t remainder; + uint32_t startCount; //There is really no reason to bother with a duration of 0qs if(*duration==0) { @@ -165,7 +165,7 @@ static StStatus internalSleepForQs(boolean useGpioWakeMask, return status; } -StStatus halSleepForQsWithOptions(int32u *duration, int32u gpioWakeBitMask) +StStatus halSleepForQsWithOptions(uint32_t *duration, uint32_t gpioWakeBitMask) { return internalSleepForQs(TRUE, duration, gpioWakeBitMask); } diff --git a/cpu/stm32w108/hal/micro/cortexm3/temperature_sensor.c b/cpu/stm32w108/hal/micro/cortexm3/temperature-sensor.c similarity index 87% rename from cpu/stm32w108/hal/micro/cortexm3/temperature_sensor.c rename to cpu/stm32w108/hal/micro/cortexm3/temperature-sensor.c index b4bcc7a9d..152b3bd90 100644 --- a/cpu/stm32w108/hal/micro/cortexm3/temperature_sensor.c +++ b/cpu/stm32w108/hal/micro/cortexm3/temperature-sensor.c @@ -1,4 +1,4 @@ -/**@file temperature_sensor.c +/**@file temperature-sensor.c * @brief MB851 temperature sensor APIS * * @@ -8,7 +8,7 @@ #include BOARD_HEADER #include "hal/hal.h" #include "hal/error.h" -#include "hal/micro/temperature_sensor.h" +#include "hal/micro/temperature-sensor.h" #include "hal/micro/adc.h" void temperatureSensor_Init(void) @@ -29,10 +29,10 @@ void temperatureSensor_Init(void) #endif /* ENABLE_ADC_EXTENDED_RANGE_BROKEN */ }/* end temperatureSensor_Init() */ -int32u temperatureSensor_GetValue(void) +uint32_t temperatureSensor_GetValue(void) { - static int16u ADCvalue; - static int16s volts; + static uint16_t ADCvalue; + static int16_t volts; /* NOTE: @@ -47,6 +47,6 @@ int32u temperatureSensor_GetValue(void) // 100 uVolts volts = halConvertValueToVolts(ADCvalue); - return ((18641 - (int32s)volts)*100)/1171; + return ((18641 - (int32_t)volts)*100)/1171; }/* end temperatureSensor_GetValue() */ diff --git a/cpu/stm32w108/hal/micro/cortexm3/token-manufacturing.h b/cpu/stm32w108/hal/micro/cortexm3/token-manufacturing.h index 597b50305..cbcd92d6f 100644 --- a/cpu/stm32w108/hal/micro/cortexm3/token-manufacturing.h +++ b/cpu/stm32w108/hal/micro/cortexm3/token-manufacturing.h @@ -83,72 +83,72 @@ #ifndef __MFG_TYPES_DEFINED__ #define __MFG_TYPES_DEFINED__ //--- Fixed Information Block --- -typedef int8u tokTypeMfgChipData[24]; -typedef int8u tokTypeMfgPartData[6]; -typedef int8u tokTypeMfgTesterData[6]; -typedef int8u tokTypeMfgStEui64[8]; +typedef uint8_t tokTypeMfgChipData[24]; +typedef uint8_t tokTypeMfgPartData[6]; +typedef uint8_t tokTypeMfgTesterData[6]; +typedef uint8_t tokTypeMfgStEui64[8]; typedef struct { - int16u iffilterL; - int16u lna; - int16u ifamp; - int16u rxadcH; - int16u prescalar; - int16u phdet; - int16u vco; - int16u loopfilter; - int16u pa; - int16u iqmixer; + uint16_t iffilterL; + uint16_t lna; + uint16_t ifamp; + uint16_t rxadcH; + uint16_t prescalar; + uint16_t phdet; + uint16_t vco; + uint16_t loopfilter; + uint16_t pa; + uint16_t iqmixer; } tokTypeMfgAnalogueTrim; typedef struct { - int16u iffilterH; - int16u biasmaster; - int16u moddac; - int16u auxadc; - int16u caladc; + uint16_t iffilterH; + uint16_t biasmaster; + uint16_t moddac; + uint16_t auxadc; + uint16_t caladc; } tokTypeMfgAnalogueTrimBoth; typedef struct { - int8u regTrim1V2; - int8u regTrim1V8; + uint8_t regTrim1V2; + uint8_t regTrim1V8; } tokTypeMfgRegTrim; -typedef int16u tokTypeMfgRegVoltage1V8; -typedef int16u tokTypeMfgAdcVrefVoltage; -typedef int16u tokTypeMfgTempCal; -typedef int16u tokTypeMfgFibVersion; -typedef int16u tokTypeMfgFibChecksum; +typedef uint16_t tokTypeMfgRegVoltage1V8; +typedef uint16_t tokTypeMfgAdcVrefVoltage; +typedef uint16_t tokTypeMfgTempCal; +typedef uint16_t tokTypeMfgFibVersion; +typedef uint16_t tokTypeMfgFibChecksum; typedef struct { - int16u ob2; - int16u ob3; - int16u ob0; - int16u ob1; + uint16_t ob2; + uint16_t ob3; + uint16_t ob0; + uint16_t ob1; } tokTypeMfgFibObs; //--- Customer Information Block --- typedef struct { - int16u ob0; - int16u ob1; - int16u ob2; - int16u ob3; - int16u ob4; - int16u ob5; - int16u ob6; - int16u ob7; + uint16_t ob0; + uint16_t ob1; + uint16_t ob2; + uint16_t ob3; + uint16_t ob4; + uint16_t ob5; + uint16_t ob6; + uint16_t ob7; } tokTypeMfgCibObs; -typedef int16u tokTypeMfgCustomVersion; -typedef int8u tokTypeMfgCustomEui64[8]; -typedef int8u tokTypeMfgString[16]; -typedef int8u tokTypeMfgBoardName[16]; -typedef int16u tokTypeMfgManufId; -typedef int16u tokTypeMfgPhyConfig; -typedef int8u tokTypeMfgBootloadAesKey[16]; -typedef int8u tokTypeMfgEui64[8]; -typedef int8u tokTypeMfgEzspStorage[8]; -typedef int16u tokTypeMfgAshConfig; +typedef uint16_t tokTypeMfgCustomVersion; +typedef uint8_t tokTypeMfgCustomEui64[8]; +typedef uint8_t tokTypeMfgString[16]; +typedef uint8_t tokTypeMfgBoardName[16]; +typedef uint16_t tokTypeMfgManufId; +typedef uint16_t tokTypeMfgPhyConfig; +typedef uint8_t tokTypeMfgBootloadAesKey[16]; +typedef uint8_t tokTypeMfgEui64[8]; +typedef uint8_t tokTypeMfgEzspStorage[8]; +typedef uint16_t tokTypeMfgAshConfig; typedef struct { - int8u certificate[48]; - int8u caPublicKey[22]; - int8u privateKey[21]; + uint8_t certificate[48]; + uint8_t caPublicKey[22]; + uint8_t privateKey[21]; // The bottom flag bit is 1 for uninitialized, 0 for initialized. // The other flag bits should be set to 0 at initialization. - int8u flags; + uint8_t flags; } tokTypeMfgCbkeData; typedef struct { // The bottom flag bit is 1 for uninitialized, 0 for initialized. @@ -158,11 +158,11 @@ typedef struct { // Special flags support. Due to a bug in the way some customers // had programmed the flags field, we will also examine the upper // bits 9 and 10 for the size field. Those bits are also reserved. - int16u flags; - int8u value[16]; - int16u crc; + uint16_t flags; + uint8_t value[16]; + uint16_t crc; } tokTypeMfgInstallationCode; -typedef int16u tokTypeMfgOsc24mBiasTrim; +typedef uint16_t tokTypeMfgOsc24mBiasTrim; #endif //__MFG_TYPES_DEFINED__ diff --git a/cpu/stm32w108/hal/micro/cortexm3/uart.c b/cpu/stm32w108/hal/micro/cortexm3/uart.c index 831742274..e42b396ac 100644 --- a/cpu/stm32w108/hal/micro/cortexm3/uart.c +++ b/cpu/stm32w108/hal/micro/cortexm3/uart.c @@ -28,18 +28,18 @@ int putchar (int c) #endif #define RECEIVE_QUEUE_SIZE (128) -int8u rxQ[RECEIVE_QUEUE_SIZE]; -int16u rxHead; -int16u rxTail; -int16u rxUsed; +uint8_t rxQ[RECEIVE_QUEUE_SIZE]; +uint16_t rxHead; +uint16_t rxTail; +uint16_t rxUsed; ////////////////////////////////////////////////////////////////////////////// // Initialization -void uartInit(int32u baudrate, int8u databits, SerialParity parity, int8u stopbits) +void uartInit(uint32_t baudrate, uint8_t databits, SerialParity parity, uint8_t stopbits) { - int32u tempcfg; - int32u tmp; + uint32_t tempcfg; + uint32_t tmp; assert( (baudrate >= 300) && (baudrate <=921600) ); @@ -171,10 +171,10 @@ static void halInternalUart1RxIsr(void) // data, processing any errors noted // along the way. while ( SC1_UARTSTAT & SC_UARTRXVAL ) { - int8u errors = SC1_UARTSTAT & (SC_UARTFRMERR | + uint8_t errors = SC1_UARTSTAT & (SC_UARTFRMERR | SC_UARTRXOVF | SC_UARTPARERR ); - int8u incoming = (int8u) SC1_DATA; + uint8_t incoming = (uint8_t) SC1_DATA; if ( (errors == 0) && (rxUsed < (RECEIVE_QUEUE_SIZE-1)) ) { rxQ[rxHead] = incoming; @@ -194,7 +194,7 @@ static void halInternalUart1RxIsr(void) void halSc1Isr(void) { - int32u interrupt; + uint32_t interrupt; //this read and mask is performed in two steps otherwise the compiler //will complain about undefined order of volatile access @@ -233,7 +233,7 @@ void halSc1Isr(void) * Output : dataByte: buffer containing the read byte if any * Return : TRUE if there is a data, FALSE otherwise *******************************************************************************/ -boolean __io_getcharNonBlocking(int8u *data) +boolean __io_getcharNonBlocking(uint8_t *data) { if (__read(_LLIO_STDIN,data,1)) return TRUE; diff --git a/cpu/stm32w108/hal/micro/cortexm3/uart.h b/cpu/stm32w108/hal/micro/cortexm3/uart.h index 9d81f6c01..2eb45c0af 100644 --- a/cpu/stm32w108/hal/micro/cortexm3/uart.h +++ b/cpu/stm32w108/hal/micro/cortexm3/uart.h @@ -36,7 +36,7 @@ typedef enum * @return stopbits The number of stop bits used for communication. * Valid values are 1 or 2 */ -void uartInit(int32u baudrate, int8u databits, SerialParity parity, int8u stopbits); +void uartInit(uint32_t baudrate, uint8_t databits, SerialParity parity, uint8_t stopbits); #ifdef __ICCARM__ /** @@ -63,7 +63,7 @@ size_t fflush(int handle); /** * @brief Read the input byte if any. */ -boolean __io_getcharNonBlocking(int8u *data); +boolean __io_getcharNonBlocking(uint8_t *data); void __io_putchar( char c ); int __io_getchar(void); void __io_flush( void ); diff --git a/cpu/stm32w108/hal/micro/generic/compiler/platform-common.h b/cpu/stm32w108/hal/micro/generic/compiler/platform-common.h index 3e939cf0f..ee56fa6df 100644 --- a/cpu/stm32w108/hal/micro/generic/compiler/platform-common.h +++ b/cpu/stm32w108/hal/micro/generic/compiler/platform-common.h @@ -1,11 +1,5 @@ -/** @file hal/micro/generic/compiler/platform-common.h - * See @ref platform_common for detailed documentation. - * - * - */ - -/** @addtogroup platform_common - * @brief Compiler and Platform specific definitions and typedefs common to +/** \addtogroup platform_common + * \brief Compiler and Platform specific definitions and typedefs common to * all platforms. * * platform-common.h provides PLATFORM_HEADER defaults and common definitions. @@ -15,6 +9,13 @@ * See platform-common.h for source code. *@{ */ + +/** \file hal/micro/generic/compiler/platform-common.h + * See \ref platform_common for detailed documentation. + * + * + */ + #ifndef PLATCOMMONOKTOINCLUDE // This header should only be included by a PLATFORM_HEADER @@ -36,23 +37,23 @@ */ //@{ /** - * @brief Standard program memory delcaration. + * \brief Standard program memory delcaration. */ #define PGM const /** - * @brief Char pointer to program memory declaration. + * \brief Char pointer to program memory declaration. */ #define PGM_P const char * /** - * @brief Unsigned char pointer to program memory declaration. + * \brief Unsigned char pointer to program memory declaration. */ #define PGM_PU const unsigned char * /** - * @brief Sometimes a second PGM is needed in a declaration. Having two + * \brief Sometimes a second PGM is needed in a declaration. Having two * 'const' declarations generates a warning so we have a second PGM that turns * into nothing under gcc. */ @@ -72,32 +73,32 @@ */ //@{ /** - * @brief Provide a portable name for the int32u by int16u division + * \brief Provide a portable name for the uint32_t by uint16_t division * library function (which can perform the division with only a single * assembly instruction on some platforms) */ - #define halCommonUDiv32By16(x, y) ((int16u) (((int32u) (x)) / ((int16u) (y)))) + #define halCommonUDiv32By16(x, y) ((uint16_t) (((uint32_t) (x)) / ((uint16_t) (y)))) /** - * @brief Provide a portable name for the int32s by int16s division + * \brief Provide a portable name for the int32_t by int16_t division * library function (which can perform the division with only a single * assembly instruction on some platforms) */ - #define halCommonSDiv32By16(x, y) ((int16s) (((int32s) (x)) / ((int16s) (y)))) + #define halCommonSDiv32By16(x, y) ((int16_t) (((int32_t) (x)) / ((int16_t) (y)))) /** - * @brief Provide a portable name for the int32u by int16u modulo + * \brief Provide a portable name for the uint32_t by uint16_t modulo * library function (which can perform the division with only a single * assembly instruction on some platforms) */ - #define halCommonUMod32By16(x, y) ((int16u) (((int32u) (x)) % ((int16u) (y)))) + #define halCommonUMod32By16(x, y) ((uint16_t) (((uint32_t) (x)) % ((uint16_t) (y)))) /** - * @brief Provide a portable name for the int32s by int16s modulo + * \brief Provide a portable name for the int32_t by int16_t modulo * library function (which can perform the division with only a single * assembly instruction on some platforms) */ - #define halCommonSMod32By16(x, y) ((int16s) (((int32s) (x)) % ((int16s) (y)))) + #define halCommonSMod32By16(x, y) ((int16_t) (((int32_t) (x)) % ((int16_t) (y)))) //@} \\END DIVIDE and MODULUS OPERATIONS #endif //_HAL_USE_COMMON_DIVMOD_ @@ -118,25 +119,25 @@ //@{ /** - * @brief Refer to the C stdlib memcpy(). + * \brief Refer to the C stdlib memcpy(). */ - void halCommonMemCopy(void *dest, const void *src, int8u bytes); + void halCommonMemCopy(void *dest, const void *src, uint8_t bytes); /** - * @brief Refer to the C stdlib memset(). + * \brief Refer to the C stdlib memset(). */ - void halCommonMemSet(void *dest, int8u val, int16u bytes); + void halCommonMemSet(void *dest, uint8_t val, uint16_t bytes); /** - * @brief Refer to the C stdlib memcmp(). + * \brief Refer to the C stdlib memcmp(). */ - int8s halCommonMemCompare(const void *source0, const void *source1, int8u bytes); + int8_t halCommonMemCompare(const void *source0, const void *source1, uint8_t bytes); /** - * @brief Friendly convenience macro pointing to the full HAL function. + * \brief Friendly convenience macro pointing to the full HAL function. */ #define MEMSET(d,v,l) halCommonMemSet(d,v,l) #define MEMCOPY(d,s,l) halCommonMemCopy(d,s,l) @@ -165,18 +166,18 @@ */ /** - * @brief An alias for one, used for clarity. + * \brief An alias for one, used for clarity. */ #define TRUE 1 /** - * @brief An alias for zero, used for clarity. + * \brief An alias for zero, used for clarity. */ #define FALSE 0 #ifndef NULL /** - * @brief The null pointer. + * \brief The null pointer. */ #define NULL ((void *)0) #endif @@ -190,50 +191,50 @@ //@{ /** - * @brief Useful to reference a single bit of a byte. + * \brief Useful to reference a single bit of a byte. */ #define BIT(x) (1U << (x)) // Unsigned avoids compiler warnings re BIT(15) /** - * @brief Useful to reference a single bit of an int32u type. + * \brief Useful to reference a single bit of an uint32_t type. */ -#define BIT32(x) (((int32u) 1) << (x)) +#define BIT32(x) (((uint32_t) 1) << (x)) /** - * @brief Sets \c bit in the \c reg register or byte. + * \brief Sets \c bit in the \c reg register or byte. * @note Assuming \c reg is an IO register, some platforms * can implement this in a single atomic operation. */ #define SETBIT(reg, bit) reg |= BIT(bit) /** - * @brief Sets the bits in the \c reg register or the byte + * \brief Sets the bits in the \c reg register or the byte * as specified in the bitmask \c bits. * @note This is never a single atomic operation. */ #define SETBITS(reg, bits) reg |= (bits) /** - * @brief Clears a bit in the \c reg register or byte. + * \brief Clears a bit in the \c reg register or byte. * @note Assuming \c reg is an IO register, some platforms (such as the AVR) * can implement this in a single atomic operation. */ #define CLEARBIT(reg, bit) reg &= ~(BIT(bit)) /** - * @brief Clears the bits in the \c reg register or byte + * \brief Clears the bits in the \c reg register or byte * as specified in the bitmask \c bits. * @note This is never a single atomic operation. */ #define CLEARBITS(reg, bits) reg &= ~(bits) /** - * @brief Returns the value of \c bit within the register or byte \c reg. + * \brief Returns the value of \c bit within the register or byte \c reg. */ #define READBIT(reg, bit) (reg & (BIT(bit))) /** - * @brief Returns the value of the bitmask \c bits within + * \brief Returns the value of the bitmask \c bits within * the register or byte \c reg. */ #define READBITS(reg, bits) (reg & (bits)) @@ -248,43 +249,43 @@ //@{ /** - * @brief Returns the low byte of the 16-bit value \c n as an \c int8u. + * \brief Returns the low byte of the 16-bit value \c n as an \c uint8_t. */ -#define LOW_BYTE(n) ((int8u)((n) & 0xFF)) +#define LOW_BYTE(n) ((uint8_t)((n) & 0xFF)) /** - * @brief Returns the high byte of the 16-bit value \c n as an \c int8u. + * \brief Returns the high byte of the 16-bit value \c n as an \c uint8_t. */ -#define HIGH_BYTE(n) ((int8u)(LOW_BYTE((n) >> 8))) +#define HIGH_BYTE(n) ((uint8_t)(LOW_BYTE((n) >> 8))) /** - * @brief Returns the value built from the two \c int8u + * \brief Returns the value built from the two \c uint8_t * values \c high and \c low. */ #define HIGH_LOW_TO_INT(high, low) ( \ - (( (int16u) (high) ) << 8) + \ - ( (int16u) ( (low) & 0xFF)) \ + (( (uint16_t) (high) ) << 8) + \ + ( (uint16_t) ( (low) & 0xFF)) \ ) /** - * @brief Returns the low byte of the 32-bit value \c n as an \c int8u. + * \brief Returns the low byte of the 32-bit value \c n as an \c uint8_t. */ -#define BYTE_0(n) ((int8u)((n) & 0xFF)) +#define BYTE_0(n) ((uint8_t)((n) & 0xFF)) /** - * @brief Returns the second byte of the 32-bit value \c n as an \c int8u. + * \brief Returns the second byte of the 32-bit value \c n as an \c uint8_t. */ -#define BYTE_1(n) ((int8u)(BYTE_0((n) >> 8))) +#define BYTE_1(n) ((uint8_t)(BYTE_0((n) >> 8))) /** - * @brief Returns the third byte of the 32-bit value \c n as an \c int8u. + * \brief Returns the third byte of the 32-bit value \c n as an \c uint8_t. */ -#define BYTE_2(n) ((int8u)(BYTE_0((n) >> 16))) +#define BYTE_2(n) ((uint8_t)(BYTE_0((n) >> 16))) /** - * @brief Returns the high byte of the 32-bit value \c n as an \c int8u. + * \brief Returns the high byte of the 32-bit value \c n as an \c uint8_t. */ -#define BYTE_3(n) ((int8u)(BYTE_0((n) >> 24))) +#define BYTE_3(n) ((uint8_t)(BYTE_0((n) >> 24))) //@} \\END Byte manipulation macros @@ -296,28 +297,28 @@ //@{ /** - * @brief Returns the elapsed time between two 8 bit values. + * \brief Returns the elapsed time between two 8 bit values. * Result may not be valid if the time samples differ by more than 127 */ #define elapsedTimeInt8u(oldTime, newTime) \ - ((int8u) ((int8u)(newTime) - (int8u)(oldTime))) + ((uint8_t) ((uint8_t)(newTime) - (uint8_t)(oldTime))) /** - * @brief Returns the elapsed time between two 16 bit values. + * \brief Returns the elapsed time between two 16 bit values. * Result may not be valid if the time samples differ by more than 32767 */ #define elapsedTimeInt16u(oldTime, newTime) \ - ((int16u) ((int16u)(newTime) - (int16u)(oldTime))) + ((uint16_t) ((uint16_t)(newTime) - (uint16_t)(oldTime))) /** - * @brief Returns the elapsed time between two 32 bit values. + * \brief Returns the elapsed time between two 32 bit values. * Result may not be valid if the time samples differ by more than 2147483647 */ #define elapsedTimeInt32u(oldTime, newTime) \ - ((int32u) ((int32u)(newTime) - (int32u)(oldTime))) + ((uint32_t) ((uint32_t)(newTime) - (uint32_t)(oldTime))) /** - * @brief Returns TRUE if t1 is greater than t2. Can only account for 1 wrap + * \brief Returns TRUE if t1 is greater than t2. Can only account for 1 wrap * around of the variable before it is wrong. */ #define MAX_INT8U_VALUE 0xFF @@ -325,7 +326,7 @@ (elapsedTimeInt8u(t2, t1) <= ((MAX_INT8U_VALUE + 1) / 2)) /** - * @brief Returns TRUE if t1 is greater than t2. Can only account for 1 wrap + * \brief Returns TRUE if t1 is greater than t2. Can only account for 1 wrap * around of the variable before it is wrong. */ #define MAX_INT16U_VALUE 0xFFFF @@ -333,7 +334,7 @@ (elapsedTimeInt16u(t2, t1) <= ((MAX_INT16U_VALUE + 1) / 2)) /** - * @brief Returns TRUE if t1 is greater than t2. Can only account for 1 wrap + * \brief Returns TRUE if t1 is greater than t2. Can only account for 1 wrap * around of the variable before it is wrong. */ #define MAX_INT32U_VALUE 0xFFFFFFFF diff --git a/cpu/stm32w108/hal/micro/led.h b/cpu/stm32w108/hal/micro/led.h index f6dcd0cc9..c34fca1ff 100644 --- a/cpu/stm32w108/hal/micro/led.h +++ b/cpu/stm32w108/hal/micro/led.h @@ -22,7 +22,7 @@ void halInitLed(void); /** @brief Ensures that the definitions from the BOARD_HEADER * are always used as parameters to the LED functions. */ - typedef int8u HalBoardLed; + typedef uint8_t HalBoardLed; // Note: Even though many compilers will use 16 bits for an enum instead of 8, // we choose to use an enum here. The possible compiler inefficiency does not // affect stack-based parameters and local variables, which is the diff --git a/cpu/stm32w108/hal/micro/mems_regs.h b/cpu/stm32w108/hal/micro/mems-regs.h similarity index 94% rename from cpu/stm32w108/hal/micro/mems_regs.h rename to cpu/stm32w108/hal/micro/mems-regs.h index bd06552df..63c21418d 100644 --- a/cpu/stm32w108/hal/micro/mems_regs.h +++ b/cpu/stm32w108/hal/micro/mems-regs.h @@ -1,4 +1,4 @@ -/** @file hal/micro/mems_regs.h +/** @file hal/micro/mems-regs.h * @brief stm32w108 mems registers * * @@ -112,14 +112,14 @@ //-reg_addr is the address of the register to be written--// //-pBuffer is the storage destination for the read data---// //-NoOfBytes is the amount of data to read----------------// -int8u i2c_read_reg (int8u slave_addr, int8u reg_addr, int8u *pBuffer, int8u NoOfBytes); +uint8_t i2c_read_reg (uint8_t slave_addr, uint8_t reg_addr, uint8_t *pBuffer, uint8_t NoOfBytes); //*********************i2c_write_reg**********************// //----------Writes a register on the I2C target-----------// //------slave addr is the is the I2C target device--------// //-reg_addr is the address of the register to be written--// //-reg_value is the value of the register to be written---// -int8u i2c_write_reg (int8u slave_addr, int8u reg_addr, int8u reg_value); +uint8_t i2c_write_reg (uint8_t slave_addr, uint8_t reg_addr, uint8_t reg_value); #endif /* _MEMS_REGS_H_ */ diff --git a/cpu/stm32w108/hal/micro/mems.h b/cpu/stm32w108/hal/micro/mems.h index 6697924bd..9b0649f66 100644 --- a/cpu/stm32w108/hal/micro/mems.h +++ b/cpu/stm32w108/hal/micro/mems.h @@ -8,29 +8,29 @@ #ifndef _MEMS_H_ #define _MEMS_H_ -#include "hal/micro/mems_regs.h" +#include "hal/micro/mems-regs.h" /** @brief Mems data type: three acceleration values each related to a specific direction Watch out: only lower data values (e.g. those terminated by the _l) are currently used by the device */ typedef struct { - int8u outx_l; - int8u outx_h; - int8u outy_l; - int8u outy_h; - int8u outz_l; - int8u outz_h; + uint8_t outx_l; + uint8_t outx_h; + uint8_t outy_l; + uint8_t outy_h; + uint8_t outz_l; + uint8_t outz_h; } t_mems_data; /** @brief Mems Initialization function */ -int8u mems_Init(void); +uint8_t mems_Init(void); /** @brief Get mems acceleration values */ -int8u mems_GetValue(t_mems_data *mems_data); +uint8_t mems_GetValue(t_mems_data *mems_data); #endif /* _MEMS_H_ */ diff --git a/cpu/stm32w108/hal/micro/micro-common.h b/cpu/stm32w108/hal/micro/micro-common.h index db4895361..75ce88cb0 100644 --- a/cpu/stm32w108/hal/micro/micro-common.h +++ b/cpu/stm32w108/hal/micro/micro-common.h @@ -21,7 +21,7 @@ //This is necessary here because halSleepForQsWithOptions returns an //StStatus and not adding this typedef to this file breaks a //whole lot of builds. - typedef int8u StStatus; + typedef uint8_t StStatus; #endif //__STSTATUS_TYPE__ #endif // DOXYGEN_SHOULD_SKIP_THIS @@ -58,7 +58,7 @@ void halInternalEnableWatchDog(void); * * @param magicKey A value (::MICRO_DISABLE_WATCH_DOG_KEY) that enables the function. */ -void halInternalDisableWatchDog(int8u magicKey); +void halInternalDisableWatchDog(uint8_t magicKey); /** @brief Determines whether the watchdog has been enabled or disabled. * @@ -90,7 +90,7 @@ boolean halInternalWatchDogEnabled( void ); */ enum SleepModes #else -typedef int8u SleepModes; +typedef uint8_t SleepModes; enum #endif { @@ -116,7 +116,7 @@ enum * @param us The specified time, in microseconds. Values should be between 1 and 65535 microseconds. */ -void halCommonDelayMicroseconds(int16u us); +void halCommonDelayMicroseconds(uint16_t us); /** @brief Request the appplication to enter in bootloader mode * @@ -132,7 +132,7 @@ void halCommonDelayMicroseconds(int16u us); * default panID (only vaild for RF mode). * @return An error code or it will never return. */ -StStatus halBootloaderStart(int8u mode, int8u channel, int16u panId); +StStatus halBootloaderStart(uint8_t mode, uint8_t channel, uint16_t panId); #ifdef CORTEXM3_STM32F103 #include "micro/cortexm3/stm32f103ret/micro-specific.h" diff --git a/cpu/stm32w108/hal/micro/system-timer.h b/cpu/stm32w108/hal/micro/system-timer.h index 965d3ec8b..c2df6166e 100644 --- a/cpu/stm32w108/hal/micro/system-timer.h +++ b/cpu/stm32w108/hal/micro/system-timer.h @@ -38,7 +38,7 @@ * @return Time to update the async registers after RTC is started (units of 100 * microseconds). */ -int16u halInternalStartSystemTimer(void); +uint16_t halInternalStartSystemTimer(void); /** @@ -48,7 +48,7 @@ int16u halInternalStartSystemTimer(void); * @return The least significant 16 bits of the current system time, in system * ticks. */ -int16u halCommonGetInt16uMillisecondTick(void); +uint16_t halCommonGetInt16uMillisecondTick(void); /** * @brief Returns the current system time in system ticks, as a 32-bit @@ -59,7 +59,7 @@ int16u halCommonGetInt16uMillisecondTick(void); * @return The least significant 32 bits of the current system time, in * system ticks. */ -int32u halCommonGetInt32uMillisecondTick(void); +uint32_t halCommonGetInt32uMillisecondTick(void); /** * @brief Returns the current system time in quarter second ticks, as a @@ -70,7 +70,7 @@ int32u halCommonGetInt32uMillisecondTick(void); * @return The least significant 16 bits of the current system time, in system * ticks multiplied by 256. */ -int16u halCommonGetInt16uQuarterSecondTick(void); +uint16_t halCommonGetInt16uQuarterSecondTick(void); #endif //__SYSTEM_TIMER_H__ diff --git a/cpu/stm32w108/hal/micro/temperature_sensor.h b/cpu/stm32w108/hal/micro/temperature-sensor.h similarity index 90% rename from cpu/stm32w108/hal/micro/temperature_sensor.h rename to cpu/stm32w108/hal/micro/temperature-sensor.h index 49aec4d86..d012a9bf4 100644 --- a/cpu/stm32w108/hal/micro/temperature_sensor.h +++ b/cpu/stm32w108/hal/micro/temperature-sensor.h @@ -1,4 +1,4 @@ -/** @file temperature_sensor.h +/** @file temperature-sensor.h * @brief Header for temperature sensor driver * * @@ -21,7 +21,7 @@ void temperatureSensor_Init(void); /** @brief Get temperature sensor value */ -int32u temperatureSensor_GetValue(void); +uint32_t temperatureSensor_GetValue(void); #endif /* _TEMP_SENSOR_H_ */ diff --git a/cpu/stm32w108/hal/token-phy.h b/cpu/stm32w108/hal/token-phy.h index 91a1042b8..f073a45e6 100644 --- a/cpu/stm32w108/hal/token-phy.h +++ b/cpu/stm32w108/hal/token-phy.h @@ -18,10 +18,10 @@ #ifdef DEFINETYPES typedef struct { - int8u vcoAtLna; // the VCO tune value at the time LNA value was calculated. - int8u modDac; // msb : cal needed , bit 0-5 : value - int8u filter; // msb : cal needed , bit 0-4 : value - int8u lna; // msb : cal needed , bit 0-5 : value + uint8_t vcoAtLna; // the VCO tune value at the time LNA value was calculated. + uint8_t modDac; // msb : cal needed , bit 0-5 : value + uint8_t filter; // msb : cal needed , bit 0-4 : value + uint8_t lna; // msb : cal needed , bit 0-5 : value } tokTypeStackCalData; #endif diff --git a/cpu/stm32w108/leds-arch.c b/cpu/stm32w108/leds-arch.c index 38acbcfb6..1d9bdb50b 100644 --- a/cpu/stm32w108/leds-arch.c +++ b/cpu/stm32w108/leds-arch.c @@ -1,3 +1,9 @@ +/** + * \addtogroup mb851-platform + * + * @{ + */ + /* * Copyright (c) 2010, STMicroelectronics. * All rights reserved. @@ -27,17 +33,14 @@ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * This file is part of the Contiki OS - * */ -/*---------------------------------------------------------------------------*/ + /** * \file * Leds. * \author * Salvatore Pitrulli */ -/*---------------------------------------------------------------------------*/ #include PLATFORM_HEADER #include BOARD_HEADER @@ -46,32 +49,30 @@ #include "hal/micro/micro-common.h" #include "hal/micro/cortexm3/micro-common.h" -#define LEDS_PORT *((volatile int32u *)(GPIO_PxOUT_BASE+(GPIO_Px_OFFSET*(LEDS_CONF_PORT/8)))) +#define LEDS_PORT *((volatile uint32_t *)(GPIO_PxOUT_BASE+(GPIO_Px_OFFSET*(LEDS_CONF_PORT/8)))) /*---------------------------------------------------------------------------*/ void leds_arch_init(void) -{ - halGpioConfig(PORTx_PIN(LEDS_CONF_PORT,LEDS_CONF_RED_PIN),GPIOCFG_OUT); - halGpioConfig(PORTx_PIN(LEDS_CONF_PORT,LEDS_CONF_GREEN_PIN),GPIOCFG_OUT); - +{ + halGpioConfig(PORTx_PIN(LEDS_CONF_PORT, LEDS_CONF_RED_PIN), GPIOCFG_OUT); + halGpioConfig(PORTx_PIN(LEDS_CONF_PORT, LEDS_CONF_GREEN_PIN), GPIOCFG_OUT); LEDS_PORT |= (LEDS_CONF_RED | LEDS_CONF_GREEN); } /*---------------------------------------------------------------------------*/ unsigned char leds_arch_get(void) { - return ((LEDS_PORT & LEDS_CONF_RED) ? 0 : LEDS_RED) - | ((LEDS_PORT & LEDS_CONF_GREEN) ? 0 : LEDS_GREEN); + return ((LEDS_PORT & LEDS_CONF_RED) ? 0 : LEDS_RED) | + ((LEDS_PORT & LEDS_CONF_GREEN) ? 0 : LEDS_GREEN); } /*---------------------------------------------------------------------------*/ void leds_arch_set(unsigned char leds) { - - LEDS_PORT = (LEDS_PORT & ~(LEDS_CONF_RED|LEDS_CONF_GREEN)) - | ((leds & LEDS_RED) ? 0 : LEDS_CONF_RED) - | ((leds & LEDS_GREEN) ? 0 : LEDS_CONF_GREEN); - + LEDS_PORT = (LEDS_PORT & ~(LEDS_CONF_RED | LEDS_CONF_GREEN)) | + ((leds & LEDS_RED) ? 0 : LEDS_CONF_RED) | + ((leds & LEDS_GREEN) ? 0 : LEDS_CONF_GREEN); } /*---------------------------------------------------------------------------*/ +/** @} */ diff --git a/cpu/stm32w108/mtarch.h b/cpu/stm32w108/mtarch.h index a61c7be97..f4da378ee 100644 --- a/cpu/stm32w108/mtarch.h +++ b/cpu/stm32w108/mtarch.h @@ -1,5 +1,42 @@ +/** + * \addtogroup mb851-platform + * + * @{ + */ + /* - * Implementation of multithreading in ARM Cortex-M3. To be done. + * Copyright (c) 2010, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* + * Implementation of multithreading in ARM Cortex-M3. To do. */ @@ -10,4 +47,5 @@ struct mtarch_thread { short mt_thread; }; -#endif /* __MTARCH_H__ */ \ No newline at end of file +#endif /* __MTARCH_H__ */ +/** @} */ diff --git a/cpu/stm32w108/rand.c b/cpu/stm32w108/rand.c index e09444a9c..a9a33306e 100644 --- a/cpu/stm32w108/rand.c +++ b/cpu/stm32w108/rand.c @@ -1,3 +1,9 @@ +/** + * \addtogroup mb851-platform + * + * @{ + */ + /* * Copyright (c) 2010, STMicroelectronics. * All rights reserved. @@ -27,17 +33,14 @@ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * This file is part of the Contiki OS - * */ -/*---------------------------------------------------------------------------*/ + /** * \file * Random number functions for STM32W. * \author * Salvatore Pitrulli */ -/*---------------------------------------------------------------------------*/ #include "dev/stm32w-radio.h" #include "lib/random.h" @@ -46,18 +49,20 @@ #warning "RANDOM_RAND_MAX is not defined as 65535." #endif -int rand(void) +/*--------------------------------------------------------------------------*/ +int +rand(void) { - uint16_t rand_num; - - ST_RadioGetRandomNumbers(&rand_num, 1); - - return (int)rand_num; + uint16_t rand_num; + ST_RadioGetRandomNumbers(&rand_num, 1); + return (int)rand_num; } - +/*--------------------------------------------------------------------------*/ /* * It does nothing, since the rand already generates true random numbers. */ -void srand(unsigned int seed) +void +srand(unsigned int seed) { } +/** @} */ diff --git a/cpu/stm32w108/rtimer-arch.c b/cpu/stm32w108/rtimer-arch.c index 5b3a8cbf4..5599797be 100644 --- a/cpu/stm32w108/rtimer-arch.c +++ b/cpu/stm32w108/rtimer-arch.c @@ -1,3 +1,9 @@ +/** + * \addtogroup mb851-platform + * + * @{ + */ + /* * Copyright (c) 2010, STMicroelectronics. * All rights reserved. @@ -27,23 +33,18 @@ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * This file is part of the Contiki OS - * */ -/*---------------------------------------------------------------------------*/ + /** * \file * Real-timer specific implementation for STM32W. * \author * Salvatore Pitrulli */ -/*---------------------------------------------------------------------------*/ - #include "sys/energest.h" #include "sys/rtimer.h" - #define DEBUG 0 #if DEBUG #include @@ -52,123 +53,116 @@ #define PRINTF(...) #endif +static uint16_t saved_TIM1CFG; +static uint32_t time_msb = 0; /* Most significant bits of the current time. */ - -static uint32_t time_msb = 0; // Most significant bits of the current time. - -// time of the next rtimer event. Initially is set to the max value. +/* time of the next rtimer event. Initially is set to the max + value. */ static rtimer_clock_t next_rtimer_time = 0; -static uint16_t saved_TIM1CFG; - - /*---------------------------------------------------------------------------*/ -void halTimer1Isr(void){ - - - if(INT_TIM1FLAG & INT_TIMUIF){ // Overflow event. - - //PRINTF("O %4x.\r\n", TIM1_CNT); - //printf("OV "); - +void +halTimer1Isr(void) +{ + if(INT_TIM1FLAG & INT_TIMUIF) { + rtimer_clock_t now, clock_to_wait; + /* Overflow event. */ + /* PRINTF("O %4x.\r\n", TIM1_CNT); */ + /* printf("OV "); */ time_msb++; - rtimer_clock_t now = ((rtimer_clock_t)time_msb << 16)|TIM1_CNT; - - rtimer_clock_t clock_to_wait = next_rtimer_time - now; - - if(clock_to_wait <= 0x10000 && clock_to_wait > 0){ // We must set now the Timer Compare Register. - - TIM1_CCR1 = (int16u)clock_to_wait; + now = ((rtimer_clock_t) time_msb << 16) | TIM1_CNT; + clock_to_wait = next_rtimer_time - now; + + if(clock_to_wait <= 0x10000 && clock_to_wait > 0) { + /* We must now set the Timer Compare Register. */ + TIM1_CCR1 = (uint16_t) clock_to_wait; INT_TIM1FLAG = INT_TIMCC1IF; - INT_TIM1CFG |= INT_TIMCC1IF; // Compare 1 interrupt enable. - } - + INT_TIM1CFG |= INT_TIMCC1IF; /* Compare 1 interrupt enable. */ + } INT_TIM1FLAG = INT_TIMUIF; - + } else { + if(INT_TIM1FLAG & INT_TIMCC1IF) { + /* Compare event. */ + INT_TIM1CFG &= ~INT_TIMCC1IF; /* Disable the next compare interrupt */ + PRINTF("\nCompare event %4x\r\n", TIM1_CNT); + PRINTF("INT_TIM1FLAG %2x\r\n", INT_TIM1FLAG); + ENERGEST_ON(ENERGEST_TYPE_IRQ); + rtimer_run_next(); + ENERGEST_OFF(ENERGEST_TYPE_IRQ); + INT_TIM1FLAG = INT_TIMCC1IF; + } } - - else if(INT_TIM1FLAG & INT_TIMCC1IF){ // Compare event. - - INT_TIM1CFG &= ~INT_TIMCC1IF; // Disable the next compare interrupt - - PRINTF("\nCompare event %4x\r\n", TIM1_CNT); - PRINTF("INT_TIM1FLAG %2x\r\n", INT_TIM1FLAG); - ENERGEST_ON(ENERGEST_TYPE_IRQ); - rtimer_run_next(); - ENERGEST_OFF(ENERGEST_TYPE_IRQ); - INT_TIM1FLAG = INT_TIMCC1IF; - - } - } /*---------------------------------------------------------------------------*/ void rtimer_arch_init(void) { TIM1_CR1 = 0; - - TIM1_PSC = RT_PRESCALER; - - TIM1_ARR = 0xffff; // Counting from 0 to the maximum value. - - // Bits of TIMx_CCMR1 as default. - - TIM1_EGR = TIM_UG; // Update Generation. - + TIM1_PSC = RTIMER_ARCH_PRESCALER; + + /* Counting from 0 to the maximum value. */ + TIM1_ARR = 0xffff; + + /* Bits of TIMx_CCMR1 as default. */ + /* Update Generation. */ + TIM1_EGR = TIM_UG; INT_TIM1FLAG = 0xffff; - - INT_TIM1CFG = INT_TIMUIF; // Update interrupt enable (interrupt on overflow). - - TIM1_CR1 = TIM_CEN; // Counter enable. - - INT_CFGSET = INT_TIM1; // Enable top level interrupt. + + /* Update interrupt enable (interrupt on overflow).*/ + INT_TIM1CFG = INT_TIMUIF; + + /* Counter enable. */ + TIM1_CR1 = TIM_CEN; + + /* Enable top level interrupt. */ + INT_CFGSET = INT_TIM1; } /*---------------------------------------------------------------------------*/ -void rtimer_arch_disable_irq(void) +void +rtimer_arch_disable_irq(void) { - ATOMIC( - saved_TIM1CFG = INT_TIM1CFG; - INT_TIM1CFG = 0; - ) + ATOMIC(saved_TIM1CFG = INT_TIM1CFG; INT_TIM1CFG = 0;) } /*---------------------------------------------------------------------------*/ -void rtimer_arch_enable_irq(void) +void +rtimer_arch_enable_irq(void) { INT_TIM1CFG = saved_TIM1CFG; } /*---------------------------------------------------------------------------*/ -rtimer_clock_t rtimer_arch_now(void) +rtimer_clock_t +rtimer_arch_now(void) { - return ((rtimer_clock_t)time_msb << 16)|TIM1_CNT; + rtimer_clock_t t; + + ATOMIC(t = ((rtimer_clock_t) time_msb << 16) | TIM1_CNT;) + return t; } /*---------------------------------------------------------------------------*/ - void rtimer_arch_schedule(rtimer_clock_t t) { - - PRINTF("rtimer_arch_schedule time %4x\r\n", /*((uint32_t*)&t)+1,*/(uint32_t)t); - + rtimer_clock_t now, clock_to_wait; + PRINTF("rtimer_arch_schedule time %4x\r\n", /*((uint32_t*)&t)+1, */ + (uint32_t)t); next_rtimer_time = t; - - rtimer_clock_t now = rtimer_arch_now(); - - rtimer_clock_t clock_to_wait = t - now; - + now = rtimer_arch_now(); + clock_to_wait = t - now; + PRINTF("now %2x\r\n", TIM1_CNT); PRINTF("clock_to_wait %4x\r\n", clock_to_wait); - - if(clock_to_wait <= 0x10000){ // We must set now the Timer Compare Register. - - TIM1_CCR1 = (int16u)now + (int16u)clock_to_wait; + + if(clock_to_wait <= 0x10000) { + /* We must now set the Timer Compare Register. */ + TIM1_CCR1 = (uint16_t)now + (uint16_t)clock_to_wait; INT_TIM1FLAG = INT_TIMCC1IF; - INT_TIM1CFG |= INT_TIMCC1IF; // Compare 1 interrupt enable. - + INT_TIM1CFG |= INT_TIMCC1IF; /* Compare 1 interrupt enable. */ PRINTF("2-INT_TIM1FLAG %2x\r\n", INT_TIM1FLAG); - } - // else compare register will be set at overflow interrupt closer to the rtimer event. - + /* else compare register will be set at overflow interrupt closer to + the rtimer event. */ } +/*---------------------------------------------------------------------------*/ +/** @} */ diff --git a/cpu/stm32w108/rtimer-arch.h b/cpu/stm32w108/rtimer-arch.h index f7606cd46..cb5090617 100644 --- a/cpu/stm32w108/rtimer-arch.h +++ b/cpu/stm32w108/rtimer-arch.h @@ -1,3 +1,9 @@ +/** + * \addtogroup mb851-platform + * + * @{ + */ + /* * Copyright (c) 2010, STMicroelectronics. * All rights reserved. @@ -27,8 +33,6 @@ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * This file is part of the Contiki OS - * */ /** @@ -41,43 +45,53 @@ #ifndef __RTIMER_ARCH_H__ #define __RTIMER_ARCH_H__ +#define RTIMER_ARCH_RES_341US 0 +#define RTIMER_ARCH_RES_171US 1 +#define RTIMER_ARCH_RES_85US 2 + #include "contiki-conf.h" #include "sys/clock.h" +#ifdef RTIMER_ARCH_CONF_RESOLUTION +#define RTIMER_ARCH_RESOLUTION RTIMER_ARCH_CONF_RESOLUTION +#else /* RTIMER_ARCH_CONF_RESOLUTION */ +#define RTIMER_ARCH_RESOLUTION RTIMER_ARCH_RES_171US +#endif /* RTIMER_ARCH_CONF_RESOLUTION */ -//#define RT_RESOLUTION RES_85US -#ifdef RT_CONF_RESOLUTION -#define RT_RESOLUTION RT_CONF_RESOLUTION -#else -#define RT_RESOLUTION RES_171US -#endif +/* + * If it was possible to define a custom size for the rtimer_clock_t + * type: typedef unsigned long long rtimer_clock_t; Only 48 bit are + * used. It's enough for hundreds of years. + */ +#if RTIMER_ARCH_RESOLUTION == RTIMER_ARCH_RES_341US +/* CK_CNT = PCLK/4096 = 12 MHz/4096 = 2929.6875 Hz */ +#define RTIMER_ARCH_PRESCALER 12 +/* One tick: 341.33 us. Using this value we will delay about 9.22 sec + after a day. */ +#define RTIMER_ARCH_SECOND 2930 +#endif /* RTIMER_ARCH_RESOLUTION == RTIMER_ARCH_RES_341US */ -#define RES_341US 0 -#define RES_171US 1 -#define RES_85US 2 +#if RTIMER_ARCH_RESOLUTION == RTIMER_ARCH_RES_171US +/* CK_CNT = PCLK/2048 = 12 MHz/2048 = 5859.375 Hz */ +#define RTIMER_ARCH_PRESCALER 11 +/* One tick: 170.66 us. Using this value we will advance about 5.53 + sec after a day. */ +#define RTIMER_ARCH_SECOND 5859 +#endif /* RTIMER_ARCH_RESOLUTION == RTIMER_ARCH_RES_171US */ -// If it was possible to define a custom size for the rtimer_clock_t type: -//typedef unsigned long long rtimer_clock_t; // Only 48 bit are used. It's enough for hundreds of years. - -#if RT_RESOLUTION == RES_341US -#define RT_PRESCALER 12 // CK_CNT = PCLK/4096 = 12 MHz/4096 = 2929.6875 Hz -#define RTIMER_ARCH_SECOND 2930 // One tick: 341.33 us. Using this value we will delay about 9.22 sec after a day. -#endif /* RT_RESOLUTION == RES_341US */ - -#if RT_RESOLUTION == RES_171US -#define RT_PRESCALER 11 // CK_CNT = PCLK/2048 = 12 MHz/2048 = 5859.375 Hz -#define RTIMER_ARCH_SECOND 5859 // One tick: 170.66 us. Using this value we will advance about 5.53 sec after a day. -#endif /* RT_RESOLUTION == RES_171US */ - -#if RT_RESOLUTION == RES_85US -#define RT_PRESCALER 10 // CK_CNT = PCLK/2048 = 12 MHz/2048 = 5859.375 Hz -#define RTIMER_ARCH_SECOND 11719 // One tick: 85.33 us. Using this value we will delay about 1.84 sec after a day. -#endif /* RT_RESOLUTION == RES_85US */ +#if RTIMER_ARCH_RESOLUTION == RTIMER_ARCH_RES_85US +/* CK_CNT = PCLK/2048 = 12 MHz/2048 = 5859.375 Hz */ +#define RTIMER_ARCH__PRESCALER 10 +/* One tick: 85.33 us. Using this value we will delay about 1.84 sec + after a day. */ +#define RTIMER_ARCH_SECOND 11719 +#endif /* RTIMER_ARCH_RESOLUTION == RTIMER_ARCH_RES_85US */ rtimer_clock_t rtimer_arch_now(void); -//#define rtimer_arch_now() clock_time() void rtimer_arch_disable_irq(void); + void rtimer_arch_enable_irq(void); #endif /* __RTIMER_ARCH_H__ */ +/** @} */ diff --git a/cpu/stm32w108/sleep.h b/cpu/stm32w108/sleep.h deleted file mode 100644 index 6b87814e6..000000000 --- a/cpu/stm32w108/sleep.h +++ /dev/null @@ -1,10 +0,0 @@ - -/* Enter system in deep sleep 1 (core power domain is fully - * powered down and sleep timer is active). - * Execution is suspended for a given number of seconds. - * - * Pay attention! All system peripherals (including sensors) have - * to be reinitialized before being used again. UART, LEDs and - * real timers are automatically reinitialized. */ - -void sleep_seconds(int seconds); diff --git a/cpu/stm32w108/slip_uart1.c b/cpu/stm32w108/slip-uart1.c similarity index 94% rename from cpu/stm32w108/slip_uart1.c rename to cpu/stm32w108/slip-uart1.c index 02c06b5ec..904fd964d 100644 --- a/cpu/stm32w108/slip_uart1.c +++ b/cpu/stm32w108/slip-uart1.c @@ -1,3 +1,9 @@ +/** + * \addtogroup mb851-platform + * + * @{ + */ + /* * Copyright (c) 2010, STMicroelectronics. * All rights reserved. @@ -27,35 +33,30 @@ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * This file is part of the Contiki OS - * */ -/*---------------------------------------------------------------------------*/ + /** * \file * Machine dependent STM32W SLIP routines for UART1. * \author * Salvatore Pitrulli */ -/*---------------------------------------------------------------------------*/ #include - - #include "contiki.h" - #include "dev/slip.h" #include "dev/uart1.h" +/*--------------------------------------------------------------------------*/ void slip_arch_init(unsigned long ubr) -{ - uart1_set_input(slip_input_byte); +{ + uart1_set_input(slip_input_byte); } - +/*--------------------------------------------------------------------------*/ void slip_arch_writeb(unsigned char c) { uart1_writeb(c); } - +/** @} */ diff --git a/cpu/stm32w108/small_printf/Makefile b/cpu/stm32w108/small-printf/Makefile similarity index 82% rename from cpu/stm32w108/small_printf/Makefile rename to cpu/stm32w108/small-printf/Makefile index df004dd3a..c74672932 100644 --- a/cpu/stm32w108/small_printf/Makefile +++ b/cpu/stm32w108/small-printf/Makefile @@ -1,33 +1,20 @@ - - - CC = arm-none-eabi-gcc AR = arm-none-eabi-ar CFLAGS = -mthumb -mcpu=cortex-m3 -I "." -I "C:/Program\ Files/Raisonance/Ride/Lib/ARM/include" \ -fsigned-char -D _SMALL_PRINTF -D INTEGER_ONLY -Os -ffunction-sections -mlittle-endian AROPTS = cq - - -SOURCE_FILES = _SP_printf.c _SP_puts.c _SP_sprintf.c _SP_snprintf.c _SP_vfprintf.c - - +SOURCE_FILES = sp-printf.c sp-puts.c sp-sprintf.c sp-snprintf.c sp-vfprintf.c SOURCE_OBJS = ${patsubst %.c,%.o,$(SOURCE_FILES)} - - LIB = smallprintf_thumb2.a - - all: clean $(LIB) clean: rm -f $(LIB) - %.a: $(SOURCE_OBJS) $(AR) $(AROPTS) $@ $^ - %.o: %.c $(CC) $(CFLAGS) -c $< -o $@ diff --git a/cpu/stm32w108/small-printf/sp-printf.c b/cpu/stm32w108/small-printf/sp-printf.c new file mode 100644 index 000000000..95ab7e807 --- /dev/null +++ b/cpu/stm32w108/small-printf/sp-printf.c @@ -0,0 +1,84 @@ +/** + * \addtogroup stm32w-cpu + * + * @{ + */ + +#ifdef INTEGER_ONLY + #define _vfprintf_r _vfiprintf_r + #define _vfprintf _vfiprintf + #define vfprintf vfiprintf +#endif /* INTEGER_ONLY */ + +#include <_ansi.h> +#include + +#ifndef _SMALL_PRINTF + #include "local.h" +#endif /* _SMALL_PRINTF */ + +#ifdef _HAVE_STDC +#include +#else /* _HAVE_STDC */ +#include +#endif /* _HAVE_STDC */ + +/*--------------------------------------------------------------------------*/ +#ifndef _SMALL_PRINTF +#ifdef _HAVE_STDC +int +_printf_r (struct _reent *ptr, const char *fmt, ...) +#else /* _HAVE_STDC */ +int +_printf_r (ptr, fmt, va_alist) + struct _reent *ptr; + char *fmt; + va_dcl +#endif /* _HAVE_STDC */ +{ + int ret; + va_list ap; + + //_REENT_SMALL_CHECK_INIT(_stdout_r (ptr)); +#ifdef _HAVE_STDC + va_start (ap, fmt); +#else /* _HAVE_STDC */ + va_start (ap); +#endif /* _HAVE_STDC */ + ret = _vfprintf_r (ptr, _stdout_r (ptr), fmt, ap); + va_end (ap); + return ret; +} +#endif /* _SMALL_PRINTF */ +/*--------------------------------------------------------------------------*/ +#ifndef _REENT_ONLY +#ifdef _HAVE_STDC +int +printf (const char *fmt, ...) +#else /* _HAVE_STDC */ +int +printf (fmt, va_alist) + char *fmt; + va_dcl +#endif /* _HAVE_STDC */ +{ + int ret; + va_list ap; + + //_REENT_SMALL_CHECK_INIT(_stdout_r (_REENT)); +#ifdef _HAVE_STDC + va_start (ap, fmt); +#else /* _HAVE_STDC */ + va_start (ap); +#endif /* _HAVE_STDC */ + +#ifndef _SMALL_PRINTF + ret = vfprintf (_stdout_r (_REENT), fmt, ap); +#else /* _SMALL_PRINTF */ + ret = vfprintf (0, fmt, ap); +#endif /* _SMALL_PRINTF */ + va_end (ap); + return ret; +} +#endif /* _REENT_ONLY */ +/** @} */ diff --git a/cpu/stm32w108/small-printf/sp-puts.c b/cpu/stm32w108/small-printf/sp-puts.c new file mode 100644 index 000000000..fb377602f --- /dev/null +++ b/cpu/stm32w108/small-printf/sp-puts.c @@ -0,0 +1,39 @@ +/** + * \addtogroup stm32w-cpu + * + * @{ + */ + +#include +#include + +void __io_putchar (char); + +/*--------------------------------------------------------------------------*/ +void +_SMALL_PRINTF_puts(const char *ptr, int len, FILE *fp) +{ + /* No file => sprintf */ + if (fp && (fp->_file == -1) && (fp->_flags & (__SWR | __SSTR))) { + char *str = fp->_p; + for (; len ; len--) { + *str ++ = *ptr++; + } + fp->_p = str; + } else { + /* file => printf */ + for (; len ; len--) { + __io_putchar (*ptr++); + } + } +} +/*--------------------------------------------------------------------------*/ +int +puts(const char *str) +{ + int len = strlen (str); + _SMALL_PRINTF_puts(str, len, 0) ; + __io_putchar ('\n'); + return len; +} +/** @} */ diff --git a/cpu/stm32w108/small_printf/_SP_snprintf.c b/cpu/stm32w108/small-printf/sp-snprintf.c similarity index 94% rename from cpu/stm32w108/small_printf/_SP_snprintf.c rename to cpu/stm32w108/small-printf/sp-snprintf.c index 2dfcd8599..9b08cd380 100644 --- a/cpu/stm32w108/small_printf/_SP_snprintf.c +++ b/cpu/stm32w108/small-printf/sp-snprintf.c @@ -1,3 +1,9 @@ +/** + * \addtogroup stm32w-cpu + * + * @{ + */ + /* * Copyright (c) 1990 The Regents of the University of California. * All rights reserved. @@ -14,8 +20,9 @@ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. */ -/* doc in _SP_sprintf.c */ -/* This code created by modifying _SP_sprintf.c so copyright inherited. */ + +/* doc in sp-sprintf.c */ +/* This code created by modifying sp-sprintf.c so copyright inherited. */ #include #ifdef _HAVE_STDC @@ -121,4 +128,4 @@ snprintf (str, size, fmt, va_alist) } #endif - +/** @} */ diff --git a/cpu/stm32w108/small_printf/_SP_sprintf.c b/cpu/stm32w108/small-printf/sp-sprintf.c similarity index 99% rename from cpu/stm32w108/small_printf/_SP_sprintf.c rename to cpu/stm32w108/small-printf/sp-sprintf.c index b64048c31..65d65fa77 100644 --- a/cpu/stm32w108/small_printf/_SP_sprintf.c +++ b/cpu/stm32w108/small-printf/sp-sprintf.c @@ -1,3 +1,9 @@ +/** + * \addtogroup stm32w-cpu + * + * @{ + */ + /* * Copyright (c) 1990 The Regents of the University of California. * All rights reserved. @@ -386,4 +392,4 @@ sprintf (str, fmt, va_alist) } #endif - +/** @} */ diff --git a/cpu/stm32w108/small_printf/_SP_vfprintf.c b/cpu/stm32w108/small-printf/sp-vfprintf.c similarity index 99% rename from cpu/stm32w108/small_printf/_SP_vfprintf.c rename to cpu/stm32w108/small-printf/sp-vfprintf.c index 80ad4bab4..70b78b6ff 100644 --- a/cpu/stm32w108/small_printf/_SP_vfprintf.c +++ b/cpu/stm32w108/small-printf/sp-vfprintf.c @@ -1,3 +1,9 @@ +/** + * \addtogroup stm32w-cpu + * + * @{ + */ + /* FUNCTION <>, <>, <>---format argument list @@ -1765,10 +1771,14 @@ get_arg (struct _reent *data, int n, char *fmt, va_list *ap, } } - /* alter the global numargs value and keep a reference to the last bit of the fmt - string we processed here because the caller will continue processing where we started */ + /* + * alter the global numargs value and keep a reference to the last bit of the + * fmt string we processed here because the caller will continue processing + * where we started + */ *numargs_p = numargs; *last_fmt = fmt; return &args[n]; } #endif /* !_NO_POS_ARGS */ +/** @} */ diff --git a/cpu/stm32w108/small_printf/vfieeefp.h b/cpu/stm32w108/small-printf/vfieeefp.h similarity index 91% rename from cpu/stm32w108/small_printf/vfieeefp.h rename to cpu/stm32w108/small-printf/vfieeefp.h index 1b240fcde..ead4067f4 100644 --- a/cpu/stm32w108/small_printf/vfieeefp.h +++ b/cpu/stm32w108/small-printf/vfieeefp.h @@ -1,3 +1,9 @@ +/** + * \addtogroup stm32w-cpu + * + * @{ + */ + /**************************************************************** * * The author of this software is David M. Gay. @@ -26,8 +32,13 @@ dmg@research.att.com or research!dmg */ -/* This header file is a modification of mprec.h that only contains floating - point union code. */ +#ifndef __VFIEEEFP_H__ +#define __VFIEEEFP_H__ + +/* + * This header file is a modification of mprec.h that only contains floating + * point union code. + */ #include #include @@ -58,11 +69,12 @@ Exactly one of IEEE_8087, IEEE_MC68k, VAX, or IBM should be defined. #endif #ifdef WANT_IO_LONG_DBL -/* If we are going to examine or modify specific bits in a long double using - the lword0 or lwordx macros, then we must wrap the long double inside - a union. This is necessary to avoid undefined behavior according to - the ANSI C spec. */ - +/* + * If we are going to examine or modify specific bits in a long double using + * the lword0 or lwordx macros, then we must wrap the long double inside + * a union. This is necessary to avoid undefined behavior according to + * the ANSI C spec. + */ #ifdef IEEE_8087 #if LDBL_MANT_DIG == 24 struct ldieee @@ -136,10 +148,12 @@ struct ldieee #endif /* !IEEE_8087 */ #endif /* WANT_IO_LONG_DBL */ -/* If we are going to examine or modify specific bits in a double using - the word0 and/or word1 macros, then we must wrap the double inside - a union. This is necessary to avoid undefined behavior according to - the ANSI C spec. */ +/* + * If we are going to examine or modify specific bits in a double using + * the word0 and/or word1 macros, then we must wrap the double inside + * a union. This is necessary to avoid undefined behavior according to + * the ANSI C spec. + */ union double_union { double d; @@ -281,4 +295,5 @@ union double_union #endif #endif - +#endif /* __VFIEEEFP_H__ */ +/** @} */ diff --git a/cpu/stm32w108/small_printf/_SP_printf.c b/cpu/stm32w108/small_printf/_SP_printf.c deleted file mode 100644 index 65386b2af..000000000 --- a/cpu/stm32w108/small_printf/_SP_printf.c +++ /dev/null @@ -1,78 +0,0 @@ -#ifdef INTEGER_ONLY - #define _vfprintf_r _vfiprintf_r - #define _vfprintf _vfiprintf - #define vfprintf vfiprintf -#endif - -#include <_ansi.h> -#include - -#ifndef _SMALL_PRINTF - #include "local.h" -#endif - -#ifdef _HAVE_STDC -#include -#else -#include -#endif - -#ifndef _SMALL_PRINTF - - #ifdef _HAVE_STDC - int - _printf_r (struct _reent *ptr, const char *fmt, ...) - #else - int - _printf_r (ptr, fmt, va_alist) - struct _reent *ptr; - char *fmt; - va_dcl - #endif - { - int ret; - va_list ap; - - //_REENT_SMALL_CHECK_INIT(_stdout_r (ptr)); - #ifdef _HAVE_STDC - va_start (ap, fmt); - #else - va_start (ap); - #endif - ret = _vfprintf_r (ptr, _stdout_r (ptr), fmt, ap); - va_end (ap); - return ret; - } -#endif - -#ifndef _REENT_ONLY - -#ifdef _HAVE_STDC -int -printf (const char *fmt, ...) -#else -int -printf (fmt, va_alist) - char *fmt; - va_dcl -#endif -{ - int ret; - va_list ap; - - //_REENT_SMALL_CHECK_INIT(_stdout_r (_REENT)); -#ifdef _HAVE_STDC - va_start (ap, fmt); -#else - va_start (ap); -#endif -#ifndef _SMALL_PRINTF - ret = vfprintf (_stdout_r (_REENT), fmt, ap); -#else - ret = vfprintf (0, fmt, ap); -#endif - va_end (ap); - return ret; -} - -#endif /* ! _REENT_ONLY */ diff --git a/cpu/stm32w108/small_printf/_SP_puts.c b/cpu/stm32w108/small_printf/_SP_puts.c deleted file mode 100644 index 0e6a719f9..000000000 --- a/cpu/stm32w108/small_printf/_SP_puts.c +++ /dev/null @@ -1,34 +0,0 @@ -#include -#include - - -void __io_putchar ( char ); - -void _SMALL_PRINTF_puts(const char *ptr, int len, FILE *fp) - { - if ( fp && ( fp->_file == -1 ) /* No file => sprintf */ - && (fp->_flags & (__SWR | __SSTR) ) ) - { - char *str = fp->_p; - - for ( ; len ; len-- ) - { - *str ++ = *ptr++; - } - fp->_p = str; - } - else /* file => printf */ - { - for ( ; len ; len-- ) - __io_putchar ( *ptr++ ); - } - } - -int puts(const char *str) - { - int len = strlen ( str ); - _SMALL_PRINTF_puts(str, len, 0) ; - __io_putchar ( '\n' ); - return len; - } - diff --git a/cpu/stm32w108/uip_arch.c b/cpu/stm32w108/uip-arch.c similarity index 76% rename from cpu/stm32w108/uip_arch.c rename to cpu/stm32w108/uip-arch.c index 0ab4a500c..4646dc919 100644 --- a/cpu/stm32w108/uip_arch.c +++ b/cpu/stm32w108/uip-arch.c @@ -1,3 +1,9 @@ +/** + * \addtogroup mb851-platform + * + * @{ + */ + /* * Copyright (c) 2010, STMicroelectronics. * All rights reserved. @@ -27,40 +33,34 @@ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * This file is part of the uIP TCP/IP stack. - * */ -/*---------------------------------------------------------------------------*/ + /** * \file -* uip_arch.c +* uip-arch.c * \author * Salvatore Pitrulli */ -/*---------------------------------------------------------------------------*/ - - - #include "net/uip.h" #include "net/uip_arch.h" -/*-----------------------------------------------------------------------------------*/ #if UIP_TCP void -uip_add32(uint8_t *op32, uint16_t op16) +uip_add32(uint8_t * op32, uint16_t op16) { uint32_t op32_align, uip_acc32_align; - op32_align = ((uint32_t)op32[0])<<24 | ((uint32_t)op32[1])<<16 | ((uint16_t)op32[2])<<8 | op32[3]; - + op32_align = + ((uint32_t) op32[0]) << 24 | ((uint32_t) op32[1]) << 16 | + ((uint16_t) op32[2]) << 8 | op32[3]; + uip_acc32_align = op32_align + op16; - uip_acc32[3] = uip_acc32_align; - uip_acc32[2] = uip_acc32_align>>8; - uip_acc32[1] = uip_acc32_align>>16; - uip_acc32[0] = uip_acc32_align>>24; - + uip_acc32[2] = uip_acc32_align >> 8; + uip_acc32[1] = uip_acc32_align >> 16; + uip_acc32[0] = uip_acc32_align >> 24; } #endif /*-----------------------------------------------------------------------------------*/ +/** @} */ diff --git a/cpu/stm32w108/watchdog.c b/cpu/stm32w108/watchdog.c index 5a29472e7..6591bfaa2 100644 --- a/cpu/stm32w108/watchdog.c +++ b/cpu/stm32w108/watchdog.c @@ -1,3 +1,9 @@ +/** + * \addtogroup mb851-platform + * + * @{ + */ + /* * Copyright (c) 2010, STMicroelectronics. * All rights reserved. @@ -27,27 +33,21 @@ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * This file is part of the Contiki OS - * */ -/*---------------------------------------------------------------------------*/ + /** * \file * Watchdog * \author * Salvatore Pitrulli */ -/*---------------------------------------------------------------------------*/ #include - #include "dev/watchdog.h" - #include PLATFORM_HEADER #include "hal/error.h" #include "hal/hal.h" - /*---------------------------------------------------------------------------*/ void watchdog_init(void) @@ -58,16 +58,17 @@ watchdog_init(void) void watchdog_start(void) { - /* We setup the watchdog to reset the device after 2.048 seconds, - unless watchdog_periodic() is called. */ + /* + * We setup the watchdog to reset the device after 2.048 seconds, + * unless watchdog_periodic() is called. + */ halInternalEnableWatchDog(); } /*---------------------------------------------------------------------------*/ void watchdog_periodic(void) { - /* This function is called periodically to restart the watchdog - timer. */ + /* This function is called periodically to restart the watchdog timer. */ halResetWatchdog(); } /*---------------------------------------------------------------------------*/ @@ -83,3 +84,4 @@ watchdog_reboot(void) halReboot(); } /*---------------------------------------------------------------------------*/ +/** @} */ diff --git a/platform/mb851/Makefile.mb851 b/platform/mb851/Makefile.mb851 index 2c9c14da3..40971e8ab 100644 --- a/platform/mb851/Makefile.mb851 +++ b/platform/mb851/Makefile.mb851 @@ -1,6 +1,3 @@ -# $Id: Makefile.mb851,v 1.2 2010/12/15 11:18:09 salvopitru Exp $ - - ARCH= irq.c sensors.c acc-sensor.c button-sensor.c temperature-sensor.c mems.c CONTIKI_TARGET_DIRS = . dev diff --git a/platform/mb851/apps/shell-sensors.c b/platform/mb851/apps/shell-sensors.c index 1f822cbfd..a0d223838 100644 --- a/platform/mb851/apps/shell-sensors.c +++ b/platform/mb851/apps/shell-sensors.c @@ -1,3 +1,8 @@ +/** + * \addtogroup mb851-platform + * + * @{ + */ /* * Copyright (c) 2010, STMicroelectronics. * All rights reserved. @@ -29,7 +34,6 @@ * This file is part of the Contiki operating system. * */ - /** * \file * Shell function for temp and acc sensors. @@ -49,40 +53,33 @@ /*---------------------------------------------------------------------------*/ PROCESS(shell_sensors_process, "sensors"); SHELL_COMMAND(sensors_command, - "sensors", - "sensors {temp|acc}: get sensor value", - &shell_sensors_process); + "sensors", + "sensors {temp|acc}: get sensor value", &shell_sensors_process); /*---------------------------------------------------------------------------*/ PROCESS_THREAD(shell_sensors_process, ev, data) { - char str_buf[22]; - - PROCESS_BEGIN(); + PROCESS_BEGIN(); if(data == NULL) { shell_output_str(&sensors_command, - "sensors {temp|acc}: a sensor must be specified", ""); + "sensors {temp|acc}: a sensor must be specified", ""); PROCESS_EXIT(); } - - if(strcmp(data,"temp")==0) { - + + if(strcmp(data, "temp") == 0) { unsigned int temp = temperature_sensor.value(0); - - snprintf(str_buf,sizeof(str_buf),"%d.%d degC",temp/10,temp-(temp/10)*10); - + snprintf(str_buf, sizeof(str_buf), "%d.%d degC", temp / 10, + temp - (temp / 10) * 10); shell_output_str(&sensors_command, "Temp: ", str_buf); - + } else { + if(strcmp(data, "acc") == 0) { + snprintf(str_buf, sizeof(str_buf), "%d,%d,%d) mg", + acc_sensor.value(ACC_X_AXIS), acc_sensor.value(ACC_Y_AXIS), + acc_sensor.value(ACC_Z_AXIS)); + shell_output_str(&sensors_command, "(X,Y,Z): (", str_buf); + } } - else if (strcmp(data,"acc")==0) { - - snprintf(str_buf,sizeof(str_buf),"%d,%d,%d) mg",acc_sensor.value(ACC_X_AXIS),acc_sensor.value(ACC_Y_AXIS),acc_sensor.value(ACC_Z_AXIS)); - - shell_output_str(&sensors_command, "(X,Y,Z): (", str_buf); - - } - PROCESS_END(); } /*---------------------------------------------------------------------------*/ @@ -90,7 +87,7 @@ void shell_sensors_init(void) { SENSORS_ACTIVATE(acc_sensor); - shell_register_command(&sensors_command); } /*---------------------------------------------------------------------------*/ +/** @} */ diff --git a/platform/mb851/apps/shell-sensors.h b/platform/mb851/apps/shell-sensors.h index 4c4fc8fff..08edd2bfb 100644 --- a/platform/mb851/apps/shell-sensors.h +++ b/platform/mb851/apps/shell-sensors.h @@ -1,3 +1,8 @@ +/** + * \addtogroup mb851-platform + * + * @{ + */ /* * Copyright (c) 2010, STMicroelectronics. * All rights reserved. @@ -29,7 +34,6 @@ * This file is part of the Contiki operating system. * */ - /** * \file * Header file for Contik shell sensors command. @@ -45,3 +49,4 @@ void shell_sensors_init(void); #endif /* __SHELL_SENSORS_H__ */ +/** @} */ diff --git a/platform/mb851/board-mb851.c b/platform/mb851/board-mb851.c index 138c32e6a..d08640fc9 100644 --- a/platform/mb851/board-mb851.c +++ b/platform/mb851/board-mb851.c @@ -1,3 +1,40 @@ +/** + * \addtogroup mb851-platform + * + * @{ + */ + +/* + * Copyright (c) 2010, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + #include PLATFORM_HEADER #include BOARD_HEADER #include "hal/micro/micro-common.h" @@ -8,117 +45,130 @@ #include "dev/acc-sensor.h" #include "dev/leds.h" -void halBoardInit(void) -{ - - return; -} - +/*---------------------------------------------------------------------------*/ static uint8_t sensors_status; #define BUTTON_STATUS_ACTIVE (1 << 0) #define TEMP_STATUS_ACTIVE (1 << 1) #define ACC_STATUS_ACTIVE (1 << 2) - - -void halBoardPowerDown(void) +/*---------------------------------------------------------------------------*/ +/** + * \brief Init board (currently does nothing) + */ +void +board_init(void) { - /* Set everything to input value except LEDs */ - GPIO_PACFGL = (GPIOCFG_IN < * Simon Duquennoy */ -/*---------------------------------------------------------------------------*/ #ifndef __CONTIKI_CONF_H__ #define __CONTIKI_CONF_H__ @@ -52,9 +55,9 @@ /* Radio and 802.15.4 params */ /* 802.15.4 radio channel */ -#define RF_CHANNEL 16 +#define RF_CHANNEL 26 /* 802.15.4 PAN ID */ -#define IEEE802154_CONF_PANID 0x1234 +#define IEEE802154_CONF_PANID 0xabcd /* Use EID 64, enable hardware autoack and address filtering */ #define RIMEADDR_CONF_SIZE 8 #define UIP_CONF_LL_802154 1 @@ -70,7 +73,7 @@ /* TX routine does automatic cca and optional backoff */ #define RDC_CONF_HARDWARE_CSMA 0 /* RDC debug with LED */ -#define RDC_CONF_DEBUG_LED 1 +#define RDC_CONF_DEBUG_LED 0 /* Channel check rate (per second) */ #define NETSTACK_CONF_RDC_CHANNEL_CHECK_RATE 8 /* Use ACK for optimization (LPP, XMAC) */ @@ -83,9 +86,10 @@ #define NETSTACK_CONF_RADIO stm32w_radio_driver /* ContikiMAC config */ -#define CONTIKIMAC_CONF_COMPOWER 1 +#define CONTIKIMAC_CONF_COMPOWER 0 #define CONTIKIMAC_CONF_BROADCAST_RATE_LIMIT 0 #define CONTIKIMAC_CONF_ANNOUNCEMENTS 0 +#define CONTIKIMAC_CONF_WITH_PHASE_OPTIMIZATION 0 /* CXMAC config */ #define CXMAC_CONF_ANNOUNCEMENTS 0 @@ -100,7 +104,7 @@ #define QUEUEBUF_CONF_NUM 2 #define QUEUEBUF_CONF_REF_NUM 0 #define UIP_CONF_DS6_NBR_NBU 4 -#define UIP_CONF_DS6_ROUTE_NBU 4 +#define UIP_CONF_MAX_ROUTES 4 #define RPL_CONF_MAX_PARENTS_PER_DAG 4 #define RPL_CONF_MAX_INSTANCES 1 #define RPL_CONF_MAX_DAG_PER_INSTANCE 1 @@ -109,31 +113,34 @@ #if WITH_UIP6 /* Network setup for IPv6 */ -#define NETSTACK_CONF_NETWORK sicslowpan_driver +#define NETSTACK_CONF_NETWORK sicslowpan_driver -/* Specify a minimum packet size for 6lowpan compression to be - enabled. This is needed for ContikiMAC, which needs packets to be - larger than a specified size, if no ContikiMAC header should be - used. */ +/* + * Specify a minimum packet size for 6lowpan compression to be + * enabled. This is needed for ContikiMAC, which needs packets to be + * larger than a specified size, if no ContikiMAC header should + * be used. + */ #define SICSLOWPAN_CONF_COMPRESSION_THRESHOLD 63 #define CONTIKIMAC_CONF_WITH_CONTIKIMAC_HEADER 0 -#define UIP_CONF_ROUTER 1 -#define UIP_CONF_IPV6_RPL 1 -#define UIP_CONF_ND6_SEND_RA 0 +#define UIP_CONF_ROUTER 1 +#define UIP_CONF_IPV6_RPL 1 +#define UIP_CONF_ND6_SEND_RA 0 -#define UIP_CONF_IPV6 1 -#define UIP_CONF_IPV6_QUEUE_PKT 0 -#define UIP_CONF_IPV6_CHECKS 1 -#define UIP_CONF_IPV6_REASSEMBLY 0 -#define UIP_CONF_ND6_MAX_PREFIXES 2 -#define UIP_CONF_ND6_MAX_NEIGHBORS 2 -#define UIP_CONF_ND6_MAX_DEFROUTERS 1 -#define UIP_CONF_IP_FORWARD 0 -#define UIP_CONF_BUFFER_SIZE 140 -#define UIP_CONF_MAX_CONNECTIONS 4 -#define UIP_CONF_MAX_LISTENPORTS 8 -#define UIP_CONF_UDP_CONNS 4 +#define UIP_CONF_BUFFER_SIZE 140 + +#define UIP_CONF_IPV6 1 +#define UIP_CONF_IPV6_QUEUE_PKT 0 +#define UIP_CONF_IPV6_CHECKS 1 +#define UIP_CONF_IPV6_REASSEMBLY 0 +#define UIP_CONF_ND6_MAX_PREFIXES 2 +#define UIP_CONF_ND6_MAX_NEIGHBORS 2 +#define UIP_CONF_ND6_MAX_DEFROUTERS 1 +#define UIP_CONF_IP_FORWARD 0 +#define UIP_CONF_MAX_CONNECTIONS 4 +#define UIP_CONF_MAX_LISTENPORTS 8 +#define UIP_CONF_UDP_CONNS 4 #define SICSLOWPAN_CONF_COMPRESSION SICSLOWPAN_COMPRESSION_HC06 #ifndef SICSLOWPAN_CONF_FRAG @@ -149,7 +156,7 @@ #else /* WITH_UIP6 */ /* Network setup for non-IPv6 (rime). */ -#define NETSTACK_CONF_NETWORK rime_driver +#define NETSTACK_CONF_NETWORK rime_driver #endif /* WITH_UIP6 */ @@ -157,4 +164,9 @@ #include PROJECT_CONF_H #endif /* PROJECT_CONF_H */ +#ifdef PLATFORM_CONF +#include PLATFORM_CONF +#endif /* PLATFORM_CONF */ + #endif /* __CONTIKI_CONF_H__ */ +/** @} */ diff --git a/platform/mb851/contiki-init-net.c b/platform/mb851/contiki-init-net.c index 76ad078fe..ef2e8a739 100644 --- a/platform/mb851/contiki-init-net.c +++ b/platform/mb851/contiki-init-net.c @@ -1,3 +1,9 @@ +/** + * \addtogroup mb851-platform + * + * @{ + */ + /* * Copyright (c) 2010, STMicroelectronics. * All rights reserved. @@ -27,17 +33,14 @@ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * This file is part of the Contiki OS - * */ -/*---------------------------------------------------------------------------*/ + /** * \file * Functions for net initialization. * \author * Salvatore Pitrulli */ -/*---------------------------------------------------------------------------*/ #include "contiki-net.h" @@ -54,82 +57,80 @@ #define PRINT6ADDR(addr) #define PRINTLLADDR(addr) #endif - -void print_address(uip_ds6_addr_t *lladdr) +/*--------------------------------------------------------------------------*/ +void +print_address(uip_ds6_addr_t * lladdr) { int i; - + for(i = 0; i < 7; ++i) { - printf("%02x%02x:", lladdr->ipaddr.u8[i * 2], lladdr->ipaddr.u8[i * 2 + 1]); + printf("%02x%02x:", lladdr->ipaddr.u8[i * 2], + lladdr->ipaddr.u8[i * 2 + 1]); } printf("%02x%02x", lladdr->ipaddr.u8[14], lladdr->ipaddr.u8[15]); } - /*---------------------------------------------------------------------------*/ -void print_addresses(void) +void +print_addresses(void) { uip_ds6_addr_t *lladdr; - - printf("link-local IPv6 address: "); - + lladdr = uip_ds6_get_link_local(-1); - if(lladdr != NULL){ - print_address(lladdr); + if(lladdr != NULL) { + print_address(lladdr); printf("\r\n"); - } - else + } else { printf("None\r\n"); - + } + printf("global IPv6 address: "); - + lladdr = uip_ds6_get_global(-1); - if(lladdr != NULL){ - print_address(lladdr); + if(lladdr != NULL) { + print_address(lladdr); printf("\r\n"); - } - else + } else { printf("None\r\n"); - + } } - +/*--------------------------------------------------------------------------*/ #if FIXED_NET_ADDRESS - #include "net/rpl/rpl.h" - - -void set_net_address(void) +void +set_net_address(void) { uip_ipaddr_t ipaddr; + #if RPL_BORDER_ROUTER rpl_dag_t *dag; #endif - uip_ip6addr(&ipaddr, NET_ADDR_A, NET_ADDR_B, NET_ADDR_C, NET_ADDR_D, 0, 0, 0, 0); + uip_ip6addr(&ipaddr, NET_ADDR_A, NET_ADDR_B, NET_ADDR_C, NET_ADDR_D, 0, 0, + 0, 0); uip_ds6_set_addr_iid(&ipaddr, &uip_lladdr); - uip_ds6_addr_add(&ipaddr, 0, ADDR_TENTATIVE); + uip_ds6_addr_add(&ipaddr, 0, ADDR_TENTATIVE); + + + /* #if !UIP_CONF_ROUTER */ + /* uip_ds6_prefix_add(&ipaddr, 64, 0); For on-link determination. */ + /* #else */ + /* uip_ds6_prefix_add(&ipaddr, 64, 0, 0, 600, 600); */ + /* #endif */ - -//#if !UIP_CONF_ROUTER -// uip_ds6_prefix_add(&ipaddr, 64, 0); // For on-link determination. -//#else -// uip_ds6_prefix_add(&ipaddr, 64, 0, 0, 600, 600); -//#endif - print_addresses(); - + #if RPL_BORDER_ROUTER - dag = rpl_set_root(RPL_DEFAULT_INSTANCE,&ipaddr); + dag = rpl_set_root(RPL_DEFAULT_INSTANCE, &ipaddr); if(dag != NULL) { PRINTF("This node is setted as root of a DAG.\r\n"); - } - else { + } else { PRINTF("Error while setting this node as root of a DAG.\r\n"); } #endif - + } #endif /* FIXED_GLOBAL_ADDRESS */ - - +/*--------------------------------------------------------------------------*/ #endif /* UIP_CONF_IPV6 */ +/** @} */ diff --git a/platform/mb851/contiki-init-net.h b/platform/mb851/contiki-init-net.h index 10abd828e..9f47375ca 100644 --- a/platform/mb851/contiki-init-net.h +++ b/platform/mb851/contiki-init-net.h @@ -1,6 +1,44 @@ +/** + * \addtogroup mb851-platform + * + * @{ + */ + +/* + * Copyright (c) 2010, STMicroelectronics. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * 3. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + #ifndef __CONTIKI_INIT_NET_H__ #define __CONTIKI_INIT_NET_H__ void print_address(uip_ds6_addr_t *lladdr); -#endif /* __CONTIKI_INIT_NET_H__ */ \ No newline at end of file +#endif /* __CONTIKI_INIT_NET_H__ */ +/** @} */ diff --git a/platform/mb851/contiki-main.c b/platform/mb851/contiki-main.c index 540de2719..9a093263b 100644 --- a/platform/mb851/contiki-main.c +++ b/platform/mb851/contiki-main.c @@ -1,3 +1,9 @@ +/** + * \addtogroup mb851-platform + * + * @{ + */ + /* * Copyright (c) 2010, STMicroelectronics. * All rights reserved. @@ -27,10 +33,8 @@ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * This file is part of the Contiki OS - * */ -/*---------------------------------------------------------------------------*/ + /** * \file * Contiki main file. @@ -38,20 +42,14 @@ * Salvatore Pitrulli * Chi-Anh La */ -/*---------------------------------------------------------------------------*/ - #include PLATFORM_HEADER #include "hal/error.h" #include "hal/hal.h" #include BOARD_HEADER #include "micro/adc.h" - #include - - #include "contiki.h" - #include "dev/watchdog.h" #include "dev/leds.h" #include "dev/button-sensor.h" @@ -95,8 +93,22 @@ SENSORS(&button_sensor, &temperature_sensor, &acc_sensor); /* The default CCA threshold is set to -77, which is the same as the default setting on the TI CC2420. */ -#define DEFAULT_RADIO_CCA_THRESHOLD -77 +#define DEFAULT_RADIO_CCA_THRESHOLD (-77) +/*---------------------------------------------------------------------------*/ +static void +print_processes(struct process * const processes[]) +{ +#if !PROCESS_CONF_NO_PROCESS_NAMES + /* const struct process * const * p = processes;*/ + printf("Starting"); + while(*processes != NULL) { + printf(" '%s'", (*processes)->name); + processes++; + } + printf("\n"); +#endif /* !PROCESS_CONF_NO_PROCESS_NAMES */ +} /*---------------------------------------------------------------------------*/ static void set_rime_addr(void) @@ -106,9 +118,9 @@ set_rime_addr(void) uint8_t u8[8]; } eui64; - int8u *stm32w_eui64 = ST_RadioGetEui64(); + uint8_t *stm32w_eui64 = ST_RadioGetEui64(); { - int8u c; + uint8_t c; /* Copy the EUI-64 to lladdr converting from Little-Endian to Big-Endian. */ for(c = 0; c < 8; c++) { @@ -121,9 +133,9 @@ set_rime_addr(void) #endif #if UIP_CONF_IPV6 - rimeaddr_set_node_addr((rimeaddr_t *)&eui64); + rimeaddr_set_node_addr((rimeaddr_t *) &eui64); #else - rimeaddr_set_node_addr((rimeaddr_t *)&eui64.u8[8 - RIMEADDR_SIZE]); + rimeaddr_set_node_addr((rimeaddr_t *) &eui64.u8[8 - RIMEADDR_SIZE]); #endif printf("Rime started with address "); @@ -136,16 +148,14 @@ set_rime_addr(void) int main(void) { - /* * Initalize hardware. */ halInit(); clock_init(); - uart1_init(115200); - /* Led initialization */ + /* LED initialization */ leds_init(); INTERRUPTS_ON(); @@ -157,7 +167,6 @@ main(void) /* * Initialize Contiki and our processes. */ - process_init(); #if WITH_SERIAL_LINE_INPUT @@ -177,10 +186,10 @@ main(void) printf("%s %s, channel check rate %lu Hz\n", NETSTACK_MAC.name, NETSTACK_RDC.name, - CLOCK_SECOND / (NETSTACK_RDC.channel_check_interval() == 0 ? 1: - NETSTACK_RDC.channel_check_interval())); + CLOCK_SECOND / (NETSTACK_RDC.channel_check_interval() == 0 ? 1 : + NETSTACK_RDC.channel_check_interval())); printf("802.15.4 PAN ID 0x%x, EUI-%d:", - IEEE802154_CONF_PANID, UIP_CONF_LL_802154?64:16); + IEEE802154_CONF_PANID, UIP_CONF_LL_802154 ? 64 : 16); uip_debug_lladdr_print(&rimeaddr_node_addr); printf(", radio channel %u\n", RF_CHANNEL); @@ -198,12 +207,15 @@ main(void) defined in this file. */ ST_RadioSetEdCcaThreshold(DEFAULT_RADIO_CCA_THRESHOLD); + print_processes(autostart_processes); autostart_start(autostart_processes); #if UIP_CONF_IPV6 printf("Tentative link-local IPv6 address "); { uip_ds6_addr_t *lladdr; + int i; + lladdr = uip_ds6_get_link_local(-1); for(i = 0; i < 7; ++i) { printf("%02x%02x:", lladdr->ipaddr.u8[i * 2], @@ -215,24 +227,23 @@ main(void) if(!UIP_CONF_IPV6_RPL) { uip_ipaddr_t ipaddr; + int i; + uip_ip6addr(&ipaddr, 0xaaaa, 0, 0, 0, 0, 0, 0, 0); uip_ds6_set_addr_iid(&ipaddr, &uip_lladdr); uip_ds6_addr_add(&ipaddr, 0, ADDR_TENTATIVE); printf("Tentative global IPv6 address "); for(i = 0; i < 7; ++i) { - printf("%02x%02x:", - ipaddr.u8[i * 2], ipaddr.u8[i * 2 + 1]); + printf("%02x%02x:", ipaddr.u8[i * 2], ipaddr.u8[i * 2 + 1]); } - printf("%02x%02x\n", - ipaddr.u8[7 * 2], ipaddr.u8[7 * 2 + 1]); + printf("%02x%02x\n", ipaddr.u8[7 * 2], ipaddr.u8[7 * 2 + 1]); } #endif /* UIP_CONF_IPV6 */ watchdog_start(); while(1) { - int r; do { @@ -241,74 +252,81 @@ main(void) r = process_run(); } while(r > 0); - - ENERGEST_OFF(ENERGEST_TYPE_CPU); /* watchdog_stop(); */ ENERGEST_ON(ENERGEST_TYPE_LPM); /* Go to idle mode. */ - halSleepWithOptions(SLEEPMODE_IDLE,0); + halSleepWithOptions(SLEEPMODE_IDLE, 0); /* We are awake. */ /* watchdog_start(); */ ENERGEST_OFF(ENERGEST_TYPE_LPM); ENERGEST_ON(ENERGEST_TYPE_CPU); - } - } +/*---------------------------------------------------------------------------*/ - - -/*int8u errcode __attribute__(( section(".noinit") )); - -void halBaseBandIsr(){ - +#if 0 +uint8_t errcode __attribute__(( section(".noinit") )); +/*--------------------------------------------------------------------------*/ +void +halBaseBandIsr(void) +{ errcode = 1; leds_on(LEDS_RED); } - -void BusFault_Handler(){ - - errcode = 2; - leds_on(LEDS_RED); -} - -void halDebugIsr(){ - - errcode = 3; - leds_on(LEDS_RED); -} - -void DebugMon_Handler(){ - - errcode = 4; - //leds_on(LEDS_RED); -} - -void HardFault_Handler(){ - - errcode = 5; - //leds_on(LEDS_RED); - //halReboot(); -} - -void MemManage_Handler(){ - - errcode = 6; - //leds_on(LEDS_RED); - //halReboot(); -} - -void UsageFault_Handler(){ - - errcode = 7; - //leds_on(LEDS_RED); - //halReboot(); -} - -void Default_Handler() +/*--------------------------------------------------------------------------*/ +void +BusFault_Handler(void) { - //errcode = 8; + errcode = 2; + leds_on(LEDS_RED); +} +/*--------------------------------------------------------------------------*/ +void +halDebugIsr(void) +{ + errcode = 3; + leds_on(LEDS_RED); +} +/*--------------------------------------------------------------------------*/ +void +DebugMon_Handler(void) +{ + errcode = 4; + /* leds_on(LEDS_RED); */ +} +/*--------------------------------------------------------------------------*/ +void +HardFault_Handler(void) +{ + errcode = 5; + /* leds_on(LEDS_RED); */ + /* halReboot(); */ +} +/*--------------------------------------------------------------------------*/ +void +MemManage_Handler(void) +{ + errcode = 6; + /* leds_on(LEDS_RED); */ + /* halReboot(); */ +} +/*--------------------------------------------------------------------------*/ +void +UsageFault_Handler(void) +{ + errcode = 7; + /* leds_on(LEDS_RED); */ + /* halReboot(); */ +} +/*--------------------------------------------------------------------------*/ +void +Default_Handler() +{ + /* errcode = 8; */ leds_on(LEDS_RED); halReboot(); -}*/ +} +/*--------------------------------------------------------------------------*/ +#endif +/** @} */ diff --git a/platform/mb851/dev/acc-sensor.c b/platform/mb851/dev/acc-sensor.c index 387ae3a12..d10dd52f6 100644 --- a/platform/mb851/dev/acc-sensor.c +++ b/platform/mb851/dev/acc-sensor.c @@ -1,3 +1,8 @@ +/** + * \addtogroup mb851-platform + * + * @{ + */ /* * Copyright (c) 2010, STMicroelectronics. * All rights reserved. @@ -27,18 +32,13 @@ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * This file is part of the Contiki OS - * */ -/*---------------------------------------------------------------------------*/ /** * \file -* Accelerometer. +* Accelerometer driver. * \author * Salvatore Pitrulli */ -/*---------------------------------------------------------------------------*/ - #include "dev/acc-sensor.h" #include "mems.h" @@ -46,82 +46,79 @@ #define FALSE 0 #define TRUE 1 - /*---------------------------------------------------------------------------*/ static int active(void) { - int8u reg; - if(!i2c_read_reg (kLIS3L02DQ_SLAVE_ADDR,CTRL_REG1, ®, 1)) + uint8_t reg; + + if(!i2c_read_reg(KLIS3L02DQ_SLAVE_ADDR, CTRL_REG1, ®, 1)) { return FALSE; - - return (reg & 0x40) ? TRUE : FALSE ; + } + + return (reg & 0x40) ? TRUE : FALSE; } /*---------------------------------------------------------------------------*/ static int value(int type) { - - int8s i2c_data = 0; - int8u reg_addr; - - switch(type) { - case ACC_X_AXIS: - reg_addr = OUTX_H; - break; - - case ACC_Y_AXIS: - reg_addr = OUTY_H; - break; - - case ACC_Z_AXIS: - reg_addr = OUTZ_H; - break; - - default: - return 0; - } - - i2c_read_reg(kLIS3L02DQ_SLAVE_ADDR, reg_addr, (int8u *)&i2c_data, 1); - - if(MEMS_GetFullScale()==ACC_HIGH_RANGE){ - return ((int16s)i2c_data)*HIGH_RANGE_SENSITIVITY; - } - else { - return ((int16s)i2c_data)*LOW_RANGE_SENSITIVITY; + int8_t i2c_data = 0; + uint8_t reg_addr; + + switch (type) { + case ACC_X_AXIS: + reg_addr = OUTX_H; + break; + + case ACC_Y_AXIS: + reg_addr = OUTY_H; + break; + + case ACC_Z_AXIS: + reg_addr = OUTZ_H; + break; + + default: + return 0; } + i2c_read_reg(KLIS3L02DQ_SLAVE_ADDR, reg_addr, (uint8_t *) &i2c_data, 1); + + if(mems_get_fullscale() == ACC_HIGH_RANGE) { + return ((int16_t) i2c_data) * HIGH_RANGE_SENSITIVITY; + } else { + return ((int16_t) i2c_data) * LOW_RANGE_SENSITIVITY; + } } /*---------------------------------------------------------------------------*/ static int configure(int type, int value) { - switch(type) { - - case SENSORS_HW_INIT: - return Mems_Init(); - - case SENSORS_ACTIVE: - if(value){ - if(MEMS_On()){ - clock_wait(8); - return 1; - } - return 0; - } - else - return MEMS_Off(); - - case ACC_RANGE: - return MEMS_SetFullScale((boolean)value); - - case ACC_HPF: - if(value < ACC_HPF_DISABLE){ - return i2c_write_reg(kLIS3L02DQ_SLAVE_ADDR, CTRL_REG2, (1<<4) | (int8u)value); - } - else { - return i2c_write_reg(kLIS3L02DQ_SLAVE_ADDR, CTRL_REG2, 0x00); + switch (type) { + case SENSORS_HW_INIT: + return mems_init(); + + case SENSORS_ACTIVE: + if(value) { + if(mems_on()) { + clock_wait(8); + return 1; } + return 0; + } else { + return mems_off(); + } + + case ACC_RANGE: + return mems_set_fullscale((boolean) value); + + case ACC_HPF: + if(value < ACC_HPF_DISABLE) { + return i2c_write_reg(KLIS3L02DQ_SLAVE_ADDR, CTRL_REG2, + (1 << 4) | (uint8_t) value); + } else { + return i2c_write_reg(KLIS3L02DQ_SLAVE_ADDR, CTRL_REG2, 0x00); + } } return 0; } @@ -129,18 +126,12 @@ configure(int type, int value) static int status(int type) { - switch(type) { - + switch (type) { case SENSORS_READY: return active(); } - return 0; } /*---------------------------------------------------------------------------*/ -SENSORS_SENSOR(acc_sensor, ACC_SENSOR, - value, configure, status); - - - - +SENSORS_SENSOR(acc_sensor, ACC_SENSOR, value, configure, status); +/** @} */ diff --git a/platform/mb851/dev/acc-sensor.h b/platform/mb851/dev/acc-sensor.h index 4809c192f..091403950 100644 --- a/platform/mb851/dev/acc-sensor.h +++ b/platform/mb851/dev/acc-sensor.h @@ -1,3 +1,8 @@ +/** + * \addtogroup mb851-platform + * + * @{ + */ /* * Copyright (c) 2010, STMicroelectronics. * All rights reserved. @@ -27,17 +32,13 @@ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * This file is part of the Contiki OS - * */ -/*---------------------------------------------------------------------------*/ /** * \file * Accelerometer header file. * \author * Salvatore Pitrulli */ -/*---------------------------------------------------------------------------*/ #ifndef __ACC_SENSOR_H__ #define __ACC_SENSOR_H__ @@ -49,29 +50,28 @@ extern const struct sensors_sensor acc_sensor; #define ACC_SENSOR "Acc" -/* The type values used in the configure() function. -*/ - -/* Full-scale*/ -#define ACC_RANGE 1 // type - -#define ACC_LOW_RANGE MEMS_LOW_RANGE // Values +/* The type values used in the configure() function. */ +/* Full-scale */ +#define ACC_RANGE 1 +#define ACC_LOW_RANGE MEMS_LOW_RANGE #define ACC_HIGH_RANGE MEMS_HIGH_RANGE -/* High pass filter and cut-off frequencies*/ -#define ACC_HPF 2 // type +/* High pass filter and cut-off frequencies */ +#define ACC_HPF 2 -#define ACC_HPF_DISABLE 4 // Values +#define ACC_HPF_DISABLE 4 #define ACC_1HZ 3 #define ACC_2HZ 2 #define ACC_4HZ 1 #define ACC_8HZ 0 -/* The type values used in the value() function. +/* + * The type values used in the value() function. * The returned value is expressed in mg units and can be negative. -*/ + */ #define ACC_X_AXIS 1 #define ACC_Y_AXIS 2 #define ACC_Z_AXIS 3 #endif /* __ACC_SENSOR_H__ */ +/** @} */ diff --git a/platform/mb851/dev/button-sensor.c b/platform/mb851/dev/button-sensor.c index d1bb69d13..4ae22b2e0 100644 --- a/platform/mb851/dev/button-sensor.c +++ b/platform/mb851/dev/button-sensor.c @@ -1,3 +1,8 @@ +/** + * \addtogroup mb851-platform + * + * @{ + */ /* * Copyright (c) 2010, STMicroelectronics. * All rights reserved. @@ -27,28 +32,23 @@ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * This file is part of the Contiki OS - * */ -/*---------------------------------------------------------------------------*/ /** * \file * Button sensor. * \author * Salvatore Pitrulli */ -/*---------------------------------------------------------------------------*/ #include "dev/button-sensor.h" #include "hal/micro/micro-common.h" #include "hal/micro/cortexm3/micro-common.h" #include BOARD_HEADER - #define DEBOUNCE 1 /** - * @brief Port and pin for BUTTON0. + * \brief Port and pin for BUTTON0. */ #undef BUTTON_S1 #define BUTTON_S1 PORTA_PIN(7) @@ -57,27 +57,27 @@ #define BUTTON_S1_OUTPUT_GPIO GPIO_PAOUT /** - * @brief Point the proper IRQ at the desired pin for BUTTON0. + * \brief Point the proper IRQ at the desired pin for BUTTON0. */ #define BUTTON_S1_SEL() do { GPIO_IRQCSEL = BUTTON_S1; } while(0) /** - * @brief The interrupt service routine for BUTTON_S1. + * \brief The interrupt service routine for BUTTON_S1. */ #define BUTTON_S1_ISR halIrqCIsr /** - * @brief The interrupt configuration register for BUTTON_S1. + * \brief The interrupt configuration register for BUTTON_S1. */ #define BUTTON_S1_INTCFG GPIO_INTCFGC /** - * @brief The interrupt bit for BUTTON_S1. + * \brief The interrupt bit for BUTTON_S1. */ #define BUTTON_S1_INT_EN_BIT INT_IRQC /** - * @brief The interrupt bit for BUTTON_S1. + * \brief The interrupt bit for BUTTON_S1. */ #define BUTTON_S1_FLAG_BIT INT_IRQCFLAG /** - * @brief The missed interrupt bit for BUTTON_S1. + * \brief The missed interrupt bit for BUTTON_S1. */ #define BUTTON_S1_MISS_BIT INT_MISSIRQC @@ -92,20 +92,16 @@ static struct timer debouncetimer; static void init(void) { - #if DEBOUNCE +#if DEBOUNCE timer_set(&debouncetimer, 0); - #endif - - /* Configure GPIO for BUTTONSs */ - - //Input, pulled up or down (selected by GPIO_PxOUT: 0 = pull-down, 1 = pull-up). - halGpioConfig(BUTTON_S1,GPIOCFG_IN_PUD); +#endif + + /* Configure GPIO */ + /* Input, pulled up or down (selected by GPIO_PxOUT: 0 = pull-down). */ + halGpioConfig(BUTTON_S1, GPIOCFG_IN_PUD); BUTTON_S1_OUTPUT_GPIO |= GPIOOUT_PULLUP << BUTTON_S1_GPIO_PIN; - - BUTTON_S1_SEL(); - BUTTON_S1_INTCFG = 0x40; // Falling edge triggered. - + BUTTON_S1_INTCFG = 0x40; /* Falling edge triggered. */ } /*---------------------------------------------------------------------------*/ static void @@ -123,58 +119,55 @@ deactivate(void) static int active(void) { - return (INT_CFGSET & BUTTON_S1_INT_EN_BIT) ? TRUE : FALSE ; + return (INT_CFGSET & BUTTON_S1_INT_EN_BIT) ? TRUE : FALSE; } /*---------------------------------------------------------------------------*/ static int value(int type) { #if DEBOUNCE - return (BUTTON_S1_INPUT_GPIO & (1< +*/ +/*--------------------------------------------------------------------------*/ void irq_init(void) { } - +/*--------------------------------------------------------------------------*/ +/** @} */ diff --git a/platform/mb851/dev/mems-regs.h b/platform/mb851/dev/mems-regs.h new file mode 100644 index 000000000..198655248 --- /dev/null +++ b/platform/mb851/dev/mems-regs.h @@ -0,0 +1,123 @@ +/** + * \addtogroup mb851-platform + * + * @{ + */ +/******************** (C) COPYRIGHT 2009 STMicroelectronics ******************** +* File Name : mems-regs.h +* Author : MCD Application Team +* Version : V1.0 +* Date : January 2010 +* Description : stm32w108 mems registers +******************************************************************************** +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ + +#ifndef _MEMS_REGS_H_ +#define _MEMS_REGS_H_ +#include + +/* Size of MEMs data */ +#define MEMS_DATA_SIZE 6 + +/* address of slave */ +#define KLIS3L02DQ_SLAVE_ADDR 0x38 + +/* accelerometer register addresses */ +#define OFFSET_X 0x16 +#define OFFSET_Y 0x17 +#define OFFSET_Z 0x18 +#define GAIN_X 0x19 +#define GAIN_Y 0x1A +#define GAIN_Z 0x1B +#define CTRL_REG1 0x20 +#define CTRL_REG2 0x21 +#define STATUS_REG 0x27 +#define OUTX_L 0x28 +#define OUTX_H 0x29 +#define OUTY_L 0x2A +#define OUTY_H 0x2B +#define OUTZ_L 0x2C +#define OUTZ_H 0x2D +#define FF_WU_CFG 0x30 +#define FF_WU_SRC 0x31 +#define FF_WU_ACK 0x32 +#define FF_WU_THS_L 0x34 +#define FF_WU_THS_H 0x35 +#define FF_WU_DURATION 0x36 +#define DD_CFG 0x38 +#define DD_SRC 0x39 +#define DD_ACK 0x3A +#define DD_THSI_L 0x3C +#define DD_THSI_H 0x3D +#define DD_THSE_L 0x3E +#define DD_THSE_H 0x3F + +/* Communication control settings */ +/* I2C */ +#define REPETIR 0x80 +/* SPI */ +#define MEMS_SPI_WRITE 0x00 +#define MEMS_SPI_READ 0x80 +#define MEMS_SPI_MULTIPLE_BYTES 0x40 + +/*--------------------------------------------------------------------------*/ +/* Settings for CTRL_REG1 */ +/* Power Down Control (PD) */ +#define LIS_PD_OFF 0x00 +#define LIS_PD_ON 0x40 + +/* Decimation Factor Control (DF) */ +#define LIS_DF_BY128 0x00 +#define LIS_DF_BY64 0x10 +#define LIS_DF_BY32 0x20 +#define LIS_DF_BY8 0x30 + +/* Self Test */ +#define LIS_ST_NORMAL 0x00 +#define LIS_ST_TEST 0x08 + +/* Enable Axis */ +#define LIS_EA_ALL 0x07 + +/*--------------------------------------------------------------------------*/ +/* Settings for CTRL_REG2 */ + +/* Full Scale (FS) */ +#define LIS_FS_2G 0x00 +#define LIS_FS_6G 0x80 + +/* Block Data Update (BDU) */ +#define LIS_BDU_CONTINUOUS 0x00 +#define LIS_BDU_WAIT 0x40 + +/* Big/Little Endian Selection (BLE) */ +#define LIS_BLE_LE 0x00 +#define LIS_BLE_BE 0x20 +#define LIS_BLE_XX LIS_BLE_BE + +/* Data Alignment Selection DAS */ +#define LIS_DAS_12BIT 0x00 +#define LIS_DAS_16BIT 0x01 + +/* Interrupt Enable */ +#define LIS_INTR_DISABLE 0x00 +#define LIS_INTR_ENABLE 0x08 + +/* Data Ready Enable */ +#define LIS_DRDY_DISABLE 0x00 +#define LIS_DRDY_ENABLE 0x04 + +/*--------------------------------------------------------------------------*/ +uint8_t i2c_write_reg(uint8_t slave_addr, uint8_t reg_addr, + uint8_t reg_value); +uint8_t i2c_read_reg(uint8_t slave_addr, uint8_t reg_addr, uint8_t *p_buf, + uint8_t len); +/*--------------------------------------------------------------------------*/ +#endif /* _MEMS_REGS_H_ */ +/** @} */ diff --git a/platform/mb851/dev/mems.c b/platform/mb851/dev/mems.c index 88dd3de26..fe945ea1a 100644 --- a/platform/mb851/dev/mems.c +++ b/platform/mb851/dev/mems.c @@ -1,3 +1,8 @@ +/** + * \addtogroup mb851-platform + * + * @{ + */ /******************** (C) COPYRIGHT 2009 STMicroelectronics ******************** * File Name : hal_led.c * Author : MCD Application Team @@ -13,356 +18,331 @@ * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *******************************************************************************/ -/* Includes ------------------------------------------------------------------*/ - #include PLATFORM_HEADER #include "mems.h" #include "timer.h" -/* Private define -- ---------------------------------------------------------*/ +/*--------------------------------------------------------------------------*/ +#define TIMEOUT 20000 +#define SUCCESS 1 +#define FAIL 0 -#define TIMEOUT 20000 +#define SEND_BYTE(data) do { SC2_DATA=(data); SC2_TWICTRL1 |= SC_TWISEND; \ + } while(0) -#define SUCCESS 1 -#define FAIL 0 - -#define SEND_BYTE(data) do{ SC2_DATA=(data); SC2_TWICTRL1 |= SC_TWISEND; }while(0) - -#define WAIT_CMD_FIN() { \ - struct timer t; \ - timer_set(&t, CLOCK_SECOND/100); \ - while((SC2_TWISTAT&SC_TWICMDFIN)!=SC_TWICMDFIN){ \ - if(timer_expired(&t)){ \ - return FAIL; \ - } \ - } \ +#define WAIT_CMD_FIN() { \ + struct timer t; \ + timer_set(&t, CLOCK_SECOND/100); \ + while((SC2_TWISTAT&SC_TWICMDFIN)!=SC_TWICMDFIN){ \ + if(timer_expired(&t)){ \ + return FAIL; \ + } \ + } \ } -#define WAIT_TX_FIN() { \ - struct timer t; \ - timer_set(&t, CLOCK_SECOND/100); \ - while((SC2_TWISTAT&SC_TWITXFIN)!=SC_TWITXFIN){ \ - if(timer_expired(&t)){ \ - return FAIL; \ - } \ - } \ +#define WAIT_TX_FIN() { \ + struct timer t; \ + timer_set(&t, CLOCK_SECOND/100); \ + while((SC2_TWISTAT&SC_TWITXFIN)!=SC_TWITXFIN){ \ + if(timer_expired(&t)){ \ + return FAIL; \ + } \ + } \ } -#define WAIT_RX_FIN() { \ - struct timer t; \ - timer_set(&t, CLOCK_SECOND/100); \ - while((SC2_TWISTAT&SC_TWIRXFIN)!=SC_TWIRXFIN){ \ - if(timer_expired(&t)){ \ - return FAIL; \ - } \ - } \ +#define WAIT_RX_FIN() { \ + struct timer t; \ + timer_set(&t, CLOCK_SECOND/100); \ + while((SC2_TWISTAT&SC_TWIRXFIN)!=SC_TWIRXFIN){ \ + if(timer_expired(&t)){ \ + return FAIL; \ + } \ + } \ } -/* Private variables ---------------------------------------------------------*/ +/*--------------------------------------------------------------------------*/ static boolean fullscale_state; -/* Private functions ---------------------------------------------------------*/ -static int8u I2C_MEMS_Init (void); -//extern void halInternalResetWatchDog(void); -static int8u I2C_Send_Frame (int8u DeviceAddress, int8u *pBuffer, int8u NoOfBytes); -int8u i2c_write_reg (int8u slave_addr, int8u reg_addr, int8u reg_value); -//static int8u I2C_MEMS_Read (t_mems_data *mems_data); +static uint8_t i2c_mems_init(void); -/* Functions -----------------------------------------------------------------*/ +static uint8_t i2c_send_frame(uint8_t address, uint8_t *p_buf, uint8_t len); -/******************************************************************************* -* Function Name : Mems_Init -* Description : It inits mems -* Input : None -* Output : status -* Return : None -*******************************************************************************/ -int8u Mems_Init(void) -{ - int8u ret = 0; - - // GPIO assignments - // PA1: SC2SDA (Serial Data) - // PA2: SC2SCL (Serial Clock) +uint8_t i2c_write_reg(uint8_t slave_addr, uint8_t reg_addr, + uint8_t reg_value); - //-----SC2 I2C Master GPIO configuration + /* static uint8_t i2c_mems_read (mems_data_t *mems_data); */ +/*--------------------------------------------------------------------------*/ +/** + * \brief Init MEMS + * \return None + */ +uint8_t +mems_init(void) +{ + uint8_t ret = 0; + /* GPIO assignments */ + /* PA1: SC2SDA (Serial Data) */ + /* PA2: SC2SCL (Serial Clock) */ + /* -----SC2 I2C Master GPIO configuration */ TIM2_CCER &= 0xFFFFEEEE; - SC2_MODE = SC2_MODE_I2C; + SC2_MODE = SC2_MODE_I2C; GPIO_PACFGL &= 0xFFFFF00F; GPIO_PACFGL |= 0x00000DD0; - - SC2_RATELIN = 14; // generates standard 100kbps or 400kbps - SC2_RATEEXP = 1; // 3 yields 100kbps; 1 yields 400kbps - SC2_TWICTRL1 = 0; // start from a clean state - SC2_TWICTRL2 = 0; // start from a clean state - - ret = I2C_MEMS_Init(); - + + SC2_RATELIN = 14; /* generates standard 100kbps or 400kbps */ + SC2_RATEEXP = 1; /* 3 yields 100kbps; 1 yields 400kbps */ + SC2_TWICTRL1 = 0; /* start from a clean state */ + SC2_TWICTRL2 = 0; /* start from a clean state */ + + ret = i2c_mems_init(); fullscale_state = MEMS_LOW_RANGE; -//Add later if really needed -#ifdef ST_DBG - if (!ret) - I2C_DeInit(MEMS_I2C); + /* Add later if really needed */ +#ifdef ST_DBG + if(!ret) + I2C_DeInit(MEMS_I2C); #endif - + return ret; -}/* end Mems_Init */ - -/******************************************************************************* -* Function Name : Mems_GetValue -* Description : It returns the 3 mems acceleration values related to x,y,z -* axes in mems_data -* Input : mems_data -* Output : status -* Return : None -*******************************************************************************/ -//int8u Mems_GetValue(t_mems_data *mems_data) -//{ -// int8u i; -// i = I2C_MEMS_Read(mems_data); -// return i; -//} - - -/* Private Functions ---------------------------------------------------------*/ - -/******************************************************************************* -* Function Name : I2C_Send_Frame -* Description : It sends I2C frame -* Input : DeviceAddress is the destination device address -* pBUffer is the buffer data -* NoOfBytes is the number of bytes -* Output : None -* Return : 1 if the frame has been successfully sent, 0 otherwise. -*******************************************************************************/ -static int8u I2C_Send_Frame (int8u DeviceAddress, int8u *pBuffer, int8u NoOfBytes) +} +/*--------------------------------------------------------------------------*/ +/** + * \brief Returns the 3 mems acceleration values related to x,y,z axes + * \param mems_data pointer to mems_data_t that will be filled with the values + * \return None + */ +#if 0 +uint8_t mems_get_value(mems_data_t *mems_data) +{ + uint8_t i; + i = i2c_mems_read(mems_data); + return i; +} +#endif +/*--------------------------------------------------------------------------*/ +/** + * \brief Send I2C frame + * \param address destination device address + * \param p_buf pointer to data buffer + * \param len length of data + * \retval 0 frame has not been successfully sent + * \retval 1 frame has been successfully sent + */ +static uint8_t +i2c_send_frame(uint8_t address, uint8_t *p_buf, uint8_t len) { - int8u i, data; + uint8_t i, data; - SC2_TWICTRL1 |= SC_TWISTART; // send start + SC2_TWICTRL1 |= SC_TWISTART; /* send start */ WAIT_CMD_FIN(); - - SEND_BYTE(DeviceAddress); // send the address low byte + SEND_BYTE(address); /* send the address low byte */ WAIT_TX_FIN(); - - // loop sending the data - for (i=0; i 1) + uint8_t i, addr = reg_addr; + + if(len > 1) { addr += REPETIR; - - SC2_TWICTRL1 |= SC_TWISTART; // send start + } + + SC2_TWICTRL1 |= SC_TWISTART; /* send start */ WAIT_CMD_FIN(); - - SEND_BYTE(slave_addr | 0x00); // send the address low byte + + SEND_BYTE(slave_addr | 0x00); /* send the address low byte */ WAIT_TX_FIN(); - + SEND_BYTE(addr); WAIT_TX_FIN(); - SC2_TWICTRL1 |= SC_TWISTART; // send start + SC2_TWICTRL1 |= SC_TWISTART; /* send start */ WAIT_CMD_FIN(); - - SEND_BYTE(slave_addr | 0x01); // send the address low byte + + SEND_BYTE(slave_addr | 0x01); /* send the address low byte */ WAIT_TX_FIN(); - - // loop receiving the data - for (i=0;ioutx_h = i2c_buffer[0]; -// mems_data->outx_l = i2c_buffer[1]; -// mems_data->outy_h = i2c_buffer[2]; -// mems_data->outy_l = i2c_buffer[3]; -// mems_data->outz_h = i2c_buffer[4]; -// mems_data->outz_l = i2c_buffer[5]; -// -// return i; -//}/* end I2C_MEMS_Read() */ + i = i2c_read_reg (KLIS3L02DQ_SLAVE_ADDR, OUTX_L, i2c_buffer, 8); + mems_data->outx_h = i2c_buffer[0]; + mems_data->outx_l = i2c_buffer[1]; + mems_data->outy_h = i2c_buffer[2]; + mems_data->outy_l = i2c_buffer[3]; + mems_data->outz_h = i2c_buffer[4]; + mems_data->outz_l = i2c_buffer[5]; -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ + return i; +} +#endif +/*--------------------------------------------------------------------------*/ +/** @} */ diff --git a/platform/mb851/dev/mems.h b/platform/mb851/dev/mems.h index 45fa920fc..2b38384fb 100644 --- a/platform/mb851/dev/mems.h +++ b/platform/mb851/dev/mems.h @@ -1,3 +1,8 @@ +/** + * \addtogroup mb851-platform + * + * @{ + */ /******************** (C) COPYRIGHT 2009 STMicroelectronics ******************** * File Name : mems.h * Author : MCD Application Team @@ -15,45 +20,42 @@ #ifndef _MEMS_H_ #define _MEMS_H_ +#include "mems-regs.h" +#include -/* Define --------------------------------------------------------------------*/ -#include "mems_regs.h" +/* Sensitivity values in mg/digit */ +#define HIGH_RANGE_SENSITIVITY 72 +#define LOW_RANGE_SENSITIVITY 18 -/* Define --------------------------------------------------------------------*/ -// Sensitivity values in mg/digit -#define HIGH_RANGE_SENSITIVITY 72 -#define LOW_RANGE_SENSITIVITY 18 +#define MEMS_LOW_RANGE 0 +#define MEMS_HIGH_RANGE 1 -#define MEMS_LOW_RANGE 0 -#define MEMS_HIGH_RANGE 1 +/* + * Mems data type: three acceleration values each related to a specific + * direction. + * Watch out: only lower data values (e.g. those terminated by the _l) are + * currently used by the device. + */ +typedef struct mems_data_s { + int8_t outx_l; + int8_t outx_h; + int8_t outy_l; + int8_t outy_h; + int8_t outz_l; + int8_t outz_h; +} mems_data_t; -/* Typedef -------------------------------------------------------------------*/ -/* Mems data type: three acceleration values each related to a specific direction - Watch out: only lower data values (e.g. those terminated by the _l) are - currently used by the device */ +uint8_t mems_init(void); -typedef struct { - int8s outx_l; - int8s outx_h; - int8s outy_l; - int8s outy_h; - int8s outz_l; - int8s outz_h; -} t_mems_data; +uint8_t mems_on(void); -/* Functions -----------------------------------------------------------------*/ +uint8_t mems_off(void); -/* Mems Initialization function */ -int8u Mems_Init(void); +uint8_t mems_set_fullscale(boolean range); -int8u MEMS_On(void); -int8u MEMS_Off(void); -int8u MEMS_SetFullScale(boolean range); -boolean MEMS_GetFullScale(void); +boolean mems_get_fullscale(void); -/* Get mems acceleration values */ -int8u Mems_GetValue(t_mems_data *mems_data); +uint8_t mems_get_value(mems_data_t * mems_data); #endif /* _MEMS_H_ */ - -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ +/** @} */ diff --git a/platform/mb851/dev/mems_regs.h b/platform/mb851/dev/mems_regs.h deleted file mode 100644 index 9796339a4..000000000 --- a/platform/mb851/dev/mems_regs.h +++ /dev/null @@ -1,139 +0,0 @@ -/******************** (C) COPYRIGHT 2009 STMicroelectronics ******************** -* File Name : mems_regs.h -* Author : MCD Application Team -* Version : V1.0 -* Date : January 2010 -* Description : stm32w108 mems registers -******************************************************************************** -* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -*******************************************************************************/ - -#ifndef _MEMS_REGS_H_ -#define _MEMS_REGS_H_ - -/* Private include ------------------------------------------------------------*/ - -/* Private define ------------------------------------------------------------*/ - -//---Size of MEMs data--- -#define MEMS_DATA_SIZE 6 - -//---address of slave I want to communicate with--- -#define kLIS3L02DQ_SLAVE_ADDR 0x38 - -//----------------------------------------------------------------------------- -//---accelerometer register addresses--- -#define OFFSET_X 0x16 -#define OFFSET_Y 0x17 -#define OFFSET_Z 0x18 -#define GAIN_X 0x19 -#define GAIN_Y 0x1A -#define GAIN_Z 0x1B -#define CTRL_REG1 0x20 -#define CTRL_REG2 0x21 -#define STATUS_REG 0x27 -#define OUTX_L 0x28 -#define OUTX_H 0x29 -#define OUTY_L 0x2A -#define OUTY_H 0x2B -#define OUTZ_L 0x2C -#define OUTZ_H 0x2D -#define FF_WU_CFG 0x30 -#define FF_WU_SRC 0x31 -#define FF_WU_ACK 0x32 -#define FF_WU_THS_L 0x34 -#define FF_WU_THS_H 0x35 -#define FF_WU_DURATION 0x36 -#define DD_CFG 0x38 -#define DD_SRC 0x39 -#define DD_ACK 0x3A -#define DD_THSI_L 0x3C -#define DD_THSI_H 0x3D -#define DD_THSE_L 0x3E -#define DD_THSE_H 0x3F - -// Communication control settings -// I2C -#define REPETIR 0x80 -// SPI -#define MEMS_SPI_WRITE 0x00 -#define MEMS_SPI_READ 0x80 -#define MEMS_SPI_MULTIPLE_BYTES 0x40 - -//----------------------------------------------------------------------------- -//---Settings for CTRL_REG1--- - -// Power Down Control (PD) -#define LIS_PD_OFF 0x00 -#define LIS_PD_ON 0x40 - -// Decimation Factor Control (DF) -#define LIS_DF_BY128 0x00 -#define LIS_DF_BY64 0x10 -#define LIS_DF_BY32 0x20 -#define LIS_DF_BY8 0x30 - -// Self Test -#define LIS_ST_NORMAL 0x00 -#define LIS_ST_TEST 0x08 - -// Enable Axis -#define LIS_EA_ALL 0x07 - -//----------------------------------------------------------------------------- -//---Settings for CTRL_REG2--- - -// Full Scale (FS) -#define LIS_FS_2G 0x00 -#define LIS_FS_6G 0x80 - -// Block Data Update (BDU) -#define LIS_BDU_CONTINUOUS 0x00 -#define LIS_BDU_WAIT 0x40 - -// Big/Little Endian Selection (BLE) -#define LIS_BLE_LE 0x00 -#define LIS_BLE_BE 0x20 - -// Data Alignment Selection DAS -#define LIS_DAS_12BIT 0x00 -#define LIS_DAS_16BIT 0x01 - -// Interrupt Enable -#define LIS_INTR_DISABLE 0x00 -#define LIS_INTR_ENABLE 0x08 - -// Data Ready Enable -#define LIS_DRDY_DISABLE 0x00 -#define LIS_DRDY_ENABLE 0x04 - -//----------------------------------------------------------------------------- - -#define LIS_BLE_XX LIS_BLE_BE - - -/* Private Functions Prototypes ----------------------------------------------*/ - -//*********************i2c_read_reg***********************// -//----------Reads a register on the I2C target------------// -//------slave addr is the is the I2C target device--------// -//-reg_addr is the address of the register to be written--// -//-pBuffer is the storage destination for the read data---// -//-NoOfBytes is the amount of data to read----------------// -int8u i2c_read_reg (int8u slave_addr, int8u reg_addr, int8u *pBuffer, int8u NoOfBytes); - -//*********************i2c_write_reg**********************// -//----------Writes a register on the I2C target-----------// -//------slave addr is the is the I2C target device--------// -//-reg_addr is the address of the register to be written--// -//-reg_value is the value of the register to be written---// -int8u i2c_write_reg (int8u slave_addr, int8u reg_addr, int8u reg_value); - -#endif /* _MEMS_REGS_H_ */ - -/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/platform/mb851/dev/temperature-sensor.c b/platform/mb851/dev/temperature-sensor.c index 0f25494b4..f98c1831e 100644 --- a/platform/mb851/dev/temperature-sensor.c +++ b/platform/mb851/dev/temperature-sensor.c @@ -1,3 +1,8 @@ +/** + * \addtogroup mb851-platform + * + * @{ + */ /* * Copyright (c) 2010, STMicroelectronics. * All rights reserved. @@ -27,25 +32,13 @@ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * This file is part of the Contiki OS - * */ -/*---------------------------------------------------------------------------*/ /** * \file * Temperature sensor. * \author * Salvatore Pitrulli */ -/*---------------------------------------------------------------------------*/ - -/** - * NOTE: - * For the temperature measurement, the ADC extended range mode is needed; - * but this is inaccurate due to the high voltage mode bug of the general purpose ADC - * (see STM32W108 errata). - */ - #include PLATFORM_HEADER #include BOARD_HEADER @@ -58,12 +51,11 @@ #undef TEMPERATURE_SENSOR_GPIO #define TEMPERATURE_SENSOR_GPIO PORTB_PIN(7) - /*---------------------------------------------------------------------------*/ static void init(void) { - halGpioConfig(TEMPERATURE_SENSOR_GPIO,GPIOCFG_ANALOG); + halGpioConfig(TEMPERATURE_SENSOR_GPIO, GPIOCFG_ANALOG); halInternalInitAdc(); halAdcSetRange(TRUE); } @@ -71,46 +63,48 @@ init(void) static int value(int type) { - static int16u ADCvalue; - static int16s volts; - - halStartAdcConversion(ADC_USER_APP, ADC_REF_INT, ADC_SOURCE_ADC2_VREF2, ADC_CONVERSION_TIME_US_4096); - - halReadAdcBlocking(ADC_USER_APP, &ADCvalue); // This blocks for a while, about 4ms. - - // 100 uVolts + static uint16_t ADCvalue; + static int16_t volts; + halStartAdcConversion(ADC_USER_APP, ADC_REF_INT, ADC_SOURCE_ADC2_VREF2, + ADC_CONVERSION_TIME_US_4096); + + /* This blocks for a while, about 4ms. */ + halReadAdcBlocking(ADC_USER_APP, &ADCvalue); + + /* 100 uVolts */ volts = halConvertValueToVolts(ADCvalue); - - //return ((18641 - (int32s)volts)*100)/1171; // +- 0.23 degC in the range (-10;65) degC - return ((18663 - (int32s)volts)*100)/1169; // +- 0.004 degC in the range (20;30) degC - + + /* +- 0.23 degC in the range (-10;65) degC */ + /* return ((18641 - (int32_t)volts)*100)/1171;*/ + + /* +- 0.004 degC in the range (20;30) degC */ + return ((18663 - (int32_t) volts) * 100) / 1169; } /*---------------------------------------------------------------------------*/ static int configure(int type, int value) { - switch(type){ - case SENSORS_HW_INIT: - init(); - return 1; - case SENSORS_ACTIVE: - return 1; + switch (type) { + case SENSORS_HW_INIT: + init(); + return 1; + case SENSORS_ACTIVE: + return 1; } - return 0; } /*---------------------------------------------------------------------------*/ static int status(int type) { - switch(type) { - - case SENSORS_READY: - return 1; + switch (type) { + case SENSORS_READY: + return 1; } - return 0; } /*---------------------------------------------------------------------------*/ SENSORS_SENSOR(temperature_sensor, TEMPERATURE_SENSOR, - value, configure, status); + value, configure, status); +/*--------------------------------------------------------------------------*/ +/** @} */ diff --git a/platform/mb851/dev/temperature-sensor.h b/platform/mb851/dev/temperature-sensor.h index 56b58e487..af954f76f 100644 --- a/platform/mb851/dev/temperature-sensor.h +++ b/platform/mb851/dev/temperature-sensor.h @@ -1,3 +1,8 @@ +/** + * \addtogroup mb851-platform + * + * @{ + */ /* * Copyright (c) 2010, STMicroelectronics. * All rights reserved. @@ -27,35 +32,35 @@ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * This file is part of the Contiki OS - * */ -/*---------------------------------------------------------------------------*/ /** * \file * Temperature sensor. * \author * Salvatore Pitrulli */ -/*---------------------------------------------------------------------------*/ - -/* - * Value returned by temperature_sensor.value() is expressed in units of 0.1 °C. - */ -/** - * NOTE: - * For the temperature measurement, the ADC extended range mode is needed; - * but this is inaccurate due to the high voltage mode bug of the general purpose ADC - * (see STM32W108 errata). - */ #ifndef __TEMPERATURE_SENSOR_H__ #define __TEMPERATURE_SENSOR_H__ #include "lib/sensors.h" +/* + * Value returned by temperature_sensor.value() is expressed in units of 0.1 degC. + * + * NOTES: + * + * For the temperature measurement, the ADC extended range mode is needed; + * but this is inaccurate due to the high voltage mode bug of the general purpose ADC + * (see STM32W108 errata). + * + * For the temperature measurement, the ADC extended range mode is needed; + * but this is inaccurate due to the high voltage mode bug of the general purpose ADC + * (see STM32W108 errata). + */ extern const struct sensors_sensor temperature_sensor; #define TEMPERATURE_SENSOR "Temperature" #endif /* __TEMPERATURE_SENSOR_H__ */ +/** @} */ diff --git a/platform/mb851/platform-conf.h b/platform/mb851/platform-conf.h index 6e3d6811b..f211fc82d 100644 --- a/platform/mb851/platform-conf.h +++ b/platform/mb851/platform-conf.h @@ -1,3 +1,11 @@ +/** + * \defgroup mb851-platform The STM32W MB851 platform. + * + * The STM32W MB851 platform. + * + * @{ + */ + /* * Copyright (c) 2010, STMicroelectronics. * All rights reserved. @@ -27,10 +35,8 @@ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * This file is part of the Contiki OS - * - */ -/*---------------------------------------------------------------------------*/ + */ + /** * \file * platform-conf.h for MB851. @@ -38,57 +44,53 @@ * Salvatore Pitrulli * Chi-Anh La * Simon Duquennoy -*/ -/*---------------------------------------------------------------------------*/ +*/ #ifndef __PLATFORM_CONF_H__ #define __PLATFORM_CONF_H__ - + #include PLATFORM_HEADER - + #include -#include // For memcpm(). - -/* Platform-dependent definitions */ -#define CC_CONF_REGISTER_ARGS 0 -#define CC_CONF_FUNCTION_POINTER_ARGS 1 +#include /* For memcpm() */ + +/* Platform-dependent definitions */ +#define CC_CONF_REGISTER_ARGS 0 +#define CC_CONF_FUNCTION_POINTER_ARGS 1 #define CC_CONF_FASTCALL -#define CC_CONF_VA_ARGS 1 -#define CC_CONF_INLINE inline - +#define CC_CONF_VA_ARGS 1 +#define CC_CONF_INLINE inline + #define CCIF #define CLIF typedef unsigned short uip_stats_t; +typedef unsigned long clock_time_t; +typedef unsigned long rtimer_clock_t; + +#define CLOCK_CONF_SECOND 1000 +#define RTIMER_CLOCK_LT(a,b) ((signed short)((a)-(b)) < 0) +/* rtimer_second = 11719 */ +#define RT_CONF_RESOLUTION 2 #define UART1_CONF_TX_WITH_INTERRUPT 0 -#define WITH_SERIAL_LINE_INPUT 1 - -/* rtimer_second = 11719 */ -#define RT_CONF_RESOLUTION 2 - -/* A trick to resolve a compilation error with IAR. */ +#define WITH_SERIAL_LINE_INPUT 1 + +/* A trick to resolve a compilation error with IAR. */ #ifdef __ICCARM__ -#define UIP_CONF_DS6_AADDR_NBU 1 -#endif - -typedef unsigned long clock_time_t; - -#define CLOCK_CONF_SECOND 1000 - -typedef unsigned long rtimer_clock_t; -#define RTIMER_CLOCK_LT(a,b) ((signed short)((a)-(b)) < 0) - -/* LEDs ports MB851 */ -#define LEDS_CONF_RED_PIN 5 -#define LEDS_CONF_GREEN_PIN 6 -#define LEDS_CONF_PORT PORTB -#define LEDS_CONF_RED (1<