x86, galileo: Use IMRs to restrict DMA

This patch configures Isolated Memory Regions (IMRs) to block DMA to
code and data regions that do not contain any data that needs to be
DMA-accessible.

cpu/x86/Makefile.x86_quarkX1000

@@ -9,6 +9,12 @@ CFLAGS += -m32 -march=i586 -mtune=i586
 LDFLAGS += -m32 -Xlinker -T -Xlinker $(CONTIKI)/cpu/x86/quarkX1000.ld
 ASFLAGS += --32 -march=i586 -mtune=i586
 
+ifeq ($(X86_CONF_RESTRICT_DMA),1)
+CONTIKI_SOURCEFILES += imr-conf.c
+CFLAGS += -DX86_CONF_RESTRICT_DMA
+LDFLAGS += -Xlinker -T -Xlinker $(CONTIKI)/cpu/x86/quarkX1000_dma.ld
+endif
+
 ### UEFI support
 
 UEFI_DIR = $(CONTIKI_CPU)/uefi

cpu/x86/dma.h

@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2016, Intel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef CPU_X86_DMA_H_
+#define CPU_X86_DMA_H_
+
+#ifdef X86_CONF_RESTRICT_DMA
+#define ATTR_BSS_DMA __attribute__((section(".dma_bss")))
+#else
+#define ATTR_BSS_DMA
+#endif
+
+#endif /* CPU_X86_DMA_H_ */

cpu/x86/drivers/quarkX1000/eth.c

@@ -32,6 +32,7 @@
 #include <assert.h>
 #include <stdio.h>
 #include "contiki-net.h"
+#include "dma.h"
 #include "eth.h"
 #include "helpers.h"
 #include "net/ip/uip.h"
@@ -188,7 +189,7 @@ typedef struct quarkX1000_eth_meta {
 #define REG_ADDR_DMA_OPERATION         0x1018
 
 static quarkX1000_eth_driver_t drv;
-static quarkX1000_eth_meta_t meta;
+static quarkX1000_eth_meta_t ATTR_BSS_DMA meta;
 
 /*---------------------------------------------------------------------------*/
 /**

cpu/x86/drivers/quarkX1000/imr-conf.c

@@ -0,0 +1,73 @@
+/*
+ * Copyright (C) 2015-2016, Intel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "imr.h"
+
+extern int _sbss_dma_addr, _ebss_dma_addr;
+
+/*---------------------------------------------------------------------------*/
+void
+quarkX1000_imr_conf(void)
+{
+  quarkX1000_imr_t imr;
+  int imr_idx = 0;
+
+  imr.lo.raw = 0;
+  imr.hi.raw = 0;
+  imr.rdmsk.raw = 0;
+  imr.wrmsk.raw = 0;
+
+  imr.lo.lock = 1;
+
+  imr.rdmsk.cpu0 = imr.rdmsk.cpu_0 = 1;
+  imr.wrmsk.cpu0 = imr.wrmsk.cpu_0 = 1;
+
+  imr.lo.addr = 0;
+  imr.hi.addr = (((uint32_t)&_sbss_dma_addr) - 1) >> QUARKX1000_IMR_SHAMT;
+  quarkX1000_imr_write(imr_idx, imr);
+  imr_idx++;
+
+  imr.lo.addr = ((uint32_t)&_ebss_dma_addr) >> QUARKX1000_IMR_SHAMT;
+  imr.hi.addr = ~0;
+  quarkX1000_imr_write(imr_idx, imr);
+  imr_idx++;
+
+  imr.lo.addr = 0;
+  imr.hi.addr = 0;
+  imr.rdmsk.raw = ~0;
+  imr.wrmsk.raw = ~0;
+
+  /* Lock the other IMRs open */
+  while(imr_idx < QUARKX1000_IMR_CNT) {
+    quarkX1000_imr_write(imr_idx, imr);
+    imr_idx++;
+  }
+}
+/*---------------------------------------------------------------------------*/

cpu/x86/drivers/quarkX1000/imr-conf.h

@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2015-2016, Intel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef CPU_X86_DRIVERS_QUARKX1000_IMR_CONF_H_
+#define CPU_X86_DRIVERS_QUARKX1000_IMR_CONF_H_
+
+void quarkX1000_imr_conf(void);
+
+#endif /* CPU_X86_DRIVERS_QUARKX1000_IMR_CONF_H_ */

cpu/x86/quarkX1000_dma.ld

@@ -0,0 +1,51 @@
+/*
+ * Copyright (C) 2015-2016, Intel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+SECTIONS {
+
+    /*
+       It would be more natural to use a 1K alignment for this entire section.
+       However, the UEFI GenFw program ratchets up its alignment
+       granularity to the maximum granularity discovered in its input file.
+       Using 1K-alignment perturbs the symbols, hindering debugging.  Thus,
+       this section is simply padded out to the desired alignment and
+       declared to have a section alignment of only 32 bytes.
+    */
+    .bss.dma ALIGN (32) (NOLOAD) :
+    {
+        /* The IMR feature operates at 1K granularity. */
+        . = ALIGN(1K);
+        _sbss_dma_addr = .;
+        *(.dma_bss)
+        . = ALIGN(1K);
+        _ebss_dma_addr = .;
+    }
+
+}

platform/galileo/README.md

@@ -86,6 +86,12 @@ you can run the following command prior to building applications:
 $ cpu/x86/uefi/build_uefi.sh
 ```
 
+To restrict DMA so that peripherals are blocked from accessing memory
+regions that do not contain any data that needs to be DMA-accessible,
+specify X86_CONF_RESTRICT_DMA=1 as a command-line argument to the make
+command that is used to build the image.  This will configure and lock
+the IMRs.
+
 Running
 -------
 

platform/galileo/contiki-main.c

@@ -37,6 +37,7 @@
 #include "galileo-pinmux.h"
 #include "gpio.h"
 #include "i2c.h"
+#include "imr-conf.h"
 #include "interrupt.h"
 #include "shared-isr.h"
 #include "uart.h"
@@ -52,6 +53,9 @@ int
 main(void)
 {
   cpu_init();
+#ifdef X86_CONF_RESTRICT_DMA
+  quarkX1000_imr_conf();
+#endif
   /* Initialize UART connected to Galileo Gen2 FTDI header */
   quarkX1000_uart_init(QUARK_X1000_UART_1);
   clock_init();