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commit
cc37a1e46e
@ -87,7 +87,7 @@ dma_reset(uint8_t c)
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dma_conf[c].len_h = 0;
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dma_conf[c].len_h = 0;
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dma_conf[c].len_l = 1;
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dma_conf[c].len_l = 1;
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dma_conf[c].wtt = DMA_BLOCK;
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dma_conf[c].wtt = DMA_BLOCK;
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dma_conf[c].inc_prio = DMA_PRIO_GUARANTEED;
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dma_conf[c].inc_prio = DMA_PRIO_ASSURED;
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DMA_TRIGGER(c); /** The operation order is important */
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DMA_TRIGGER(c); /** The operation order is important */
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DMA_ARM(c);
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DMA_ARM(c);
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while(DMAARM & (1 << c));
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while(DMAARM & (1 << c));
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@ -95,9 +95,8 @@
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/* Descriptor Byte 7, Bits[3:0] */
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/* Descriptor Byte 7, Bits[3:0] */
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#define DMA_IRQ_MASK_ENABLE 0x08
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#define DMA_IRQ_MASK_ENABLE 0x08
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#define DMA_MODE_7_BIT 0x04
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#define DMA_MODE_7_BIT 0x04
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#define DMA_PRIO_HIGHEST 0x03
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#define DMA_PRIO_HIGH 0x02
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#define DMA_PRIO_HIGH 0x02
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#define DMA_PRIO_GUARANTEED 0x01
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#define DMA_PRIO_ASSURED 0x01
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#define DMA_PRIO_LOW 0x00
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#define DMA_PRIO_LOW 0x00
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/** DMA configuration structure */
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/** DMA configuration structure */
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