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https://github.com/oliverschmidt/contiki.git
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MSP430 setup for f2xxx based on Z1
This commit is contained in:
Niclas Finne
parent
9ffcd53868
commit
f3db12c19d
@ -27,20 +27,15 @@
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* SUCH DAMAGE.
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*
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* This file is part of the Contiki operating system.
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*
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* @(#)$Id: msp430.c,v 1.1 2010/08/24 16:26:38 joxe Exp $
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*/
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#include "contiki.h"
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#include "dev/watchdog.h"
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#ifndef __IAR_SYSTEMS_ICC__
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#if defined(__MSP430__) && defined(__GNUC__)
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#define asmv(arg) __asm__ __volatile__(arg)
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#endif
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#include "msp430def.h"
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#include "dev/watchdog.h"
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#include "net/uip.h"
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/*---------------------------------------------------------------------------*/
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#if defined(__MSP430__) && defined(__GNUC__) && MSP430_MEMCPY_WORKAROUND
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void *
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@ -83,11 +78,12 @@ msp430_init_dco(void)
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}
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/*BCSCTL1 |= XT2OFF; // Make sure XT2 is off */
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/* BCSCTL2 = 0x00; // MCLK = DCOCLK/1 */
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/* BCSCTL2 = 0x00; // MCLK = DCOCLK/1 */
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/* SMCLK = DCOCLK/1 */
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/* DCO Internal Resistor */
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}
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/* Start CPU with full speed (? good or bad?) and go downwards */
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/*---------------------------------------------------------------------------*/
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@ -142,69 +138,13 @@ msp430_quick_synch_dco(void) {
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/* vals[current_bit] = diff; */
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/* should we keep the bit cleared or not ? */
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if (diff < DELTA_2) { /* DCO is too slow - fewer ticks than desired */
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if(diff < DELTA_2) { /* DCO is too slow - fewer ticks than desired */
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/* toggle bit again to get it back to one */
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dco_reg = dco_reg ^ (1 << current_bit);
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}
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}
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}
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/*---------------------------------------------------------------------------*/
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void
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msp430_init_dco_old(void) /*Enric NOT IN USE, RIGHT NOW */
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{
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/* This code taken from the FU Berlin sources and reformatted. */
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#define DELTA ((MSP430_CPU_SPEED) / (32768 / 8))
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unsigned int compare, oldcapture = 0;
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unsigned int i;
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BCSCTL1 = 0xa4; /* ACLK is devided by 4. RSEL=6 no division for MCLK
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and SSMCLK. XT2 is off. */
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BCSCTL2 = 0x00; /* Init FLL to desired frequency using the 32762Hz
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crystal DCO frquenzy = 2,4576 MHz */
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BCSCTL1 |= DIVA1 + DIVA0; /* ACLK = LFXT1CLK/8 */
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for(i = 0xffff; i > 0; i--) { /* Delay for XTAL to settle */
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asm("nop");
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}
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CCTL2 = CCIS0 + CM0 + CAP; /* Define CCR2, CAP, ACLK */
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TACTL = TASSEL1 + TACLR + MC1; // SMCLK, continous mode
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while(1) {
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while((CCTL2 & CCIFG) != CCIFG); /* Wait until capture occured! */
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CCTL2 &= ~CCIFG; /* Capture occured, clear flag */
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compare = CCR2; /* Get current captured SMCLK */
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compare = compare - oldcapture; /* SMCLK difference */
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oldcapture = CCR2; /* Save current captured SMCLK */
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if(DELTA == compare) {
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break; /* if equal, leave "while(1)" */
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} else if(DELTA < compare) { /* DCO is too fast, slow it down */
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DCOCTL--;
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if(DCOCTL == 0xFF) { /* Did DCO role under? */
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BCSCTL1--;
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}
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} else { /* -> Select next lower RSEL */
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DCOCTL++;
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if(DCOCTL == 0x00) { /* Did DCO role over? */
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BCSCTL1++;
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}
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/* -> Select next higher RSEL */
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}
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}
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CCTL2 = 0; /* Stop CCR2 function */
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TACTL = 0; /* Stop Timer_A */
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BCSCTL1 &= ~(DIVA1 + DIVA0); /* remove /8 divisor from ACLK again */
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}
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/*---------------------------------------------------------------------------*/
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static void
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init_ports(void)
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{
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@ -258,12 +198,22 @@ init_ports(void)
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P6OUT = 0;
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#endif
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#ifdef P7DIR
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P7DIR = 0;
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P7OUT = 0;
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#endif
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#ifdef P8DIR
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P8DIR = 0;
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P8OUT = 0;
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#endif
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P1IE = 0;
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P2IE = 0;
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}
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/*---------------------------------------------------------------------------*/
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/* msp430-ld may align _end incorrectly. Workaround in cpu_init. */
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#ifdef __GNUC__
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#if defined(__MSP430__) && defined(__GNUC__)
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extern int _end; /* Not in sys/unistd.h */
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static char *cur_break = (char *)&_end;
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#endif
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@ -276,7 +226,7 @@ msp430_cpu_init(void)
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init_ports();
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msp430_quick_synch_dco();
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eint();
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#ifdef __GNUC__
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#if defined(__MSP430__) && defined(__GNUC__)
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if((uintptr_t)cur_break & 1) { /* Workaround for msp430-ld bug! */
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cur_break++;
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}
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@ -284,8 +234,6 @@ msp430_cpu_init(void)
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}
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/*---------------------------------------------------------------------------*/
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#define STACK_EXTRA 32
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/*---------------------------------------------------------------------------*/
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/*
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* Mask all interrupts that can be masked.
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@ -308,17 +256,33 @@ splhigh_(void)
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/*
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* Restore previous interrupt mask.
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*/
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void
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splx_(int sr)
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{
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#ifdef __IAR_SYSTEMS_ICC__
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__bis_SR_register(sr);
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#else
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/* If GIE was set, restore it. */
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asmv("bis %0, r2" : : "r" (sr));
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#endif
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}
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/* void */
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/* splx_(int sr) */
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/* { */
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/* #ifdef __IAR_SYSTEMS_ICC__ */
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/* __bis_SR_register(sr); */
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/* #else */
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/* /\* If GIE was set, restore it. *\/ */
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/* asmv("bis %0, r2" : : "r" (sr)); */
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/* #endif */
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/* } */
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/*---------------------------------------------------------------------------*/
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#ifdef __IAR_SYSTEMS_ICC__
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int __low_level_init(void)
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{
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/* turn off watchdog so that C-init will run */
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WDTCTL = WDTPW + WDTHOLD;
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/*
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* Return value:
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*
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* 1 - Perform data segment initialization.
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* 0 - Skip data segment initialization.
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*/
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return 1;
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}
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#endif
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/*---------------------------------------------------------------------------*/
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#if DCOSYNCH_CONF_ENABLED
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/* this code will always start the TimerB if not already started */
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void
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msp430_sync_dco(void) {
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@ -358,11 +322,12 @@ msp430_sync_dco(void) {
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if(DCOCTL == 0xFF) { /* Did DCO role under? */
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BCSCTL1--;
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}
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} else if (DELTA_2 > diff) {
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} else if(DELTA_2 > diff) {
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DCOCTL++;
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if(DCOCTL == 0x00) { /* Did DCO role over? */
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BCSCTL1++;
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}
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}
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}
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#endif /* DCOSYNCH_CONF_ENABLED */
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/*---------------------------------------------------------------------------*/
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