Commit Graph

6 Commits

Author SHA1 Message Date
Benoît Thébaudeau
5261bb861d cc2538: lpm: Fix RTIMER_NOW() upon wake-up
When returning from PM1/2, the sleep timer value (used by RTIMER_NOW()) is not
up-to-date until a positive edge on the 32-kHz clock has been detected after the
system clock restarted. To ensure an updated value is read, wait for a positive
transition on the 32-kHz clock by polling the SYS_CTRL_CLOCK_STA.SYNC_32K bit,
before reading the sleep timer value.

Because of this RTIMER_NOW() fixup, lpm_exit() has to be called at the very
beginning of ISRs waking up the SoC. This also ensures that all clocks and
timers are enabled at the correct frequency and updated before using them
following wake-up.

Without this fix, etimers could sometimes (randomly, depending on timings)
become ultra slow (observed from 10x to 40x slower than normal) if the system
exited PM1/2 very often. This issue occurred more often with PM1.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-12-05 20:23:29 +01:00
Benoît Thébaudeau
621f4f7339 cc2538: lpm: Give access to the SRAM non-retention area for PM2
If PM2 is enabled with LPM_CONF_MAX_PM, but not active, the non-retention area
of the SRAM can be useful to place temporary data that does not fit in the
low-leakage SRAM, typically after having called lpm_set_max_pm(LPM_PM1). Hence,
give access to this non-retention area thanks to .nrdata* sections.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-11-25 15:43:37 +01:00
Benoît Thébaudeau
b8b54a033c cc2538: uart: Fix crippled output occurring upon lpm_enter()
lpm_enter() must not enter PM1+ if the UART TX FIFO is not empty. Otherwise, the
UART clock gets disabled, and its TX is broken.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-11-15 17:24:26 +01:00
Benoît Thébaudeau
0692ee251d cc2538: usb: Use the new LPM peripheral registration
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-11-15 17:14:45 +01:00
Benoît Thébaudeau
d35732505b cc2538: lpm: Add registration mechanism for peripherals
Some peripherals have their clocks automatically gated in PM1+ modes, so they
cannot operate. This new mechanism gives peripherals a way to prohibit PM1+
modes so that they can properly complete their current operations before
entering PM1+.

This mechanism is implemented with peripheral functions registered to the LPM
module. These functions return whether the associated peripheral permits or not
PM1+ modes. They are called by the LPM module each time PM1+ might be possible.
If any of the peripherals wants to block PM1+, then the system is only dropped
to PM0.

Partly from: George Oikonomou
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-11-15 17:09:22 +01:00
George Oikonomou
40f49948e6 New Platform: TI CC2538 Development Kit
This commit adds cpu, platform and example files,
providing support for running Contiki on TI's cc2538 DK
2013-04-06 21:07:31 +01:00