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abeed93da5
This patch adds a simple, space-efficient driver for the Ethernet interface built into the Intel Quark X1000. It only allocates a single packet descriptor for each of the transmit and receive directions, computes checksums on the CPU, and enables store-and-forward mode for both transmit and receive directions.
373 lines
13 KiB
C
373 lines
13 KiB
C
/*
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* Copyright (C) 2015, Intel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <string.h>
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#include <assert.h>
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#include <stdio.h>
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#include "contiki-net.h"
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#include "eth.h"
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#include "helpers.h"
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#include "net/ip/uip.h"
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#include "pci.h"
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typedef pci_driver_t quarkX1000_eth_driver_t;
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/* Refer to Intel Quark SoC X1000 Datasheet, Chapter 15 for more details on
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* Ethernet device operation.
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*
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* This driver puts the Ethernet device into a very simple and space-efficient
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* mode of operation. It only allocates a single packet descriptor for each of
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* the transmit and receive directions, computes checksums on the CPU, and
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* enables store-and-forward mode for both transmit and receive directions.
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*/
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/* Transmit descriptor */
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typedef struct quarkX1000_eth_tx_desc {
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/* First word of transmit descriptor */
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union {
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struct {
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/* Only valid in half-duplex mode. */
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uint32_t deferred_bit : 1;
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uint32_t err_underflow : 1;
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uint32_t err_excess_defer : 1;
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uint32_t coll_cnt_slot_num : 4;
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uint32_t vlan_frm : 1;
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uint32_t err_excess_coll : 1;
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uint32_t err_late_coll : 1;
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uint32_t err_no_carrier : 1;
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uint32_t err_carrier_loss : 1;
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uint32_t err_ip_payload : 1;
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uint32_t err_frm_flushed : 1;
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uint32_t err_jabber_tout : 1;
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/* OR of all other error bits. */
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uint32_t err_summary : 1;
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uint32_t err_ip_hdr : 1;
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uint32_t tx_timestamp_stat : 1;
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uint32_t vlan_ins_ctrl : 2;
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uint32_t addr2_chained : 1;
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uint32_t tx_end_of_ring : 1;
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uint32_t chksum_ins_ctrl : 2;
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uint32_t replace_crc : 1;
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uint32_t tx_timestamp_en : 1;
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uint32_t dis_pad : 1;
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uint32_t dis_crc : 1;
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uint32_t first_seg_in_frm : 1;
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uint32_t last_seg_in_frm : 1;
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uint32_t intr_on_complete : 1;
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/* When set, descriptor is owned by DMA. */
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uint32_t own : 1;
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};
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uint32_t tdes0;
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};
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/* Second word of transmit descriptor */
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union {
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struct {
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uint32_t tx_buf1_sz : 13;
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uint32_t : 3;
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uint32_t tx_buf2_sz : 13;
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uint32_t src_addr_ins_ctrl : 3;
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};
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uint32_t tdes1;
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};
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/* Pointer to frame data buffer */
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uint8_t *buf1_ptr;
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/* Unused, since this driver initializes only a single descriptor for each
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* direction.
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*/
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uint8_t *buf2_ptr;
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} quarkX1000_eth_tx_desc_t;
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/* Transmit descriptor */
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typedef struct quarkX1000_eth_rx_desc {
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/* First word of receive descriptor */
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union {
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struct {
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uint32_t ext_stat : 1;
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uint32_t err_crc : 1;
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uint32_t err_dribble_bit : 1;
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uint32_t err_rx_mii : 1;
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uint32_t err_rx_wdt : 1;
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uint32_t frm_type : 1;
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uint32_t err_late_coll : 1;
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uint32_t giant_frm : 1;
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uint32_t last_desc : 1;
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uint32_t first_desc : 1;
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uint32_t vlan_tag : 1;
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uint32_t err_overflow : 1;
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uint32_t length_err : 1;
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uint32_t s_addr_filt_fail : 1;
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uint32_t err_desc : 1;
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uint32_t err_summary : 1;
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uint32_t frm_len : 14;
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uint32_t d_addr_filt_fail : 1;
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uint32_t own : 1;
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};
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uint32_t rdes0;
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};
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/* Second word of receive descriptor */
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union {
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struct {
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uint32_t rx_buf1_sz : 13;
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uint32_t : 1;
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uint32_t addr2_chained : 1;
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uint32_t rx_end_of_ring : 1;
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uint32_t rx_buf2_sz : 13;
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uint32_t : 2;
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uint32_t dis_int_compl : 1;
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};
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uint32_t rdes1;
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};
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/* Pointer to frame data buffer */
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uint8_t *buf1_ptr;
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/* Unused, since this driver initializes only a single descriptor for each
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* direction.
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*/
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uint8_t *buf2_ptr;
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} quarkX1000_eth_rx_desc_t;
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/* Driver metadata associated with each Ethernet device */
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typedef struct quarkX1000_eth_meta {
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/* Transmit descriptor */
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volatile quarkX1000_eth_tx_desc_t tx_desc;
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/* Transmit DMA packet buffer */
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volatile uint8_t tx_buf[UIP_BUFSIZE];
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/* Receive descriptor */
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volatile quarkX1000_eth_rx_desc_t rx_desc;
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/* Receive DMA packet buffer */
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volatile uint8_t rx_buf[UIP_BUFSIZE];
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} quarkX1000_eth_meta_t;
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#define LOG_PFX "quarkX1000_eth: "
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#define MMIO_SZ 0x2000
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#define MAC_CONF_14_RMII_100M BIT(14)
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#define MAC_CONF_11_DUPLEX BIT(11)
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#define MAC_CONF_3_TX_EN BIT(3)
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#define MAC_CONF_2_RX_EN BIT(2)
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#define OP_MODE_25_RX_STORE_N_FORWARD BIT(25)
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#define OP_MODE_21_TX_STORE_N_FORWARD BIT(21)
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#define OP_MODE_13_START_TX BIT(13)
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#define OP_MODE_1_START_RX BIT(1)
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#define REG_ADDR_MAC_CONF 0x0000
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#define REG_ADDR_MACADDR_HI 0x0040
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#define REG_ADDR_MACADDR_LO 0x0044
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#define REG_ADDR_TX_POLL_DEMAND 0x1004
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#define REG_ADDR_RX_POLL_DEMAND 0x1008
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#define REG_ADDR_RX_DESC_LIST 0x100C
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#define REG_ADDR_TX_DESC_LIST 0x1010
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#define REG_ADDR_DMA_OPERATION 0x1018
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static quarkX1000_eth_driver_t drv;
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static quarkX1000_eth_meta_t meta;
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/*---------------------------------------------------------------------------*/
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/**
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* \brief Initialize the first Quark X1000 Ethernet MAC.
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*
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* This procedure assumes that an MMIO range for the device was
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* previously assigned, e.g. by firmware.
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*/
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void
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quarkX1000_eth_init(void)
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{
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pci_config_addr_t pci_addr = { .raw = 0 };
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uip_eth_addr mac_addr;
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uint32_t mac_tmp1, mac_tmp2;
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/* PCI address from section 15.4 of Intel Quark SoC X1000 Datasheet. */
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pci_addr.dev = 20;
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pci_addr.func = 6;
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/* Activate MMIO and DMA access. */
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pci_command_enable(pci_addr, PCI_CMD_2_BUS_MST_EN | PCI_CMD_1_MEM_SPACE_EN);
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printf(LOG_PFX "Activated MMIO and DMA access.\n");
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pci_addr.reg_off = PCI_CONFIG_REG_BAR0;
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/* Configure the device MMIO range and initialize the driver structure. */
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pci_init(&drv, pci_addr, (uintptr_t)&meta);
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/* Read the MAC address from the device. */
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PCI_MMIO_READL(drv, mac_tmp1, REG_ADDR_MACADDR_HI);
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PCI_MMIO_READL(drv, mac_tmp2, REG_ADDR_MACADDR_LO);
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/* Convert the data read from the device into the format expected by
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* Contiki.
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*/
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mac_addr.addr[5] = (uint8_t)(mac_tmp1 >> 8);
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mac_addr.addr[4] = (uint8_t)mac_tmp1;
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mac_addr.addr[3] = (uint8_t)(mac_tmp2 >> 24);
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mac_addr.addr[2] = (uint8_t)(mac_tmp2 >> 16);
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mac_addr.addr[1] = (uint8_t)(mac_tmp2 >> 8);
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mac_addr.addr[0] = (uint8_t)mac_tmp2;
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printf(LOG_PFX "MAC address = %02x:%02x:%02x:%02x:%02x:%02x.\n",
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mac_addr.addr[0],
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mac_addr.addr[1],
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mac_addr.addr[2],
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mac_addr.addr[3],
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mac_addr.addr[4],
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mac_addr.addr[5]
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);
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uip_setethaddr(mac_addr);
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/* Initialize transmit descriptor. */
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meta.tx_desc.tdes0 = 0;
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meta.tx_desc.tdes1 = 0;
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meta.tx_desc.buf1_ptr = (uint8_t *)meta.tx_buf;
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meta.tx_desc.tx_end_of_ring = 1;
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meta.tx_desc.first_seg_in_frm = 1;
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meta.tx_desc.last_seg_in_frm = 1;
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meta.tx_desc.tx_end_of_ring = 1;
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/* Initialize receive descriptor. */
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meta.rx_desc.rdes0 = 0;
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meta.rx_desc.rdes1 = 0;
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meta.rx_desc.buf1_ptr = (uint8_t *)meta.rx_buf;
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meta.rx_desc.own = 1;
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meta.rx_desc.first_desc = 1;
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meta.rx_desc.last_desc = 1;
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meta.rx_desc.rx_buf1_sz = UIP_BUFSIZE;
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meta.rx_desc.rx_end_of_ring = 1;
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/* Install transmit and receive descriptors. */
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PCI_MMIO_WRITEL(drv, REG_ADDR_RX_DESC_LIST, (uint32_t)&meta.rx_desc);
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PCI_MMIO_WRITEL(drv, REG_ADDR_TX_DESC_LIST, (uint32_t)&meta.tx_desc);
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PCI_MMIO_WRITEL(drv, REG_ADDR_MAC_CONF,
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/* Set the RMII speed to 100Mbps */
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MAC_CONF_14_RMII_100M |
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/* Enable full-duplex mode */
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MAC_CONF_11_DUPLEX |
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/* Enable transmitter */
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MAC_CONF_3_TX_EN |
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/* Enable receiver */
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MAC_CONF_2_RX_EN);
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PCI_MMIO_WRITEL(drv, REG_ADDR_DMA_OPERATION,
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/* Enable receive store-and-forward mode for simplicity. */
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OP_MODE_25_RX_STORE_N_FORWARD |
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/* Enable transmit store-and-forward mode for simplicity. */
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OP_MODE_21_TX_STORE_N_FORWARD |
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/* Place the transmitter state machine in the Running
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state. */
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OP_MODE_13_START_TX |
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/* Place the receiver state machine in the Running state. */
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OP_MODE_1_START_RX);
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printf(LOG_PFX "Enabled 100M full-duplex mode.\n");
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}
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/*---------------------------------------------------------------------------*/
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/**
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* \brief Poll for a received Ethernet frame.
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* \param frame_len Will be set to the size of the received Ethernet frame or
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* zero if no frame is available.
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*
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* If a frame is received, this procedure copies it into the
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* global uip_buf buffer.
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*/
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void
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quarkX1000_eth_poll(uint16_t *frame_len)
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{
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uint16_t frm_len = 0;
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/* Check whether the RX descriptor is still owned by the device. If not,
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* process the received frame or an error that may have occurred.
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*/
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if(meta.rx_desc.own == 0) {
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if(meta.rx_desc.err_summary) {
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fprintf(stderr,
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LOG_PFX "Error receiving frame: RDES0 = %08x, RDES1 = %08x.\n",
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meta.rx_desc.rdes0, meta.rx_desc.rdes1);
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assert(0);
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}
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frm_len = meta.rx_desc.frm_len;
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assert(frm_len <= UIP_BUFSIZE);
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memcpy(uip_buf, (void *)meta.rx_buf, frm_len);
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/* Return ownership of the RX descriptor to the device. */
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meta.rx_desc.own = 1;
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/* Request that the device check for an available RX descriptor, since
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* ownership of the descriptor was just transferred to the device.
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*/
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PCI_MMIO_WRITEL(drv, REG_ADDR_RX_POLL_DEMAND, 1);
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}
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*frame_len = frm_len;
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}
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/*---------------------------------------------------------------------------*/
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/**
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* \brief Transmit the current Ethernet frame.
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*
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* This procedure will block indefinitely until the Ethernet device is
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* ready to accept a new outgoing frame. It then copies the current
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* Ethernet frame from the global uip_buf buffer to the device DMA
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* buffer and signals to the device that a new frame is available to be
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* transmitted.
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*/
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void
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quarkX1000_eth_send(void)
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{
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/* Wait until the TX descriptor is no longer owned by the device. */
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while(meta.tx_desc.own == 1);
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/* Check whether an error occurred transmitting the previous frame. */
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if(meta.tx_desc.err_summary) {
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fprintf(stderr,
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LOG_PFX "Error transmitting frame: TDES0 = %08x, TDES1 = %08x.\n",
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meta.tx_desc.tdes0, meta.tx_desc.tdes1);
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assert(0);
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}
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/* Transmit the next frame. */
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assert(uip_len <= UIP_BUFSIZE);
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memcpy((void *)meta.tx_buf, uip_buf, uip_len);
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meta.tx_desc.tx_buf1_sz = uip_len;
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meta.tx_desc.own = 1;
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/* Request that the device check for an available TX descriptor, since
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* ownership of the descriptor was just transferred to the device.
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*/
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PCI_MMIO_WRITEL(drv, REG_ADDR_TX_POLL_DEMAND, 1);
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}
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/*---------------------------------------------------------------------------*/
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