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This patch implements a simple, lightweight form of protection domains using a pluggable framework. Currently, the following plugin is available: - Flat memory model with paging. The overall goal of a protection domain implementation within this framework is to define a set of resources that should be accessible to each protection domain and to prevent that protection domain from accessing other resources. The details of each implementation of protection domains may differ substantially, but they should all be guided by the principle of least privilege. However, that idealized principle is balanced against the practical objectives of limiting the number of relatively time-consuming context switches and minimizing changes to existing code. For additional information, please refer to cpu/x86/mm/README.md. This patch also causes the C compiler to be used as the default linker and assembler.
298 lines
9.2 KiB
C
298 lines
9.2 KiB
C
/*
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* Copyright (C) 2015, Intel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <string.h>
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#include "dma.h"
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#include "gdt.h"
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#include "gdt-layout.h"
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#include "helpers.h"
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#include "idt.h"
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#include "paging.h"
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#include "prot-domains.h"
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#include "segmentation.h"
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#include "stacks.h"
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#include "syscalls.h"
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#include "tss.h"
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/*#define DBG_PAGE_ALLOC*/
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/* Enable PAE-mode paging */
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#define CR4_PAE BIT(5)
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/* Extended Feature Enables MSR */
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#define MSR_EFER 0xC0000080
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/* Enable Execute Disable bit support */
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#define EFER_NXE BIT(11)
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/* Root page-directory-pointer table */
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static pdpt_t root_pgtbl __attribute__((aligned(32))) ATTR_BSS_KERN;
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/* Although the following page tables must be page-aligned, it is infeasible to
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* apply the "aligned(4096)" attribute for the reasons described in the linker
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* script.
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*/
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/* Second-level page directory */
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static page_table_t
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second_lvl_pgtbl ATTR_BSS_KERN_PAGE_ALIGNED;
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/* Leaf-level page table */
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static page_table_t leaf_pgtbl ATTR_BSS_KERN_PAGE_ALIGNED;
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#define LINEAR_ADDR_BOUND (MIN_PAGE_SIZE * ENTRIES_PER_PAGE_TABLE)
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/*---------------------------------------------------------------------------*/
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void
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prot_domains_reg(dom_client_data_t *dcd,
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uintptr_t mmio,
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size_t mmio_sz,
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uintptr_t meta,
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size_t meta_sz,
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bool pio)
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{
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dom_id_t dom_id = dcd->dom_id;
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volatile struct dom_kern_data *dkd =
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prot_domains_kern_data + dom_id;
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/* All addresses and sizes must be page-aligned */
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if((PROT_DOMAINS_ACTUAL_CNT <= dom_id) ||
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((mmio & (MIN_PAGE_SIZE - 1)) != 0) ||
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((mmio_sz & (MIN_PAGE_SIZE - 1)) != 0) ||
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((meta & (MIN_PAGE_SIZE - 1)) != 0) ||
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((meta_sz & (MIN_PAGE_SIZE - 1)) != 0) ||
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(PROT_DOMAINS_MAX_MMIO_SZ < mmio_sz) ||
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(LINEAR_ADDR_BOUND < (PROT_DOMAINS_META_LINEAR_BASE + meta_sz))) {
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halt();
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}
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if((dkd->flags & PROT_DOMAINS_FLAG_INITED) == PROT_DOMAINS_FLAG_INITED) {
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halt();
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}
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dkd->mmio = mmio;
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dkd->mmio_sz = mmio_sz;
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dkd->meta = meta;
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dkd->meta_sz = meta_sz;
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dkd->flags = PROT_DOMAINS_FLAG_INITED;
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if(pio) {
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dkd->flags |= PROT_DOMAINS_FLAG_PIO;
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}
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}
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/*---------------------------------------------------------------------------*/
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static void __attribute__((regparm(3)))
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set_ptes(uintptr_t start_la, uintptr_t start_pa, uintptr_t end_pa,
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pte_t template)
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{
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#ifdef DBG_PAGE_ALLOC
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#warning Checking page allocations at runtime.
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if(((start_la & (MIN_PAGE_SIZE - 1)) != 0) ||
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((start_pa & (MIN_PAGE_SIZE - 1)) != 0) ||
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((start_la & (MIN_PAGE_SIZE - 1)) != 0) ||
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((end_pa & (MIN_PAGE_SIZE - 1)) != 0) ||
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(LINEAR_ADDR_BOUND <= (start_la + (end_pa - start_pa)))) {
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halt();
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}
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#endif
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while(start_pa < end_pa) {
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template.addr = start_pa >> 12;
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leaf_pgtbl[start_la >> MIN_PAGE_SIZE_SHAMT] = template;
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#ifdef X86_CONF_USE_INVLPG
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__asm__("invlpg %0" :: "m" (*(uint8_t *)start_la));
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#endif
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start_la += MIN_PAGE_SIZE;
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start_pa += MIN_PAGE_SIZE;
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}
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}
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/*---------------------------------------------------------------------------*/
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static void __attribute__((fastcall))
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set_ptes_identity_map(uintptr_t start_pa, uintptr_t end_pa, pte_t template)
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{
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set_ptes(start_pa, start_pa, end_pa, template);
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}
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/*---------------------------------------------------------------------------*/
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static inline uint32_t __attribute__((always_inline))
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prot_domains_switch(dom_id_t from_id, dom_id_t to_id,
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interrupt_stack_t *intr_stk)
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{
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volatile dom_kern_data_t *from, *to;
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from = prot_domains_kern_data + from_id;
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to = prot_domains_kern_data + to_id;
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if((from_id == DOM_ID_kern) ||
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(to_id == DOM_ID_kern)) {
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pte_t to_kern_data_pte = { .raw = 0 };
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to_kern_data_pte.present = 1;
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to_kern_data_pte.exec_disable = 1;
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/* The kernel data region should always be accessible to supervisory code,
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* but it is only accessible to user mode in the kernel protection domain.
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*/
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to_kern_data_pte.user_accessible = 1;
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if(to_id == DOM_ID_kern) {
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to_kern_data_pte.writable = 1;
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}
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set_ptes_identity_map((uintptr_t)&_sbss_kern_addr,
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(uintptr_t)&_ebss_syscall_addr,
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to_kern_data_pte);
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if(to_id != DOM_ID_kern) {
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to_kern_data_pte.user_accessible = 0;
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to_kern_data_pte.writable = 0;
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}
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set_ptes_identity_map((uintptr_t)&_ebss_syscall_addr,
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(uintptr_t)&_ebss_kern_addr,
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to_kern_data_pte);
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}
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if(to->mmio_sz != 0) {
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pte_t pte = { .raw = 0 };
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pte.present = 1;
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pte.exec_disable = 1;
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pte.user_accessible = 1;
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pte.writable = 1;
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/* disable caching of MMIO accesses */
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pte.pcd = 1;
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set_ptes(PROT_DOMAINS_MMIO_LINEAR_BASE,
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to->mmio,
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to->mmio + to->mmio_sz,
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pte);
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}
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if(to->mmio_sz < from->mmio_sz) {
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pte_t pte = { .raw = 0 };
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set_ptes_identity_map(PROT_DOMAINS_MMIO_LINEAR_BASE + to->mmio_sz,
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PROT_DOMAINS_MMIO_LINEAR_BASE + from->mmio_sz,
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pte);
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}
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if(to->meta_sz != 0) {
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pte_t pte = { .raw = 0 };
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pte.present = 1;
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pte.exec_disable = 1;
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pte.user_accessible = 1;
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pte.writable = 1;
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set_ptes(PROT_DOMAINS_META_LINEAR_BASE,
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to->meta,
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to->meta + to->meta_sz,
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pte);
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}
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if(to->meta_sz < from->meta_sz) {
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pte_t pte = { .raw = 0 };
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set_ptes_identity_map(PROT_DOMAINS_META_LINEAR_BASE + to->mmio_sz,
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PROT_DOMAINS_META_LINEAR_BASE + from->mmio_sz,
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pte);
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}
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#ifndef X86_CONF_USE_INVLPG
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__asm__ __volatile__ ("mov %%cr3, %%eax\n\t"
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"mov %%eax, %%cr3\n\t" ::: "eax");
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#endif
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return 0;
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}
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/*---------------------------------------------------------------------------*/
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void
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prot_domains_gdt_init(void)
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{
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gdt_copy_desc_change_dpl(GDT_IDX_DATA, GDT_IDX_DATA_FLAT, PRIV_LVL_USER);
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gdt_copy_desc_change_dpl(GDT_IDX_STK_INT, GDT_IDX_STK_EXC, PRIV_LVL_INT);
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}
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/*---------------------------------------------------------------------------*/
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void
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prot_domains_impl_init(void)
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{
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pte_t pte = { .raw = 0 };
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syscalls_int_init();
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/* Initialize page table: */
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pte.present = 1;
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pte.addr = ((uint32_t)second_lvl_pgtbl) >> MIN_PAGE_SIZE_SHAMT;
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root_pgtbl[0] = pte;
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pte.writable = 1;
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pte.user_accessible = 1;
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pte.addr = ((uint32_t)leaf_pgtbl) >> MIN_PAGE_SIZE_SHAMT;
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second_lvl_pgtbl[0] = pte;
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/* Map code sections: */
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pte.writable = 0;
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set_ptes_identity_map((uintptr_t)&_stext_addr, (uintptr_t)&_etext_addr, pte);
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/* Map data sections: */
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pte.writable = 1;
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pte.exec_disable = 1;
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set_ptes_identity_map((uintptr_t)stacks_main,
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(uintptr_t)stacks_main +
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STACKS_SIZE_MAIN +
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STACKS_SIZE_EXC +
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STACKS_SIZE_INT,
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pte);
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set_ptes_identity_map((uintptr_t)&_sdata_addr, (uintptr_t)&_edata_addr, pte);
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/* Enable XD bit support */
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__asm__ __volatile__ ("wrmsr" :: "c" (MSR_EFER), "a" (EFER_NXE), "d" (0));
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/* Enable PAE */
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__asm__ __volatile__ ("mov %%cr4, %%eax\n\t"
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"or %0, %%eax\n\t"
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"mov %%eax, %%cr4\n\t"
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:
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: "r" (CR4_PAE)
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: "eax");
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/* Load CR3 */
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__asm__ __volatile__ ("mov %0, %%cr3" :: "r" (root_pgtbl));
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}
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/*---------------------------------------------------------------------------*/
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uintptr_t
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prot_domains_lookup_meta_phys_base(dom_client_data_t *drv)
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{
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return prot_domains_kern_data[drv->dom_id].meta;
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}
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/*---------------------------------------------------------------------------*/
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/* Enable inter-procedural optimization with procedures in the following file:
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*/
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#include "syscalls-int.c"
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