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This patch extends the protection domain framework with a third plugin that is a hybrid of the previous two. The hardware task switching mechanism has a strictly-defined format for TSS data structures that causes more space to be consumed than would otherwise be required. This patch defines a smaller data structure that is allocated for each protection domain, only requiring 32 bytes instead of 128 bytes. It uses the same multi-segment memory layout as the TSS-based plugin and leaves paging disabled. However, it uses a similar mechanism as the paging plugin to perform system call dispatches and returns. For additional information, please refer to cpu/x86/mm/README.md.
110 lines
4.3 KiB
C
110 lines
4.3 KiB
C
/*
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* Copyright (C) 2015, Intel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef CPU_X86_MM_STACKS_H_
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#define CPU_X86_MM_STACKS_H_
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#include "prot-domains.h"
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#if X86_CONF_PROT_DOMAINS == X86_CONF_PROT_DOMAINS__NONE
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#define STACKS_SIZE_INT 0
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#else
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/**
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* The necessary amount of space for the interrupt and exception stacks is
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* determined by the amount of data pushed on the stack by the CPU when
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* delivering an interrupt or exception, and by the additional data pushed
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* on the stack by the interrupt dispatcher. See interrupt.h for more details.
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*/
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#define STACKS_SIZE_INT (14 * 4)
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#endif
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#if X86_CONF_PROT_DOMAINS == X86_CONF_PROT_DOMAINS__PAGING
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/**
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* The system call and return dispatchers use this stack, so its size was
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* determined by observing their behavior. It is possible that the dispatchers
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* could overflow the stack and overwrite data on the other stacks. An
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* alternative design that would facilitate detection of such overflows would
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* place the exception handler stack on a separate page surrounded by guard
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* bands, but that would consume a substantial amount of additional memory.
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*
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* All stack sizes should be a multiple of 4 to accommodate a 4-byte alignment.
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*/
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#ifdef __clang__
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#define STACKS_SIZE_EXC 512
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#else
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#define STACKS_SIZE_EXC 256
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#endif
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#elif X86_CONF_PROT_DOMAINS == X86_CONF_PROT_DOMAINS__SWSEG
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#ifdef __clang__
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#define STACKS_SIZE_EXC 512
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#else
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#define STACKS_SIZE_EXC 256
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#endif
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#elif X86_CONF_PROT_DOMAINS == X86_CONF_PROT_DOMAINS__TSS
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/**
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* This should be large enough to execute the exception handler with the
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* largest stack requirement: double_fault_handler:
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* - 1 word for the return address from calling double_fault_handler
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* - 1 word for the saved frame pointer in double_fault_handler
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* - 2 words that GCC has been observed to skip on the stack to align it
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* to a preferred boundary
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* - 1 word for the return address for calling halt
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*/
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#define STACKS_SIZE_EXC (STACKS_SIZE_INT + (6 * 4))
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#else
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#define STACKS_SIZE_EXC STACKS_SIZE_INT
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#endif
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/**
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* The combined size of the stacks should be an even multiple of the 4K page
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* size so that they precisely fill some number of pages when paging-based
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* protection domains are in use. The stacks are arranged contiguously by
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* the linker scripts. See those and README.md for more details.
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*/
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#define STACKS_SIZE_MAIN (8192 - (STACKS_SIZE_INT + STACKS_SIZE_EXC))
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#if !__ASSEMBLER__
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/**
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* Stack for exception handlers. Also used for system call and return
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* dispatchers when paging-based protection domains are enabled.
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*/
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extern uint8_t stacks_exc[STACKS_SIZE_EXC];
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/** Stack for interrupt handlers. */
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extern uint8_t stacks_int[STACKS_SIZE_INT];
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/** Main C stack. */
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extern uint8_t stacks_main[STACKS_SIZE_MAIN];
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#define STACKS_INIT_TOP \
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((uintptr_t)stacks_main + STACKS_SIZE_MAIN - \
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(PROT_DOMAINS_INIT_RET_ADDR_CNT * sizeof(uintptr_t)))
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#endif
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#endif /* CPU_X86_MM_STACKS_H_ */
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