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This commit: * Moves all cpu files from cpu/cc26xx to cpu/cc26xx-cc13xx * Bumps the CC26xxware submodule to the latest TI release * Adds CC13xxware as a submodule * Adds support for sub-ghz mode / IEEE 802.15.4g * Splits the driver into multiple files for clarity. We now have the following structure: * A common module that handles access to the RF core, interrupts etc * A module that takes care of BLE functionality * A netstack radio driver for IEEE mode (2.4GHz) * A netstack radio driver for PROP mode (sub-ghz - multiple bands) This commit also adds tick suppression functionality, applicable to all chips of the CC26xx and CC13xx families. Instead waking up on every clock tick simply to increment our software counter, we now only wake up just in time to service the next scheduled etimer. ContikiMAC-triggered wakeups are unaffected. Laslty, this commit also applies a number of minor changes: * Addition of missing includes * Removal of stub functions * Removal of a woraround for a CC26xxware bug that has now been fixed
230 lines
6.9 KiB
C
230 lines
6.9 KiB
C
/*
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* Copyright (c) 2014, Texas Instruments Incorporated - http://www.ti.com/
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*---------------------------------------------------------------------------*/
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/**
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* \addtogroup platform
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* @{
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*
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* \defgroup cc26xx-platforms TI CC26xx-powered Platforms
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* @{
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*
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* \defgroup cc26xx The TI CC26xx and CC13xx CPUs
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*
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* This group documents the TI CC26xx and CC13xx CPUs. The two CPU families are
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* very similar, with the main difference being related to radio capability.
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*
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* Documentation in this group should be considered to be applicable to both
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* families, unless explicitly stated otherwise.
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*
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* @{
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*
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* \addtogroup cc26xx-clocks
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* @{
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*
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* \defgroup cc26xx-software-clock Software Clock
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*
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* Implementation of the clock module for the CC26xx and CC13xx.
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*
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* The software clock uses the facilities provided by the AON RTC driver
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* @{
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*
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* \file
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* Software clock implementation for the TI CC13xx/CC26xx
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*/
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/*---------------------------------------------------------------------------*/
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#include "contiki.h"
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#include "ti-lib.h"
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/*---------------------------------------------------------------------------*/
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static volatile uint64_t count;
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/*---------------------------------------------------------------------------*/
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static void
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power_domain_on(void)
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{
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ti_lib_prcm_power_domain_on(PRCM_DOMAIN_PERIPH);
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while(ti_lib_prcm_power_domain_status(PRCM_DOMAIN_PERIPH) !=
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PRCM_DOMAIN_POWER_ON);
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}
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/*---------------------------------------------------------------------------*/
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void
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clock_init(void)
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{
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count = 0;
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/*
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* Here, we configure GPT0 Timer A, which we subsequently use in
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* clock_delay_usec
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*
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* We need to access registers, so firstly power up the PD and then enable
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* the clock to GPT0.
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*/
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if(ti_lib_prcm_power_domain_status(PRCM_DOMAIN_PERIPH) !=
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PRCM_DOMAIN_POWER_ON) {
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power_domain_on();
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}
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ti_lib_prcm_peripheral_run_enable(PRCM_PERIPH_TIMER0);
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ti_lib_prcm_load_set();
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while(!ti_lib_prcm_load_get());
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/* Disable both GPT0 timers */
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HWREG(GPT0_BASE + GPT_O_CTL) &= ~(GPT_CTL_TAEN | GPT_CTL_TBEN);
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/*
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* We assume that the clock is running at 48MHz, we use GPT0 Timer A,
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* one-shot, countdown, prescaled by 48 gives us 1 tick per usec
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*/
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ti_lib_timer_configure(GPT0_BASE,
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TIMER_CFG_SPLIT_PAIR | TIMER_CFG_B_ONE_SHOT);
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/* Global config: split pair (2 x 16-bit wide) */
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HWREG(GPT0_BASE + GPT_O_CFG) = TIMER_CFG_SPLIT_PAIR >> 24;
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/*
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* Pre-scale value 47 pre-scales by 48
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*
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* ToDo: The theoretical value here should be 47 (to provide x48 prescale)
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* However, 49 seems to give results much closer to the desired delay
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*/
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ti_lib_timer_prescale_set(GPT0_BASE, TIMER_B, 49);
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/* GPT0 / Timer B: One shot, PWM interrupt enable */
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HWREG(GPT0_BASE + GPT_O_TBMR) =
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((TIMER_CFG_B_ONE_SHOT >> 8) & 0xFF) | GPT_TBMR_TBPWMIE;
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}
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/*---------------------------------------------------------------------------*/
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CCIF clock_time_t
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clock_time(void)
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{
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return (clock_time_t)(count & 0xFFFFFFFF);
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}
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/*---------------------------------------------------------------------------*/
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void
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clock_update(void)
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{
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bool interrupts_disabled;
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uint32_t aon_rtc_secs_now;
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uint16_t aon_rtc_ticks_now;
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interrupts_disabled = ti_lib_int_master_disable();
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aon_rtc_secs_now = HWREG(AON_RTC_BASE + AON_RTC_O_SEC);
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aon_rtc_ticks_now = HWREG(AON_RTC_BASE + AON_RTC_O_SUBSEC) >> 16;
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/* Convert AON RTC ticks to clock tick counter */
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count = (aon_rtc_secs_now * CLOCK_SECOND) + (aon_rtc_ticks_now >> 9);
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/* Re-enable interrupts */
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if(!interrupts_disabled) {
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ti_lib_int_master_enable();
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}
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if(etimer_pending()) {
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etimer_request_poll();
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}
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}
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/*---------------------------------------------------------------------------*/
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CCIF unsigned long
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clock_seconds(void)
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{
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bool interrupts_disabled;
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uint32_t secs_now;
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interrupts_disabled = ti_lib_int_master_disable();
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secs_now = ti_lib_aon_rtc_sec_get();
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/* Re-enable interrupts */
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if(!interrupts_disabled) {
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ti_lib_int_master_enable();
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}
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return (unsigned long)secs_now;
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}
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/*---------------------------------------------------------------------------*/
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void
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clock_wait(clock_time_t i)
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{
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clock_time_t start;
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start = clock_time();
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while(clock_time() - start < (clock_time_t)i);
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}
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/*---------------------------------------------------------------------------*/
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void
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clock_delay_usec(uint16_t len)
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{
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uint32_t clock_status;
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if(ti_lib_prcm_power_domain_status(PRCM_DOMAIN_PERIPH) !=
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PRCM_DOMAIN_POWER_ON) {
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power_domain_on();
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}
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clock_status = HWREG(PRCM_BASE + PRCM_O_GPTCLKGR) & PRCM_GPIOCLKGR_CLK_EN;
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ti_lib_prcm_peripheral_run_enable(PRCM_PERIPH_TIMER0);
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ti_lib_prcm_load_set();
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while(!ti_lib_prcm_load_get());
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ti_lib_timer_load_set(GPT0_BASE, TIMER_B, len);
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ti_lib_timer_enable(GPT0_BASE, TIMER_B);
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/*
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* Wait for TBEN to clear. CC26xxware does not provide us with a convenient
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* function, hence the direct register access here
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*/
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while(HWREG(GPT0_BASE + GPT_O_CTL) & GPT_CTL_TBEN);
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if(clock_status == 0) {
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ti_lib_prcm_peripheral_run_disable(PRCM_PERIPH_TIMER0);
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ti_lib_prcm_load_set();
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while(!ti_lib_prcm_load_get());
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}
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}
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/*---------------------------------------------------------------------------*/
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/**
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* \brief Obsolete delay function but we implement it here since some code
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* still uses it
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*/
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void
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clock_delay(unsigned int i)
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{
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clock_delay_usec(i);
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}
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/*---------------------------------------------------------------------------*/
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/**
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* @}
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* @}
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* @}
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* @}
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* @}
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*/
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