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180 lines
5.4 KiB
C
180 lines
5.4 KiB
C
/**
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* Copyright (c) 2014, Analog Devices, Inc. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted (subject to the limitations in the
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* disclaimer below) provided that the following conditions are met:
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*
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* - Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* - Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the
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* distribution.
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*
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* - Neither the name of Analog Devices, Inc. nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
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* GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
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* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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@file system_ADUCRF101.c
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@brief CMSIS Cortex-M3 Device Peripheral Access Layer Implementation File
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for the ADuCRF101
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@version v1.0
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@author PAD CSE group, Analog Devices Inc
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@date January 14th 2013
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**/
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#include <stdint.h>
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#include "ADuCRF101.h"
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/*----------------------------------------------------------------------------
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DEFINES
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*---------------------------------------------------------------------------*/
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/* Extract the Clock Divider */
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#define __CCLK_DIV (1 << (pADI_CLKCTL->CLKCON & CLKCON_CD_MSK) )
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/* define the clock multiplexer input frequencies */
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#define __HFOSC 16000000
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#define __LFXTAL 32768
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#define __LFOSC 32768
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/*----------------------------------------------------------------------------
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Internal Clock Variables
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*---------------------------------------------------------------------------*/
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static uint32_t uClk = 0; /* Undivided System Clock Frequency (UCLK) */
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static uint32_t uClkDiv = 0; /* Divided System Clock Frequency (UCLK_DIV) */
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/* Frequency of the external clock source connected to P0.5 */
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static uint32_t SystemExtClock = 0;
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/*----------------------------------------------------------------------------
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Clock functions
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*---------------------------------------------------------------------------*/
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void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
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{
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/* pre-processor verification that clock mux mask and allowed values agree */
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#if ((CLKCON_CLKMUX_HFOSC \
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| CLKCON_CLKMUX_LFXTAL \
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| CLKCON_CLKMUX_LFOSC \
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| CLKCON_CLKMUX_EXTP05) \
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== CLKCON_CLKMUX_MSK)
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/* update the system core clock according the the current clock mux setting */
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switch (pADI_CLKCTL->CLKCON & CLKCON_CLKMUX_MSK ) {
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case CLKCON_CLKMUX_HFOSC:
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uClk = __HFOSC;
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break;
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case CLKCON_CLKMUX_LFXTAL:
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uClk = __LFXTAL;
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break;
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case CLKCON_CLKMUX_LFOSC:
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uClk = __LFOSC;
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break;
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case CLKCON_CLKMUX_ECLKIN:
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uClk = SystemExtClock;
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break;
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/* no need to catch default case due to pre-processor test */
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}
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/* update the divided system clock */
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uClkDiv = uClk / __CCLK_DIV;
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#else
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#error "Clock mux mask and allowed value mismatch!"
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#endif
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}
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/**
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* Initialize the system
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*
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* @param none
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* @return none
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*
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* @brief Setup the microcontroller system.
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* Initialize the System and update the SystemFrequency variable.
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*/
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void SystemInit (void)
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{
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/* reset CLKCON register */
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pADI_CLKCTL->CLKCON = CLKCON_RVAL;
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/* reset XOSCCON register */
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pADI_CLKCTL->XOSCCON = XOSCCON_RVAL;
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/* compute internal clocks */
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SystemCoreClockUpdate();
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}
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/**
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* @brief Sets the system external clock frequency
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*
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* @param ExtClkFreq External clock frequency in Hz
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* @return none
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*
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* Sets the clock frequency of the source connected to P0.5 clock input source
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*/
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void SetSystemExtClkFreq (uint32_t ExtClkFreq)
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{
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SystemExtClock = ExtClkFreq;
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}
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/**
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* @brief Gets the system external clock frequency
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*
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* @return External Clock frequency
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*
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* Gets the clock frequency of the source connected to P0.5 clock input source
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*/
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uint32_t GetSystemExtClkFreq (void)
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{
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return SystemExtClock;
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}
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/* set the system clock dividers */
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void SystemSetClockDivider(uint16_t div)
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{
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/* critical region */
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__disable_irq();
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/* read-modify-write without any interrupts */
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pADI_CLKCTL->CLKCON &= ~(CLKCON_CD_MSK); /* keep everything else */
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pADI_CLKCTL->CLKCON |= div; /* set new value */
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/* end critical region */
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__enable_irq();
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/* refresh internal clock variables */
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SystemCoreClockUpdate();
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}
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uint32_t SystemGetClockFrequency(void)
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{
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return uClkDiv;
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}
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