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278 lines
12 KiB
C
278 lines
12 KiB
C
/**
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******************************************************************************
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* @file stm32l1xx_hal_rcc_ex.c
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* @author MCD Application Team
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* @version V1.0.0
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* @date 5-September-2014
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* @brief Extended RCC HAL module driver.
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*
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* This file provides firmware functions to manage the following
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* functionalities RCC extension peripheral:
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* + Extended Peripheral Control functions
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*
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32l1xx_hal.h"
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/** @addtogroup STM32L1xx_HAL_Driver
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* @{
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*/
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/** @defgroup RCCEx RCCEx
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* @brief RCC Extension HAL module driver
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* @{
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*/
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#ifdef HAL_RCC_MODULE_ENABLED
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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/* Private macro -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private function prototypes -----------------------------------------------*/
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/* Private functions ---------------------------------------------------------*/
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/** @defgroup RCCEx_Private_Functions RCCEx Exported Functions
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* @{
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*/
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/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
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* @brief Extended Peripheral Control functions
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*
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@verbatim
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===============================================================================
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##### Extended Peripheral Control functions #####
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===============================================================================
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[..]
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This subsection provides a set of functions allowing to control the RCC Clocks
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frequencies.
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[..]
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(@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
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select the RTC clock source; in this case the Backup domain will be reset in
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order to modify the RTC Clock source, as consequence RTC registers (including
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the backup registers) and RCC_BDCR register are set to their reset values.
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@endverbatim
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* @{
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*/
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/**
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* @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the
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* RCC_PeriphCLKInitTypeDef.
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* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
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* contains the configuration information for the Extended Peripherals clocks(RTC/LCD clock).
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
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{
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uint32_t tickstart = 0;
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uint32_t tmpreg = 0;
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/* Check the parameters */
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assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
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/*------------------------------- RTC/LCD Configuration ------------------------*/
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if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
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#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\
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defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \
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defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \
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defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \
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defined(STM32L162xE)
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|| (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD)
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#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */
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)
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{
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/* Enable Power Controller clock */
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__PWR_CLK_ENABLE();
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/* Enable write access to Backup domain */
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SET_BIT(PWR->CR, PWR_CR_DBP);
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/* Wait for Backup domain Write protection disable */
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tickstart = HAL_GetTick();
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while((PWR->CR & PWR_CR_DBP) == RESET)
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{
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if((HAL_GetTick() - tickstart ) > DBP_TIMEOUT_VALUE)
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{
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return HAL_TIMEOUT;
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}
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}
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tmpreg = (RCC->CSR & RCC_CSR_RTCSEL);
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/* Reset the Backup domain only if the RTC Clock source selection is modified */
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if((tmpreg != (PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL))
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#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\
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defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \
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defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \
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defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \
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defined(STM32L162xE)
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|| (tmpreg != (PeriphClkInit->LCDClockSelection & RCC_CSR_RTCSEL))
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#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */
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)
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{
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/* Store the content of CSR register before the reset of Backup Domain */
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tmpreg = (RCC->CSR & ~(RCC_CSR_RTCSEL));
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/* RTC Clock selection can be changed only if the Backup Domain is reset */
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__HAL_RCC_BACKUPRESET_FORCE();
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__HAL_RCC_BACKUPRESET_RELEASE();
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/* Restore the Content of CSR register */
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RCC->CSR = tmpreg;
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}
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/* If LSE is selected as RTC clock source, wait for LSE reactivation */
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if ((PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)
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#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\
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defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \
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defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \
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defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \
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defined(STM32L162xE)
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|| (PeriphClkInit->LCDClockSelection == RCC_RTCCLKSOURCE_LSE)
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#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */
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)
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{
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/* Get timeout */
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tickstart = HAL_GetTick();
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/* Wait till LSE is ready */
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while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
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{
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if((HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE)
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{
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return HAL_TIMEOUT;
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}
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}
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}
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__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
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}
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return HAL_OK;
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}
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/**
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* @brief Get the PeriphClkInit according to the internal
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* RCC configuration registers.
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* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
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* returns the configuration information for the Extended Peripherals clocks(RTC/LCD clocks).
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* @retval None
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*/
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void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
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{
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uint32_t srcclk = 0;
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/* Set all possible values for the extended clock type parameter------------*/
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PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_RTC;
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#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\
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defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \
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defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \
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defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \
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defined(STM32L162xE)
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PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LCD;
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#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */
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/* Get the RTC/LCD configuration -----------------------------------------------*/
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srcclk = __HAL_RCC_GET_RTC_SOURCE();
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if (srcclk != RCC_RTCCLKSOURCE_HSE_DIV2)
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{
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/* Source clock is LSE or LSI*/
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PeriphClkInit->RTCClockSelection = srcclk;
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}
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else
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{
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/* Source clock is HSE. Need to get the prescaler value*/
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PeriphClkInit->RTCClockSelection = srcclk | (READ_BIT(RCC->CR, RCC_CR_RTCPRE));
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}
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#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\
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defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \
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defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \
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defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \
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defined(STM32L162xE)
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PeriphClkInit->LCDClockSelection = PeriphClkInit->RTCClockSelection;
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#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */
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}
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#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || \
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defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \
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defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
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defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
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/**
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* @brief Enables the LSE Clock Security System.
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* @note If a failure is detected on the external 32 kHz oscillator, the LSE clock is no longer supplied
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* to the RTC but no hardware action is made to the registers.
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* In Standby mode a wakeup is generated. In other modes an interrupt can be sent to wakeup
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* the software (see Section 5.3.4: Clock interrupt register (RCC_CIR) on page 104).
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* The software MUST then disable the LSECSSON bit, stop the defective 32 kHz oscillator
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* (disabling LSEON), and can change the RTC clock source (no clock or LSI or HSE, with
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* RTCSEL), or take any required action to secure the application.
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* @note LSE CSS available only for high density and medium+ devices
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* @retval None
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*/
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void HAL_RCCEx_EnableLSECSS(void)
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{
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*(__IO uint32_t *) CSR_LSECSSON_BB = (uint32_t)ENABLE;
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}
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/**
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* @brief Disables the LSE Clock Security System.
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* @note Once enabled this bit cannot be disabled, except after an LSE failure detection
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* (LSECSSD=1). In that case the software MUST disable the LSECSSON bit.
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* Reset by power on reset and RTC software reset (RTCRST bit).
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* @note LSE CSS available only for high density and medium+ devices
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* @retval None
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*/
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void HAL_RCCEx_DisableLSECSS(void)
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{
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*(__IO uint32_t *) CSR_LSECSSON_BB = (uint32_t)DISABLE;
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}
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#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
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/**
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* @}
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*/
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/**
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* @}
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*/
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#endif /* HAL_RCC_MODULE_ENABLED */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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