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e0aefd11d9
This patch extends the protection domain framework with a third plugin that is a hybrid of the previous two. The hardware task switching mechanism has a strictly-defined format for TSS data structures that causes more space to be consumed than would otherwise be required. This patch defines a smaller data structure that is allocated for each protection domain, only requiring 32 bytes instead of 128 bytes. It uses the same multi-segment memory layout as the TSS-based plugin and leaves paging disabled. However, it uses a similar mechanism as the paging plugin to perform system call dispatches and returns. For additional information, please refer to cpu/x86/mm/README.md.
79 lines
3.0 KiB
C
79 lines
3.0 KiB
C
/*
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* Copyright (C) 2015, Intel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "prot-domains.h"
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#include "gdt.h"
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#include <stdio.h>
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#include "interrupt.h"
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#include <stdint.h>
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#include <assert.h>
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#include "syscalls.h"
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#include "stacks.h"
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static dom_kern_data_t __attribute__((section(".kern_prot_dom_bss")))
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ATTR_KERN_ADDR_SPACE PROT_DOMAINS_PDCS_NM(kern_dcd);
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PROT_DOMAINS_ALLOC_IMPL(kern_dcd);
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static dom_client_data_t ATTR_BSS_KERN kern_dcd;
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static dom_kern_data_t __attribute__((section(".app_prot_dom_bss")))
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ATTR_KERN_ADDR_SPACE PROT_DOMAINS_PDCS_NM(app_dcd);
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PROT_DOMAINS_ALLOC_IMPL(app_dcd);
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static dom_client_data_t ATTR_BSS_KERN app_dcd;
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/*---------------------------------------------------------------------------*/
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void
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prot_domains_init(void)
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{
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segment_desc_t desc;
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gdt_lookup(GDT_IDX_CODE_EXC, &desc);
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#if X86_CONF_PROT_DOMAINS == X86_CONF_PROT_DOMAINS__SWSEG
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/* The exception code segment needs to be readable so that the general
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* protection fault handler can decode instructions, but the interrupt and
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* user level code segments should not be.
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*/
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SEG_SET_FLAG(desc, TYPE, SEG_TYPE_CODE_EX);
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#endif
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SEG_SET_FLAG(desc, DPL, PRIV_LVL_INT);
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gdt_insert(GDT_IDX_CODE_INT, desc);
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SEG_SET_FLAG(desc, DPL, PRIV_LVL_USER);
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gdt_insert(GDT_IDX_CODE, desc);
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PROT_DOMAINS_INIT_ID(kern_dcd);
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prot_domains_reg(&kern_dcd, 0, 0, 0, 0, true);
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PROT_DOMAINS_INIT_ID(app_dcd);
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prot_domains_reg(&app_dcd, 0, 0, 0, 0, false);
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prot_domains_impl_init();
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}
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/*---------------------------------------------------------------------------*/
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