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bump libmc1322x to 7bee48243c
Conflicts:
cpu/mc1322x/board/Makefile.board
cpu/mc1322x/lib/include/uart.h
cpu/mc1322x/lib/uart1.c
cpu/mc1322x/lib/uart2.c
cpu/mc1322x/src/default_lowlevel.c
255 lines
6.4 KiB
C
255 lines
6.4 KiB
C
/*
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* Copyright (c) 2010, Mariano Alvira <mar@devl.org> and other contributors
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* to the MC1322x project (http://mc1322x.devl.org)
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the Institute nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* This file is part of libmc1322x: see http://mc1322x.devl.org
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* for details.
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*
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*
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*/
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#include <mc1322x.h>
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#include <board.h>
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#include "tests.h"
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#include "config.h"
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#define DEBUG 1
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#if DEBUG
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#define dbg_putchr(...) putchr(__VA_ARGS__)
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#define dbg_putstr(...) putstr(__VA_ARGS__)
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#define dbg_put_hex(...) put_hex(__VA_ARGS__)
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#define dbg_put_hex16(...) put_hex16(__VA_ARGS__)
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#define dbg_put_hex32(...) put_hex32(__VA_ARGS__)
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#else
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#define dbg_putchr(...)
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#define dbg_putstr(...)
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#define dbg_put_hex(...)
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#define dbg_put_hex16(...)
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#define dbg_put_hex32(...)
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#endif
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uint8_t getc(void)
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{
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volatile uint8_t c;
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while(*UART1_URXCON == 0);
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c = *UART1_UDATA;
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return c;
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}
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void flushrx(void);
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uint32_t to_u32(volatile uint32_t *c);
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enum parse_states {
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SCAN_X,
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READ_CHARS,
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PROCESS,
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MAX_STATE,
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};
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void main(void) {
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nvmType_t type=0;
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nvmErr_t err;
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volatile uint8_t c;
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volatile uint32_t i;
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volatile uint32_t buf[4];
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volatile uint32_t len=0;
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volatile uint32_t state = SCAN_X;
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volatile uint32_t addr,data;
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uart_init(UART1, 115200);
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disable_irq(UART1);
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vreg_init();
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dbg_putstr("Detecting internal nvm\n\r");
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err = nvm_detect(gNvmInternalInterface_c, &type);
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dbg_putstr("nvm_detect returned: 0x");
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dbg_put_hex(err);
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dbg_putstr(" type is: 0x");
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dbg_put_hex32(type);
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dbg_putstr("\n\r");
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/* erase the flash */
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err = nvm_erase(gNvmInternalInterface_c, type, 0x7fffffff);
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dbg_putstr("nvm_erase returned: 0x");
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dbg_put_hex(err);
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dbg_putstr("\n\r");
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dbg_putstr(" type is: 0x");
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dbg_put_hex32(type);
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dbg_putstr("\n\r");
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/* say we are ready */
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len = 0;
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putstr("ready");
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flushrx();
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/* read the length */
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for(i=0; i<4; i++) {
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c = uart1_getc();
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/* bail if the first byte of the length is zero */
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len += (c<<(i*8));
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}
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dbg_putstr("len: ");
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dbg_put_hex32(len);
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dbg_putstr("\n\r");
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/* write the OKOK magic */
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#if BOOT_OK
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((uint8_t *)buf)[0] = 'O'; ((uint8_t *)buf)[1] = 'K'; ((uint8_t *)buf)[2] = 'O'; ((uint8_t *)buf)[3] = 'K';
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#elif BOOT_SECURE
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((uint8_t *)buf)[0] = 'S'; ((uint8_t *)buf)[1] = 'E'; ((uint8_t *)buf)[2] = 'C'; ((uint8_t *)buf)[3] = 'U';
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#else
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((uint8_t *)buf)[0] = 'N'; ((uint8_t *)buf)[1] = 'O'; ((uint8_t *)buf)[2] = 'N'; ((uint8_t *)buf)[3] = 'O';
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#endif
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dbg_putstr(" type is: 0x");
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dbg_put_hex32(type);
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dbg_putstr("\n\r");
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/* don't make a valid boot image if the received length is zero */
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if(len == 0) {
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((uint8_t *)buf)[0] = 'N';
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((uint8_t *)buf)[1] = 'O';
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((uint8_t *)buf)[2] = 'N';
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((uint8_t *)buf)[3] = 'O';
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}
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err = nvm_write(gNvmInternalInterface_c, type, (uint8_t *)buf, 0, 4);
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dbg_putstr("nvm_write returned: 0x");
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dbg_put_hex(err);
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dbg_putstr("\n\r");
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/* write the length */
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err = nvm_write(gNvmInternalInterface_c, type, (uint8_t *)&len, 4, 4);
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/* read a byte, write a byte */
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for(i=0; i<len; i++) {
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c = getc();
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err = nvm_write(gNvmInternalInterface_c, type, (uint8_t *)&c, 8+i, 1);
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}
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putstr("flasher done\n\r");
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state = SCAN_X; addr=0;
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while((c=getc())) {
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if(state == SCAN_X) {
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/* read until we see an 'x' */
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if(c==0) { break; }
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if(c!='x'){ continue; }
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/* go to read_chars once we have an 'x' */
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state = READ_CHARS;
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i = 0;
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}
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if(state == READ_CHARS) {
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/* read all the chars up to a ',' */
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((uint8_t *)buf)[i++] = c;
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/* after reading a ',' */
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/* goto PROCESS state */
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if((c == ',') || (c == 0)) { state = PROCESS; }
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}
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if(state == PROCESS) {
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if(addr==0) {
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/*interpret the string as the starting address */
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addr = to_u32(buf);
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} else {
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/* string is data to write */
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data = to_u32(buf);
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putstr("writing addr ");
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put_hex32(addr);
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putstr(" data ");
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put_hex32(data);
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putstr("\n\r");
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err = nvm_write(gNvmInternalInterface_c, 1, (uint8_t *)&data, addr, 4);
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addr += 4;
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}
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/* look for the next 'x' */
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state=SCAN_X;
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}
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}
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while(1) {continue;};
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}
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void flushrx(void)
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{
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volatile uint8_t c;
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while(*UART1_URXCON !=0) {
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c = *UART1_UDATA;
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}
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}
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/* Convert from ASCII hex. Returns
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the value, or 16 if it was space/newline, or
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32 if some other character. */
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uint8_t from_hex(uint8_t ch)
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{
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if(ch==' ' || ch=='\r' || ch=='\n')
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return 16;
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if(ch < '0')
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goto bad;
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if(ch <= '9')
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return ch - '0';
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ch |= 0x20;
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if(ch < 'a')
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goto bad;
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if(ch <= 'f')
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return ch - 'a' + 10;
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bad:
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return 32;
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}
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uint32_t to_u32(volatile uint32_t *c)
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{
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volatile uint32_t ret=0;
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volatile uint32_t i,val;
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/* c should be /x\d+,/ */
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i=1; /* skip x */
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while(((uint8_t *)c)[i] != ',') {
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ret = ret<<4;
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val = from_hex(((uint8_t *)c)[i++]);
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ret += val;
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}
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return ret;
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}
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