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The Intel Quark X1000 SoC includes support for Isolated Memory Regions (IMRs), which are specified using range registers and associated control registers that are accessible via the message bus. This patch adds a driver for accessing those registers.
90 lines
3.5 KiB
C
90 lines
3.5 KiB
C
/*
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* Copyright (C) 2015-2016, Intel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <assert.h>
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#include "imr.h"
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#include "msg-bus.h"
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#define MEM_MANAGER_PORT 5
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#define IMR_BASE_OFFSET 0x40
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#define IMR_REG_COUNT 4
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#define IMR_LO_OFFSET 0
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#define IMR_HI_OFFSET 1
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#define IMR_RDMSK_OFFSET 2
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#define IMR_WRMSK_OFFSET 3
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/*---------------------------------------------------------------------------*/
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/**
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* \brief Read the contents of the specified IMR.
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*/
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quarkX1000_imr_t
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quarkX1000_imr_read(uint32_t imr_idx)
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{
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quarkX1000_imr_t imr;
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uint32_t reg_base = IMR_BASE_OFFSET + (IMR_REG_COUNT * imr_idx);
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assert(imr_idx < QUARKX1000_IMR_CNT);
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quarkX1000_msg_bus_read(MEM_MANAGER_PORT,
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reg_base + IMR_LO_OFFSET, &imr.lo.raw);
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quarkX1000_msg_bus_read(MEM_MANAGER_PORT,
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reg_base + IMR_HI_OFFSET, &imr.hi.raw);
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quarkX1000_msg_bus_read(MEM_MANAGER_PORT,
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reg_base + IMR_RDMSK_OFFSET, &imr.rdmsk.raw);
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quarkX1000_msg_bus_read(MEM_MANAGER_PORT,
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reg_base + IMR_WRMSK_OFFSET, &imr.wrmsk.raw);
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return imr;
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}
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/*---------------------------------------------------------------------------*/
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/**
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* \brief Overwrite the contents of the specified IMR.
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*/
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void
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quarkX1000_imr_write(uint32_t imr_idx, quarkX1000_imr_t imr)
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{
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uint32_t reg_base = IMR_BASE_OFFSET + (IMR_REG_COUNT * imr_idx);
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assert(imr_idx < QUARKX1000_IMR_CNT);
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quarkX1000_msg_bus_write(MEM_MANAGER_PORT,
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reg_base + IMR_HI_OFFSET, imr.hi.raw);
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quarkX1000_msg_bus_write(MEM_MANAGER_PORT,
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reg_base + IMR_RDMSK_OFFSET, imr.rdmsk.raw);
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quarkX1000_msg_bus_write(MEM_MANAGER_PORT,
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reg_base + IMR_WRMSK_OFFSET, imr.wrmsk.raw);
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/* This register must be programmed last, in case it sets the lock bit. */
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quarkX1000_msg_bus_write(MEM_MANAGER_PORT,
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reg_base + IMR_LO_OFFSET, imr.lo.raw);
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}
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/*---------------------------------------------------------------------------*/
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