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b92a5afcc4
Using the AES interrupt allows the user process not to waste time polling for the completion of the operation. This time can be used by the user process to do something else, or to let the system enter PM0. Since the system is now free to perform various operations during a crypto operation, a protection of the crypto resource is added, and PM1+ is prohibited in order not to stall crypto operations. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
416 lines
14 KiB
C
416 lines
14 KiB
C
/*
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* Original file:
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* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
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* All rights reserved.
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*
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* Port to Contiki:
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* Copyright (c) 2013, ADVANSEE - http://www.advansee.com/
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* \addtogroup cc2538-ccm
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* @{
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*
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* \file
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* Implementation of the cc2538 AES-CCM driver
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*/
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#include "contiki.h"
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#include "sys/cc.h"
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#include "dev/rom-util.h"
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#include "dev/nvic.h"
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#include "dev/ccm.h"
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#include "reg.h"
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#include <stdbool.h>
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#include <stdint.h>
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/*---------------------------------------------------------------------------*/
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uint8_t
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ccm_auth_encrypt_start(uint8_t len_len, uint8_t key_area, const void *nonce,
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const void *adata, uint16_t adata_len, void *pdata,
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uint16_t pdata_len, uint8_t mic_len,
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struct process *process)
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{
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uint32_t iv[4];
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if(REG(AES_CTRL_ALG_SEL) != 0x00000000) {
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return CRYPTO_RESOURCE_IN_USE;
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}
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/* Workaround for AES registers not retained after PM2 */
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REG(AES_CTRL_INT_CFG) = AES_CTRL_INT_CFG_LEVEL;
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REG(AES_CTRL_INT_EN) = AES_CTRL_INT_EN_DMA_IN_DONE |
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AES_CTRL_INT_EN_RESULT_AV;
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REG(AES_CTRL_ALG_SEL) = AES_CTRL_ALG_SEL_AES;
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REG(AES_CTRL_INT_CLR) = AES_CTRL_INT_CLR_DMA_IN_DONE |
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AES_CTRL_INT_CLR_RESULT_AV;
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REG(AES_KEY_STORE_READ_AREA) = key_area;
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/* Wait until key is loaded to the AES module */
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while(REG(AES_KEY_STORE_READ_AREA) & AES_KEY_STORE_READ_AREA_BUSY);
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/* Check for Key Store read error */
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if(REG(AES_CTRL_INT_STAT) & AES_CTRL_INT_STAT_KEY_ST_RD_ERR) {
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/* Clear the Keystore Read error bit */
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REG(AES_CTRL_INT_CLR) = AES_CTRL_INT_CLR_KEY_ST_RD_ERR;
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/* Disable the master control / DMA clock */
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REG(AES_CTRL_ALG_SEL) = 0x00000000;
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return AES_KEYSTORE_READ_ERROR;
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}
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/* Prepare the encryption initialization vector
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* Flags: L' = L - 1 */
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((uint8_t *)iv)[0] = len_len - 1;
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/* Nonce */
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rom_util_memcpy(&((uint8_t *)iv)[1], nonce, 15 - len_len);
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/* Initialize counter to 0 */
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rom_util_memset(&((uint8_t *)iv)[16 - len_len], 0, len_len);
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/* Write initialization vector */
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REG(AES_AES_IV_0) = iv[0];
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REG(AES_AES_IV_1) = iv[1];
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REG(AES_AES_IV_2) = iv[2];
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REG(AES_AES_IV_3) = iv[3];
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/* Program AES-CCM-128 encryption */
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REG(AES_AES_CTRL) = AES_AES_CTRL_SAVE_CONTEXT | /* Save context */
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(((MAX(mic_len, 2) - 2) >> 1) << AES_AES_CTRL_CCM_M_S) | /* M */
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((len_len - 1) << AES_AES_CTRL_CCM_L_S) | /* L */
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AES_AES_CTRL_CCM | /* CCM */
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AES_AES_CTRL_CTR_WIDTH_128 | /* CTR width 128 */
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AES_AES_CTRL_CTR | /* CTR */
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AES_AES_CTRL_KEY_SIZE_128 | /* Key = 128 */
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AES_AES_CTRL_DIRECTION_ENCRYPT; /* Encryption */
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/* Write the length of the crypto block (lo) */
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REG(AES_AES_C_LENGTH_0) = pdata_len;
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/* Write the length of the crypto block (hi) */
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REG(AES_AES_C_LENGTH_1) = 0;
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/* Write the length of the AAD data block (may be non-block size-aligned) */
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REG(AES_AES_AUTH_LENGTH) = adata_len;
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if(adata_len != 0) {
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/* Configure DMAC to fetch the AAD data
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* Enable DMA channel 0 */
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REG(AES_DMAC_CH0_CTRL) = AES_DMAC_CH_CTRL_EN;
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/* Base address of the AAD input data in ext. memory */
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REG(AES_DMAC_CH0_EXTADDR) = (uint32_t)adata;
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/* AAD data length in bytes */
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REG(AES_DMAC_CH0_DMALENGTH) = adata_len;
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/* Wait for completion of the AAD data transfer, DMA_IN_DONE */
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while(!(REG(AES_CTRL_INT_STAT) & AES_CTRL_INT_STAT_DMA_IN_DONE));
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/* Check for the absence of error */
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if(REG(AES_CTRL_INT_STAT) & AES_CTRL_INT_STAT_DMA_BUS_ERR) {
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/* Clear the DMA error */
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REG(AES_CTRL_INT_CLR) = AES_CTRL_INT_CLR_DMA_BUS_ERR;
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/* Disable the master control / DMA clock */
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REG(AES_CTRL_ALG_SEL) = 0x00000000;
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return CRYPTO_DMA_BUS_ERROR;
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}
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}
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/* Clear interrupt status */
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REG(AES_CTRL_INT_CLR) = AES_CTRL_INT_CLR_DMA_IN_DONE |
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AES_CTRL_INT_CLR_RESULT_AV;
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if(process != NULL) {
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crypto_register_process_notification(process);
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nvic_interrupt_unpend(NVIC_INT_AES);
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nvic_interrupt_enable(NVIC_INT_AES);
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}
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/* Enable result available bit in interrupt enable */
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REG(AES_CTRL_INT_EN) = AES_CTRL_INT_EN_RESULT_AV;
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if(pdata_len != 0) {
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/* Configure DMAC
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* Enable DMA channel 0 */
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REG(AES_DMAC_CH0_CTRL) = AES_DMAC_CH_CTRL_EN;
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/* Base address of the payload data in ext. memory */
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REG(AES_DMAC_CH0_EXTADDR) = (uint32_t)pdata;
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/* Payload data length in bytes */
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REG(AES_DMAC_CH0_DMALENGTH) = pdata_len;
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/* Enable DMA channel 1 */
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REG(AES_DMAC_CH1_CTRL) = AES_DMAC_CH_CTRL_EN;
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/* Base address of the output data buffer */
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REG(AES_DMAC_CH1_EXTADDR) = (uint32_t)pdata;
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/* Output data length in bytes */
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REG(AES_DMAC_CH1_DMALENGTH) = pdata_len;
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}
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return CRYPTO_SUCCESS;
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}
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/*---------------------------------------------------------------------------*/
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uint8_t
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ccm_auth_encrypt_check_status(void)
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{
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return !!(REG(AES_CTRL_INT_STAT) &
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(AES_CTRL_INT_STAT_DMA_BUS_ERR | AES_CTRL_INT_STAT_KEY_ST_WR_ERR |
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AES_CTRL_INT_STAT_KEY_ST_RD_ERR | AES_CTRL_INT_STAT_RESULT_AV));
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}
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/*---------------------------------------------------------------------------*/
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uint8_t
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ccm_auth_encrypt_get_result(void *mic, uint8_t mic_len)
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{
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uint32_t aes_ctrl_int_stat;
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uint32_t tag[4];
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aes_ctrl_int_stat = REG(AES_CTRL_INT_STAT);
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/* Clear the error bits */
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REG(AES_CTRL_INT_CLR) = AES_CTRL_INT_CLR_DMA_BUS_ERR |
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AES_CTRL_INT_CLR_KEY_ST_WR_ERR |
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AES_CTRL_INT_CLR_KEY_ST_RD_ERR;
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nvic_interrupt_disable(NVIC_INT_AES);
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crypto_register_process_notification(NULL);
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/* Disable the master control / DMA clock */
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REG(AES_CTRL_ALG_SEL) = 0x00000000;
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if(aes_ctrl_int_stat & AES_CTRL_INT_STAT_DMA_BUS_ERR) {
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return CRYPTO_DMA_BUS_ERROR;
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}
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if(aes_ctrl_int_stat & AES_CTRL_INT_STAT_KEY_ST_WR_ERR) {
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return AES_KEYSTORE_WRITE_ERROR;
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}
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if(aes_ctrl_int_stat & AES_CTRL_INT_STAT_KEY_ST_RD_ERR) {
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return AES_KEYSTORE_READ_ERROR;
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}
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/* Read tag
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* Wait for the context ready bit */
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while(!(REG(AES_AES_CTRL) & AES_AES_CTRL_SAVED_CONTEXT_READY));
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/* Read the tag registers */
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tag[0] = REG(AES_AES_TAG_OUT_0);
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tag[1] = REG(AES_AES_TAG_OUT_1);
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tag[2] = REG(AES_AES_TAG_OUT_2);
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tag[3] = REG(AES_AES_TAG_OUT_3);
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/* Clear the interrupt status */
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REG(AES_CTRL_INT_CLR) = AES_CTRL_INT_CLR_DMA_IN_DONE |
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AES_CTRL_INT_CLR_RESULT_AV;
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/* Copy tag to MIC */
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rom_util_memcpy(mic, tag, mic_len);
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return CRYPTO_SUCCESS;
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}
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/*---------------------------------------------------------------------------*/
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uint8_t
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ccm_auth_decrypt_start(uint8_t len_len, uint8_t key_area, const void *nonce,
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const void *adata, uint16_t adata_len, void *cdata,
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uint16_t cdata_len, uint8_t mic_len,
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struct process *process)
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{
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uint16_t pdata_len = cdata_len - mic_len;
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uint32_t iv[4];
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if(REG(AES_CTRL_ALG_SEL) != 0x00000000) {
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return CRYPTO_RESOURCE_IN_USE;
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}
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/* Workaround for AES registers not retained after PM2 */
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REG(AES_CTRL_INT_CFG) = AES_CTRL_INT_CFG_LEVEL;
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REG(AES_CTRL_INT_EN) = AES_CTRL_INT_EN_DMA_IN_DONE |
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AES_CTRL_INT_EN_RESULT_AV;
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REG(AES_CTRL_ALG_SEL) = AES_CTRL_ALG_SEL_AES;
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REG(AES_CTRL_INT_CLR) = AES_CTRL_INT_CLR_DMA_IN_DONE |
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AES_CTRL_INT_CLR_RESULT_AV;
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REG(AES_KEY_STORE_READ_AREA) = key_area;
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/* Wait until key is loaded to the AES module */
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while(REG(AES_KEY_STORE_READ_AREA) & AES_KEY_STORE_READ_AREA_BUSY);
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/* Check for Key Store read error */
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if(REG(AES_CTRL_INT_STAT) & AES_CTRL_INT_STAT_KEY_ST_RD_ERR) {
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/* Clear the Keystore Read error bit */
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REG(AES_CTRL_INT_CLR) = AES_CTRL_INT_CLR_KEY_ST_RD_ERR;
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/* Disable the master control / DMA clock */
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REG(AES_CTRL_ALG_SEL) = 0x00000000;
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return AES_KEYSTORE_READ_ERROR;
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}
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/* Prepare the decryption initialization vector
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* Flags: L' = L - 1 */
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((uint8_t *)iv)[0] = len_len - 1;
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/* Nonce */
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rom_util_memcpy(&((uint8_t *)iv)[1], nonce, 15 - len_len);
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/* Initialize counter to 0 */
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rom_util_memset(&((uint8_t *)iv)[16 - len_len], 0, len_len);
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/* Write initialization vector */
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REG(AES_AES_IV_0) = iv[0];
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REG(AES_AES_IV_1) = iv[1];
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REG(AES_AES_IV_2) = iv[2];
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REG(AES_AES_IV_3) = iv[3];
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/* Program AES-CCM-128 decryption */
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REG(AES_AES_CTRL) = AES_AES_CTRL_SAVE_CONTEXT | /* Save context */
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(((MAX(mic_len, 2) - 2) >> 1) << AES_AES_CTRL_CCM_M_S) | /* M */
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((len_len - 1) << AES_AES_CTRL_CCM_L_S) | /* L */
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AES_AES_CTRL_CCM | /* CCM */
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AES_AES_CTRL_CTR_WIDTH_128 | /* CTR width 128 */
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AES_AES_CTRL_CTR | /* CTR */
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AES_AES_CTRL_KEY_SIZE_128; /* Key = 128 */
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/* Write the length of the crypto block (lo) */
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REG(AES_AES_C_LENGTH_0) = pdata_len;
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/* Write the length of the crypto block (hi) */
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REG(AES_AES_C_LENGTH_1) = 0;
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/* Write the length of the AAD data block (may be non-block size-aligned) */
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REG(AES_AES_AUTH_LENGTH) = adata_len;
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if(adata_len != 0) {
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/* Configure DMAC to fetch the AAD data
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* Enable DMA channel 0 */
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REG(AES_DMAC_CH0_CTRL) = AES_DMAC_CH_CTRL_EN;
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/* Base address of the AAD input data in ext. memory */
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REG(AES_DMAC_CH0_EXTADDR) = (uint32_t)adata;
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/* AAD data length in bytes */
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REG(AES_DMAC_CH0_DMALENGTH) = adata_len;
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/* Wait for completion of the AAD data transfer, DMA_IN_DONE */
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while(!(REG(AES_CTRL_INT_STAT) & AES_CTRL_INT_STAT_DMA_IN_DONE));
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/* Check for the absence of error */
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if(REG(AES_CTRL_INT_STAT) & AES_CTRL_INT_STAT_DMA_BUS_ERR) {
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/* Clear the DMA error */
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REG(AES_CTRL_INT_CLR) = AES_CTRL_INT_CLR_DMA_BUS_ERR;
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/* Disable the master control / DMA clock */
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REG(AES_CTRL_ALG_SEL) = 0x00000000;
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return CRYPTO_DMA_BUS_ERROR;
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}
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}
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/* Clear interrupt status */
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REG(AES_CTRL_INT_CLR) = AES_CTRL_INT_CLR_DMA_IN_DONE |
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AES_CTRL_INT_CLR_RESULT_AV;
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if(process != NULL) {
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crypto_register_process_notification(process);
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nvic_interrupt_unpend(NVIC_INT_AES);
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nvic_interrupt_enable(NVIC_INT_AES);
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}
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/* Enable result available bit in interrupt enable */
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REG(AES_CTRL_INT_EN) = AES_CTRL_INT_EN_RESULT_AV;
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if(pdata_len != 0) {
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/* Configure DMAC
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* Enable DMA channel 0 */
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REG(AES_DMAC_CH0_CTRL) = AES_DMAC_CH_CTRL_EN;
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/* Base address of the payload data in ext. memory */
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REG(AES_DMAC_CH0_EXTADDR) = (uint32_t)cdata;
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/* Payload data length in bytes */
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REG(AES_DMAC_CH0_DMALENGTH) = pdata_len;
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/* Enable DMA channel 1 */
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REG(AES_DMAC_CH1_CTRL) = AES_DMAC_CH_CTRL_EN;
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/* Base address of the output data buffer */
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REG(AES_DMAC_CH1_EXTADDR) = (uint32_t)cdata;
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/* Output data length in bytes */
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REG(AES_DMAC_CH1_DMALENGTH) = pdata_len;
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}
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return CRYPTO_SUCCESS;
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}
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/*---------------------------------------------------------------------------*/
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uint8_t
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ccm_auth_decrypt_check_status(void)
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{
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/* Check if result is available or some error has occured */
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return ccm_auth_encrypt_check_status();
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}
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/*---------------------------------------------------------------------------*/
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uint8_t
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ccm_auth_decrypt_get_result(const void *cdata, uint16_t cdata_len,
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void *mic, uint8_t mic_len)
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{
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uint32_t aes_ctrl_int_stat;
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uint16_t pdata_len = cdata_len - mic_len;
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uint32_t tag[4];
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aes_ctrl_int_stat = REG(AES_CTRL_INT_STAT);
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/* Clear the error bits */
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REG(AES_CTRL_INT_CLR) = AES_CTRL_INT_CLR_DMA_BUS_ERR |
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AES_CTRL_INT_CLR_KEY_ST_WR_ERR |
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AES_CTRL_INT_CLR_KEY_ST_RD_ERR;
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nvic_interrupt_disable(NVIC_INT_AES);
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crypto_register_process_notification(NULL);
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/* Disable the master control / DMA clock */
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REG(AES_CTRL_ALG_SEL) = 0x00000000;
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if(aes_ctrl_int_stat & AES_CTRL_INT_STAT_DMA_BUS_ERR) {
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return CRYPTO_DMA_BUS_ERROR;
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}
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if(aes_ctrl_int_stat & AES_CTRL_INT_STAT_KEY_ST_WR_ERR) {
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return AES_KEYSTORE_WRITE_ERROR;
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}
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if(aes_ctrl_int_stat & AES_CTRL_INT_STAT_KEY_ST_RD_ERR) {
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return AES_KEYSTORE_READ_ERROR;
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}
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/* Read tag
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* Wait for the context ready bit */
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while(!(REG(AES_AES_CTRL) & AES_AES_CTRL_SAVED_CONTEXT_READY));
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/* Read the tag registers */
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tag[0] = REG(AES_AES_TAG_OUT_0);
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tag[1] = REG(AES_AES_TAG_OUT_1);
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tag[2] = REG(AES_AES_TAG_OUT_2);
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tag[3] = REG(AES_AES_TAG_OUT_3);
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/* Clear the interrupt status */
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REG(AES_CTRL_INT_CLR) = AES_CTRL_INT_CLR_DMA_IN_DONE |
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AES_CTRL_INT_CLR_RESULT_AV;
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/* Check MIC */
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if(rom_util_memcmp(tag, &((const uint8_t *)cdata)[pdata_len], mic_len)) {
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return CCM_AUTHENTICATION_FAILED;
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}
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/* Copy tag to MIC */
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rom_util_memcpy(mic, tag, mic_len);
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return CRYPTO_SUCCESS;
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}
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/** @} */
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