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c815fa4511
This patch permits interrupts to be generated by both the I2C and GPIO controllers for simultaneously-executing applications. The controllers share a single interrupt pin, INTC. Prior to this patch, quarkX1000_gpio_init() routed INTA to PIRQC and IRQ 10 (due to an incorrect assumption that INTA is connected to the GPIO controller), and quarkX1000_i2c_init() routed INTC to PIRQC and IRQ 9. The I2C controller initialization is a prerequisite for GPIO initialization, so the final configuration was that INTA and INTC were both routed to PIRQC and IRQ 10. Thus, only the GPIO ISR was being invoked, even if the I2C controller was actually responsible for the interrupt. This patch refactors the I2C and GPIO ISR setup and handler code so that the shared portions are combined in cpu/x86/drivers/legacy_pc/shared-isr.[ch]. The I2C and GPIO drivers communicate their interrupt information to the shared component by placing structures in a specific section of the binary. |
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| 6502 | ||
| arm | ||
| avr | ||
| cc26xx-cc13xx | ||
| cc253x | ||
| cc2538 | ||
| mc1322x | ||
| msp430 | ||
| native | ||
| pic32 | ||
| rl78 | ||
| stm32w108 | ||
| x86 | ||