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c2a71ee62b
I. Build Ethernet drivers individually for each target. After all the Ethernet cards/carts are different enough to ask for customized drivers. Building the drivers individually opens the option to use .ifdef's to customize them. II. Removed Ethernet driver I/O base. So far the base address of the Ethernet chip was a general property of all Ethernet drivers. It served two purposes: 1. Allowing to use a single Ethernet driver for a certain Ethernet chip, no matter what machine was connected to the chip. 2. Allowing use an Ethernet card in all Apple II slots. However, we now use customized Ethernet drivers for the individual machines so 1.) isn't relevant anymore. In fact one wants to omit the overhead of a runtime-adjustable base address where it isn't needed. So only the Apple II slots are left. But this should rather be a driver-internal approach then. We should just hand the driver the slot number the user wants to use and have the driver do its thing. III. With per-target Ethernet drivers we can have per-target MAC addresses. IV. Added support for RR-Net MK3 unique MAC addresses. The RR-Net MK3 can be operated in two modes: - In cartrigde mode it has a startup-ROM that sets the CS8900A MAC address to the unique MAC address. - In clockport mode the driver has to read the two lowest MAC address bytes from the EEPROM and combine them with 28:CD:4C:FF. See http://wiki.icomp.de/wiki/RR-Net#Detecting_MK3 for details. The driver first checks if the current CS8900A MAC address starts with 28:CD:4C:FF. If it does, it overwrites its built in default MAC address with the CS8900A MAC address. If the CS8900A MAC address didn't start with 28:CD:4C:FF, it checks if there are two valid MAC address bytes in the EEPROM. If they are there, it overwrites its built in default MAC address with a combination of 28:CD:4C:FF and those two bytes. V. Added support for the upcoming 'Dracarys' Ethernet PBI for the ATARI. See http://atariage.com/forums/topic/287376-preannouncement-dragon-cart-ii/ for details on Dracarys. So far there was only one Ethernet solution for the ATARI. Therefore the relevant driver was loaded statically. With now having two solutions we have to load the corresponding driver dynamically (like on the other machines). Fortunately this doesn't mean significant additional overhead as there are several mouse drivers for the ATARI asking for dynamic mouse driver loading. Therefore the dynamic driver loading infrastructure was linked already. Another aspect of more than one Ethernet solution is that the Ethernet config program becomes necessary on the ATARI to select the correct driver. Although that program is pretty simple and therefore rather small it means that now only one "major" program fits on a 130kB disk. So we need now 5(!) 130kB disk images instead 3 so far.
495 lines
12 KiB
ArmAsm
495 lines
12 KiB
ArmAsm
;
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; Copyright (c) 2003-2007, Adam Dunkels, Josef Soucek and Oliver Schmidt
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; All rights reserved.
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions
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; are met:
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; 1. Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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; 2. Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in the
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; documentation and/or other materials provided with the distribution.
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; 3. Neither the name of the Institute nor the names of its contributors
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; may be used to endorse or promote products derived from this software
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; without specific prior written permission.
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;
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; THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
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; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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; ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
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; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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; OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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; HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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; LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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; OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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; SUCH DAMAGE.
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;
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; This file is part of the Contiki operating system.
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;
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; Author: Adam Dunkels <adam@sics.se>, Josef Soucek <josef.soucek@ide64.org>,
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; Oliver Schmidt <ol.sc@web.de>
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;
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;---------------------------------------------------------------------
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.macpack module
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module_header _lan91c96
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; Driver signature
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.byte $65, $74, $68 ; "eth"
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.byte $01 ; Ethernet driver API version number
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; Ethernet address
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mac: .byte $00, $80, $0F ; OUI of Standard Microsystems
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.ifdef __C64__
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.byte $64, $64, $64
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.endif
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.ifdef __C128__
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.byte $28, $28, $28
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.endif
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.ifdef __APPLE2__
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.byte $A2, $A2, $A2
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.endif
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; Buffer attributes
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bufaddr:.res 2 ; Address
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bufsize:.res 2 ; Size
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; Jump table.
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jmp init
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jmp poll
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jmp send
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jmp exit
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;---------------------------------------------------------------------
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.if DYN_DRV
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.zeropage
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sp: .res 2 ; Stack pointer (Do not trash !)
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reg: .res 2 ; Address of register base
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ptr: .res 2 ; Indirect addressing pointer
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len: .res 2 ; Frame length
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.else
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.include "zeropage.inc"
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reg := ptr1 ; Address of register base
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ptr := ptr2 ; Indirect addressing pointer
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len := ptr3 ; Frame length
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.endif
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;=====================================================================
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.if .defined (__C64__) .or .defined (__C128__)
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ethbsr := $DE0E ; Bank select register R/W (2B)
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; Register bank 0
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ethtcr := $DE00 ; Transmition control register R/W (2B)
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ethephsr := $DE02 ; EPH status register R/O (2B)
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ethrcr := $DE04 ; Receive control register R/W (2B)
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ethecr := $DE06 ; Counter register R/O (2B)
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ethmir := $DE08 ; Memory information register R/O (2B)
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ethmcr := $DE0A ; Memory Config. reg. +0 R/W +1 R/O (2B)
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; Register bank 1
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ethcr := $DE00 ; Configuration register R/W (2B)
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ethbar := $DE02 ; Base address register R/W (2B)
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ethiar := $DE04 ; Individual address register R/W (6B)
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ethgpr := $DE0A ; General address register R/W (2B)
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ethctr := $DE0C ; Control register R/W (2B)
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; Register bank 2
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ethmmucr := $DE00 ; MMU command register W/O (1B)
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ethautotx := $DE01 ; AUTO TX start register R/W (1B)
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ethpnr := $DE02 ; Packet number register R/W (1B)
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etharr := $DE03 ; Allocation result register R/O (1B)
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ethfifo := $DE04 ; FIFO ports register R/O (2B)
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ethptr := $DE06 ; Pointer register R/W (2B)
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ethdata := $DE08 ; Data register R/W (4B)
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ethist := $DE0C ; Interrupt status register R/O (1B)
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ethack := $DE0C ; Interrupt acknowledge register W/O (1B)
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ethmsk := $DE0D ; Interrupt mask register R/W (1B)
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; Register bank 3
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ethmt := $DE00 ; Multicast table R/W (8B)
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ethmgmt := $DE08 ; Management interface R/W (2B)
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ethrev := $DE0A ; Revision register R/W (2B)
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ethercv := $DE0C ; Early RCV register R/W (2B)
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;---------------------------------------------------------------------
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.code
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init:
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.endif
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;=====================================================================
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.ifdef __APPLE2__
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.rodata
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fixup: .byte fixup02-fixup01, fixup03-fixup02, fixup04-fixup03
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.byte fixup05-fixup04, fixup06-fixup05, fixup07-fixup06
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.byte fixup08-fixup07, fixup09-fixup08, fixup10-fixup09
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.byte fixup11-fixup10, fixup12-fixup11, fixup13-fixup12
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.byte fixup14-fixup13, fixup15-fixup14, fixup16-fixup15
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.byte fixup17-fixup16, fixup18-fixup17, fixup19-fixup18
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.byte fixup20-fixup19, fixup21-fixup20, fixup22-fixup21
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.byte fixup23-fixup22, fixup24-fixup23, fixup25-fixup24
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.byte fixup26-fixup25, fixup27-fixup26, fixup28-fixup27
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.byte fixup29-fixup28, fixup30-fixup29, fixup31-fixup30
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.byte fixup32-fixup31, fixup33-fixup32, fixup34-fixup33
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.byte fixup35-fixup34, fixup36-fixup35, fixup37-fixup36
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.byte fixup38-fixup37, fixup39-fixup38
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fixups = * - fixup
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;---------------------------------------------------------------------
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; The addresses are fixed up at runtime
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ethbsr := $C08E ; Bank select register R/W (2B)
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; Register bank 0
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ethtcr := $C080 ; Transmition control register R/W (2B)
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ethephsr := $C082 ; EPH status register R/O (2B)
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ethrcr := $C084 ; Receive control register R/W (2B)
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ethecr := $C086 ; Counter register R/O (2B)
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ethmir := $C088 ; Memory information register R/O (2B)
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ethmcr := $C08A ; Memory Config. reg. +0 R/W +1 R/O (2B)
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; Register bank 1
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ethcr := $C080 ; Configuration register R/W (2B)
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ethbar := $C082 ; Base address register R/W (2B)
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ethiar := $C084 ; Individual address register R/W (6B)
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ethgpr := $C08A ; General address register R/W (2B)
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ethctr := $C08C ; Control register R/W (2B)
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; Register bank 2
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ethmmucr := $C080 ; MMU command register W/O (1B)
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ethautotx := $C081 ; AUTO TX start register R/W (1B)
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ethpnr := $C082 ; Packet number register R/W (1B)
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etharr := $C083 ; Allocation result register R/O (1B)
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ethfifo := $C084 ; FIFO ports register R/O (2B)
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ethptr := $C086 ; Pointer register R/W (2B)
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ethdata := $C088 ; Data register R/W (4B)
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ethist := $C08C ; Interrupt status register R/O (1B)
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ethack := $C08C ; Interrupt acknowledge register W/O (1B)
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ethmsk := $C08D ; Interrupt mask register R/W (1B)
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; Register bank 3
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ethmt := $C080 ; Multicast table R/W (8B)
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ethmgmt := $C088 ; Management interface R/W (2B)
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ethrev := $C08A ; Revision register R/W (2B)
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ethercv := $C08C ; Early RCV register R/W (2B)
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;---------------------------------------------------------------------
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.data
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init:
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; Convert slot number to slot I/O offset
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asl
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asl
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asl
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asl
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sta reg
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; Start with first fixup location
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lda #<(fixup01+1)
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ldx #>(fixup01+1)
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sta ptr
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stx ptr+1
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ldx #$FF
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ldy #$00
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; Fixup address at location
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: lda (ptr),y
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and #%10001111 ; Allow for re-init
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ora reg
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sta (ptr),y
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; Advance to next fixup location
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inx
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cpx #fixups
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bcs :+
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lda ptr
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clc
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adc fixup,x
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sta ptr
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bcc :-
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inc ptr+1
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bcs :- ; Always
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:
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.endif
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;=====================================================================
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; Check bank select register upper byte to always read as $33
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ldy #$00
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fixup01:sty ethbsr+1
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fixup02:lda ethbsr+1
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cmp #$33
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beq :+
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sec
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rts
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; Reset ETH card
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: ; Bank 0
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fixup03:sty ethbsr
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lda #%10000000 ; Software reset
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fixup04:sta ethrcr+1
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fixup05:sty ethrcr
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fixup06:sty ethrcr+1
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; Delay
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: cmp ($FF,x) ; 6 cycles
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cmp ($FF,x) ; 6 cycles
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iny ; 2 cycles
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bne :- ; 3 cycles
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; 17 * 256 = 4352 -> 4,4 ms
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; Enable transmit and receive
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lda #%10000001 ; Enable transmit TXENA, PAD_EN
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ldx #%00000011 ; Enable receive, strip CRC ???
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fixup07:sta ethtcr
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fixup08:stx ethrcr+1
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lda #$01 ; Bank 1
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fixup09:sta ethbsr
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fixup10:lda ethcr+1
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ora #%00010000 ; No wait (IOCHRDY)
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fixup11:sta ethcr+1
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lda #%00001001 ; Auto release
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fixup12:sta ethctr+1
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; Set MAC address
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ldy #$00
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: lda mac,y
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fixup13:sta ethiar,y
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iny
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cpy #$06
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bcc :-
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; Set interrupt mask
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lda #$02 ; Bank 2
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fixup14:sta ethbsr
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lda #%00000000 ; No interrupts
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fixup15:sta ethmsk
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tax
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clc
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rts
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;---------------------------------------------------------------------
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poll:
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fixup16:lda ethist
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and #%00000001 ; RCV INT
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beq :+
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; Process the incoming packet
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; ---------------------------
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lda #$00
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ldx #%11100000 ; RCV, AUTO INCR., READ
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fixup17:sta ethptr
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fixup18:stx ethptr+1
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; Last word contains 'last data byte' and $60 or 'fill byte' and $40
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fixup19:lda ethdata ; Status word
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fixup20:lda ethdata ; Need high byte only
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; Move ODDFRM bit into carry:
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; - Even packet length -> carry clear -> subtract 6 bytes
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; - Odd packet length -> carry set -> subtract 5 bytes
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lsr
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lsr
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lsr
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lsr
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lsr
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; The packet contains 3 extra words
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fixup21:lda ethdata ; Total number of bytes
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sbc #$05 ; Actually 5 or 6 depending on carry
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sta len
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fixup22:lda ethdata
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sbc #$00
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sta len+1
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; Is bufsize < len ?
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lda bufsize
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cmp len
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lda bufsize+1
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sbc len+1
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bcs :++
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; Yes, skip packet
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jsr releasepacket
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; No packet available
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lda #$00
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: tax
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sec
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rts
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; Read bytes into buffer
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: jsr adjustptr
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:
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fixup23:lda ethdata
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sta (ptr),y
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iny
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bne :-
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inc ptr+1
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dex
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bpl :-
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; Remove and release RX packet from the FIFO
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jsr releasepacket
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; Return packet length
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lda len
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ldx len+1
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clc
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rts
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;---------------------------------------------------------------------
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send:
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; Save packet length
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sta len
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stx len+1
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; Allocate memory for TX
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txa
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ora #%00100000
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fixup24:sta ethmmucr
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; 8 retries
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ldy #$08
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; Wait for allocation ready
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:
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fixup25:lda ethist
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and #%00001000 ; ALLOC INT
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bne :+
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; No space avaliable, skip a received frame
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jsr releasepacket
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; And try again
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dey
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bne :-
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sec
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rts
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; Acknowledge interrupt, is it necessary ???
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: lda #%00001000
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fixup26:sta ethack
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; Set packet address
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fixup27:lda etharr
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fixup28:sta ethpnr
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lda #$00
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ldx #%01000000 ; AUTO INCR.
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fixup29:sta ethptr
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fixup30:stx ethptr+1
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; Status written by CSMA
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lda #$00
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fixup31:sta ethdata
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fixup32:sta ethdata
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; Check packet length parity:
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; - Even packet length -> carry set -> add 6 bytes
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; - Odd packet length -> carry clear -> add 5 bytes
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lda len
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eor #$01
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lsr
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; The packet contains 3 extra words
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lda len
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adc #$05 ; Actually 5 or 6 depending on carry
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fixup33:sta ethdata
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lda len+1
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adc #$00
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fixup34:sta ethdata
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; Send the packet
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; ---------------
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; Write bytes from buffer
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jsr adjustptr
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: lda (ptr),y
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fixup35:sta ethdata
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iny
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bne :-
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inc ptr+1
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dex
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bpl :-
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; Odd packet length ?
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lda len
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lsr
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bcc :+
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; Yes
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lda #%00100000 ; ODD
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bne :++ ; Always
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; No
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: lda #$00
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fixup36:sta ethdata ; Fill byte
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:
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fixup37:sta ethdata ; Control byte
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; Add packet to FIFO
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lda #%11000000 ; ENQUEUE PACKET - transmit packet
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fixup38:sta ethmmucr
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clc
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rts
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;---------------------------------------------------------------------
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exit:
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rts
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;---------------------------------------------------------------------
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releasepacket:
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; Remove and release RX packet from the FIFO
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lda #%10000000
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fixup39:sta ethmmucr
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rts
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;---------------------------------------------------------------------
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adjustptr:
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lda len
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ldx len+1
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eor #$FF ; Two's complement part 1
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tay
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iny ; Two's complement part 2
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sty reg
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sec
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lda bufaddr
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sbc reg
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sta ptr
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lda bufaddr+1
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sbc #$00
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sta ptr+1
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rts
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;---------------------------------------------------------------------
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