From d85eda74bf9c602c1dfcba5334257f5face3e7ba Mon Sep 17 00:00:00 2001
From: Vince Weaver <vincent.weaver@maine.edu>
Date: Mon, 12 Mar 2018 13:49:15 -0400
Subject: [PATCH] chiptune_player: had timing of absolute store wrong :(

it's 4 cycles, not 3
---
 chiptune_player/README.chiptune     | 12 ++++++------
 chiptune_player/interrupt_handler.s | 27 +++++++++++++--------------
 2 files changed, 19 insertions(+), 20 deletions(-)

diff --git a/chiptune_player/README.chiptune b/chiptune_player/README.chiptune
index d92d840f..889a0473 100644
--- a/chiptune_player/README.chiptune
+++ b/chiptune_player/README.chiptune
@@ -467,17 +467,17 @@ Interrupt Timing / AY write latency:
 ====================================
 	Originally roughly 1500 cycles from start of interrupt
 	to all AY registers being written.
-		1500
+		1600
 
 	Moved clock to after, near the visualization stuff, more like
-		1378 = 13+ (105*13)
+		1534 = 13+ (117*13)
 
 	Load frame data for next time at end of IRQ, instead of begin
-		1029 =	13+2+(78*13)
+		1185 =	13+2+(90*13)
 
 	Inlined the mockingboard write routine
-		873 =	13+2+(66*13)
+		1029 =	13+2+(78*13)
 
 	Only write registers that change.  Added 6 cycles per loop
-		951 worst case			= 13+2+(10+5+50+7)*13
-		304 if only one reg changed	= 13+2+(18*13)+55
+		1107 worst case			= 13+2+(10+5+62+7)*13
+		316 if only one reg changed	= 13+2+(18*13)+67
diff --git a/chiptune_player/interrupt_handler.s b/chiptune_player/interrupt_handler.s
index 2c21091d..7e1c5036 100644
--- a/chiptune_player/interrupt_handler.s
+++ b/chiptune_player/interrupt_handler.s
@@ -69,29 +69,28 @@ mb_not_13:
 	; inlined "write_ay_both" to save 12 cycles
 
 	; address
-	stx	MOCK_6522_ORA1		; put address on PA1		; 3
-	stx	MOCK_6522_ORA2		; put address on PA2		; 3
+	stx	MOCK_6522_ORA1		; put address on PA1		; 4
+	stx	MOCK_6522_ORA2		; put address on PA2		; 4
 	lda	#MOCK_AY_LATCH_ADDR	; latch_address for PB1		; 2
-	sta	MOCK_6522_ORB1		; latch_address on PB1          ; 3
-	sta	MOCK_6522_ORB2		; latch_address on PB2		; 3
+	sta	MOCK_6522_ORB1		; latch_address on PB1          ; 4
+	sta	MOCK_6522_ORB2		; latch_address on PB2		; 4
 	lda	#MOCK_AY_INACTIVE	; go inactive			; 2
-	sta	MOCK_6522_ORB1						; 3
-	sta	MOCK_6522_ORB2						; 3
+	sta	MOCK_6522_ORB1						; 4
+	sta	MOCK_6522_ORB2						; 4
 
         ; value
         lda	MB_VALUE						; 3
-        sta	MOCK_6522_ORA1		; put value on PA1		; 3
-        sta	MOCK_6522_ORA2		; put value on PA2		; 3
+        sta	MOCK_6522_ORA1		; put value on PA1		; 4
+        sta	MOCK_6522_ORA2		; put value on PA2		; 4
         lda	#MOCK_AY_WRITE		;				; 2
-        sta	MOCK_6522_ORB1		; write on PB1			; 3
-        sta	MOCK_6522_ORB2		; write on PB2			; 3
+        sta	MOCK_6522_ORB1		; write on PB1			; 4
+        sta	MOCK_6522_ORB2		; write on PB2			; 4
         lda	#MOCK_AY_INACTIVE	; go inactive			; 2
-        sta	MOCK_6522_ORB1						; 3
-        sta	MOCK_6522_ORB2						; 3
+        sta	MOCK_6522_ORB1						; 4
+        sta	MOCK_6522_ORB2						; 4
 
-									; 50
 								;===========
-								; 	50
+								; 	62
 mb_no_write:
 	inx				; point to next register	; 2
 	cpx	#14			; if 14 we're done		; 2