mirror of
https://github.com/deater/dos33fsprogs.git
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chiptune_debug: no luck, but have minimal reproducer
This commit is contained in:
Vince Weaver
parent
058882cb54
commit
fc6b3fd391
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@ -26,4 +26,49 @@ always volume 12 still issue
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fix clear accidentally wr r14 still issue
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generate single tone FINE!!!
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only play first 16 notes still issue
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only change C-fine value still issue
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only write val, not address still issue
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use handshake-free porta/6522 still issue
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Look at interrupt registers on 6522
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Emulator: IFR=$C0 IER=$80, Actual: IFR=$C0,IER=$C0
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For 6552-2 it is $00/$80 on both
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Tried soldering so pin 18 (PB1) always high
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still issue
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Tried reading back value from AY-3-8910, always match.
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Channel A and B now have glitches offset by 320ms?
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Interrupt happens at 50Hz=20ms? 16 samples??!??
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NOTE: Applewin Bugs
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+ Doesn't support reading back AY-3-8910 (Always returns
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last written value?)
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+ IER doesn't show Timer1 enabled? (returns 80 rather than C0)
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Now glitch happens exactly every 640ms (32 50Hz interrupts) when playing
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pattern of 8 notes repeatedly
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Remove other cards from machine to see if power issue
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still issue
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When down to writing 4 values,
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$51,$3c,$32,$50, issue seems to often hit on
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the 51->3C transition
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Down to two values, still only hit on the 51->3c transition.
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Sometimes everytime, sometimes every Xth time.
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$51 by itself = fine
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$3c by itself = fine
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50/3c and 50/32 also have issues, but not quite the same
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(Some, audio fading instead of glitch?)
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@ -4,6 +4,45 @@
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MB_CHUNK_OFFSET = $94
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MB_VALUE = $91
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; left speaker
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MOCK_6522_1_ORB = $C400 ; 6522 #1 port b data
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MOCK_6522_1_ORA = $C401 ; 6522 #1 port a data
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MOCK_6522_1_DDRB = $C402 ; 6522 #1 data direction port B
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MOCK_6522_1_DDRA = $C403 ; 6522 #1 data direction port A
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MOCK_6522_1_T1C_L = $C404 ; 6522 #1 Low-order counter
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MOCK_6522_1_T1C_H = $C405 ; 6522 #1 High-order counter
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MOCK_6522_1_T1L_L = $C406 ; 6522 #1 Low-order latch
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MOCK_6522_1_T1L_H = $C407 ; 6522 #1 High-order latch
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MOCK_6522_1_T2C_L = $C408 ; 6522 #1 Timer2 Low-order Latch/Counter
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MOCK_6522_1_T2C_H = $C409 ; 6522 #1 Timer2 High-order Latch/Counter
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MOCK_6522_1_SR = $C40A ; 6522 #1 Shift Register
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MOCK_6522_1_ACR = $C40B ; 6522 #1 Auxiliary Control Register
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MOCK_6522_1_PCR = $C40C ; 6522 #1 Peripheral Control Register
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MOCK_6522_1_IFR = $C40D ; 6522 #1 Interrupt Flag Register
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MOCK_6522_1_IER = $C40E ; 6522 #1 Interrupt Enable Register
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MOCK_6522_1_ORAN = $C40F ; 6522 #1 port a data, no handshake
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; right speaker
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MOCK_6522_2_ORB = $C480 ; 6522 #2 port b data
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MOCK_6522_2_ORA = $C481 ; 6522 #2 port a data
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MOCK_6522_2_DDRB = $C482 ; 6522 #2 data direction port B
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MOCK_6522_2_DDRA = $C483 ; 6522 #2 data direction port A
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MOCK_6522_2_T1C_L = $C484 ; 6522 #2 Low-order counter
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MOCK_6522_2_T1C_H = $C485 ; 6522 #2 High-order counter
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MOCK_6522_2_T1L_L = $C486 ; 6522 #2 Low-order latch
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MOCK_6522_2_T1L_H = $C487 ; 6522 #2 High-order latch
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MOCK_6522_2_T2C_L = $C488 ; 6522 #2 Timer2 Low-order Latch/Counter
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MOCK_6522_2_T2C_H = $C489 ; 6522 #2 Timer2 High-order Latch/Counter
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MOCK_6522_2_SR = $C48A ; 6522 #2 Shift Register
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MOCK_6522_2_ACR = $C48B ; 6522 #2 Auxiliary Control Register
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MOCK_6522_2_PCR = $C48C ; 6522 #2 Peripheral Control Register
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MOCK_6522_2_IFR = $C48D ; 6522 #2 Interrupt Flag Register
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MOCK_6522_2_IER = $C48E ; 6522 #2 Interrupt Enable Register
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MOCK_6522_2_ORAN = $C48F ; 6522 #2 port a data, no handshake
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;=========================
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; Init Variables
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;=========================
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@ -36,26 +75,54 @@ MB_VALUE = $91
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sei ; disable interrupts just in case
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lda #$40 ; Continuous interrupts, don't touch PB7
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sta $C40B ; ACR register
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sta MOCK_6522_1_ACR ; ACR register
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lda #$7F ; clear all interrupt flags
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sta $C40E ; IER register (interrupt enable)
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sta MOCK_6522_1_IER ; IER register (interrupt enable)
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lda #$C0
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sta $C40D ; IFR: 1100, enable interrupt on timer one oflow
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sta $C40E ; IER: 1100, enable timer one interrupt
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sta MOCK_6522_1_IFR ; IFR: 1100 0000
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; clear timer interrupt in flag register
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; should we try to clear all?
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sta MOCK_6522_1_IER ; IER: 1100 0000, enable timer1 interrupt
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lda #$E7
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sta $C404 ; write into low-order latch
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sta MOCK_6522_1_T1C_L ; write into low-order latch
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lda #$4f
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sta $C405 ; write into high-order latch,
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; load both values into counter
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; clear interrupt and start counting
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sta MOCK_6522_1_T1C_H ; write into high-order latch,
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; load both values into counter
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; clear interrupt and start counting
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; 4fe7 / 1e6 = .020s, 50Hz
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;==================
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; load first song
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;==================
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;=========================
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; Setup initial conditions
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;=========================
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; 5: C CHANNEL COARSE
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; ldx #5
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; lda #$0 ; always 0
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; sta MB_VALUE
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; jsr write_ay_both
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; 7: ENABLE
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ldx #7
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lda #$38 ; noise disabled, ABC enabled
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sta MB_VALUE
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jsr write_ay_both
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; 10: C Amplitude
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ldx #10
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lda #$c ; always volume 12
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sta MB_VALUE
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jsr write_ay_both
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; 4: C CHANNEL FINE
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ldx #4
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lda #$51
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sta MB_VALUE
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jsr write_ay_both
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;============================
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@ -78,17 +145,6 @@ main_loop:
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;routines
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;=========
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; left speaker
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MOCK_6522_ORB1 = $C400 ; 6522 #1 port b data
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MOCK_6522_ORA1 = $C401 ; 6522 #1 port a data
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MOCK_6522_DDRB1 = $C402 ; 6522 #1 data direction port B
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MOCK_6522_DDRA1 = $C403 ; 6522 #1 data direction port A
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; right speaker
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MOCK_6522_ORB2 = $C480 ; 6522 #2 port b data
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MOCK_6522_ORA2 = $C481 ; 6522 #2 port a data
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MOCK_6522_DDRB2 = $C482 ; 6522 #2 data direction port B
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MOCK_6522_DDRA2 = $C483 ; 6522 #2 data direction port A
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; AY-3-8910 commands on port B
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; RESET BDIR BC1
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@ -106,11 +162,16 @@ MOCK_AY_LATCH_ADDR = $7 ; 1 1 1
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; set the data direction for all pins of PortA/PortB to be output
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mockingboard_init:
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lda #$ff ; all output (1)
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sta MOCK_6522_DDRB1
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sta MOCK_6522_DDRA1
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sta MOCK_6522_DDRB2
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sta MOCK_6522_DDRA2
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lda #$ff ; all 8 pins output (1), portA
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sta MOCK_6522_1_DDRA
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sta MOCK_6522_2_DDRA
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; only 3 pins output (1), port B
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lda #$7
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sta MOCK_6522_1_DDRB
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sta MOCK_6522_2_DDRB
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rts
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reset_ay_both:
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@ -119,18 +180,18 @@ reset_ay_both:
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;======================
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reset_ay_left:
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lda #MOCK_AY_RESET
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sta MOCK_6522_ORB1
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sta MOCK_6522_1_ORB
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lda #MOCK_AY_INACTIVE
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sta MOCK_6522_ORB1
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sta MOCK_6522_1_ORB
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;======================
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; Reset Right AY-3-8910
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;======================
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reset_ay_right:
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lda #MOCK_AY_RESET
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sta MOCK_6522_ORB2
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sta MOCK_6522_2_ORB
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lda #MOCK_AY_INACTIVE
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sta MOCK_6522_ORB2
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sta MOCK_6522_2_ORB
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rts
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@ -144,30 +205,77 @@ reset_ay_right:
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; value in MB_VALUE
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write_ay_both:
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; address
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stx MOCK_6522_ORA1 ; put address on PA1 ; 3
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stx MOCK_6522_ORA2 ; put address on PA2 ; 3
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lda #MOCK_AY_LATCH_ADDR ; latch_address on PB1 ; 2
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sta MOCK_6522_ORB1 ; latch_address on PB1 ; 3
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sta MOCK_6522_ORB2 ; latch_address on PB2 ; 3
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lda #MOCK_AY_INACTIVE ; go inactive ; 2
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sta MOCK_6522_ORB1 ; 3
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sta MOCK_6522_ORB2 ; 3
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write_ay_address:
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; value
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lda MB_VALUE ; 3
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sta MOCK_6522_ORA1 ; put value on PA1 ; 3
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sta MOCK_6522_ORA2 ; put value on PA2 ; 3
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lda #MOCK_AY_WRITE ; ; 2
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sta MOCK_6522_ORB1 ; write on PB1 ; 3
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sta MOCK_6522_ORB2 ; write on PB2 ; 3
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lda #$ff
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sta MOCK_6522_1_DDRA
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; address
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stx MOCK_6522_1_ORA ; put address on PA1 ; 3
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stx MOCK_6522_2_ORA ; put address on PA2 ; 3
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lda #MOCK_AY_LATCH_ADDR ; latch_address on PB1 ; 2
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sta MOCK_6522_1_ORB ; latch_address on PB1 ; 3
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sta MOCK_6522_2_ORB ; latch_address on PB2 ; 3
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lda #MOCK_AY_INACTIVE ; go inactive ; 2
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sta MOCK_6522_ORB1 ; 3
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sta MOCK_6522_ORB2 ; 3
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sta MOCK_6522_1_ORB ; 3
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sta MOCK_6522_2_ORB ; 3
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write_ay_value:
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; value
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lda #$ff
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sta MOCK_6522_1_DDRA
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lda MB_VALUE ; 3
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sta MOCK_6522_1_ORA ; put value on PA1 ; 3
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sta MOCK_6522_2_ORA ; put value on PA2 ; 3
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lda #MOCK_AY_WRITE ; ; 2
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sta MOCK_6522_1_ORB ; write on PB1 ; 3
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sta MOCK_6522_2_ORB ; write on PB2 ; 3
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lda #MOCK_AY_INACTIVE ; go inactive ; 2
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sta MOCK_6522_1_ORB ; 3
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sta MOCK_6522_2_ORB ; 3
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rts ; 6
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;===========
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; 53
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read_ay_both:
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; value
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lda #$ff
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sta MOCK_6522_1_DDRA
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; address
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stx MOCK_6522_1_ORA ; put address on PA1 ; 3
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lda #MOCK_AY_LATCH_ADDR ; latch_address on PB1 ; 2
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sta MOCK_6522_1_ORB ; latch_address on PB1 ; 3
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lda #MOCK_AY_INACTIVE ; go inactive ; 2
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sta MOCK_6522_1_ORB ; 3
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read_ay_value:
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; value
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lda #$0
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sta MOCK_6522_1_DDRA
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lda #MOCK_AY_READ ; ; 2
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sta MOCK_6522_1_ORB ; read on PB1 ; 3
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ldy MOCK_6522_1_ORA ; read value
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lda #MOCK_AY_INACTIVE ; go inactive ; 2
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sta MOCK_6522_1_ORB ; 3
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tya
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rts ; 6
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;=======================================
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; clear ay -- clear all 14 AY registers
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; should silence the card
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@ -196,7 +304,72 @@ interrupt_handler:
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pha ; save A ; 3
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; Should we save X and Y too?
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bit $C404 ; clear 6522 interrupt by reading T1C-L ; 4
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.if 0
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lda MOCK_6522_1_IFR
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tay
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and #$f
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clc
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adc #'0'+$80
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sta $401
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tya
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lsr
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lsr
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lsr
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lsr
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clc
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adc #'0'+$80
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sta $400
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lda MOCK_6522_1_IER
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tay
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and #$f
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clc
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adc #'0'+$80
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sta $403
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tya
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lsr
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lsr
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lsr
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lsr
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clc
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adc #'0'+$80
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sta $402
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lda MOCK_6522_2_IFR
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tay
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and #$f
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clc
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adc #'0'+$80
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sta $407
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tya
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lsr
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lsr
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lsr
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lsr
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clc
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adc #'0'+$80
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sta $406
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lda MOCK_6522_2_IER
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tay
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and #$f
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clc
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adc #'0'+$80
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sta $409
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tya
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lsr
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lsr
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lsr
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lsr
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clc
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adc #'0'+$80
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sta $408
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.endif
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bit MOCK_6522_1_T1C_L ; clear 6522 interrupt by
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; reading T1C-L ; 4
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mb_play_music:
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@ -213,34 +386,32 @@ mb_write_frame:
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; 4: C CHANNEL FINE
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ldx #4
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; lda #$51
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lda c_fine,Y
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sta MB_VALUE
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jsr write_ay_both
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sta expected+4
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; 5: C CHANNEL COARSE
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ldx #5
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lda #$0 ; always 0
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sta MB_VALUE
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ldx #4
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jsr write_ay_both
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; jsr write_ay_value
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; 7: ENABLE
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ldx #7
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lda #$38 ; noise disabled, ABC enabled
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sta MB_VALUE
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jsr write_ay_both
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; read out all of AY registers and see if match expected
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ldx #0
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loop:
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jsr read_ay_both
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cmp expected,X
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beq good
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; 10: C Amplitude
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ldx #10
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lda #$c ; always volume 12
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sta MB_VALUE
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jsr write_ay_both
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brk
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good:
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inx
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cpx #14
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bne loop
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increment_offset:
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inc MB_CHUNK_OFFSET ; increment offset
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lda MB_CHUNK_OFFSET
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and #$f
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and #$1
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sta MB_CHUNK_OFFSET
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done_interrupt:
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@ -250,10 +421,17 @@ done_interrupt:
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expected: ; 0 1 2 3 4 5 6 7 8 9 10 11 12 13
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.byte $00,$00,$00,$00, $00,$00,$00,$38, $00,$00,$0c,$00, $00,$00
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; 4: C fine
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c_fine:
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.byte $51,$3c,$32,$50,$3d,$32,$50,$3c, $33,$50,$3c,$32,$51,$3c,$32,$50
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;.byte $51,$3c,$32,$50, $3d,$32,$50,$3c, $33,$50,$3c,$32,$51,$3c,$32,$50
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.byte $50,$32,$32,$50, $3d,$32,$50,$3c, $33,$50,$3c,$32,$51,$3c,$32,$50
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