mirror of
https://github.com/deater/dos33fsprogs.git
synced 2024-05-28 17:41:29 +00:00
269 lines
2.4 KiB
ArmAsm
269 lines
2.4 KiB
ArmAsm
; hgr fast vlin test
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HGR_BITS = $1C
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GBASL = $26
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GBASH = $27
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HGR_COLOR = $E4
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HGR_PAGE = $E6
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div7_table = $9000
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mod7_table = $9100
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KEYPRESS = $C000
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KEYRESET = $C010
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HGR2 = $F3D8 ; clear PAGE2 to 0
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HGR = $F3E2 ; set hires page1 and clear $2000-$3fff
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BKGND0 = $F3F4 ; clear screen to A
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HPOSN = $F411 ; (Y,X),(A) (values stores in HGRX,XH,Y)
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COLOR_SHIFT = $F47E
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COLORTBL = $F6F6
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main:
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; set graphics
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jsr HGR
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; init tables
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jsr vgi_init
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; draw lines
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; multicolor
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; for y=0 to 150 step 2:hgr_vlin 10,10+y at y: next
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ldy #0
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loop1:
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tya
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lsr
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lsr
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and #$7
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tax
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jsr set_hcolor
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tya
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pha
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tax ; X1=Y
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lda #10 ; Y1=A
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; ldy #100 ; Run = y
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jsr hgr_vlin ; vlin (x,a) to (x,a+y)
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pla
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tay
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iny
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iny
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iny
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iny
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cpy #160
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bne loop1
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jsr wait_until_keypress
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; test 2
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jsr HGR2
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; draw lines
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ldy #0
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loop2:
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ldx #7 ; draw white
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jsr set_hcolor
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tya ; save y on stack
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pha
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tax ; x1=Y
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tay ; yrun=y
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lda #0 ; y1=0
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jsr hgr_vlin
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pla
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tay
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iny
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iny
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iny
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iny
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iny
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cpy #150
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bne loop2
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jsr wait_until_keypress
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; test 3
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; jsr HGR2
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; note, clear to bgcolor=black2 or else edge looks a bit
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; ragged when $FF touches $00
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lda #$80
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jsr BKGND0
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; draw lines
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ldy #0
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loop3:
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ldx #7 ; draw white
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jsr set_hcolor
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tya
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pha
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tax ; X1=Y
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; Y1=A
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pha
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tya
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eor #$ff
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sec
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adc #191
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tay ; run=191-Y
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pla
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jsr hgr_vlin
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pla
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tay
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iny
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cpy #192
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bne loop3
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jsr wait_until_keypress
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; test 4
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jsr HGR2
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; draw lines
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ldy #0
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loop4:
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ldx #3 ; draw white1
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jsr set_hcolor
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tya
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pha
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tax ; X1=Y
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eor #$ff
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sec
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adc #192 ; Y1=192-Y
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; run = Y
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jsr hgr_vlin
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pla
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tay
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iny
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cpy #192
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bne loop4
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jsr wait_until_keypress
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; test 5
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; jsr HGR2
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; draw lines
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ldy #0
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loop5:
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ldx #0 ; draw white1
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jsr set_hcolor
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tya
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pha
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tax ; X1=Y
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eor #$ff
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sec
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adc #192 ; Y1=192-Y
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; run = Y
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jsr hgr_vlin
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pla
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tay
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iny
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cpy #192
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bne loop5
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jsr wait_until_keypress
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done:
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jmp main
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wait_until_keypress:
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bit KEYRESET
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keypress_loop:
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lda KEYPRESS
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bpl keypress_loop
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rts
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;=====================
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; make /7 %7 tables
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;=====================
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vgi_init:
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vgi_make_tables:
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ldy #0
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lda #0
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ldx #0
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div7_loop:
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sta div7_table,Y
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inx
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cpx #7
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bne div7_not7
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clc
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adc #1
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ldx #0
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div7_not7:
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iny
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bne div7_loop
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ldy #0
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lda #0
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mod7_loop:
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sta mod7_table,Y
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clc
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adc #1
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cmp #7
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bne mod7_not7
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lda #0
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mod7_not7:
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iny
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bne mod7_loop
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rts
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.include "hgr_vlin.s"
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