mirror of
https://github.com/deater/dos33fsprogs.git
synced 2024-12-27 17:29:49 +00:00
1078 lines
24 KiB
ArmAsm
1078 lines
24 KiB
ArmAsm
; Kansasfest18 HackFest Entry
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; by deater (Vince Weaver) <vince@deater.net>
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; Zero Page
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FRAMEBUFFER = $00 ; $00 - $0F
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YPOS = $10
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YPOS_SIN = $11
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FRAME = $60
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BLARGH = $69
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MB_VALUE = $91
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MB_ADDRL = $93
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MB_ADDRH = $94
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MBASE = $97
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MBOFFSET = $98
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DRAW_PAGE = $EE
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CURRENT_OFFSET = $EF
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OFFSET_GOVERNOR = $F0
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; Soft Switches
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SET_GR = $C050 ; Enable graphics
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FULLGR = $C052 ; Full screen, no text
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PAGE0 = $C054 ; Page0
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PAGE1 = $C055 ; Page1
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LORES = $C056 ; Enable LORES graphics
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; ROM routines
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TEXT = $FB36 ;; Set text mode
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HOME = $FC58 ;; Clear the text screen
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WAIT = $FCA8 ;; delay 1/2(26+27A+5A^2) us
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;===================
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; init screen
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jsr TEXT
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jsr HOME
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;===================
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; init vars
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lda #0
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sta DRAW_PAGE
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sta CURRENT_OFFSET
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sta OFFSET_GOVERNOR
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sta MBOFFSET
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lda #>music
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sta MBASE
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;==========================
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; setup mockingboard
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jsr mockingboard_init
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; Clear Page0
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lda #$00
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sta DRAW_PAGE
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jsr clear_gr
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; draw border line
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lda #$55
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ldy #38
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jsr hline
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; Clear Page1
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lda #$4
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sta DRAW_PAGE
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lda #$0
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jsr clear_gr
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; draw some green lines for character
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lda #$44
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ldy #28
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jsr clear_page_loop
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; draw border line
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; lda #$55
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; ldy #38
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; jsr hline
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;==================
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; Draw Blue Border on screen
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;==================
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; F -> 7 -> 6 -> 2
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lda #$0
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sta DRAW_PAGE
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lda #$6f
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ldy #0
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jsr hline
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lda #$72
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ldy #38
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jsr hline
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lda #$4
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sta DRAW_PAGE
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lda #$27
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ldy #0
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jsr hline
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lda #$f6
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ldy #38
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jsr hline
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;=====================================
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; Print the apple logos plus vmw logos
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;=====================================
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ldy #$a8
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ldx #0
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data_loop2:
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lda words,Y
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sta $450,X
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lda words2,Y
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sta $4d0,X
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lda words3,Y
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sta $850,X
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lda words4,Y
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sta $8d0,X
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iny
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inx
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cpx #40
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bne data_loop2
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;=====================================================
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; attempt vapor lock
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; by reading the "floating bus" we can see most recently
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; written value of the display
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; we look for $55 (which is the grey line)
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;=====================================================
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; See:
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; Have an Apple Split by Bob Bishop
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; Softalk, October 1982
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; Challenges: each scan line scans 40 bytes.
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; The blanking happens at the *beginning*
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; So 65 bytes are scanned, starting at adress of the line - 25
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; the scan takes 8 cycles, look for 4 repeats of the value
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; to avoid false positive found if the horiz blanking is mirroring
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; the line (max 3 repeats in that case)
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vapor_lock_loop: ; first make sure we have all zeroes
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LDA #$00
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zxloop:
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LDX #$04
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wiloop:
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CMP $C051
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BNE zxloop
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DEX
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BNE wiloop
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LDA #$72 ; now look for our border color (4 times)
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zloop:
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LDX #$04
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qloop:
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CMP $C051
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BNE zloop
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DEX
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BNE qloop
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; found first line of low-res grey, need to kill time
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; until we can enter at top of screen
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; so we want roughly 10 lines * 4 = 40*65 = 2600+4550-65
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; +4550 - 65 (for the scanline we missed) = 7085 - 12 = 7073
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; GR part
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bit LORES ; 4
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bit SET_GR ; 4
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bit FULLGR ; 4
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; want 7073
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; Try X=26 Y=52 cycles=7073
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lda #0 ; 2
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lda #0 ; 2
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ldy #52 ; 2
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loopA:
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ldx #26 ; 2
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loopB:
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dex ; 2
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bne loopB ; 2nt/3
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dey ; 2
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bne loopA ; 2nt/3
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jmp display_loop
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.align $100
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;================================================
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; Display Loop
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;================================================
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; each scan line 65 cycles
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; 1 cycle each byte (40cycles) + 25 for horizontal
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; Total of 12480 cycles to draw screen
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; Vertical blank = 4550 cycles (70 scan lines)
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; Total of 17030 cycles to get back to where was
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; We want to alternate between page1 and page2 every 65 cycles
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; vblank = 4550 cycles to do scrolling
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; 2 + 48*( (4+2+25*(2+3)) + (4+2+23*(2+3)+4+5)) + 9)
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; 48*[(6+125)-1] + [(6+115+10)-1]
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display_loop:
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ldy #48 ; 2
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outer_loop:
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bit PAGE0 ; 4
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ldx #25 ; 130 cycles with PAGE0 ; 2
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page0_loop: ; delay 126+bit
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dex ; 2
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bne page0_loop ; 2/3
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bit PAGE1 ; 4
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ldx #23 ; 130 cycles with PAGE1 ; 2
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page1_loop: ; delay 115+(7 loop)+4 (bit)+4(extra)
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dex ; 2
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bne page1_loop ; 2/3
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nop ; 2
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lda DRAW_PAGE ; 3
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dey ; 2
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bne outer_loop ; 2/3
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;======================================================
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; We have 4550 cycles in the vblank, use them wisely
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;======================================================
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; scroll_the_text should be 4550+1 -2 - 13 -13 = 4523
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; rasterbars should be 4550+1 -2 - 13 -18 = 4518
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; do_nothing should be 4550+1 -2 - 13 -19 = 4517
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inc OFFSET_GOVERNOR ; 5
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lda OFFSET_GOVERNOR ; 3
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and #$7 ; 2
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sta OFFSET_GOVERNOR ; 3
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;===========
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; 13
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cmp #$5 ; 2
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bne not_scroll
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; 2
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jsr scroll_the_text ; 6
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jmp display_loop ; 3
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not_scroll:
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; 5
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and #$1 ; 2
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bne we_should_do_nothing
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; 2
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jsr rasterbars ; 6
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jmp display_loop ; 3
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we_should_do_nothing:
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; 10
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jsr do_nothing ; 6
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jmp display_loop ; 3
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;==================================
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; HLINE
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;==================================
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; Color in A
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; Y has which line
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hline:
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pha ; 3
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ldx gr_offsets,y ; 4+
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stx hline_loop+1 ; 4
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lda gr_offsets+1,y ; 4+
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clc ; 2
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adc DRAW_PAGE ; 3
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sta hline_loop+2 ; 4
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pla ; 4
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ldx #39 ; 2
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hline_loop:
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sta $5d0,X ; 38 ; 5
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dex ; 2
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bpl hline_loop ; 2nt/3
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rts ; 6
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;==========================
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; Clear gr screen
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;==========================
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; Color in A
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clear_gr:
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ldy #46
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clear_page_loop:
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jsr hline
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dey
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dey
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bpl clear_page_loop
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rts
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;============================
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; Scroll the text
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;============================
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; we have 4523 to work with
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; we are off by two, why?
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scroll_the_text:
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; delay 2708 (4525 -1817 for scroll)
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; Try X=107 Y=5 cycles=2706 R2
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; waste 2 cycles
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nop ; 2
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ldy #5 ; 2
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loop5:
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ldx #107 ; 2
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loop6:
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dex ; 2
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bne loop6 ; 2nt/3
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dey ; 2
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bne loop5 ; 2nt/3
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;================================
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; SCROLL THE TEXT
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;================================
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; 5+ 40*(36 + 9) + 6 + 6
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; 17+40*(45) = 1817
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ldy CURRENT_OFFSET ; 3
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ldx #0 ; 2
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data_loop:
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lda words,Y ; 4+
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sta $6d0,X ; 5
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lda words2,Y ; 4+
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sta $750,X ; 5
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lda words3,Y ; 4+
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sta $ad0,X ; 5
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lda words4,Y ; 4+
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sta $b50,X ; 5
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iny ; 2
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inx ; 2
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cpx #40 ; 2
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bne data_loop ; 2nt/3
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inc CURRENT_OFFSET ; 6
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rts ; 6
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;=================================
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; do nothing
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;=================================
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; and take 4517-6 = 4511 cycles to do it
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do_nothing:
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; Try X=7 Y=110 cycles=4511
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ldy #110 ; 2
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loop1:
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ldx #7 ; 2
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loop2:
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dex ; 2
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bne loop2 ; 2nt/3
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dey ; 2
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bne loop1 ; 2nt/3
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rts ; 6
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.align $100
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;============================
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; Rasterbars
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;============================
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; we have 4518-6 = 4512 to work with
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rasterbars:
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; delay 31 (4512, -3725 draw_rasterbars
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; - 147 clear - 93 set_rasterbar - 516
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; Try X=8 Y=35 cycles=1611
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; Try X=3 Y=26 cycles=547
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; Try X=4 Y=2 cycles=53 R2
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; Try X=4 Y=1 cycles=27 R4
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nop
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nop
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ldy #1 ; 2
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loop3:
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ldx #4 ; 2
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loop4:
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dex ; 2
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bne loop4 ; 2nt/3
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dey ; 2
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bne loop3 ; 2nt/3
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;==================
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; Clear Framebuffer
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;==================
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; 4 + 16*9 - 1 = 147
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lda #0 ; 2
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ldx #15 ; 2
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clear_fb_loop:
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sta FRAMEBUFFER,X ; 4
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dex ; 2
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bpl clear_fb_loop ; 2nt/3
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;==================
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; Set Rasterbar
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;==================
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; 16 + 52 + 18 = 86 +7 = 93
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ldx YPOS ; get YPOS ; 3
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lda sine_table,X ; 4+
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sta YPOS_SIN ; 3
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and #$fc ; mask off bottom 2 bits ; 2
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lsr ; X = (YPOS / 4)*2 skip odd ; 2
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tax ; 2
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lda YPOS_SIN; get bottom 2 bits 0..3 ; 3
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and #$3 ; use to decide which pattern to use ; 2
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cmp #$0 ; 2
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; zero_rasterbar = 42 (add 10)
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; one_rasterbar = 46 (add 6)
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; two_rasterbar = 50 (add 2)
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; three_rasterbar = 52
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beq zero_rasterbar
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; 2
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cmp #$1 ; 2
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beq one_rasterbar
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; 2
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cmp #$2 ; 2
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beq two_rasterbar
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; 2
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bne three_rasterbar
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zero_rasterbar:
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; 3
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lda #$b1 ; 2
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sta FRAMEBUFFER,X ; 4
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lda #$f3 ; 2
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sta FRAMEBUFFER+1,X ; 4
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lda #$1b ; 2
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sta FRAMEBUFFER+2,X ; 4
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lda #$03 ; 2
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sta FRAMEBUFFER+3,X ; 4
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lda #$00 ; 2
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sta FRAMEBUFFER+4,X ; 4
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lda #$00 ; 2
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sta FRAMEBUFFER+5,X ; 4
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nop
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nop
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nop
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nop
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nop
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jmp done_draw_rasterbar ; 3
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;===========
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; 42
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one_rasterbar:
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; 4+3
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lda #$30 ; 2
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sta FRAMEBUFFER,X ; 4
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lda #$b1 ; 2
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sta FRAMEBUFFER+1,X ; 4
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lda #$3f ; 2
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sta FRAMEBUFFER+2,X ; 4
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lda #$1b ; 2
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sta FRAMEBUFFER+3,X ; 4
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lda #$00 ; 2
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sta FRAMEBUFFER+4,X ; 4
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lda #$00 ; 2
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sta FRAMEBUFFER+5,X ; 4
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nop
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nop
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nop
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jmp done_draw_rasterbar ; 3
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;==========
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; 46
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two_rasterbar:
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; 8+3
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lda #$10 ; 2
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sta FRAMEBUFFER,X ; 4
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lda #$30 ; 2
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sta FRAMEBUFFER+1,X ; 4
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lda #$bb ; 2
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sta FRAMEBUFFER+2,X ; 4
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lda #$3f ; 2
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sta FRAMEBUFFER+3,X ; 4
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lda #$01 ; 2
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sta FRAMEBUFFER+4,X ; 4
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lda #$00 ; 2
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sta FRAMEBUFFER+5,X ; 4
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nop
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jmp done_draw_rasterbar ; 3
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;==========
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; 50
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three_rasterbar:
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; 10+3
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lda #$00 ; 2
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sta FRAMEBUFFER,X ; 4
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lda #$10 ; 2
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sta FRAMEBUFFER+1,X ; 4
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lda #$f3 ; 2
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sta FRAMEBUFFER+2,X ; 4
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lda #$bb ; 2
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sta FRAMEBUFFER+3,X ; 4
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lda #$03 ; 2
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sta FRAMEBUFFER+4,X ; 4
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lda #$01 ; 2
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sta FRAMEBUFFER+5,X ; 4
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jmp done_draw_rasterbar ; 3
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;==========
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; 52
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done_draw_rasterbar:
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; movement = 7 + 5 + 3 +3 = 18
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ldx YPOS ; 3
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inx ; 2
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cpx #32 ; 2
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;===========
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; 7
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beq raster_bottom
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; 2
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jmp raster_move_done ; 3
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;==========
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; 5
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raster_bottom:
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; 3
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ldx #0 ; 2
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;===========
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; 5
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raster_move_done:
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stx YPOS ; 3
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jmp draw_rasterbars ; 3
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.align $100
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;==================
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; Draw Rasterbars
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;==================
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draw_rasterbars:
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; don't count the rts at end
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; 2 + YSIZE*[(8*16) + 5] - 1
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; 2 + (28*133) - 1
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; 3725 cycles
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ldx #27 ; 2
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raster_loop2:
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lda FRAMEBUFFER ; 3
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sta $606,X ; 5
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lda FRAMEBUFFER+2 ; 3
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sta $686,X ; 5
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lda FRAMEBUFFER+4 ; 3
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sta $706,X ; 5
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lda FRAMEBUFFER+6 ; 3
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sta $786,X ; 5
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lda FRAMEBUFFER+8 ; 3
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sta $42E,X ; 5
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lda FRAMEBUFFER+10 ; 3
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sta $4aE,X ; 5
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lda FRAMEBUFFER+12 ; 3
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sta $52E,X ; 5
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lda FRAMEBUFFER+14 ; 3
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sta $5aE,X ; 5
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lda FRAMEBUFFER+1
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sta $A06,X
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lda FRAMEBUFFER+3
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sta $A86,X
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lda FRAMEBUFFER+5
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sta $B06,X
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lda FRAMEBUFFER+7
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sta $B86,X
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lda FRAMEBUFFER+9
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sta $82e,X
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lda FRAMEBUFFER+11
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sta $8ae,X
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lda FRAMEBUFFER+13
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sta $92e,X
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lda FRAMEBUFFER+15
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sta $9ae,X
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dex ; 2
|
|
bpl raster_loop2 ; 2nt/3
|
|
|
|
|
|
all_done:
|
|
|
|
;=========================
|
|
; play mockingboard
|
|
;=========================
|
|
; 11+ 84*5 + 10*4 + 21 = 492
|
|
; + 24 for loop = 516
|
|
|
|
lda MBASE ; 3
|
|
sta MB_ADDRH ; 3
|
|
lda #0 ; 2
|
|
sta MB_ADDRL ; 3
|
|
;=============
|
|
; 11
|
|
|
|
ldx #0 ; 2
|
|
ldy MBOFFSET ; 3
|
|
lda (MB_ADDRL),Y ; 5
|
|
sta MB_VALUE ; 3
|
|
jsr write_ay_both ; 6+65
|
|
;===============
|
|
; 84
|
|
|
|
clc ; 2
|
|
lda #4 ; 2
|
|
adc MB_ADDRH ; 3
|
|
sta MB_ADDRH ; 3
|
|
;==============
|
|
; 10
|
|
ldx #2
|
|
ldy MBOFFSET
|
|
lda (MB_ADDRL),Y
|
|
sta MB_VALUE
|
|
jsr write_ay_both
|
|
|
|
clc
|
|
lda #4
|
|
adc MB_ADDRH
|
|
sta MB_ADDRH
|
|
|
|
ldx #3
|
|
ldy MBOFFSET
|
|
lda (MB_ADDRL),y
|
|
sta MB_VALUE
|
|
jsr write_ay_both
|
|
|
|
clc
|
|
lda #4
|
|
adc MB_ADDRH
|
|
sta MB_ADDRH
|
|
ldx #8
|
|
ldy MBOFFSET
|
|
lda (MB_ADDRL),y
|
|
sta MB_VALUE
|
|
jsr write_ay_both
|
|
|
|
clc
|
|
lda #4
|
|
adc MB_ADDRH
|
|
sta MB_ADDRH
|
|
|
|
ldx #9
|
|
ldy MBOFFSET
|
|
lda (MB_ADDRL),y
|
|
sta MB_VALUE
|
|
jsr write_ay_both
|
|
|
|
lda FRAME ; 3
|
|
lda #1 ; 2
|
|
clc ; 2
|
|
adc MBOFFSET ; 3
|
|
sta MBOFFSET ; 3
|
|
|
|
lda MBASE ; 3
|
|
adc #0 ; 2
|
|
sta MBASE ; 3
|
|
;=============
|
|
; 21
|
|
|
|
; 2=2 not loop
|
|
; 2+7+3= 12 = last page
|
|
; 2+7+15=24 = loop
|
|
|
|
; Loop mushc
|
|
|
|
cmp #>music+3 ; 2
|
|
bne waste_7 ;
|
|
; 2
|
|
lda MBOFFSET ; 3
|
|
cmp #$90 ; 2
|
|
bne waste_12 ;
|
|
; 2
|
|
lda #>music ; 2 ; loop to 0:90
|
|
sta MBASE ; 3
|
|
lda #$90 ; 2
|
|
sta MBOFFSET ; 3
|
|
jmp not_ready_to_loop ; 3
|
|
waste_7:
|
|
lda #0 ; 2
|
|
inc BLARGH ; 5
|
|
waste_12:
|
|
; 3
|
|
lda #0 ; 2
|
|
inc BLARGH ; 5
|
|
inc BLARGH ; 5
|
|
|
|
not_ready_to_loop:
|
|
|
|
rts ; 6
|
|
|
|
|
|
|
|
|
|
|
|
|
|
.align $100
|
|
words:
|
|
; H E L L O
|
|
.byte $D1,$00,$D1,$00, $D1,$01,$00, $D1,$00,$00, $D1,$00,$00, $D0,$01,$D0,$00, $00, $00
|
|
; K F E S T
|
|
.byte $D1,$00,$D1,$00, $D1,$01,$00, $D1,$01,$00, $D1,$D1,$00, $01,$D1,$01,$00
|
|
; 1 8 . . .
|
|
.byte $00,$D1,$00, $D0,$01,$D0,$00, $00,$00,$00, $00,$00,$00, $00,$00,$00, $00,$00
|
|
; H A V E
|
|
.byte $D1,$00,$D1,$00, $D0,$01,$D0,$00, $D1,$00,$D1,$00, $D1,$01,$00, $00,$00
|
|
; Y O U
|
|
.byte $D1,$00,$D1,$00, $D0,$01,$D0,$00, $D1,$00,$D1,$00, $00,$00
|
|
; E V E R
|
|
.byte $D1,$01,$00, $D1,$00,$D1,$00, $D1,$01,$00, $D1,$01,$D1,$00, $00,$00
|
|
; S E E N
|
|
.byte $D1,$D1,$00, $D1,$01,$00, $D1,$01,$00, $D1,$00,$D0,$D1,$00, $00,$00
|
|
; 4 0 x
|
|
.byte $D1,$00,$D1,$00, $D0,$01,$D0,$00, $D0,$00,$D0,$00
|
|
; 9 6
|
|
.byte $D1,$01,$D1,$00, $D1,$01,$01,$00, $00,$00
|
|
; L O -
|
|
.byte $D1,$00,$00, $D0,$01,$D0,$00, $0,$0,$0,$0
|
|
; R E S
|
|
.byte $D1,$01,$D1,$00, $D1,$01,$00, $D1,$D1,$00
|
|
; ?
|
|
.byte $01,$01,$D1,$00, $01,$01,$D1,$00
|
|
; Apple
|
|
.byte $0,$0,$00,$C0,$C0,$CC,$C0,$00,$0,$0
|
|
; VMW Logo
|
|
.byte $0,$0,$11,$11,$11,$11,$11,$44, $22,$22,$22,$22,$22,$44, $22,$22,$22,$22,$22,$00
|
|
; Apple
|
|
.byte $0,$0,$0,$00,$C0,$C0,$CC,$C0,$0,$0
|
|
.byte $0,$0,$0,$0,$0,$0,$0,$0,$0
|
|
; A ] [
|
|
.byte $99,$09,$99,$00, $09,$99,$00, $99,$09,$00,$00
|
|
; infinity
|
|
.byte $90,$D0,$D0,$90,$D0,$D0,$90,$00
|
|
|
|
|
|
.repeat 20
|
|
.byte $0
|
|
.endrep
|
|
words2:
|
|
.byte $24,$04,$24,$00, $24,$20,$00, $24,$20,$00, $24,$20,$00, $04,$20,$04,$00, $00,$00
|
|
.byte $24,$04,$20,$00, $24,$00,$00, $24,$20,$00, $20,$24,$00, $00,$24,$00,$00
|
|
.byte $00,$24,$00, $04,$20,$04,$00, $20,$20,$00, $20,$20,$00, $20,$20,$00, $00,$00
|
|
.byte $24,$04,$24,$00, $24,$00,$24,$00, $04,$20,$04,$00, $24,$20,$00, $00,$00
|
|
.byte $00,$24,$00,$00, $04,$20,$04,$00, $24,$20,$24,$00, $00,$00
|
|
.byte $24,$20,$00, $04,$20,$04,$00, $24,$20,$00, $24,$04,$20,$00, $00,$00
|
|
.byte $20,$24,$00, $24,$20,$00, $24,$20,$00, $24,$00,$00,$24,$00, $00,$00
|
|
.byte $00,$00,$24,$00, $04,$20,$04,$00, $00,$04,$00,$00
|
|
.byte $00,$00,$24,$00, $24,$20,$24,$00, $00,$00
|
|
.byte $24,$20,$00, $04,$20,$04,$00, $04,$04,$04,$0
|
|
.byte $24,$04,$20,$00, $24,$20,$00, $20,$24,$00
|
|
.byte $00,$20,$00,$00, $00,$20,$00,$00
|
|
.byte $0,$0,$29,$29,$29,$29,$20,$00,$0,$0
|
|
.byte $0,$0,$00,$01,$11,$41,$44,$44, $44,$42,$22,$42,$44,$44, $44,$42,$22,$02,$00,$00
|
|
.byte $0,$0,$0,$29,$29,$29,$29,$20,$0,$0
|
|
.byte $0,$0,$0,$0,$0,$0,$0,$0,$0
|
|
.byte $d9,$00,$d9,$00, $d0,$d9,$00, $d9,$d0,$00,$00
|
|
.byte $0D,$09,$09,$0D,$09,$09,$0D,$00
|
|
|
|
.repeat 20
|
|
.byte $0
|
|
.endrep
|
|
words3:
|
|
.byte $C9,$C0,$C9,$00, $C9,$C0,$00, $C9,$00,$00, $C9,$00,$00, $C9,$00,$C9,$00, $00,$00
|
|
.byte $C9,$C0,$09,$00, $C9,$C0,$00, $C9,$C0,$00, $C9,$C0,$00, $00,$C9,$00,$00
|
|
.byte $09,$C9,$00, $09,$C0,$09,$00, $00,$00,$00, $00,$00,$00, $00,$00,$00, $00,$00
|
|
.byte $C9,$C0,$C9,$00, $C9,$C0,$C9,$00, $C9,$00,$C9,$00, $C9,$C0,$00, $00,$00
|
|
.byte $09,$C0,$09,$00, $c9,$00,$c9,$00, $C9,$00,$C9,$00, $00,$00
|
|
.byte $C9,$C0,$00, $C9,$00,$C9,$00, $C9,$C0,$00, $C9,$C0,$C9,$00, $00,$00
|
|
.byte $C9,$C0,$00, $C9,$C0,$00, $C9,$C0,$00, $C9,$09,$00,$C9,$00, $00,$00
|
|
.byte $C9,$C0,$C9,$00, $C9,$00,$C9,$00, $00,$C0,$00,$00
|
|
.byte $C9,$C0,$C9,$00, $C9,$C0,$C0,$00, $00,$00
|
|
.byte $C9,$00,$00, $C9,$00,$C9,$00, $C0,$C0,$C0,$0
|
|
.byte $C9,$C0,$C9,$00, $C9,$C0,$00, $C9,$C0,$00
|
|
.byte $09,$C0,$C9,$00, $09,$C0,$C9,$00
|
|
.byte $0,$0,$D0,$D0,$DC,$D0,$00,$0,$0,$0
|
|
.byte $0,$0,$01,$11,$11,$11,$41,$44, $42,$22,$22,$22,$42,$44, $42,$22,$22,$22,$02,$00
|
|
.byte $0,$0,$0,$D0,$D0,$DC,$D0,$00,$0,$0
|
|
.byte $0,$0,$0,$0,$0,$0,$0,$0,$0
|
|
.byte $99,$9D,$99,$00, $0d,$99,$00, $99,$0d,$00,$00
|
|
.byte $90,$09,$09,$90,$09,$09,$90,$00
|
|
|
|
.repeat 20
|
|
.byte $0
|
|
.endrep
|
|
words4:
|
|
.byte $06,$00,$06,$00, $06,$00,$00, $06,$00,$00, $06,$00,$00, $06,$00,$06,$00, $00,$00
|
|
.byte $06,$00,$06,$00, $06,$00,$00, $06,$00,$00, $00,$06,$00, $00,$06,$00,$00
|
|
.byte $00,$06,$00, $06,$00,$06,$00, $06,$06,$00, $06,$06,$00, $06,$06,$00, $00,$00
|
|
.byte $06,$00,$06,$00, $06,$00,$06,$00, $00,$06,$00,$00, $06,$00,$00, $00,$00
|
|
.byte $00,$06,$00,$00, $06,$00,$06,$00, $06,$00,$06,$00, $00,$00
|
|
.byte $06,$00,$00, $00,$06,$00,$00, $06,$00,$00, $06,$00,$06,$00, $00,$00
|
|
.byte $00,$06,$00, $06,$00,$00, $06,$00,$00, $06,$00,$00,$06,$00, $00,$00
|
|
.byte $00,$00,$06,$00, $06,$00,$06,$00, $06,$00,$06,$00
|
|
.byte $00,$00,$06,$00, $06,$00,$06,$00, $00,$00
|
|
.byte $06,$00,$00, $06,$00,$06,$00, $0,$0,$0,$0
|
|
.byte $06,$00,$06,$00, $06,$00,$00, $00,$04,$00
|
|
.byte $00,$06,$00,$00, $00,$06,$00,$00
|
|
.byte $0,$0,$01,$61,$61,$61,$01,$00,$0,$0
|
|
.byte $0,$0,$00,$01,$11,$41,$44,$44, $44,$42,$22,$42,$44,$44, $44,$42,$22,$02,$00,$00
|
|
.byte $0,$0,$0,$01,$61,$61,$61,$01,$0,$0
|
|
.byte $0,$0,$0,$0,$0,$0,$0,$0,$0
|
|
.byte $09,$00,$09,$00, $09,$09,$00, $09,$09,$00,$00
|
|
.byte $00,$0D,$0D,$00,$0D,$0D,$00,$00
|
|
|
|
.repeat 20
|
|
.byte $0
|
|
.endrep
|
|
|
|
|
|
|
|
|
|
; Apple
|
|
;.byte $0,$0,$00,$C0,$C0,$CC,$C0,$0
|
|
;.byte $0,$0,$29,$29,$29,$29,$20,$0
|
|
;.byte $0,$0,$D0,$D0,$DC,$D0,$00,$0
|
|
;.byte $0,$0,$01,$61,$61,$61,$01,$0
|
|
|
|
; VMW Logo
|
|
;.byte $0,$0,$11,$11,$11,$11,$11,$44, $22,$22,$22,$22,$22,$44, $22,$22,$22,$22,$22,$00
|
|
;.byte $0,$0,$00,$01,$11,$41,$44,$44, $44,$42,$22,$42,$44,$44, $44,$42,$22,$02,$00,$00
|
|
;.byte $0,$0,$01,$11,$11,$11,$41,$44, $42,$22,$22,$22,$42,$44, $42,$22,$22,$22,$02,$00
|
|
;.byte $0,$0,$00,$01,$11,$41,$44,$44, $44,$42,$22,$42,$44,$44, $44,$42,$22,$02,$00,$00
|
|
|
|
|
|
gr_offsets:
|
|
.word $400,$480,$500,$580,$600,$680,$700,$780
|
|
.word $428,$4a8,$528,$5a8,$628,$6a8,$728,$7a8
|
|
.word $450,$4d0,$550,$5d0,$650,$6d0,$750,$7d0
|
|
|
|
|
|
sine_table:
|
|
.byte 12 ; 12.000000 0
|
|
.byte 14 ; 14.145992 1
|
|
.byte 16 ; 16.209514 2
|
|
.byte 18 ; 18.111268 3
|
|
.byte 20 ; 19.778169 4
|
|
.byte 21 ; 21.146161 5
|
|
.byte 22 ; 22.162671 6
|
|
.byte 23 ; 22.788636 7
|
|
.byte 23 ; 23.000000 8
|
|
.byte 23 ; 22.788641 9
|
|
.byte 22 ; 22.162682 10
|
|
.byte 21 ; 21.146177 11
|
|
.byte 20 ; 19.778190 12
|
|
.byte 18 ; 18.111292 13
|
|
.byte 16 ; 16.209541 14
|
|
.byte 14 ; 14.146020 15
|
|
.byte 12 ; 12.000029 16
|
|
.byte 10 ; 9.854037 17
|
|
.byte 8 ; 7.790513 18
|
|
.byte 6 ; 5.888756 19
|
|
.byte 4 ; 4.221851 20
|
|
.byte 3 ; 2.853856 21
|
|
.byte 2 ; 1.837341 22
|
|
.byte 1 ; 1.211370 23
|
|
.byte 1 ; 1.000000 24
|
|
.byte 1 ; 1.211353 25
|
|
.byte 2 ; 1.837307 26
|
|
.byte 3 ; 2.853807 27
|
|
.byte 4 ; 4.221789 28
|
|
.byte 6 ; 5.888683 29
|
|
.byte 8 ; 7.790432 30
|
|
.byte 10 ; 9.853951 31
|
|
|
|
.align $100
|
|
music:
|
|
.incbin "muda.tfv"
|
|
; ZP addresses
|
|
|
|
; left channel
|
|
MOCK_6522_1_ORB = $C400 ; 6522 #1 port b data
|
|
MOCK_6522_1_ORA = $C401 ; 6522 #1 port a data
|
|
MOCK_6522_1_DDRB = $C402 ; 6522 #1 data direction port B
|
|
MOCK_6522_1_DDRA = $C403 ; 6522 #1 data direction port A
|
|
MOCK_6522_1_T1C_L = $C404 ; 6522 #1 Low-order counter
|
|
MOCK_6522_1_T1C_H = $C405 ; 6522 #1 High-order counter
|
|
MOCK_6522_1_T1L_L = $C406 ; 6522 #1 Low-order latch
|
|
MOCK_6522_1_T1L_H = $C407 ; 6522 #1 High-order latch
|
|
MOCK_6522_1_T2C_L = $C408 ; 6522 #1 Timer2 Low-order Latch/Counter
|
|
MOCK_6522_1_T2C_H = $C409 ; 6522 #1 Timer2 High-order Latch/Counter
|
|
MOCK_6522_1_SR = $C40A ; 6522 #1 Shift Register
|
|
MOCK_6522_1_ACR = $C40B ; 6522 #1 Auxiliary Control Register
|
|
MOCK_6522_1_PCR = $C40C ; 6522 #1 Peripheral Control Register
|
|
MOCK_6522_1_IFR = $C40D ; 6522 #1 Interrupt Flag Register
|
|
MOCK_6522_1_IER = $C40E ; 6522 #1 Interrupt Enable Register
|
|
MOCK_6522_1_ORAN = $C40F ; 6522 #1 port a data, no handshake
|
|
|
|
; right channel
|
|
MOCK_6522_2_ORB = $C480 ; 6522 #2 port b data
|
|
MOCK_6522_2_ORA = $C481 ; 6522 #2 port a data
|
|
MOCK_6522_2_DDRB = $C482 ; 6522 #2 data direction port B
|
|
MOCK_6522_2_DDRA = $C483 ; 6522 #2 data direction port A
|
|
MOCK_6522_2_T1C_L = $C484 ; 6522 #2 Low-order counter
|
|
MOCK_6522_2_T1C_H = $C485 ; 6522 #2 High-order counter
|
|
MOCK_6522_2_T1L_L = $C486 ; 6522 #2 Low-order latch
|
|
MOCK_6522_2_T1L_H = $C487 ; 6522 #2 High-order latch
|
|
MOCK_6522_2_T2C_L = $C488 ; 6522 #2 Timer2 Low-order Latch/Counter
|
|
MOCK_6522_2_T2C_H = $C489 ; 6522 #2 Timer2 High-order Latch/Counter
|
|
MOCK_6522_2_SR = $C48A ; 6522 #2 Shift Register
|
|
MOCK_6522_2_ACR = $C48B ; 6522 #2 Auxiliary Control Register
|
|
MOCK_6522_2_PCR = $C48C ; 6522 #2 Peripheral Control Register
|
|
MOCK_6522_2_IFR = $C48D ; 6522 #2 Interrupt Flag Register
|
|
MOCK_6522_2_IER = $C48E ; 6522 #2 Interrupt Enable Register
|
|
MOCK_6522_2_ORAN = $C48F ; 6522 #2 port a data, no handshake
|
|
|
|
|
|
; AY-3-8910 commands on port B
|
|
; RESET BDIR BC1
|
|
MOCK_AY_RESET = $0 ; 0 0 0
|
|
MOCK_AY_INACTIVE = $4 ; 1 0 0
|
|
MOCK_AY_READ = $5 ; 1 0 1
|
|
MOCK_AY_WRITE = $6 ; 1 1 0
|
|
MOCK_AY_LATCH_ADDR = $7 ; 1 1 1
|
|
|
|
|
|
;========================
|
|
; Mockingboard Init
|
|
;========================
|
|
; Initialize the 6522s
|
|
; set the data direction for all pins of PortA/PortB to be output
|
|
|
|
mockingboard_init:
|
|
lda #$ff ; all 8 pins output (1), portA
|
|
|
|
sta MOCK_6522_1_DDRA
|
|
sta MOCK_6522_2_DDRA
|
|
; only 3 pins output (1), port B
|
|
lda #$7
|
|
sta MOCK_6522_1_DDRB
|
|
|
|
sta MOCK_6522_2_DDRB
|
|
|
|
|
|
reset_ay_both:
|
|
;======================
|
|
; Reset Left AY-3-8910
|
|
;======================
|
|
reset_ay_left:
|
|
lda #MOCK_AY_RESET
|
|
sta MOCK_6522_1_ORB
|
|
lda #MOCK_AY_INACTIVE
|
|
sta MOCK_6522_1_ORB
|
|
|
|
; AY-3-8913: Wait 5 us
|
|
nop
|
|
nop
|
|
nop
|
|
nop
|
|
nop
|
|
|
|
;======================
|
|
; Reset Right AY-3-8910
|
|
;======================
|
|
reset_ay_right:
|
|
lda #MOCK_AY_RESET
|
|
sta MOCK_6522_2_ORB
|
|
lda #MOCK_AY_INACTIVE
|
|
sta MOCK_6522_2_ORB
|
|
|
|
; AY-3-8913: Wait 5 us
|
|
nop
|
|
nop
|
|
nop
|
|
nop
|
|
nop
|
|
|
|
;=========================
|
|
; Setup initial conditions
|
|
;=========================
|
|
|
|
|
|
; 7: ENABLE
|
|
ldx #7
|
|
lda #$38 ; noise disabled, ABC enabled
|
|
sta MB_VALUE
|
|
jsr write_ay_both
|
|
|
|
rts
|
|
|
|
|
|
|
|
;=========================================
|
|
; Write Right/Left to save value AY-3-8910
|
|
;=========================================
|
|
; register in X
|
|
; value in MB_VALUE
|
|
|
|
write_ay_both:
|
|
; address
|
|
stx MOCK_6522_1_ORA ; put address on PA1 ; 4
|
|
stx MOCK_6522_2_ORA ; put address on PA2 ; 4
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lda #MOCK_AY_LATCH_ADDR ; latch_address on PB1 ; 2
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sta MOCK_6522_1_ORB ; latch_address on PB1 ; 4
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sta MOCK_6522_2_ORB ; latch_address on PB2 ; 4
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lda #MOCK_AY_INACTIVE ; go inactive ; 2
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sta MOCK_6522_1_ORB ; 4
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sta MOCK_6522_2_ORB ; 4
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;===========
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|
; 28
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|
; value
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lda MB_VALUE ; 3
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sta MOCK_6522_1_ORA ; put value on PA1 ; 4
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sta MOCK_6522_2_ORA ; put value on PA2 ; 4
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lda #MOCK_AY_WRITE ; ; 2
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sta MOCK_6522_1_ORB ; write on PB1 ; 4
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sta MOCK_6522_2_ORB ; write on PB2 ; 4
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lda #MOCK_AY_INACTIVE ; go inactive ; 2
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sta MOCK_6522_1_ORB ; 4
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sta MOCK_6522_2_ORB ; 4
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|
;===========
|
|
; 31
|
|
|
|
rts ; 6
|
|
;===========
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|
; 65
|
|
|
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