mirror of
https://github.com/deater/dos33fsprogs.git
synced 2025-01-29 21:31:53 +00:00
fb63c0742c
also fix some other bugs, need to check in more
165 lines
2.2 KiB
ArmAsm
165 lines
2.2 KiB
ArmAsm
; VGI Rectangle test
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COUNT = $75
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HGR_COLOR = $E4
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P0 = $F0
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P1 = $F1
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P2 = $F2
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P3 = $F3
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P4 = $F4
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P5 = $F5
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HGR2 = $F3D8 ; clear PAGE2 to 0
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BKGND0 = $F3F4 ; clear current page to A
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HPOSN = $F411 ; (Y,X),(A) (values stores in HGRX,XH,Y)
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HPLOT0 = $F457 ; plot at (Y,X), (A)
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HLINRL = $F530 ; (X,A),(Y)
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HGLIN = $F53A ; line to (A,X),(Y)
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COLORTBL = $F6F6
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;=================================
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; Simple Rectangle
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;=================================
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VGI_RCOLOR = P0
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VGI_RX1 = P1
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VGI_RY1 = P2
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VGI_RXRUN = P3
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VGI_RYRUN = P4
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test:
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; clear screen to white
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jsr HGR2
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lda #$ff
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jsr BKGND0
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; first test
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lda #$23
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sta VGI_RCOLOR
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lda #15
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sta VGI_RX1
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lda #230
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sta VGI_RXRUN
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lda #0
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sta VGI_RY1
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lda #191
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sta VGI_RYRUN
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jsr vgi_simple_rectangle
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; second test
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lda #$00
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sta VGI_RCOLOR
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lda #100
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sta VGI_RX1
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lda #1
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sta VGI_RXRUN
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lda #0
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sta VGI_RY1
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lda #191
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sta VGI_RYRUN
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jsr vgi_simple_rectangle
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end:
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jmp end
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vgi_simple_rectangle:
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simple_rectangle_loop:
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lda VGI_RCOLOR
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asl ; nibble swap by david galloway
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adc #$80
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rol
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asl
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adc #$80
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rol
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sta VGI_RCOLOR
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and #$f
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tax
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lda COLORTBL,X
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sta HGR_COLOR
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ldx VGI_RX1 ; X1 into X
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lda VGI_RY1 ; Y1 into A
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ldy #0 ; always 0
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jsr HPOSN ; (Y,X),(A) (values stores in HGRX,XH,Y)
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lda VGI_RXRUN ; XRUN into A
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ldx #0 ; always 0
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ldy #0 ; relative Y is 0
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jsr HLINRL ; (X,A),(Y)
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inc VGI_RY1
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dec VGI_RYRUN
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bne simple_rectangle_loop
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rts
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;=================================
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; Dithered Rectangle
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;=================================
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; VGI_RCOLOR = P0
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; VGI_RX1 = P1
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; VGI_RY1 = P2
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; VGI_RXRUN = P3
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; VGI_RYRUN = P4
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VGI_RCOLOR2 = P5
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vgi_dithered_rectangle:
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dithered_rectangle_loop:
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lda COUNT
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and #$1
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beq even_color
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odd_color:
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lda VGI_RCOLOR
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jmp save_color
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even_color:
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lda VGI_RCOLOR2
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save_color:
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sta HGR_COLOR
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inc COUNT
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ldx VGI_RX1 ; X1 into X
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lda VGI_RY1 ; Y1 into A
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ldy #0 ; always 0
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jsr HPOSN ; (Y,X),(A) (values stores in HGRX,XH,Y)
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lda VGI_RXRUN ; XRUN into A
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ldx #0 ; always 0
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ldy #0 ; relative Y is 0
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jsr HLINRL ; (X,A),(Y)
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inc VGI_RY1
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dec VGI_RYRUN
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bne dithered_rectangle_loop
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rts
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