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483 lines
12 KiB
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<html><head><meta http-equiv="Content-Type" content="text/html; charset=utf-8"/><link rel="stylesheet" type="text/css" href="ca65-doc-style.css"/></head><body><a href="ref_index.html"><h1>ip65 technical reference</h1></a><h1>File : drivers/lan91c96.s</h1><pre> Ethernet driver for SMC LAN91C96 chip
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</pre><h2 id="functions">functions</h2><table><tr><th>function</th><th>description</th></tr><tr><td id="eth_init">eth_init</td><td><pre>initialize the ethernet adaptor
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inputs: none
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outputs: carry flag is set if there was an error, clear otherwise
</pre></td></tr><tr><td id="eth_rx">eth_rx</td><td><pre>receive a packet
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inputs: none
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outputs:
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if there was an error receiving the packet (or no packet was ready) then carry flag is set
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if packet was received correctly then carry flag is clear,
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eth_inp contains the received packet,
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and eth_inp_len contains the length of the packet
</pre></td></tr><tr><td id="eth_tx">eth_tx</td><td><pre> send a packet
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inputs:
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eth_outp: packet to send
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eth_outp_len: length of packet to send
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outputs:
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if there was an error sending the packet then carry flag is set
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otherwise carry flag is cleared
</pre></td></tr></table><h2 id="constants">constants</h2><table><tr><th>constants</th><th>description</th><th>value</th></tr><tr><td id="eth_driver_io_base">eth_driver_io_base</td><td></td><td>fixlan01+1
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</td></tr><tr><td id="eth_driver_name">eth_driver_name</td><td></td><td>"LANceGS (91C96)"
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</td></tr></table><h2>implementation</h2><pre id="code">
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; Ethernet driver for SMC LAN91C96 chip
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;
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.ifndef KPR_API_VERSION_NUMBER
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.define EQU =
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.include "../inc/kipper_constants.i"
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.endif
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.include "../inc/common.i"
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.export eth_init
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.export eth_rx
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.export eth_tx
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.export eth_driver_name
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.export eth_driver_io_base
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.import eth_inp
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.import eth_inp_len
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.import eth_outp
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.import eth_outp_len
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.import cfg_mac
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; LANceGS hardware addresses
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ethbsr := $c00E ; Bank select register R/W (2B)
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; Register bank 0
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ethtcr := $c000 ; Transmission control register R/W (2B)
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ethephsr := $c002 ; EPH status register R/O (2B)
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ethrcr := $c004 ; Receive control register R/W (2B)
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ethecr := $c006 ; Counter register R/O (2B)
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ethmir := $c008 ; Memory information register R/O (2B)
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ethmcr := $c00A ; Memory Config. reg. +0 R/W +1 R/O (2B)
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; Register bank 1
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ethcr := $c000 ; Configuration register R/W (2B)
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ethbar := $c002 ; Base address register R/W (2B)
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ethiar := $c004 ; Individual address register R/W (6B)
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ethgpr := $c00A ; General address register R/W (2B)
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ethctr := $c00C ; Control register R/W (2B)
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; Register bank 2
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ethmmucr := $c000 ; MMU command register W/O (1B)
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ethautotx := $c001 ; AUTO TX start register R/W (1B)
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ethpnr := $c002 ; Packet number register R/W (1B)
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etharr := $c003 ; Allocation result register R/O (1B)
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ethfifo := $c004 ; FIFO ports register R/O (2B)
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ethptr := $c006 ; Pointer register R/W (2B)
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ethdata := $c008 ; Data register R/W (4B)
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ethist := $c00C ; Interrupt status register R/O (1B)
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ethack := $c00C ; Interrupt acknowledge register W/O (1B)
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ethmsk := $c00D ; Interrupt mask register R/W (1B)
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; Register bank 3
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ethmt := $c000 ; Multicast table R/W (8B)
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ethmgmt := $c008 ; Management interface R/W (2B)
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ethrev := $c00A ; Revision register R/W (2B)
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ethercv := $c00C ; Early RCV register R/W (2B)
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.segment "IP65ZP" : zeropage
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eth_packet: .res 2
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.data
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;initialize the ethernet adaptor
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;inputs: none
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;outputs: carry flag is set if there was an error, clear otherwise
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eth_init:
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jsr lan_self_modify
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lda #$01
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fixlan00:
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sta ethbsr ; Select register bank 1
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fixlan01:
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lda ethcr ; Read first four bytes - $31, $20, $67, $18
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cmp #$31
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bne lanerror
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fixlan03:
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lda ethbar
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cmp #$67
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bne lanerror
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fixlan04:
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lda ethbar+1
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cmp #$18
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bne lanerror
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; we have the magic signature
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; Reset ETH card
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lda #$00 ; Bank 0
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fixlan05:
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sta ethbsr
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lda #%10000000 ; Software reset
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fixlan06:
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sta ethrcr+1
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ldy #$00
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fixlan07:
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sty ethrcr
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fixlan08:
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sty ethrcr+1
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; Delay
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: cmp ($FF,x) ; 6 cycles
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cmp ($FF,x) ; 6 cycles
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iny ; 2 cycles
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bne :- ; 3 cycles
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; 17 * 256 = 4352 -> 4,4 ms
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; Enable transmit and receive
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lda #%10000001 ; Enable transmit TXENA, PAD_EN
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ldx #%00000011 ; Enable receive, strip CRC ???
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fixlan09:
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sta ethtcr
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fixlan10:
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stx ethrcr+1
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lda #$01 ; Bank 1
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fixlan11:
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sta ethbsr
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fixlan12:
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lda ethcr+1
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ora #%00010000 ; No wait (IOCHRDY)
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fixlan13:
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sta ethcr+1
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lda #%00001001 ; Auto release
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fixlan14:
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sta ethctr+1
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; Set MAC address
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lda cfg_mac
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ldx cfg_mac + 1
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fixlan15:
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sta ethiar
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fixlan16:
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stx ethiar + 1
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lda cfg_mac + 2
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ldx cfg_mac + 3
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fixlan17:
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sta ethiar + 2
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fixlan18:
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stx ethiar + 3
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lda cfg_mac + 4
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ldx cfg_mac + 5
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fixlan19:
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sta ethiar + 4
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fixlan20:
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stx ethiar + 5
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; Set interrupt mask
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lda #$02 ; Bank 2
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fixlan21:
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sta ethbsr
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lda #%00000000 ; No interrupts
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fixlan22:
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sta ethmsk
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clc
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rts
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lanerror:
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sec
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rts
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;receive a packet
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;inputs: none
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;outputs:
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; if there was an error receiving the packet (or no packet was ready) then carry flag is set
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; if packet was received correctly then carry flag is clear,
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; eth_inp contains the received packet,
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; and eth_inp_len contains the length of the packet
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eth_rx:
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fixlan38:
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lda ethist
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and #%00000001 ; Check receive interrupt
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bne :+
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sec ; No packet available
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rts
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: lda #$00
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ldx #%11100000 ; Receive, Auto Increment, Read
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fixlan39:
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sta ethptr
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fixlan40:
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stx ethptr + 1
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; Last word contains 'last data byte' and $60 or 'fill byte' and $40
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fixlan41:
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lda ethdata ; Status word
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fixlan42:
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lda ethdata ; Only need high byte
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; Move ODDFRM bit into carry:
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; - Even packet length -> carry clear -> subtract 6 bytes
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; - Odd packet length -> carry set -> subtract 5 bytes
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lsr
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lsr
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lsr
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lsr
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lsr
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; The packet contains 3 extra words
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fixlan43:
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lda ethdata ; Total number of bytes
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sbc #$05 ; Actually 5 or 6 depending on carry
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sta eth_inp_len
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fixlan44:
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lda ethdata
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sbc #$00
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sta eth_inp_len+1
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; Read bytes into buffer
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lda #<eth_inp
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ldx #>eth_inp
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sta eth_packet
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stx eth_packet+1
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ldx eth_inp_len+1
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ldy #$00
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lanread:
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fixlan46:
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lda ethdata
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sta (eth_packet),y
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iny
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bne :+
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inc eth_packet+1
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: cpy eth_inp_len
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bne lanread
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dex
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bpl lanread
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; Remove and release RX packet from the FIFO
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lda #%10000000
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fixlan47:
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sta ethmmucr
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clc
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rts
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; send a packet
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;inputs:
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; eth_outp: packet to send
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; eth_outp_len: length of packet to send
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;outputs:
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; if there was an error sending the packet then carry flag is set
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; otherwise carry flag is cleared
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eth_tx:
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lda eth_outp_len + 1 ;
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ora #%00100000
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fixlan23:
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sta ethmmucr ; Allocate memory for transmission
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fixlan24:
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lda ethist
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and #%00001000 ; Allocation interrupt
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bne :+
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sec
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rts ; Not able to allocate; bail
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: lda #%00001000
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fixlan25:
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sta ethack ; Acknowledge interrupt
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fixlan26:
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lda etharr
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fixlan27:
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sta ethpnr ; Set packet number
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lda #$00
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ldx #%01000000 ; Auto increment
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fixlan28:
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sta ethptr
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fixlan29:
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stx ethptr + 1
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lda #$00 ; Status written by CSMA
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fixlan30:
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sta ethdata
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fixlan31:
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sta ethdata
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lda eth_outp_len
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eor #$01
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lsr
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lda eth_outp_len
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adc #$05 ; Actually will be 5 or 6 depending on carry
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fixlan32:
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sta ethdata
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lda eth_outp_len + 1
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adc #$00
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fixlan33:
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sta ethdata
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lda #<eth_outp ; Send the packet
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ldx #>eth_outp
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sta eth_packet
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stx eth_packet + 1
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ldx eth_outp_len + 1
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ldy #$00
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lanwrite:
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lda (eth_packet),y
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fixlan34:
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sta ethdata
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iny
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bne :+
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inc eth_packet + 1
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: cpy eth_outp_len
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bne lanwrite
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dex
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bpl lanwrite
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lda eth_outp_len ; Odd packet length?
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lsr
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bcc :+
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lda #%001000000 ; Yes, Odd
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bne fixlan36 ; Always
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: lda #$00 ; No
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fixlan35:
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sta ethdata ; Fill byte
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fixlan36:
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sta ethdata ; Control byte
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lda #%11000000 ; Enqueue packet - transmit
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fixlan37:
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sta ethmmucr
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clc
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rts
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;
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; lan_self_modify - make all entry points variable so we can move the
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; LANceGS card around in the Apple
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;
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lan_self_modify:
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lda #$C0 ; FIXME - hardcoded to slot 4
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clc ; We'll be adding later, so clear carry
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; Make the accumulator contain slot number plus $80
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; i.e. Slot 1 = $90
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; i.e. Slot 2 = $A0
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; i.e. Slot 3 = $B0
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; i.e. Slot 4 = $C0
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; i.e. Slot 5 = $D0
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; i.e. Slot 6 = $E0
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; i.e. Slot 7 = $F0
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; $C0s0: Save off all ethtcr, ethcr, ethmmucr, and ethmt mods
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sta fixlan01 + 1
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sta fixlan09 + 1
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sta fixlan23 + 1
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sta fixlan37 + 1
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; sta fixlan45 + 1 ; Removed
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sta fixlan47 + 1
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; $C0s1: Save off all ethtcr+1, ethcr+1, ethmmucr+1, and ethmt+1 mods
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adc #$01
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; sta fixlan02 + 1 ; Removed
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sta fixlan12 + 1
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sta fixlan13 + 1
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; $C0s2: Save off all ethephsr, ethbar, and ethpnr mods
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adc #$01
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sta fixlan03 + 1
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sta fixlan27 + 1
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|
||
|
|
; $C0s3: Save off all ethephsr+1, ethbar+1, ethpnr+1, and etharr mods
|
||
|
|
adc #$01
|
||
|
|
sta fixlan04 + 1
|
||
|
|
sta fixlan26 + 1
|
||
|
|
|
||
|
|
; $C0s4: Save off all ethrcr, ethiar, and ethfifo mods
|
||
|
|
adc #$01
|
||
|
|
sta fixlan07 + 1
|
||
|
|
sta fixlan15 + 1
|
||
|
|
|
||
|
|
; $C0s5: Save off all ethrcr+1, ethiar+1, and ethfifo+1 mods
|
||
|
|
adc #$01
|
||
|
|
sta fixlan06 + 1
|
||
|
|
sta fixlan08 + 1
|
||
|
|
sta fixlan10 + 1
|
||
|
|
sta fixlan16 + 1
|
||
|
|
|
||
|
|
; $C0s6: Save off all ethecr, ethptr, and ethiar+2 mods
|
||
|
|
adc #$01
|
||
|
|
sta fixlan17 + 1
|
||
|
|
sta fixlan28 + 1
|
||
|
|
sta fixlan39 + 1
|
||
|
|
|
||
|
|
; $C0s7: Save off all ethecr+1, ethptr+1, and ethiar+3 mods
|
||
|
|
adc #$01
|
||
|
|
sta fixlan18 + 1
|
||
|
|
sta fixlan29 + 1
|
||
|
|
sta fixlan40 + 1
|
||
|
|
|
||
|
|
; $C0s8: Save off all ethmir, ethdata, ethmgmt, and ethiar+4 mods
|
||
|
|
adc #$01
|
||
|
|
sta fixlan19 + 1
|
||
|
|
sta fixlan30 + 1
|
||
|
|
sta fixlan31 + 1
|
||
|
|
sta fixlan32 + 1
|
||
|
|
sta fixlan33 + 1
|
||
|
|
sta fixlan34 + 1
|
||
|
|
sta fixlan35 + 1
|
||
|
|
sta fixlan36 + 1
|
||
|
|
sta fixlan41 + 1
|
||
|
|
sta fixlan42 + 1
|
||
|
|
sta fixlan43 + 1
|
||
|
|
sta fixlan44 + 1
|
||
|
|
sta fixlan46 + 1
|
||
|
|
|
||
|
|
; $C0s9: Save off all ethmir+1, ethdata+1, ethmgmt+1, and ethiar+5 mods
|
||
|
|
adc #$01
|
||
|
|
sta fixlan20 + 1
|
||
|
|
|
||
|
|
; $C0sA: Save off all ethmcr, ethgpr, and ethrev mods
|
||
|
|
; $C0sB: Save off all ethmcr+1, ethgpr+1, and ethrev+1 mods
|
||
|
|
; None
|
||
|
|
|
||
|
|
; $C0sC: Save off all ethctr, ethist, ethack, and ethercv mods
|
||
|
|
adc #$03 ; Because there were no a or b mods
|
||
|
|
sta fixlan24 + 1
|
||
|
|
sta fixlan25 + 1
|
||
|
|
sta fixlan38 + 1
|
||
|
|
|
||
|
|
; $C0sD: Save off all ethmsk, ethctr+1 mods
|
||
|
|
adc #$01
|
||
|
|
sta fixlan14 + 1
|
||
|
|
sta fixlan22 + 1
|
||
|
|
|
||
|
|
; $C0sE: Save off all ethbsr mods
|
||
|
|
adc #$01
|
||
|
|
sta fixlan00 + 1
|
||
|
|
sta fixlan05 + 1
|
||
|
|
sta fixlan11 + 1
|
||
|
|
sta fixlan21 + 1
|
||
|
|
|
||
|
|
rts
|
||
|
|
|
||
|
|
.rodata
|
||
|
|
eth_driver_name:
|
||
|
|
.asciiz "LANceGS (91C96)"
|
||
|
|
eth_driver_io_base=fixlan01+1
|
||
|
|
|
||
|
|
|
||
|
|
; The contents of this file are subject to the Mozilla Public License
|
||
|
|
; Version 1.1 (the "License"); you may not use this file except in
|
||
|
|
; compliance with the License. You may obtain a copy of the License at
|
||
|
|
; http://www.mozilla.org/MPL/
|
||
|
|
;
|
||
|
|
; Software distributed under the License is distributed on an "AS IS"
|
||
|
|
; basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the
|
||
|
|
; License for the specific language governing rights and limitations
|
||
|
|
; under the License.
|
||
|
|
;
|
||
|
|
; The Original Code is ip65.
|
||
|
|
;
|
||
|
|
; The Initial Developer of the Original Code is David Schmidt
|
||
|
|
; Portions created by the Initial Developer is Copyright (C) 2011
|
||
|
|
; All Rights Reserved.
|
||
|
|
; -- LICENSE END --
|
||
|
|
</pre></body></html>
|