2013-12-13 21:24:03 +00:00
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;
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2014-06-12 22:00:53 +00:00
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; Copyright (c) 2007, Adam Dunkels and Oliver Schmidt
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; All rights reserved.
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2013-12-27 13:57:56 +00:00
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;
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2014-06-12 22:00:53 +00:00
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions
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; are met:
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; 1. Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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; 2. Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in the
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; documentation and/or other materials provided with the distribution.
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; 3. Neither the name of the Institute nor the names of its contributors
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; may be used to endorse or promote products derived from this software
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; without specific prior written permission.
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2013-12-27 13:57:56 +00:00
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;
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2014-06-12 22:00:53 +00:00
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; THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
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; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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; ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
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; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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; OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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; HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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; LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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; OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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; SUCH DAMAGE.
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2013-12-27 13:57:56 +00:00
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;
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2014-06-12 22:00:53 +00:00
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; This file is part of the Contiki operating system.
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;
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; Author: Adam Dunkels <adam@sics.se>, Oliver Schmidt <ol.sc@web.de>
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;
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;---------------------------------------------------------------------
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.macpack module
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module_header _cs8900a
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; Driver signature
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.byte $65, $74, $68 ; "eth"
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.byte $01 ; Ethernet driver API version number
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; Ethernet address
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mac: .byte $00, $0E, $3A ; OUI of Cirrus Logic
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2019-05-05 08:41:57 +00:00
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.ifdef __C64__
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.byte $64, $64, $64
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.endif
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2019-05-08 15:16:39 +00:00
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.ifdef __C128__
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.byte $28, $28, $28
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.endif
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2019-05-05 08:41:57 +00:00
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.ifdef __APPLE2__
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.byte $A2, $A2, $A2
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.endif
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.ifdef __ATARI__
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.byte $A8, $A8, $A8
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.endif
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.ifdef __VIC20__
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.byte $20, $20, $20
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.endif
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2014-06-12 22:00:53 +00:00
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; Buffer attributes
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bufaddr:.res 2 ; Address
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bufsize:.res 2 ; Size
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; Jump table.
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jmp init
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jmp poll
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jmp send
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jmp exit
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;---------------------------------------------------------------------
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.if DYN_DRV
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.zeropage
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sp: .res 2 ; Stack pointer (Do not trash !)
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reg: .res 2 ; Address of rxtxreg
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ptr: .res 2 ; Indirect addressing pointer
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len: .res 2 ; Frame length
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cnt: .res 2 ; Frame length counter
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.else
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.include "zeropage.inc"
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reg := ptr1 ; Address of rxtxreg
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ptr := ptr2 ; Indirect addressing pointer
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len := ptr3 ; Frame length
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cnt := ptr4 ; Frame length counter
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.endif
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2019-04-30 16:54:21 +00:00
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;=====================================================================
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.ifdef __CBM__
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2019-05-05 10:33:45 +00:00
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.rodata
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; Ethernet address
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rrnet: .byte $28, $CD, $4C ; OUI of Individual Computers
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.byte $FF ; Reserved for RR-Net
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;---------------------------------------------------------------------
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2019-05-08 15:16:39 +00:00
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.if .defined (__C64__) .or .defined (__C128__)
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2019-04-30 16:54:21 +00:00
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rxtxreg := $DE08
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txcmd := $DE0C
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txlen := $DE0E
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isq := $DE00
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packetpp := $DE02
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ppdata := $DE04
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.endif
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.ifdef __VIC20__
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rxtxreg := $9808
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txcmd := $980C
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txlen := $980E
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isq := $9800
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packetpp := $9802
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ppdata := $9804
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.endif
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2014-06-12 22:00:53 +00:00
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;---------------------------------------------------------------------
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2019-04-30 16:54:21 +00:00
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.code
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init:
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; Activate C64 RR clockport in order to operate RR-Net
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; (RR config register overlays unused CS8900A ISQ register)
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lda isq+1
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ora #$01 ; Set clockport bit
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sta isq+1
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2019-05-05 10:33:45 +00:00
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; Check EISA registration number of Crystal Semiconductor
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; PACKETPP = $0000, PPDATA == $630E ?
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lda #$00
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tax
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jsr packetpp_ax
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lda #$63^$0E
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eor ppdata
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eor ppdata+1
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beq :+
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sec
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rts
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; "When the RR-Net MK3 is used in cartridge mode, the EEPROM will serve as a
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; regular 8k ROM cartridge. It is used as a startup-ROM if the unit is plugged
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; directly to a C64. The startup code will initialize the MAC address."
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; PACKETPP = $0158, PPDATA == RR-Net[0], RR-Net[1] ?
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; PACKETPP = $015A, PPDATA == RR-Net[2], RR-Net[3] ?
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; PACKETPP = $015C, AX = PPDATA
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: ldy #$58
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: tya
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jsr packetpp_a1
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lda ppdata
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ldx ppdata+1
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cpy #$58+4
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bcs copy
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cmp rrnet-$58,y
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bne :+
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txa
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cmp rrnet-$58+1,y
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bne :+
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iny
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iny
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bne :- ; Always
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; "If the RR-Net MK3 is connected to a clockport, then the last 4 bytes of the
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; EEPROM are visible by reading the last 4, normally write-only, registers."
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; MAC_LO ^ MAC_HI ^ $55 == CHKSUM0 ?
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: lda txcmd ; MAC_LO
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eor txcmd+1 ; MAC_HI
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eor #$55
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cmp txlen ; CHKSUM0
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bne reset
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; (CHKSUM0 + MAC_LO + MAC_HI) ^ $AA == CHKSUM1 ?
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clc
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adc txcmd ; MAC_LO
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clc
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adc txcmd+1 ; MAC_HI
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eor #$AA
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cmp txlen+1 ; CHKSUM1
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bne reset
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; "When both checksums match, the CS8900A should be initialized
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; to use the MAC Address 28:CD:4C:FF:<MAC_HI>:<MAC_LO>."
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; AX = MAC_LO, MAC_HI
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lda txcmd ; MAC_LO
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ldx txcmd+1 ; MAC_HI
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; MAC[4], MAC[5] = AX
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; MAC[2], MAC[3] = RR-Net[2], RR-Net[3]
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; MAC[0], MAC[1] = RR-Net[0], RR-Net[1]
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copy: ldy #$04
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bne :++ ; Always
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: lda rrnet,y
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ldx rrnet+1,y
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: sta mac,y
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txa
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sta mac+1,y
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dey
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dey
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bpl :--
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2019-04-30 16:54:21 +00:00
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.endif
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;=====================================================================
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.ifdef __APPLE2__
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2014-06-12 22:00:53 +00:00
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.rodata
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fixup: .byte fixup02-fixup01, fixup03-fixup02, fixup04-fixup03
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.byte fixup05-fixup04, fixup06-fixup05, fixup07-fixup06
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.byte fixup08-fixup07, fixup09-fixup08, fixup10-fixup09
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.byte fixup11-fixup10, fixup12-fixup11, fixup13-fixup12
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.byte fixup14-fixup13, fixup15-fixup14, fixup16-fixup15
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.byte fixup17-fixup16, fixup18-fixup17, fixup19-fixup18
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.byte fixup20-fixup19, fixup21-fixup20, fixup22-fixup21
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2019-04-30 16:54:21 +00:00
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.byte fixup23-fixup22, fixup24-fixup23
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2014-06-12 22:00:53 +00:00
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fixups = * - fixup
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;---------------------------------------------------------------------
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2019-05-02 12:44:24 +00:00
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; The addresses are fixed up at runtime
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rxtxreg := $C080
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txcmd := $C084
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txlen := $C086
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isq := $C088
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packetpp := $C08A
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ppdata := $C08C
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2014-06-12 22:00:53 +00:00
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;---------------------------------------------------------------------
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2019-04-30 16:54:21 +00:00
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.data
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2014-06-12 22:00:53 +00:00
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init:
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2019-05-02 12:44:24 +00:00
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; Convert slot number to slot I/O offset
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asl
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asl
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asl
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asl
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2014-06-12 22:00:53 +00:00
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sta reg
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; Start with first fixup location
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lda #<(fixup01+1)
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ldx #>(fixup01+1)
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sta ptr
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stx ptr+1
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ldx #$FF
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ldy #$00
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; Fixup address at location
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2015-07-08 13:42:42 +00:00
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: lda (ptr),y
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2019-05-02 12:44:24 +00:00
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and #%10001111 ; Allow for re-init
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2019-04-30 16:54:21 +00:00
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ora reg
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2014-06-12 22:00:53 +00:00
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sta (ptr),y
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; Advance to next fixup location
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inx
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cpx #fixups
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bcs :+
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lda ptr
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clc
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adc fixup,x
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sta ptr
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bcc :-
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inc ptr+1
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bcs :- ; Always
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2019-05-05 10:33:45 +00:00
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; Check EISA registration number of Crystal Semiconductor
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; PACKETPP = $0000, PPDATA == $630E ?
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: lda #$00
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tax
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jsr packetpp_ax
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lda #$63^$0E
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fixup01:eor ppdata
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fixup02:eor ppdata+1
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beq reset
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sec
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rts
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2019-04-30 16:54:21 +00:00
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.endif
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;=====================================================================
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.ifdef __ATARI__
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rxtxreg := $D500
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txcmd := $D504
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txlen := $D506
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isq := $D508
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packetpp := $D50A
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ppdata := $D50C
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;---------------------------------------------------------------------
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.code
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init:
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2014-06-12 22:00:53 +00:00
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; Check EISA registration number of Crystal Semiconductor
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; PACKETPP = $0000, PPDATA == $630E ?
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lda #$00
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tax
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jsr packetpp_ax
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lda #$63^$0E
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2019-05-05 10:33:45 +00:00
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eor ppdata
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eor ppdata+1
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beq reset
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2014-06-12 22:00:53 +00:00
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sec
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rts
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2019-05-05 10:33:45 +00:00
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.endif
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;=====================================================================
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reset:
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2014-06-12 22:00:53 +00:00
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; Initiate a chip-wide reset
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; PACKETPP = $0114, PPDATA = $0040
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2019-05-05 10:33:45 +00:00
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lda #$14
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2014-06-12 22:00:53 +00:00
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jsr packetpp_a1
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ldy #$40
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2019-04-30 16:54:21 +00:00
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fixup03:sty ppdata
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2014-06-12 22:00:53 +00:00
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: jsr packetpp_a1
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2019-04-30 16:54:21 +00:00
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fixup04:ldy ppdata
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2014-06-12 22:00:53 +00:00
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and #$40
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bne :-
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; Accept valid unicast + broadcast frames
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; PACKETPP = $0104, PPDATA = $0D05
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lda #$04
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jsr packetpp_a1
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lda #$05
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ldx #$0D
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jsr ppdata_ax
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; Set MAC address
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; PACKETPP = $0158, PPDATA = MAC[0], MAC[1]
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; PACKETPP = $015A, PPDATA = MAC[2], MAC[3]
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; PACKETPP = $015C, PPDATA = MAC[4], MAC[5]
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ldy #$58
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: tya
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jsr packetpp_a1
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lda mac-$58,y
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ldx mac-$58+1,y
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jsr ppdata_ax
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iny
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iny
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cpy #$58+6
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bcc :-
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; Turn on transmission and reception of frames
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; PACKETPP = $0112, PPDATA = $00D3
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lda #$12
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jsr packetpp_a1
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lda #$D3
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ldx #$00
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jsr ppdata_ax
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txa
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clc
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rts
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;---------------------------------------------------------------------
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poll:
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; Check receiver event register to see if there
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; are any valid unicast frames avaliable
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|
|
; PACKETPP = $0124, PPDATA & $0D00 ?
|
|
|
|
lda #$24
|
|
|
|
jsr packetpp_a1
|
2019-04-30 16:54:21 +00:00
|
|
|
fixup05:lda ppdata+1
|
2014-06-12 22:00:53 +00:00
|
|
|
and #$0D
|
|
|
|
beq :+
|
|
|
|
|
|
|
|
; Process the incoming frame
|
|
|
|
; --------------------------
|
|
|
|
|
|
|
|
; Read receiver event and discard it
|
|
|
|
; RXTXREG
|
2019-04-30 16:54:21 +00:00
|
|
|
fixup06:ldx rxtxreg+1
|
|
|
|
fixup07:lda rxtxreg
|
2014-06-12 22:00:53 +00:00
|
|
|
|
|
|
|
; Read frame length
|
|
|
|
; cnt = len = RXTXREG
|
2019-04-30 16:54:21 +00:00
|
|
|
fixup08:ldx rxtxreg+1
|
|
|
|
fixup09:lda rxtxreg
|
2014-06-12 22:00:53 +00:00
|
|
|
sta len
|
|
|
|
stx len+1
|
|
|
|
sta cnt
|
|
|
|
stx cnt+1
|
|
|
|
|
|
|
|
; Adjust odd frame length
|
|
|
|
jsr adjustcnt
|
|
|
|
|
|
|
|
; Is bufsize < cnt ?
|
|
|
|
lda bufsize
|
|
|
|
cmp cnt
|
|
|
|
lda bufsize+1
|
|
|
|
sbc cnt+1
|
|
|
|
bcs :++
|
|
|
|
|
|
|
|
; Yes, skip frame
|
|
|
|
jsr skipframe
|
|
|
|
|
|
|
|
; No frame ready
|
|
|
|
lda #$00
|
|
|
|
: tax
|
|
|
|
sec
|
|
|
|
rts
|
|
|
|
|
|
|
|
; Read bytes into buffer
|
|
|
|
: jsr adjustptr
|
|
|
|
:
|
2019-04-30 16:54:21 +00:00
|
|
|
fixup10:lda rxtxreg
|
2014-06-12 22:00:53 +00:00
|
|
|
sta (ptr),y
|
|
|
|
iny
|
2019-04-30 16:54:21 +00:00
|
|
|
fixup11:lda rxtxreg+1
|
2014-06-12 22:00:53 +00:00
|
|
|
sta (ptr),y
|
|
|
|
iny
|
|
|
|
bne :-
|
|
|
|
inc ptr+1
|
|
|
|
dex
|
|
|
|
bpl :-
|
|
|
|
|
|
|
|
; Return frame length
|
|
|
|
lda len
|
|
|
|
ldx len+1
|
|
|
|
clc
|
|
|
|
rts
|
|
|
|
|
|
|
|
;---------------------------------------------------------------------
|
|
|
|
|
|
|
|
send:
|
|
|
|
; Save frame length
|
|
|
|
sta cnt
|
|
|
|
stx cnt+1
|
|
|
|
|
|
|
|
; Transmit command
|
|
|
|
lda #$C9
|
|
|
|
ldx #$00
|
2019-04-30 16:54:21 +00:00
|
|
|
fixup12:sta txcmd
|
|
|
|
fixup13:stx txcmd+1
|
2014-06-12 22:00:53 +00:00
|
|
|
lda cnt
|
|
|
|
ldx cnt+1
|
2019-04-30 16:54:21 +00:00
|
|
|
fixup14:sta txlen
|
|
|
|
fixup15:stx txlen+1
|
2014-06-12 22:00:53 +00:00
|
|
|
|
|
|
|
; Adjust odd frame length
|
|
|
|
jsr adjustcnt
|
|
|
|
|
|
|
|
; 8 retries
|
|
|
|
ldy #$08
|
|
|
|
|
|
|
|
; Check for avaliable buffer space
|
|
|
|
; PACKETPP = $0138, PPDATA & $0100 ?
|
|
|
|
: lda #$38
|
|
|
|
jsr packetpp_a1
|
2019-04-30 16:54:21 +00:00
|
|
|
fixup16:lda ppdata+1
|
2014-06-12 22:00:53 +00:00
|
|
|
and #$01
|
|
|
|
bne :+
|
|
|
|
|
|
|
|
; No space avaliable, skip a received frame
|
|
|
|
jsr skipframe
|
|
|
|
|
|
|
|
; And try again
|
|
|
|
dey
|
|
|
|
bne :-
|
|
|
|
sec
|
|
|
|
rts
|
|
|
|
|
|
|
|
; Send the frame
|
|
|
|
; --------------
|
|
|
|
|
|
|
|
; Write bytes from buffer
|
|
|
|
: jsr adjustptr
|
|
|
|
: lda (ptr),y
|
2019-04-30 16:54:21 +00:00
|
|
|
fixup17:sta rxtxreg
|
2014-06-12 22:00:53 +00:00
|
|
|
iny
|
|
|
|
lda (ptr),y
|
2019-04-30 16:54:21 +00:00
|
|
|
fixup18:sta rxtxreg+1
|
2014-06-12 22:00:53 +00:00
|
|
|
iny
|
|
|
|
bne :-
|
|
|
|
inc ptr+1
|
|
|
|
dex
|
|
|
|
bpl :-
|
|
|
|
clc
|
|
|
|
rts
|
|
|
|
|
|
|
|
;---------------------------------------------------------------------
|
|
|
|
|
|
|
|
exit:
|
|
|
|
rts
|
|
|
|
|
|
|
|
;---------------------------------------------------------------------
|
|
|
|
|
|
|
|
packetpp_a1:
|
|
|
|
ldx #$01
|
|
|
|
packetpp_ax:
|
2019-04-30 16:54:21 +00:00
|
|
|
fixup19:sta packetpp
|
|
|
|
fixup20:stx packetpp+1
|
2014-06-12 22:00:53 +00:00
|
|
|
rts
|
|
|
|
|
|
|
|
;---------------------------------------------------------------------
|
|
|
|
|
|
|
|
ppdata_ax:
|
2019-04-30 16:54:21 +00:00
|
|
|
fixup21:sta ppdata
|
|
|
|
fixup22:stx ppdata+1
|
2014-06-12 22:00:53 +00:00
|
|
|
rts
|
|
|
|
|
|
|
|
;---------------------------------------------------------------------
|
|
|
|
|
|
|
|
skipframe:
|
|
|
|
; PACKETPP = $0102, PPDATA = PPDATA | $0040
|
|
|
|
lda #$02
|
|
|
|
jsr packetpp_a1
|
2019-04-30 16:54:21 +00:00
|
|
|
fixup23:lda ppdata
|
2014-06-12 22:00:53 +00:00
|
|
|
ora #$40
|
2019-04-30 16:54:21 +00:00
|
|
|
fixup24:sta ppdata
|
2014-06-12 22:00:53 +00:00
|
|
|
rts
|
|
|
|
|
|
|
|
;---------------------------------------------------------------------
|
|
|
|
|
|
|
|
adjustcnt:
|
|
|
|
lsr
|
|
|
|
bcc :+
|
|
|
|
inc cnt
|
|
|
|
bne :+
|
|
|
|
inc cnt+1
|
|
|
|
: rts
|
|
|
|
|
|
|
|
;---------------------------------------------------------------------
|
|
|
|
|
|
|
|
adjustptr:
|
|
|
|
lda cnt
|
|
|
|
ldx cnt+1
|
|
|
|
eor #$FF ; Two's complement part 1
|
|
|
|
tay
|
|
|
|
iny ; Two's complement part 2
|
|
|
|
sty reg
|
|
|
|
sec
|
|
|
|
lda bufaddr
|
|
|
|
sbc reg
|
|
|
|
sta ptr
|
|
|
|
lda bufaddr+1
|
|
|
|
sbc #$00
|
|
|
|
sta ptr+1
|
|
|
|
rts
|
|
|
|
|
|
|
|
;---------------------------------------------------------------------
|