2011-05-29 06:10:13 +00:00
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;.include "../inc/common.i"
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;.import cfg_get_configuration_ptr
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;.include "../inc/commonprint.i"
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;
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;.include "../drivers/w5100.i"
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2011-05-29 09:54:23 +00:00
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WIZNET_BASE=$DE04
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WIZNET_MODE_REG = WIZNET_BASE
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WIZNET_ADDR_HI = WIZNET_BASE+1
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WIZNET_ADDR_LO = WIZNET_BASE+2
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WIZNET_DATA_REG = WIZNET_BASE+3
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2011-05-29 06:10:13 +00:00
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2011-07-04 18:51:51 +00:00
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TEST_LOOPS=$FF
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2011-05-29 06:10:13 +00:00
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TX_BUFFER_START_PAGE=$40
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2011-07-04 18:51:51 +00:00
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TIMER_POSITION_ROW=5
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TIMER_POSITION_COL=15
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TIMER_POSITION=$400+TIMER_POSITION_ROW*40+TIMER_POSITION_COL
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2011-05-29 06:10:13 +00:00
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; load A/X macro
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.macro ldax arg
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.if (.match (.left (1, arg), #)) ; immediate mode
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lda #<(.right (.tcount (arg)-1, arg))
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ldx #>(.right (.tcount (arg)-1, arg))
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.else ; assume absolute or zero page
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lda arg
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ldx 1+(arg)
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.endif
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.endmacro
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; store A/X macro
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.macro stax arg
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sta arg
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stx 1+(arg)
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.endmacro
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.zeropage
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pptr: .res 2
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.segment "STARTUP" ;this is what gets put at the start of the file on the C64
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.word basicstub ; load address
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basicstub:
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.word @nextline
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.word 2003
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.byte $9e
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.byte <(((init / 1000) .mod 10) + $30)
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.byte <(((init / 100 ) .mod 10) + $30)
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.byte <(((init / 10 ) .mod 10) + $30)
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.byte <(((init ) .mod 10) + $30)
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.byte 0
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@nextline:
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.word 0
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init:
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2011-07-04 18:51:51 +00:00
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2011-05-29 06:10:13 +00:00
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2011-07-04 18:51:51 +00:00
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;set funky colours
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lda #$06 ;
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sta $D020 ;border
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lda #$00 ;dark blue
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sta $D021 ;background
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2011-05-29 06:10:13 +00:00
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2011-07-04 18:51:51 +00:00
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ldax #banner
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jsr print
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2011-07-17 08:14:08 +00:00
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lda #0
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sta clockport_mode
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lda $de01
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and #$fe ;turn off clockport
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sta $de01
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lda #$80 ;reset
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sta WIZNET_MODE_REG
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lda WIZNET_MODE_REG
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bne @try_clockport
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;writing a byte to the MODE register with bit 7 set should reset.
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;after a reset, mode register is zero
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;therefore, if there is a real W5100 at the specified address,
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;we should be able to write a $80 and read back a $00
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lda #$13 ;set indirect mode, with autoinc, no auto PING
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sta WIZNET_MODE_REG
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lda WIZNET_MODE_REG
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cmp #$13
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beq @w5100_found
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2011-07-04 18:51:51 +00:00
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2011-07-17 08:14:08 +00:00
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@try_clockport:
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inc clockport_mode
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;now try with clockport on
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2011-07-04 18:51:51 +00:00
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lda $de01
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ora #1 ;turn on clockport
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sta $de01
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2011-05-29 06:10:13 +00:00
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2011-07-17 08:14:08 +00:00
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2011-05-29 06:10:13 +00:00
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lda #$80 ;reset
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sta WIZNET_MODE_REG
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lda WIZNET_MODE_REG
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beq @reset_ok
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2011-07-04 18:51:51 +00:00
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;writing a byte to the MODE register with bit 7 set should reset.
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2011-05-29 06:10:13 +00:00
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;after a reset, mode register is zero
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;therefore, if there is a real W5100 at the specified address,
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;we should be able to write a $80 and read back a $00
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2011-07-04 18:51:51 +00:00
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@error:
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ldax #not_found
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jsr print
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lda #>WIZNET_MODE_REG
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jsr print_hex
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lda #<WIZNET_MODE_REG
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jsr print_hex
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jsr print_cr
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jmp $e37b
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2011-05-29 06:10:13 +00:00
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@reset_ok:
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lda #$13 ;set indirect mode, with autoinc, no auto PING
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sta WIZNET_MODE_REG
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lda WIZNET_MODE_REG
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cmp #$13
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2011-07-04 18:51:51 +00:00
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bne @error
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2011-05-29 06:10:13 +00:00
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;make sure if we write to mode register without bit 7 set,
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;the value persists.
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2011-07-17 08:14:08 +00:00
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@w5100_found:
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2011-05-29 06:10:13 +00:00
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ldax #w5100_found
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jsr print
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2011-07-04 18:51:51 +00:00
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lda #>WIZNET_MODE_REG
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jsr print_hex
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lda #<WIZNET_MODE_REG
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jsr print_hex
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2011-07-17 08:14:08 +00:00
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lda clockport_mode
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bne @clockport
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ldax #direct
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jmp :+
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@clockport:
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ldax #clockport
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:
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jsr print
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2011-07-04 18:51:51 +00:00
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jsr print_cr
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;set up to keep the timer updated
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lda #0
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sta update_clock
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ldax $314 ;old tick_handler
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stax old_tick_handler
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ldax #tick_handler
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sei
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stax $314
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cli
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jsr reset_clock
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ldax #test_duration
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jsr print
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2011-07-17 08:14:08 +00:00
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ldax #test_0
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jsr print
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2011-07-04 18:51:51 +00:00
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ldax #test_1
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jsr print
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ldax #test_2
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jsr print
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ldax #test_3
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jsr print
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ldax #prompt
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jsr print
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main:
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lda #0
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sta update_clock
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jsr get_key
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cmp #' '
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bne @not_space
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jsr reset_clock
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@loop_test:
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2011-07-17 08:14:08 +00:00
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jsr do_test_0
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bcs main
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2011-07-04 18:51:51 +00:00
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jsr do_test_1
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bcs main
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jsr do_test_2
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bcs main
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jsr do_test_3
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bcs main
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jsr get_key_if_available
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bne main
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jmp @loop_test
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@not_space:
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2011-07-17 08:14:08 +00:00
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cmp #'0'
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bne @not_0
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jsr reset_clock
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jsr do_test_0
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jmp main
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@not_0:
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2011-07-04 18:51:51 +00:00
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cmp #'1'
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bne @not_1
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jsr reset_clock
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jsr do_test_1
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jmp main
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@not_1:
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cmp #'2'
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bne @not_2
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jsr reset_clock
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jsr do_test_2
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jmp main
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@not_2:
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cmp #'3'
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bne @not_3
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jsr reset_clock
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jsr do_test_3
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jmp main
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@not_3:
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lda $cb ;current key pressed
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cmp #$3F
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bne main
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jmp return_to_basic
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2011-05-29 06:10:13 +00:00
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2011-07-04 18:51:51 +00:00
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failed:
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2011-07-17 08:14:08 +00:00
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lda #$02
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sta $d020
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2011-07-04 18:51:51 +00:00
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sec
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rts
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2011-07-17 08:14:08 +00:00
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do_test_0:
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lda #0
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sta address_inc_mode
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ldax #test_0
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jsr print
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lda #$11 ;set indirect mode, with no autoinc, no auto PING
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jmp set_address_mode
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2011-07-04 18:51:51 +00:00
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do_test_1:
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2011-07-17 08:14:08 +00:00
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2011-05-29 06:10:13 +00:00
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lda #0
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sta intersperse_address_reads
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2011-07-17 08:14:08 +00:00
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lda #1
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sta address_inc_mode
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2011-07-04 18:51:51 +00:00
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ldax #test_1
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do_w5100_test:
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jsr print
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2011-07-17 08:14:08 +00:00
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lda #$13 ;set indirect mode, with autoinc, no auto PING
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set_address_mode:
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sta WIZNET_MODE_REG
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lda #$06 ;
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sta $D020 ;border
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2011-07-04 18:51:51 +00:00
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jsr w5100_access_test
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bcs failed
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ok:
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ldax #OK
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jsr print
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clc
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rts
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do_test_2:
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2011-07-17 08:14:08 +00:00
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2011-07-04 18:51:51 +00:00
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lda #1
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sta intersperse_address_reads
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2011-07-17 08:14:08 +00:00
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sta address_inc_mode
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2011-07-04 18:51:51 +00:00
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ldax #test_2
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jmp do_w5100_test
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do_test_3:
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2011-07-17 08:14:08 +00:00
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lda #$06 ;
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sta $D020 ;border
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2011-07-04 18:51:51 +00:00
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ldax #test_3
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jsr print
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sei
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ldax #nmi_handler
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stax $318
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cli
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clc
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lda #1
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sta update_clock
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2011-07-17 08:14:08 +00:00
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lda #$11 ;set indirect mode, with no autoinc, no auto PING
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sta WIZNET_MODE_REG
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2011-07-04 18:51:51 +00:00
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;set up the W5100 to trigger an interrupt
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lda #1
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lda #$00
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sta WIZNET_ADDR_HI
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lda #$16 ;00016 = interrupt mask register
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sta WIZNET_ADDR_LO
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lda #$04 ;enable interruopt on socket 2 event
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sta WIZNET_DATA_REG
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lda #$17 ;retry period
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sta WIZNET_ADDR_LO
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lda #$00 ;retry period high byte
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sta WIZNET_DATA_REG
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2011-07-17 08:14:08 +00:00
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lda #$18 ;retry period
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sta WIZNET_ADDR_LO
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2011-07-04 18:51:51 +00:00
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lda #$01 ;retry period low byte
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sta WIZNET_DATA_REG
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lda #$19 ;retry count
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sta WIZNET_ADDR_LO
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lda #$01 ;trigger timeout after single attempt
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sta WIZNET_DATA_REG
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lda #$06 ;06xx = socket 2
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sta WIZNET_ADDR_HI
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lda #$00 ;socket mode register
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sta WIZNET_ADDR_LO
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lda #$01 ;TCP socket
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sta WIZNET_DATA_REG
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lda #$02 ;$0602 = interrupt register, socket 2
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sta WIZNET_ADDR_LO
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lda #$FF
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sta WIZNET_DATA_REG
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lda #0
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sta timeout_count
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@trigger_one_timeout:
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lda #0
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sta got_nmi
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;clear interrupt register
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lda #$02 ;$0602 = interrupt register, socket 2
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sta WIZNET_ADDR_LO
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lda #$FF
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sta WIZNET_DATA_REG
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lda #$01 ;$0601 = command register, socket 2
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sta WIZNET_ADDR_LO
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lda #$04 ;connect
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sta WIZNET_DATA_REG
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@loop_till_timeout:
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lda #$02 ;$0602 = interrupt register, socket 2
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sta WIZNET_ADDR_LO
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lda WIZNET_DATA_REG
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beq @loop_till_timeout
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lda got_nmi
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bne @ok
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jmp failed
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@ok:
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ldax #reset_cursor
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jsr print
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lda timeout_count
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jsr print_hex
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inc timeout_count
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bne @trigger_one_timeout
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jmp ok
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nmi_handler:
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; inc $d020
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inc got_nmi
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rti
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2011-05-29 06:10:13 +00:00
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2011-07-04 18:51:51 +00:00
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return_to_basic:
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|
|
ldax #after_prompt
|
|
|
|
jsr print
|
|
|
|
sei
|
|
|
|
ldax old_tick_handler
|
|
|
|
stax $314 ;old tick_handler
|
|
|
|
ldax #$FE47
|
|
|
|
stax $318
|
|
|
|
cli
|
|
|
|
jmp $e37b
|
|
|
|
|
|
|
|
w5100_access_test:
|
|
|
|
|
|
|
|
lda #1
|
|
|
|
sta update_clock
|
|
|
|
|
2011-05-29 06:10:13 +00:00
|
|
|
lda #0
|
|
|
|
sta loop_count
|
|
|
|
|
|
|
|
@next_loop:
|
|
|
|
lda loop_count
|
|
|
|
and #$1f
|
|
|
|
clc
|
|
|
|
adc #TX_BUFFER_START_PAGE
|
|
|
|
sta test_page
|
|
|
|
|
|
|
|
lda test_page
|
|
|
|
sta WIZNET_ADDR_HI
|
|
|
|
|
|
|
|
lda #$00
|
|
|
|
sta WIZNET_ADDR_LO
|
|
|
|
|
2011-07-04 18:51:51 +00:00
|
|
|
ldax #reset_cursor
|
2011-05-29 06:10:13 +00:00
|
|
|
jsr print
|
2011-07-04 18:51:51 +00:00
|
|
|
lda loop_count
|
2011-05-29 06:10:13 +00:00
|
|
|
jsr print_hex
|
|
|
|
|
|
|
|
|
|
|
|
lda #0
|
|
|
|
sta byte_counter
|
|
|
|
@write_one_byte:
|
|
|
|
lda byte_counter
|
|
|
|
sta WIZNET_DATA_REG
|
|
|
|
lda intersperse_address_reads
|
|
|
|
beq :+
|
|
|
|
lda WIZNET_ADDR_LO ;see if we can force a glitch!
|
|
|
|
:
|
2011-07-17 08:14:08 +00:00
|
|
|
|
|
|
|
lda address_inc_mode
|
|
|
|
bne :+
|
|
|
|
inc WIZNET_ADDR_LO ;see if we can force a glitch!
|
|
|
|
:
|
|
|
|
|
2011-05-29 06:10:13 +00:00
|
|
|
inc byte_counter
|
|
|
|
bne @write_one_byte
|
|
|
|
|
|
|
|
;reset the pointer to start of this page
|
|
|
|
|
|
|
|
lda test_page
|
|
|
|
sta WIZNET_ADDR_HI
|
|
|
|
|
|
|
|
lda #$00
|
|
|
|
sta WIZNET_ADDR_LO
|
|
|
|
|
|
|
|
ldx #0
|
|
|
|
@test_one_byte:
|
|
|
|
lda WIZNET_DATA_REG
|
|
|
|
sta last_byte
|
|
|
|
cpx last_byte
|
|
|
|
beq @ok
|
2011-07-04 18:51:51 +00:00
|
|
|
sec
|
|
|
|
rts
|
2011-07-17 08:14:08 +00:00
|
|
|
@ok:
|
|
|
|
lda address_inc_mode
|
|
|
|
bne :+
|
|
|
|
inc WIZNET_ADDR_LO ;see if we can force a glitch!
|
|
|
|
:
|
|
|
|
|
2011-05-29 06:10:13 +00:00
|
|
|
inx
|
|
|
|
bne @test_one_byte
|
|
|
|
|
|
|
|
@after_test:
|
|
|
|
inc loop_count
|
|
|
|
lda loop_count
|
|
|
|
cmp #<(TEST_LOOPS+1)
|
|
|
|
beq :+
|
|
|
|
jmp @next_loop
|
|
|
|
:
|
|
|
|
|
|
|
|
@exit:
|
2011-07-04 18:51:51 +00:00
|
|
|
clc
|
|
|
|
rts
|
2011-05-29 06:10:13 +00:00
|
|
|
|
|
|
|
|
|
|
|
|
2011-07-04 18:51:51 +00:00
|
|
|
reset_clock:
|
|
|
|
lda #0
|
|
|
|
sta tick_counter
|
|
|
|
sta $dc0b
|
|
|
|
sta $dc0a
|
|
|
|
sta $dc09
|
|
|
|
sta $dc08
|
|
|
|
rts
|
2011-05-29 06:10:13 +00:00
|
|
|
;---------------------
|
|
|
|
;standard printing helper routines
|
|
|
|
print_hex:
|
|
|
|
pha
|
|
|
|
pha
|
|
|
|
lsr
|
|
|
|
lsr
|
|
|
|
lsr
|
|
|
|
lsr
|
|
|
|
tax
|
|
|
|
lda hexdigits,x
|
|
|
|
jsr print_a
|
|
|
|
pla
|
|
|
|
and #$0F
|
|
|
|
tax
|
|
|
|
lda hexdigits,x
|
|
|
|
jsr print_a
|
|
|
|
pla
|
|
|
|
rts
|
|
|
|
|
|
|
|
hexdigits:
|
|
|
|
.byte "0123456789ABCDEF"
|
|
|
|
|
|
|
|
print_a=$ffd2
|
|
|
|
|
|
|
|
print_cr:
|
|
|
|
lda #13
|
|
|
|
jmp print_a
|
|
|
|
|
|
|
|
print:
|
|
|
|
sta pptr
|
|
|
|
stx pptr + 1
|
|
|
|
|
|
|
|
@print_loop:
|
|
|
|
ldy #0
|
|
|
|
lda (pptr),y
|
|
|
|
beq @done_print
|
|
|
|
jsr print_a
|
|
|
|
inc pptr
|
|
|
|
bne @print_loop
|
|
|
|
inc pptr+1
|
|
|
|
bne @print_loop ;if we ever get to $ffff, we've probably gone far enough ;-)
|
|
|
|
@done_print:
|
|
|
|
rts
|
|
|
|
|
2011-07-04 18:51:51 +00:00
|
|
|
tick_handler:
|
|
|
|
lda update_clock
|
|
|
|
beq @done
|
|
|
|
inc tick_counter
|
|
|
|
lda tick_counter
|
|
|
|
cmp #10
|
|
|
|
bne @done
|
|
|
|
lda #0
|
|
|
|
sta tick_counter
|
|
|
|
jsr show_timer
|
|
|
|
@done:
|
|
|
|
jmp (old_tick_handler)
|
|
|
|
|
|
|
|
show_timer:
|
|
|
|
lda $dc08 ;read 10ths of seconds in case the time was latched
|
|
|
|
lda $dc0b ;hours as BCD
|
|
|
|
bpl @not_pm
|
|
|
|
and $7f ;clear bit 7
|
|
|
|
clc
|
|
|
|
adc #$12
|
|
|
|
@not_pm:
|
|
|
|
pha
|
|
|
|
lsr
|
|
|
|
lsr
|
|
|
|
lsr
|
|
|
|
lsr
|
|
|
|
jsr make_digit
|
|
|
|
sta TIMER_POSITION
|
|
|
|
pla
|
|
|
|
jsr make_digit
|
|
|
|
sta TIMER_POSITION+1
|
|
|
|
lda #':'
|
|
|
|
sta TIMER_POSITION+2
|
|
|
|
lda $dc0a ;minutes as BCD
|
|
|
|
pha
|
|
|
|
lsr
|
|
|
|
lsr
|
|
|
|
lsr
|
|
|
|
lsr
|
|
|
|
jsr make_digit
|
|
|
|
sta TIMER_POSITION+3
|
|
|
|
pla
|
|
|
|
jsr make_digit
|
|
|
|
sta TIMER_POSITION+4
|
|
|
|
lda #':'
|
|
|
|
sta TIMER_POSITION+5
|
|
|
|
|
|
|
|
lda $dc09 ;seconds as BCD
|
|
|
|
pha
|
|
|
|
lsr
|
|
|
|
lsr
|
|
|
|
lsr
|
|
|
|
lsr
|
|
|
|
jsr make_digit
|
|
|
|
sta TIMER_POSITION+6
|
|
|
|
pla
|
|
|
|
|
|
|
|
jsr make_digit
|
|
|
|
sta TIMER_POSITION+7
|
|
|
|
rts
|
|
|
|
|
|
|
|
make_digit:
|
|
|
|
and #$0f
|
|
|
|
clc
|
|
|
|
adc #$30
|
|
|
|
rts
|
|
|
|
|
|
|
|
get_key_if_available=$f142 ;not officially documented - where F13E (GETIN) falls through to if device # is 0
|
|
|
|
get_key:
|
|
|
|
jsr get_key_if_available
|
|
|
|
beq get_key
|
|
|
|
rts
|
2011-05-29 06:10:13 +00:00
|
|
|
.data
|
|
|
|
|
2011-07-04 18:51:51 +00:00
|
|
|
banner:
|
|
|
|
.byte $93 ;CLS
|
|
|
|
.byte $9a;
|
2011-07-17 08:14:08 +00:00
|
|
|
.byte $0d,"RR-NET MK3 DIAGNOSTICS 0.23"
|
2011-07-04 18:51:51 +00:00
|
|
|
|
|
|
|
.include "timestamp.i"
|
|
|
|
.byte $0d
|
|
|
|
.byte 0
|
|
|
|
|
|
|
|
test_duration:
|
|
|
|
.byte $13 ;home
|
|
|
|
.byte $11,$11,$11,$11,$11
|
|
|
|
.byte "TEST DURATION: 00:00:00"
|
|
|
|
.byte $0d
|
|
|
|
.byte 0
|
|
|
|
|
|
|
|
OK:
|
|
|
|
.byte 157,157,"OK ",0
|
|
|
|
|
2011-07-17 08:14:08 +00:00
|
|
|
test_0:
|
2011-07-04 18:51:51 +00:00
|
|
|
.byte $13 ;home
|
|
|
|
.byte $11,$11,$11,$11,$11,$11,$11
|
2011-07-17 08:14:08 +00:00
|
|
|
.byte "0) W5100 MEMORY ACCESS 0 : "
|
|
|
|
.byte 0
|
|
|
|
|
|
|
|
test_1:
|
|
|
|
.byte $13 ;home
|
|
|
|
.byte $11,$11,$11,$11,$11,$11,$11,$11
|
2011-07-04 18:51:51 +00:00
|
|
|
.byte "1) W5100 MEMORY ACCESS 1 : "
|
|
|
|
.byte 0
|
|
|
|
test_2:
|
|
|
|
.byte $13 ;home
|
2011-07-17 08:14:08 +00:00
|
|
|
.byte $11,$11,$11,$11,$11,$11,$11,$11,$11
|
2011-07-04 18:51:51 +00:00
|
|
|
.byte "2) W5100 MEMORY ACCESS 2 : "
|
|
|
|
.byte 0
|
|
|
|
test_3:
|
|
|
|
.byte $13 ;home
|
2011-07-17 08:14:08 +00:00
|
|
|
.byte $11,$11,$11,$11,$11,$11,$11,$11,$11,$11
|
2011-07-04 18:51:51 +00:00
|
|
|
.byte "3) NMI TEST : "
|
|
|
|
.byte 0
|
|
|
|
prompt:
|
|
|
|
.byte $13 ;home
|
2011-07-17 08:14:08 +00:00
|
|
|
.byte $11,$11,$11,$11,$11,$11,$11,$11,$11,$11,$11,$11,$11
|
|
|
|
.byte "PRESS 0..3 TO RUN A SINGLE TEST",13
|
2011-07-04 18:51:51 +00:00
|
|
|
.byte "SPACE TO CYCLE ALL TESTS",13
|
|
|
|
.byte 0
|
|
|
|
after_prompt:
|
|
|
|
.byte $13 ;home
|
2011-07-17 08:14:08 +00:00
|
|
|
.byte $11,$11,$11,$11,$11,$11,$11,$11,$11,$11,$11,$11,$11,$11,$11
|
2011-07-04 18:51:51 +00:00
|
|
|
.byte 0
|
2011-05-29 06:10:13 +00:00
|
|
|
loop: .byte "TEST $",0
|
|
|
|
not_found: .byte "NO "
|
|
|
|
w5100_found: .byte "W5100 FOUND AT $",0
|
|
|
|
error_offset: .byte 13,"OFFSET $",0
|
|
|
|
was: .byte " WAS $",0
|
2011-07-04 18:51:51 +00:00
|
|
|
reset_cursor: .byte 157,157,0
|
2011-07-17 08:14:08 +00:00
|
|
|
clockport: .byte " [CLOCKPORT]",0
|
|
|
|
direct: .byte " [DIRECT]",0
|
|
|
|
|
2011-05-29 06:10:13 +00:00
|
|
|
.bss
|
|
|
|
last_byte: .res 1
|
|
|
|
loop_count: .res 1
|
|
|
|
byte_counter: .res 1
|
|
|
|
current_register:.res 1
|
|
|
|
current_byte_in_row: .res 1
|
|
|
|
test_page: .res 1
|
|
|
|
last_row: .res 1
|
|
|
|
intersperse_address_reads: .res 1
|
2011-07-04 18:51:51 +00:00
|
|
|
old_tick_handler: .res 2
|
|
|
|
update_clock: .res 1
|
|
|
|
tick_counter: .res 1
|
|
|
|
timeout_count: .res 1
|
2011-07-17 08:14:08 +00:00
|
|
|
got_nmi: .res 1
|
|
|
|
clockport_mode: .res 1
|
|
|
|
address_inc_mode: .res 1
|