allow flashing of MK3 EEPROM

git-svn-id: http://svn.code.sf.net/p/netboot65/code@319 93682198-c243-4bdb-bd91-e943c89aac3b

client/wiznet/Makefile

@@ -47,6 +47,9 @@ wizboot.bin: wizboot.o $(IP65WIZNETLIB) $(C64WIZNETLIB) $(INCFILES) ../cfg/c64_8
 wizboot.prg: wizboot.bin cartheader.prg
 	cat cartheader.prg wizboot.bin > $@
 
+wizflash.prg: wizboot.bin wizflashheader.prg
+	cat wizflashheader.prg wizboot.bin > $@
+
 telnetd.o: ../carts/telnetd.s $(INCFILES) timestamp.rb
 	$(AS) $(AFLAGS) ../carts/telnetd.s -o telnetd.o
 
@@ -64,8 +67,11 @@ wizbobcart.bin: wizbobcart.o $(IP65WIZNETLIB) $(C64WIZNETLIB) $(INCFILES) wizbob
 wizbobcart.prg: wizbobcart.bin cartheader.prg
 	cat cartheader.prg wizbobcart.bin > $@
 	
-wiztest.d64: wiztest.prg
+wiztest.d64: wiztest.prg wizboot.prg wizflash.prg
-	ripxplore.rb -I CbmDos -a wiztest.prg $@
+	ripxplore.rb -I CbmDos $@
+	ripxplore.rb -a wizboot.prg $@
+	ripxplore.rb -a wiztest.prg $@
+	ripxplore.rb -a	wizflash.prg $@
 	
 clean:
 	rm -f *.o *.bin *.map *.prg *.pg2 *.dsk *.d64
@@ -88,3 +94,4 @@ bootc64.prg:
 #	cp telnetd.prg ../../server/boot/bootc64.prg
 #	cp wizboot2.prg ../../server/boot/bootc64.prg	
 	cp wiztest.prg	../../server/boot/bootc64.prg
+#	cp wizflash.prg	../../server/boot/bootc64.prg

client/wiznet/wizboot.s

@@ -72,7 +72,6 @@ call_downloaded_prg:
 .code
 
   
-  
 cold_init:
   
   ;first let the kernal do a normal startup
@@ -83,6 +82,30 @@ cold_init:
   jsr $ff5B   ;init. VIC
   cli         ;KERNAL init. finished
   
+  
+  	;do the 'secret knock' to disable writes to the EEPROM
+
+	lda #$55 
+	sta $9c55 
+	lda #$aa 
+	sta $83aa 
+	lda #$05 
+	sta $9c55
+
+@poll_loop:
+	lda	$8000	
+	cmp	$8000	
+	bne	@poll_loop
+	
+	;copy ourselves to the C64 RAM
+	;so if we go into 'SHUTUP' mode, we keep executing from the same address, in C64 RAM
+	ldax #$8000	
+  	stax copy_src
+  	stax copy_dest
+  	ldax #$2000
+  	jsr copymem
+	
+    
 warm_init:  
 
   jsr SCNKEY ;Query keyboard - put matrix code into  $00CB & status of shift keys $028D 

client/wiznet/wizflashheader.s

@@ -0,0 +1,289 @@
+
+.include "../inc/common.i"
+print_a = $ffd2
+
+
+
+.zeropage
+cart_data_ptr:	.res 2
+eeprom_ptr:	.res 2
+pptr: .res 2
+
+.segment "STARTUP"    ;this is what gets put at the start of the file on the C64
+
+.word basicstub		; load address
+
+basicstub:
+	.word @nextline
+	.word 2003
+	.byte $9e 
+	.byte <(((init / 1000) .mod 10) + $30)
+	.byte <(((init / 100 ) .mod 10) + $30)
+	.byte <(((init / 10  ) .mod 10) + $30)
+	.byte <(((init       ) .mod 10) + $30)
+	.byte 0
+@nextline:
+	.word 0
+
+init:
+
+	ldax #banner
+	jsr	print
+	cli
+	
+	ldax #$8000
+	stax eeprom_ptr
+
+	;set up access to READ/WRITE external ROM
+	
+	lda #$37
+	sta $01
+	sta  $de02 ;leave 'shut up' mode
+	sta $de08  ;enable ROM
+	sta $de0a	;set banking bit 0
+	sta $de0c	;set banking bit 1
+
+	lda	$d011
+	sta	old_d011
+	and #$ef		;turn off bit 4
+	sta	$d011
+	jsr	turn_off_write_protect
+
+	ldax #cart_data
+	stax cart_data_ptr
+	ldax #$8000
+	stax eeprom_ptr
+
+@copy_64_bytes:
+;	lda	cart_data_ptr+1
+;	jsr	print_hex
+;	lda	cart_data_ptr
+;	jsr	print_hex
+;	lda	eeprom_ptr+1
+;	jsr	print_hex
+;	lda	eeprom_ptr
+;	jsr	print_hex
+	inc $d020	
+	
+	ldy	#0
+@copy_1_byte:
+	lda	(cart_data_ptr),y
+	sta	(eeprom_ptr),y
+	iny
+	cpy	#64
+	bne @copy_1_byte
+	jsr	poll_till_stable
+
+	clc
+	tya
+	adc eeprom_ptr
+	sta eeprom_ptr
+	bcc	:+
+	inc	eeprom_ptr+1
+:
+	clc
+	tya
+	adc cart_data_ptr
+	sta cart_data_ptr
+	bcc	:+
+	inc	cart_data_ptr+1
+:
+	
+	lda eeprom_ptr+1
+	cmp	#$A0
+	bne	@copy_64_bytes			
+
+;now validate the data
+	ldax #cart_data
+	stax cart_data_ptr
+	ldax #$8000
+	stax eeprom_ptr
+	ldy #0
+@compare_loop:
+	lda (cart_data_ptr),y
+	cmp	(eeprom_ptr),y
+	bne	@validation_error
+	iny
+	bne	@compare_loop
+	inc	cart_data_ptr+1
+	inc	eeprom_ptr+1
+	lda eeprom_ptr+1
+	cmp	#$A0
+	bne	@compare_loop
+	ldax #ok
+	jsr	print
+	ldax #$8000
+	stax eeprom_ptr
+
+	jsr turn_on_write_protect	
+
+	jmp	@exit_to_basic
+	
+@validation_error:
+	sty	error_offset
+
+	ldax #validation_error
+	jsr	print
+	lda eeprom_ptr+1
+	jsr	print_hex
+	lda eeprom_ptr
+	jsr	print_hex
+	ldax #offset
+	jsr	print
+	lda error_offset
+	jsr print_hex
+	jsr	print_cr
+	
+
+	ldax #wr
+	jsr	print
+	lda #0
+	sta	byte_ptr
+@wr_loop:
+	ldy	byte_ptr
+	lda (cart_data_ptr),y
+	jsr	print_hex
+	
+	lda byte_ptr
+	cmp	error_offset
+	beq	:+
+	inc	byte_ptr
+	bne	@wr_loop
+:	
+	jsr	print_cr
+	
+	ldax #rd
+	jsr	print
+	lda #0
+	sta	byte_ptr
+@rd_loop:
+	ldy	byte_ptr
+	lda (eeprom_ptr),y
+	jsr	print_hex
+	lda byte_ptr
+	cmp	error_offset
+	beq	:+
+	inc	byte_ptr
+	bne	@rd_loop
+:	
+	jsr	print_cr
+	
+;if there is an error somewhere in the eeprom, but we have a valid 'CBM80' header bad things can happen
+;so overwrite the signature bytes
+	lda #$FF
+	sta $8004
+	sta $8005
+	sta $8006
+	sta $8007
+	sta $8008
+	
+@exit_to_basic:	
+	sei
+	lda	old_d011
+	sta	$d011
+	rts	
+
+turn_off_write_protect:
+	;do the 'secret knock' to enable writes
+	lda #$55
+	sta $9c55
+	lda #$aa
+	sta $83aa
+	lda #$01
+	sta $9c55
+	lda #$55
+	sta $9c55
+	lda #$aa
+	sta $83aa
+	lda #$04
+	sta $9c55
+	jmp	poll_till_stable
+
+turn_on_write_protect:
+	;do the 'secret knock' to disable writes
+
+	lda #$55 
+	sta $9c55 
+	lda #$aa 
+	sta $83aa 
+	lda #$05 
+	sta $9c55
+
+poll_till_stable:
+	ldax eeprom_ptr
+	stax	@offset_1+1
+	stax	@offset_2+1
+@poll_loop:
+@offset_1:	
+	lda	$8000	;address will get overwritten
+@offset_2:	
+	cmp	$8000	;address will get overwritten
+	bne	poll_till_stable
+	
+@done:
+	rts
+
+
+print_cr:
+  lda #13
+  jmp print_a
+
+print:
+	sta pptr
+	stx pptr + 1
+	
+@print_loop:
+  ldy #0
+  lda (pptr),y
+	beq @done_print  
+	jsr print_a
+	inc pptr
+	bne @print_loop
+  inc pptr+1
+  bne @print_loop ;if we ever get to $ffff, we've probably gone far enough ;-)
+@done_print:
+  rts
+
+print_hex:
+  pha  
+  pha  
+  lsr
+  lsr
+  lsr
+  lsr
+  tax
+  lda hexdigits,x
+  jsr print_a
+  pla
+  and #$0F
+  tax
+  lda hexdigits,x
+  jsr print_a
+  pla
+  rts
+	
+.rodata
+hexdigits:
+.byte "0123456789ABCDEF"
+
+banner:
+.byte 147	;cls
+.byte 142	;upper case
+.byte 13," RR-NET MK3 FLASHER V0.02"
+.include "timestamp.i"
+.byte 13
+.byte 0
+ok: .byte 13,"OK",13,0
+validation_error:
+.byte 13,"VALIDATION ERROR : $",0
+offset: .byte " OFFSET : $",0
+
+rd: .byte "RD :",0
+wr: .byte "WR :",0
+.bss
+cart_data:	;this should point to where the cart data gets appended.
+	.res $2000
+	
+error_offset: .res 1
+byte_ptr: .res 1
+old_d011: .res 1

client/wiznet/wiztest.s

@@ -71,10 +71,35 @@ init:
 	ldax #banner
 	jsr	print
 
+	lda #0
+	sta	clockport_mode
+  	lda $de01
+	and #$fe			;turn off clockport
+	sta $de01
+
+	lda #$80  ;reset
+	sta WIZNET_MODE_REG
+	lda WIZNET_MODE_REG
+	bne @try_clockport
+	          	;writing a byte to the MODE register with bit 7 set should reset.
+				;after a reset, mode register is zero
+				;therefore, if there is a real W5100 at the specified address,
+				;we should be able to write a $80 and read back a $00
+				
+	lda #$13  ;set indirect mode, with autoinc, no auto PING
+	sta WIZNET_MODE_REG
+	lda WIZNET_MODE_REG
+	cmp #$13
+	beq	@w5100_found
+	
+@try_clockport:
+	inc	clockport_mode
+	;now try with clockport	on
   	lda $de01
 	ora #1			;turn on clockport
 	sta $de01
 
+
 	lda #$80  ;reset
 	sta WIZNET_MODE_REG
 	lda WIZNET_MODE_REG
@@ -103,12 +128,23 @@ init:
 				;make sure if we write to mode register without bit 7 set,
 				;the value persists.
 	
+
+@w5100_found:
+
 	ldax #w5100_found
 	jsr	print
 	lda #>WIZNET_MODE_REG
 	jsr	print_hex
 	lda #<WIZNET_MODE_REG
 	jsr	print_hex
+	lda clockport_mode
+	bne	@clockport
+	ldax #direct
+	jmp :+
+@clockport:	
+	ldax	#clockport
+:	
+	jsr	print
 	jsr	print_cr	
 
 
@@ -127,6 +163,8 @@ init:
 	ldax #test_duration
 	jsr print
 
+	ldax #test_0
+	jsr	print
 
 	ldax #test_1
 	jsr	print
@@ -148,6 +186,8 @@ main:
 	bne	@not_space
 	jsr reset_clock
 @loop_test:	
+	jsr	do_test_0
+	bcs	main
 	jsr	do_test_1
 	bcs	main
 	jsr	do_test_2
@@ -158,6 +198,12 @@ main:
 	bne	main
 	jmp	@loop_test
 @not_space:
+	cmp #'0'
+	bne	@not_0
+	jsr reset_clock
+	jsr	do_test_0
+	jmp	main
+@not_0:
 	cmp #'1'
 	bne	@not_1
 	jsr reset_clock
@@ -185,17 +231,38 @@ main:
 
 	
 failed:
-	ldax	#FAILED
+	lda #$02
-	jsr	print
+	sta $d020
 	sec
 	rts
 
+
+do_test_0:
+
+	lda	#0
+	sta address_inc_mode
+
+	ldax #test_0
+	jsr	print
+	lda #$11  ;set indirect mode, with no autoinc, no auto PING
+	jmp set_address_mode
+	
 do_test_1:
+
 	lda	#0
 	sta	intersperse_address_reads
+	lda	#1
+	sta address_inc_mode
+
 	ldax #test_1
 do_w5100_test:	
 	jsr	print
+	lda #$13  ;set indirect mode, with autoinc, no auto PING
+set_address_mode:	
+	
+	sta WIZNET_MODE_REG
+	lda #$06  ;
+    sta $D020 ;border
 	
 	jsr	w5100_access_test
 	bcs	failed
@@ -206,13 +273,19 @@ ok:
 	rts
 
 do_test_2:
+
 	lda	#1
 	sta	intersperse_address_reads
+	sta address_inc_mode
+
 	ldax #test_2
 	jmp do_w5100_test
 
 
 do_test_3:
+	lda #$06  ;
+    sta $D020 ;border
+
 	ldax #test_3
 	jsr	print
 	sei
@@ -224,6 +297,9 @@ do_test_3:
 	lda	#1
 	sta	update_clock
 
+	lda #$11  ;set indirect mode, with no autoinc, no auto PING
+	sta WIZNET_MODE_REG
+
 	;set up the W5100 to trigger an interrupt
 	lda #1
 	lda #$00
@@ -236,6 +312,8 @@ do_test_3:
 	sta	WIZNET_ADDR_LO
 	lda #$00	;retry period high byte
 	sta WIZNET_DATA_REG
+	lda	#$18		;retry period
+	sta	WIZNET_ADDR_LO
 	lda #$01	;retry period low byte
 	sta WIZNET_DATA_REG
 
@@ -346,6 +424,11 @@ w5100_access_test:
 	lda	WIZNET_ADDR_LO	;see if we can force a glitch!
 :	
 
+	lda address_inc_mode
+	bne :+
+	inc	WIZNET_ADDR_LO	;see if we can force a glitch!
+:	
+
 	inc byte_counter
 	bne	@write_one_byte
 
@@ -366,6 +449,11 @@ w5100_access_test:
 	sec
 	rts	
 @ok:
+	lda address_inc_mode
+	bne :+
+	inc	WIZNET_ADDR_LO	;see if we can force a glitch!
+:	
+
 	inx
 	bne	@test_one_byte
 
@@ -513,7 +601,7 @@ get_key:
 banner:
 .byte $93 ;CLS
 .byte $9a;
-.byte $0d,"RR-NET MK3 DIAGNOSTICS 0.21"
+.byte $0d,"RR-NET MK3 DIAGNOSTICS 0.23"
 
 .include "timestamp.i"
 .byte $0d
@@ -528,33 +616,37 @@ test_duration:
 
 OK:
 	.byte 157,157,"OK ",0
-FAILED:
+
-	.byte 157,157,"!!",0
+test_0:
+.byte $13	;home
+.byte  $11,$11,$11,$11,$11,$11,$11
+.byte "0) W5100 MEMORY ACCESS 0 :   "
+.byte 0
 
 test_1:
 .byte $13	;home
-.byte  $11,$11,$11,$11,$11,$11,$11
+.byte  $11,$11,$11,$11,$11,$11,$11,$11
 .byte "1) W5100 MEMORY ACCESS 1 :   "
 .byte 0
 test_2:
 .byte $13	;home
-.byte  $11,$11,$11,$11,$11,$11,$11,$11
+.byte  $11,$11,$11,$11,$11,$11,$11,$11,$11
 .byte "2) W5100 MEMORY ACCESS 2 :   "
 .byte 0
 test_3:
 .byte $13	;home
-.byte  $11,$11,$11,$11,$11,$11,$11,$11,$11
+.byte  $11,$11,$11,$11,$11,$11,$11,$11,$11,$11
 .byte "3) NMI TEST              :   "
 .byte 0
 prompt:
 .byte $13	;home
-.byte  $11,$11,$11,$11,$11,$11,$11,$11,$11,$11,$11,$11
+.byte  $11,$11,$11,$11,$11,$11,$11,$11,$11,$11,$11,$11,$11
-.byte "PRESS 1..3 TO RUN A SINGLE TEST",13
+.byte "PRESS 0..3 TO RUN A SINGLE TEST",13
 .byte "SPACE TO CYCLE ALL TESTS",13
 .byte 0
 after_prompt:
 .byte $13	;home
-.byte  $11,$11,$11,$11,$11,$11,$11,$11,$11,$11,$11,$11,$11,$11
+.byte  $11,$11,$11,$11,$11,$11,$11,$11,$11,$11,$11,$11,$11,$11,$11
 .byte 0
 loop: .byte "TEST $",0
 not_found: .byte "NO "
@@ -562,6 +654,9 @@ w5100_found: .byte "W5100 FOUND AT $",0
 error_offset: .byte 13,"OFFSET $",0
 was: .byte " WAS $",0
 reset_cursor: .byte 157,157,0
+clockport: .byte " [CLOCKPORT]",0
+direct: .byte " [DIRECT]",0
+
 .bss
 last_byte: .res 1
 loop_count: .res 1
@@ -576,3 +671,5 @@ update_clock: .res 1
 tick_counter: .res 1
 timeout_count: .res 1
 got_nmi: .res 1
+clockport_mode: .res 1
+address_inc_mode: .res 1