franklin/ace2000_c000_cfff.s

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2021-11-12 04:09:01 +00:00
;;; ============================================================
;;; Franklin ACE 2X00 ROM V6.0 Disassembly
;;;
;;; First $1000 bytes of U2 ROM (usually banked in $C000-$CFFF)
;;;
;;; Build with CC65's ca65 assembler
;;; ============================================================
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.setcpu "65C02"
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.include "opcodes.inc"
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.feature string_escapes
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;;; ============================================================
;;; Patches
;;; Set to 1 to include fixes for:
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;;; * CH not working to set horizontal cursor position.
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;;; * MouseText mode failing to exist on $18 output.
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;;; * MouseText displaying if $40-$5F sent to COUT.
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INCLUDE_PATCHES = 0
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;;; ============================================================
;;; Equates
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;;; Zero Page
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WNDLFT := $20
WNDWDTH := $21
WNDTOP := $22
WNDBTM := $23
CH := $24
CV := $25
BASL := $28
BASH := $29
BAS2L := $2A
BAS2H := $2B
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INVFLG := $32
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CSWL := $36
CSWH := $37
KSWL := $38
KSWH := $39
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A1L := $3C
A1H := $3D
A2L := $3E
A2H := $3F
A4L := $42
A4H := $43
RNDL := $4E
RNDH := $4F
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;;; Page 3 Vectors
XFERVEC := $3ED
;;; Screen Holes
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SAVEA := $4F8
SAVEX := $578
SAVEY := $478
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SAVECV := $6F8
SAVECH := $778
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OLDCH := $47B
MODE := $4FB
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;; Bit 7 = Escape Mode
;; Bit 6 = MouseText active
;; Bit 5 = ??? set when "normal"
;; Bit 4 = ??? set when "normal"
;; Bit 3 = ??? unused ???
;; Bit 2 = ??? unused ???
;; Bit 1 = ??? used for ???
;; Bit 0 = ??? used for ???
M_ESC = %10000000
M_MOUSE = %01000000
M_NORMAL= %00110000
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M_INACTIVE = $FF ; When firmware is inactive
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OURCH := $57B
OURCV := $5FB
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CHAR := $67B
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XCOORD := $6FB
TEMP1 := $77B ; Unused
OLDBASL := $77B
TEMP2 := $7FB
OLDBASH := $7FB
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FKEYPTR := $479 ; Holds offset from Aux $200 to FKEY def
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;;; I/O Soft Switches
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KBD := $C000
CLR80COL:= $C000
SET80COL:= $C001
RDMAINRAM := $C002
RDCARDRAM := $C003
WRMAINRAM := $C004
WRCARDRAM := $C005
ALTZPOFF:= $C008
ALTZPON := $C009
CLR80VID:= $C00C
SET80VID:= $C00D
CLRALTCHAR := $C00E
SETALTCHAR := $C00F
KBDSTRB := $C010
RDLCBNK2:= $C011
RDLCRAM := $C012
RDRAMRD := $C013
RDRAMWRT:= $C014
RD80COL := $C018
RDTEXT := $C01A
ALTCHARSET := $C01E
RD80VID := $C01F
TXTPAGE1:= $C054
TXTPAGE2:= $C055
ROMIN := $C081
ROMIN2 := $C082
LCBANK2 := $C083
LCBANK1 := $C08B
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;;; Documented Firmware Entry Points
C3KeyIn := $C305
C3COut1 := $C307
AUXMOVE := $C311
XFER := $C314
CLRROM := $CFFF
;;; Monitor ROM
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BELLB := $FBE2
SETWND := $FB4B
SETKBD := $FE89
SETVID := $FE93
MON_VTAB:= $FC22
CLREOP := $FC42
HOME := $FC58
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LINEFEED:= $FC66
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CLREOL := $FC9C
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CANCEL := $FD62
MON_INPRT := $FE8D
REGZ := $FEBF
USR := $FECA
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;;; Franklin ACE 2X00-specific softswitches
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BankU1In := $C079 ; Map U1 into $A000-$BFFF
BankU1Out := $C078 ; Map U1 out, and RAM back in to $A000-$BFFF
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;;; ============================================================
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;;; U2 $0000 - Mapped to Page $C1 - Parallel Port Firmware
;;; ============================================================
.org $C100
.scope offset00_pageC1
bra @l5
bra @l1
nop
pha
pla
@l1: pha
pla
clc
clv
@l2: pha
phx
phy
sta $0679
sta CLRROM
sta BankU1In
bvc @l3
ldx #<@l1
stx $36
ldx #>@l1
stx $37
jsr $B000 ; Entry point in U1
@l3: jsr $B02C ; Entry point in U1
sta BankU1Out
ply
plx
pla
@l4: rts
@l5: bit @l4
bra @l2
.res $C1D0 - *, 0
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.byte $ff, $ff, $00, $00, $ff, $ff, $00, $00
.byte $ff, $ff, $00, $00, $ff, $ff, $00, $00
.byte $ff, $ff, $00, $00, $ff, $ff, $00, $00
.byte $ff, $ff, $00, $00, $ff, $ff, $00, $00
.byte $ff, $ff, $00, $00, $ff, $ff, $00, $00
.byte $ff, $ff, $00, $00, $ff, $ff, $00, $00
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.endscope
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;;; ============================================================
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;;; U2 $0100 - Mapped to ??? - ???
;;; ============================================================
.org $0100
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.scope offset01
@l1: lda $24
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pha
lda $22
sta $25
stz $24
jsr MON_VTAB
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@l2: jsr $FA37 ; ???
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ldy $29
sty $2B
ldy $28
sty $2A
lda $23
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beq @l7
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dec a
cmp $25
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beq @l7
bcc @l7
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inc $25
jsr MON_VTAB
ldy $21
dey
bit RD80VID
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@l3: bmi @l5
@l4: lda ($28),y
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sta ($2A),y
dey
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bpl @l4
bra @l2
@l5: tya
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lsr a
tay
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@l6: bit TXTPAGE1
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lda ($28),y
sta ($2A),y
bit TXTPAGE2
lda ($28),y
sta ($2A),y
dey
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bpl @l6
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bit TXTPAGE1
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bra @l2
@l7: stz $24
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jsr CLREOL
plx
stx $24
jmp MON_VTAB
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.endscope
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;;; ============================================================
;;; U2 $0200 - Empty
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;;; ============================================================
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.res $0300 - *, 0
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;;; ============================================================
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;;; U2 $0300 - Mapped to Page $C3 - Enhanced 80 Column Firmware
;;; ============================================================
.org $C300
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;; Init
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LC300: bit SETV ; V = init
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bra MainEntry
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;; Input
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.assert * = C3KeyIn, error, "Entry point mismatch"
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LC305: sec
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.byte OPC_BCC ; never taken; skip next byte
;; Output
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.assert * = C3COut1, error, "Entry point mismatch"
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LC307: clc
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clv
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bra MainEntry
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;; Signature bytes
.byte $01, $88
;; Pascal 1.1 Firmware Protocol Table
.byte <JPINIT
.byte <JPREAD
.byte <JPWRITE
.byte <JPSTAT
;; AUXMOVE
.assert * = AUXMOVE, error, "Entry point mismatch"
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jmp JumpAuxMove
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;; XFER
.assert * = XFER, error, "Entry point mismatch"
php
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bit CLRROM
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plp
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jmp DoXfer
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;;; ============================================================
;;; Pascal Entry Points
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JPINIT: bit CLRROM
jmp PascalInit
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JPREAD: bit CLRROM
jmp PascalRead
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JPWRITE:bit CLRROM
jmp PascalWrite
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JPSTAT: bit CLRROM
jmp PascalStatus
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JumpAuxMove:
bit CLRROM
jmp DoAuxMove
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;;; ============================================================
;;; Main Entry Points
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MainEntry:
sta CLRROM
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sta SAVEA
stx SAVEX
sty SAVEY
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pha
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bvc l1
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;; Init firmware
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lda #<LC305
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sta KSWL
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ldx #>LC305
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stx KSWH
lda #<LC307
sta CSWL
stx CSWH
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jsr LC800
clc
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l1: php
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bit RD80VID
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bpl l2
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lsr WNDWDTH
asl WNDWDTH
sta SET80COL
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;; NOTE: In ACE 500 ROM, the below is patched to
;; address the CH/OURCH issue.
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.if !INCLUDE_PATCHES
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lda OURCH
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.else
jsr Patch1
.endif
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sta CH
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l2: plp
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pla
bcs l3 ; input or output?
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;; Output
jsr OutputChar
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bra l9
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;; Input
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l3: ldx SAVEX
beq l4
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dex
lda $0678
cmp #$88 ; left?
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beq l4
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cmp $0200,x
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bne l7
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sta $0200,x
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l4: jsr LC877
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cmp #$9B ; escape?
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beq EscapeMode
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cmp #$8D ; return?
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bne l5
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pha
jsr DoClearEOL
pla
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l5: cmp #$95 ; right?
bne l6
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jsr LCEBE
ora #$80
cmp #$A0 ; non-control char
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bcs l6
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ora #$40
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l6: sta $0678
bra l8
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l7: jsr LC850
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stz $0678
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l8: bra l10
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l9: lda SAVEA
l10: ldx SAVEX
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ldy CH
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.if !INCLUDE_PATCHES
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sty OURCH
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.else
jsr Patch2
.endif
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ldy SAVEY
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SETV: rts ; has V flag set
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;;; ============================================================
;;; Escape Mode
EscapeMode:
lda #M_ESC
tsb MODE
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jsr LC850
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jsr ProcessEscapeModeKey
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cmp #$98 ; ctrl-x (clear)
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beq l6
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lda MODE ; still in escape mode?
bmi EscapeMode
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bra l4
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;;; ============================================================
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.assert * = $C3DC, error, "Potential entry point moved"
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;; ???
bit CLRROM
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jmp UnknownEP1
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;;; ============================================================
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brk
brk
brk
brk
brk
brk
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;;; ============================================================
;;; Entry points called by Monitor ROM
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.assert * = $C3E8, error, "Entry point moved"
;; Called by U3 ROM ($F37A)
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bit CLRROM
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jmp UnknownEP2
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;; Called by U3 ROM ($F809)
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bit CLRROM
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jmp InitFKEYDefinitions
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;; Called by U3 ROM ($F9B7)
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bit CLRROM
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jmp UnknownEP4
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;; Called by U3 ROM ($FA9E)
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bit CLRROM
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jmp HandleSpecialKeys
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;;; ==================================================
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;;; U2 $0400 - Mapped to Page $C4 - ???
;;; ==================================================
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.assert * = $C400, error, "Mismatch"
.scope
LF813 := $F813 ; Not an Apple II entry point
LF981 := $F981 ; Not an Apple II entry point
LFA37 := $FA37 ; Not an Apple II entry point
LFA52 := $FA52 ; Not an Apple II entry point
LFC45 := $FC45 ; Not an Apple II entry point
LFEEB := $FEEB ; Not an Apple II entry point
;; Called from $F88C
LC400:
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ldx #$00
eor #$20
beq @l1
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and #$9F
beq @l3
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asl a
eor #$12
beq @l2
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and #$1A
eor #$02
beq @l3
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and #$10
bne @l2
@l1: inx
@l2: inx
@l3: stx $2F
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jmp LF813
;;; ============================================================
;; Called from $F8C5
LC420:
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lda KBD
eor #$93
bne @l2
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lda KBDSTRB
@l1: jsr LFA37
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lda KBD
bpl @l1
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eor #$83
beq @l2
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sta KBDSTRB
@l2: jmp LF813
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;;; ============================================================
;; Called from $F957
LC43:
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lda $2E
eor #$FF
and ($26),y
sta ($26),y
lda $2E
and $30
ora ($26),y
sta ($26),y
jmp LF813
;;; ============================================================
;; Called from $FE4B
LC44F:
ldx #$3C
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jsr LFC45
beq @l1
jsr @l2
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jsr LFA52
ldx #$42
jsr LFA52
bra LC44F
@l1: jsr @l2
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jmp LF813
@l2: lda ($00,x)
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sta ($06,x)
rts
;;; ============================================================
;; Called from $FEAA
LC46E:
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and #$0F
asl a
tax
lda @l1,x
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pha
lda @l1+1,x
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tax
pla
jmp LF813
;; Jump Table (target address-1 ???)
@l1:
.addr $FDF0
.addr $C100
.addr $C200
.addr $C300
.addr $C400
.addr $C500
.addr $C600
.addr $C700
.addr $FD1B
;;; ============================================================
;; Called from $FFA7
LC490:
lda #$00
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stz A2L
stz A2H
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stz $2C
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@l1: ora A2L
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sta A2L
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lda $0200,y
iny
jsr LFEEB
bmi @l4
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dec $2C
ldx #$04
@l2: asl A2L
@l3: rol A2H
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dex
bne @l2
bra @l1
@l4: jmp LF813
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;;; ============================================================
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;; Called from $F847
lC4B5:
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lsr a
phx
php
ldx #$26
jsr LF981
plp
php
lda #$00
adc #$00
tax
lda LC4CE,x
sta $2E
plp
plx
LC4CB: jmp LF813
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;; Data table
LC4CE: .byte $0F, $F0
;;; ============================================================
;; Called from $F854
LC4D0:
phx
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and #$0F
tax
lda @table,x
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sta $30
plx
jmp LF813
@table:
.byte $00, $11, $22, $33, $44, $55, $66, $77
.byte $88, $99, $AA, $BB, $CC, $DD, $EE, $FF
;;; ============================================================
;; Called from $FC00
LC4ED:
2021-11-06 00:44:04 +00:00
tya
@l1: ldy $C4FD,x
beq @l2
2021-11-06 00:44:04 +00:00
cmp $C000,y
inx
bra @l1
@l2: tay
2021-11-06 00:44:04 +00:00
jmp LF813
;; Display mode softswitch table
@swtable:
.byte $52, $54, $56, $00 ; Full-screen, Page1, LoRes
.byte $56, $50, $53, $00 ; LoRes, Graphics, Split-screen
;; Dispatch table for RTS dispatch?
2021-11-12 04:50:10 +00:00
.macro TABLE_ENTRY char, addr
.byte char, .lobyte(addr-1), .hibyte(addr-1)
.endmacro
@table:
2021-11-12 04:50:10 +00:00
TABLE_ENTRY $9b, $FA1D ; ^[ aka <ESC>
TABLE_ENTRY $88, $FA0A ; ^H aka <-
TABLE_ENTRY $98, CANCEL ; ^X
TABLE_ENTRY $95, $FA22 ; ^U aka ->
TABLE_ENTRY $8d, $FA17 ; ^M aka <RETURN>
.byte $00
2021-11-12 04:50:10 +00:00
TABLE_ENTRY $8d, $FC3B ; ^M aka <RETURN>
TABLE_ENTRY $8a, LINEFEED ; ^J aka “down”
TABLE_ENTRY $87, BELLB ; ^G aka BELL
TABLE_ENTRY $88, $FA43 ; ^H aka <-
.byte $00
2021-11-12 04:50:10 +00:00
TABLE_ENTRY $49, $FCF6 ; I
TABLE_ENTRY $4a, $FA5C ; J
TABLE_ENTRY $4b, $FBF6 ; K
TABLE_ENTRY $4d, $FCBD ; M
.byte $00
2021-11-12 04:50:10 +00:00
TABLE_ENTRY $8d, REGZ ; ^M aka <RETURN>
TABLE_ENTRY $a0, USR ; Space
TABLE_ENTRY $ae, $FDAB ; .
TABLE_ENTRY $ba, $FD48 ; :
TABLE_ENTRY $bc, $FE13 ; <
TABLE_ENTRY $c7, $F881 ; G
TABLE_ENTRY $ce, MON_INPRT ; N
TABLE_ENTRY $82, $E000 ; ^B
TABLE_ENTRY $83, $E003 ; ^C
TABLE_ENTRY $99, $03F8 ; ^Y
TABLE_ENTRY $90, $FD26 ; ^P
2021-11-06 01:21:23 +00:00
.endscope
2021-11-06 00:44:04 +00:00
;;; ============================================================
2021-11-11 07:17:24 +00:00
.res $C800 - *, 0
2021-11-06 00:44:04 +00:00
;;; ============================================================
2021-11-14 16:58:48 +00:00
;;; U2 $0800 - Pages $C8-$CF - Enhanced 80 Column Firmware
;;; ============================================================
2021-11-06 00:44:04 +00:00
2021-11-06 03:00:40 +00:00
LC800: lda #M_NORMAL
2021-11-06 01:21:23 +00:00
sta MODE
jsr Enable80Col
2021-11-06 03:00:40 +00:00
jsr DoSETWND
2021-11-06 00:44:04 +00:00
jmp DoHomeAndClear
LC80E: ldy #$00
ldx #$00
LC812: cpy WNDWDTH
bcs LC820
jsr LCEC0
sta $0200,x
inx
iny
bra LC812
LC820: dey
sty CH
2021-11-06 01:21:23 +00:00
stx SAVEX
2021-11-06 00:44:04 +00:00
lda #$8D
2021-11-06 01:21:23 +00:00
rts1: rts
2021-11-06 00:44:04 +00:00
Do40Col:
bit RD80VID
php
jsr Disable80Col
2021-11-10 04:55:40 +00:00
jsr SaveCHCV
2021-11-06 03:00:40 +00:00
jsr DoSETWND
2021-11-06 00:44:04 +00:00
plp
2021-11-06 01:21:23 +00:00
bpl rts1
2021-11-06 00:44:04 +00:00
jmp LCC4E
2021-11-10 04:55:40 +00:00
;;; ============================================================
2021-11-11 07:17:24 +00:00
.if !INCLUDE_PATCHES
2021-11-06 00:44:04 +00:00
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
2021-11-11 07:17:24 +00:00
.else
Patch4:
lda CHAR ; char to be printed
bit INVFLG
bmi :+ ; normal
and #$7F ; clear high bit
: and #$FF ; set N flag
rts
.endif
;;; ============================================================
.res $C84D - *, 0
2021-11-06 01:21:23 +00:00
2021-11-10 04:55:40 +00:00
;;; ============================================================
;; ???
jsr InitTextWindow
2021-11-06 00:44:04 +00:00
LC850: jsr LCBC7
2021-11-06 01:21:23 +00:00
LC853: inc RNDL
bne :+
inc RNDH
:
2021-11-10 04:55:40 +00:00
jsr UnknownEP4
2021-11-06 00:44:04 +00:00
bcc LC853
2021-11-23 18:40:21 +00:00
jsr HandleSpecialKeys
2021-11-06 00:44:04 +00:00
cmp #$06
bcc LC86E
and #$7F
sta CHAR
ora #$80
bra LC871
LC86E: sta CHAR
LC871: pha
jsr LCBDE
pla
2021-11-06 01:21:23 +00:00
rts2: rts
2021-11-06 00:44:04 +00:00
2021-11-07 20:52:15 +00:00
;;; ============================================================
2021-11-06 00:44:04 +00:00
LC877: jsr LC850
cmp #$00
2021-11-07 20:52:15 +00:00
beq @l4
2021-11-06 00:44:04 +00:00
cmp #$02
beq LC80E
cmp #$05
2021-11-06 01:21:23 +00:00
bne rts2
2021-11-06 00:44:04 +00:00
ldy CH
2021-11-07 20:52:15 +00:00
@l1: iny
2021-11-06 00:44:04 +00:00
cpy WNDWDTH
2021-11-07 20:52:15 +00:00
beq @l2
2021-11-06 00:44:04 +00:00
jsr LCEC0
dey
jsr LCECB
iny
2021-11-07 20:52:15 +00:00
bra @l1
2021-11-06 00:44:04 +00:00
2021-11-07 20:52:15 +00:00
@l2: dey
@l3: lda #$A0
2021-11-06 00:44:04 +00:00
jsr LCECB
bra LC877
2021-11-07 20:52:15 +00:00
@l4: ldy WNDWDTH
2021-11-06 00:44:04 +00:00
dey
2021-11-07 20:52:15 +00:00
@l5: cpy CH
beq @l3
2021-11-06 00:44:04 +00:00
dey
jsr LCEC0
iny
jsr LCECB
dey
2021-11-07 20:52:15 +00:00
bra @l5
;;; ============================================================
2021-11-06 00:44:04 +00:00
OutputChar:
sta CHAR
2021-11-07 20:52:15 +00:00
LC8B4: jsr CheckPauseListing
2021-11-06 01:21:23 +00:00
lda MODE
2021-11-11 05:07:34 +00:00
and #$03 ; test low 2 bits (why???)
2021-11-07 20:52:15 +00:00
beq @l1
2021-11-06 00:44:04 +00:00
jmp LCA11
2021-11-07 20:52:15 +00:00
@l1: lda CHAR
2021-11-06 00:44:04 +00:00
and #$7F
cmp #$20
2021-11-06 03:00:40 +00:00
bcc DoCtrlCharOut
2021-11-06 00:44:04 +00:00
ldy CH
cpy WNDWDTH
2021-11-07 20:52:15 +00:00
bcc @l2
2021-11-06 00:44:04 +00:00
jsr DoReturn
2021-11-11 05:07:34 +00:00
;; If MouseText is not active, make sure to map inverse
;; uppercase range to the control character range.
2021-11-11 07:17:24 +00:00
@l2:
.if !INCLUDE_PATCHES
lda CHAR ; char to be printed
2021-11-11 05:07:34 +00:00
bit INVFLG ; inverse?
2021-11-11 07:17:24 +00:00
.else
jsr Patch4 ; sets N flag if inverse char
nop
nop
.endif
2021-11-11 05:07:34 +00:00
bmi @l3 ; no, so not MT, just print it
2021-11-06 00:44:04 +00:00
and #$7F
2021-11-11 05:07:34 +00:00
bit MODE ; MT active? (bit 6 = M_MOUSE)
bvs @l3 ; yes, so skip correction
bit ALTCHARSET ; also skip correction if
bpl @l3 ; alt charset is disabled
;; If within "@ABC...XYZ[\]^_" range, map to $00-$1F
;; so it shows as inverse uppercase, not MouseText.
cmp #'@'
bcc :+
cmp #'_'+1
bcs :+
2021-11-06 00:44:04 +00:00
and #$1F
2021-11-11 05:07:34 +00:00
:
2021-11-07 20:52:15 +00:00
@l3: jsr LCBF9
2021-11-06 00:44:04 +00:00
jmp DoForwardSpace
2021-11-07 03:06:39 +00:00
;;; ============================================================
2021-11-06 00:44:04 +00:00
DoNothing:
rts
;;; ============================================================
2021-11-06 03:00:40 +00:00
;;; Output control character handling
2021-11-06 00:44:04 +00:00
;; Input is char, < $20
2021-11-06 03:00:40 +00:00
DoCtrlCharOut:
sec
2021-11-06 00:44:04 +00:00
sbc #$07
bcc DoNothing
asl a
tax
2021-11-07 20:52:15 +00:00
jmp (@jt,x)
2021-11-06 00:44:04 +00:00
2021-11-07 20:52:15 +00:00
@jt:
2021-11-06 00:44:04 +00:00
.addr DoBell ; $07 Ctrl-G Bell
2021-11-06 01:21:23 +00:00
.addr DoBackspace ; $08 Ctrl-H Backspace
.addr DoNothing ; $09 Ctrl-I
2021-11-06 00:44:04 +00:00
.addr DoLineFeed ; $0A Ctrl-J Line feed
.addr DoClearEOS ; $0B Ctrl-K Clear EOS
.addr DoHomeAndClear ; $0C Ctrl-L Home and clear
.addr DoReturn ; $0D Ctrl-M Return
.addr DoNormal ; $0E Ctrl-N Normal
.addr DoInverse ; $0F Ctrl-O Inverse
2021-11-06 01:21:23 +00:00
.addr DoNothing ; $10 Ctrl-P
2021-11-06 00:44:04 +00:00
.addr Do40Col ; $11 Ctrl-Q 40-column
.addr Do80Col ; $12 Ctrl-R 80-column
2021-11-06 01:21:23 +00:00
.addr DoNothing ; $13 Ctrl-S
.addr DoNothing ; $14 Ctrl-T
2021-11-06 00:44:04 +00:00
.addr DoQuit ; $15 Ctrl-U Quit
.addr DoScroll ; $16 Ctrl-V Scroll
.addr DoScrollUp ; $17 Ctrl-W Scroll-up
.addr DoDisableMouseText ; $18 Ctrl-X Disable MouseText
.addr DoHome ; $19 Ctrl-Y Home
.addr DoClearLine ; $1A Ctrl-Z Clear line
.addr DoEnableMouseText ; $1B Ctrl-[ Enable MouseText
.addr DoForwardSpace ; $1C Ctrl-\ Forward space
.addr DoClearEOL ; $1D Ctrl-] Clear EOL
2021-11-07 03:27:30 +00:00
.addr DoCtrlCaret ; $1E Ctrl-^ ???
2021-11-06 00:44:04 +00:00
.addr DoUp ; $1F Ctrl-_ Up
;;; ============================================================
2021-11-06 03:00:40 +00:00
;;; For Escape key sequences
2021-11-06 00:44:04 +00:00
2021-11-07 20:52:15 +00:00
ProcessEscapeModeKey:
pha
2021-11-06 03:00:40 +00:00
lda #M_ESC
2021-11-07 20:52:15 +00:00
trb MODE
2021-11-06 00:44:04 +00:00
pla
and #$7F
cmp #'a'
2021-11-07 20:52:15 +00:00
bcc @l1
2021-11-06 00:44:04 +00:00
cmp #'z'+1
2021-11-07 20:52:15 +00:00
bcs @l1
2021-11-06 00:44:04 +00:00
and #$DF ; convert to uppercase
;; Scan table for match
2021-11-07 20:52:15 +00:00
@l1: ldx #$00
@l2: ldy @code_table,x
2021-11-06 00:44:04 +00:00
beq DoNothing
2021-11-07 20:52:15 +00:00
cmp @code_table,x
beq @l3
2021-11-06 00:44:04 +00:00
inx
2021-11-07 20:52:15 +00:00
bra @l2
2021-11-06 00:44:04 +00:00
2021-11-07 20:52:15 +00:00
@l3: txa
2021-11-06 00:44:04 +00:00
asl a
tax
2021-11-07 20:52:15 +00:00
jmp (@jt,x)
2021-11-06 00:44:04 +00:00
2021-11-07 20:52:15 +00:00
@code_table:
2021-11-06 03:00:40 +00:00
.byte '@' ; Escape @ - clear, home & exit mode
.byte 'A' ; Escape A - right & exit mode
.byte 'B' ; Escape B - left & exit mode
.byte 'C' ; Escape C - down & exit mode
.byte 'D' ; Escape D - up & exit mode
.byte 'E' ; Escape E - clear EOL & exit mode
.byte 'F' ; Escape F - clear EOS & exit mode
.byte 'I' ; Escape I - up
.byte 'J' ; Escape J - left
.byte 'K' ; Escape K - right
.byte 'M' ; Escape M - down
.byte $0b ; Escape up - up
.byte $0a ; Escape down - down
.byte $08 ; Escape left - left
.byte $15 ; Escape right - right
.byte '4' ; Escape 4 - 40 col mode
.byte '8' ; Escape 8 - 80 col mode
.byte $11 ; Escape Ctrl+Q - deactivate
2021-11-06 00:44:04 +00:00
.byte $00 ; sentinel
2021-11-07 20:52:15 +00:00
@jt:
2021-11-06 03:00:40 +00:00
.addr DoHomeAndClear ; Escape @ - clear, home & exit mode
.addr DoForwardSpace ; Escape A - right & exit mode
.addr DoBackspace ; Escape B - left & exit mode
.addr DoLineFeed ; Escape C - down & exit mode
.addr DoUp ; Escape D - up & exit mode
.addr DoClearEOL ; Escape E - clear EOL & exit mode
.addr DoClearEOS ; Escape F - clear EOS & exit mode
.addr DoUpRemain ; Escape I - up
.addr DoLeftRemain ; Escape J - left
.addr DoRightRemain ; Escape K - right
.addr DoDownRemain ; Escape M - down
.addr DoUpRemain ; Escape up - up
.addr DoDownRemain ; Escape down - down
.addr DoLeftRemain ; Escape left - left
.addr DoRightRemain ; Escape right - right
.addr Do40Col ; Escape 4 - 40 col mode
.addr Do80Col ; Escape 8 - 80 col mode
.addr DoQuit ; Escape Ctrl+Q - deactivate
2021-11-06 00:44:04 +00:00
;;; ============================================================
2021-11-07 20:52:15 +00:00
CheckPauseListing:
2021-11-06 03:00:40 +00:00
lda KBD
2021-11-06 00:44:04 +00:00
cmp #$93 ; Ctrl-S
2021-11-06 01:21:23 +00:00
bne rts3
2021-11-06 00:44:04 +00:00
bit KBDSTRB
2021-11-06 01:21:23 +00:00
: lda KBD
bpl :-
2021-11-06 00:44:04 +00:00
cmp #$83 ; Ctrl-C
2021-11-06 01:21:23 +00:00
beq rts3
2021-11-06 00:44:04 +00:00
bit KBDSTRB
2021-11-06 01:21:23 +00:00
rts3: rts
2021-11-06 00:44:04 +00:00
2021-11-06 03:00:40 +00:00
;;; ============================================================
;; Unused???
2021-11-06 00:44:04 +00:00
nop
jmp LCB60
2021-11-06 03:00:40 +00:00
;;; ============================================================
DoUpRemain:
jsr DoUp
bra Remain
2021-11-06 00:44:04 +00:00
2021-11-06 03:00:40 +00:00
DoDownRemain:
jsr DoLineFeed
bra Remain
2021-11-06 00:44:04 +00:00
2021-11-06 03:00:40 +00:00
DoRightRemain:
jsr DoForwardSpace
bra Remain
2021-11-06 00:44:04 +00:00
2021-11-06 03:00:40 +00:00
DoLeftRemain:
jsr DoBackspace
2021-11-07 03:56:03 +00:00
;; fall through
2021-11-06 03:00:40 +00:00
Remain: lda #M_ESC ; stay in Escape Mode
jmp SetModeBits
2021-11-06 00:44:04 +00:00
2021-11-07 03:56:03 +00:00
;;; ============================================================
2021-11-06 00:44:04 +00:00
DoInverse:
ldy #$3F
bra LC9CA
DoNormal:
ldy #$FF
2021-11-06 01:21:23 +00:00
LC9CA: sty INVFLG
rts4: rts
2021-11-06 00:44:04 +00:00
2021-11-07 03:56:03 +00:00
;;; ============================================================
2021-11-06 00:44:04 +00:00
Do80Col:
bit RD80VID
php
jsr Enable80Col
2021-11-10 04:55:40 +00:00
jsr SaveCHCV
2021-11-06 03:00:40 +00:00
jsr DoSETWND
2021-11-06 00:44:04 +00:00
plp
2021-11-06 01:21:23 +00:00
bmi rts4
2021-11-06 00:44:04 +00:00
jmp LCBFE
2021-11-07 03:56:03 +00:00
;;; ============================================================
2021-11-06 00:44:04 +00:00
DoQuit:
jsr Do40Col
2021-11-06 03:00:40 +00:00
jsr DoSETVID
jsr DoSETKBD
lda #23
ldx #0
2021-11-10 04:55:40 +00:00
jsr SetCHCV
2021-11-06 03:00:40 +00:00
2021-11-10 02:17:23 +00:00
lda #M_INACTIVE
2021-11-06 00:44:04 +00:00
sta MODE ; set all mode bits (???)
2021-11-06 03:00:40 +00:00
lda #$98 ; Ctrl-X ???
2021-11-06 00:44:04 +00:00
rts
2021-11-06 03:00:40 +00:00
;;; ============================================================
;;; Adusting MODE Bits
2021-11-07 03:27:30 +00:00
DoCtrlCaret:
lda #$FC ; clear mode bits %xxxxxx00
2021-11-06 03:00:40 +00:00
jsr PreserveModeBits
2021-11-06 00:44:04 +00:00
lda #$32 ; set mode bits %xx11xx1x
2021-11-06 03:00:40 +00:00
bra SetModeBits
2021-11-06 00:44:04 +00:00
DoDisableMouseText:
2021-11-10 02:17:23 +00:00
.if !INCLUDE_PATCHES
lda #M_MOUSE ; BUG! Should be ~M_MOUSE
.else
lda #.lobyte(~M_MOUSE)
.endif
2021-11-06 03:00:40 +00:00
PreserveModeBits:
and MODE
bra StoreMode
2021-11-06 00:44:04 +00:00
DoEnableMouseText:
2021-11-06 03:00:40 +00:00
lda #M_MOUSE
SetModeBits:
ora MODE
StoreMode:
sta MODE
2021-11-06 00:44:04 +00:00
rts
2021-11-06 03:00:40 +00:00
;;; ============================================================
2021-11-06 00:44:04 +00:00
LCA11: lda CHAR ; character to read/print
sec
sbc #$20
and #$7F
pha
2021-11-06 01:21:23 +00:00
dec MODE ; clear low bit???
2021-11-06 00:44:04 +00:00
lda MODE
2021-11-06 01:21:23 +00:00
and #$03 ; test low 2 bits
2021-11-07 04:07:03 +00:00
bne @l2
2021-11-06 00:44:04 +00:00
pla
cmp #$18 ; +$20 is $38 = '8' ???
2021-11-07 04:07:03 +00:00
bcs @l1
2021-11-10 04:55:40 +00:00
jsr SetCV
2021-11-07 04:07:03 +00:00
@l1: lda $05F8
2021-11-06 00:44:04 +00:00
cmp WNDWDTH
2021-11-06 03:00:40 +00:00
bcs :+
2021-11-06 00:44:04 +00:00
sta CH
2021-11-06 03:00:40 +00:00
: rts
2021-11-06 00:44:04 +00:00
2021-11-07 04:07:03 +00:00
@l2: pla
2021-11-06 00:44:04 +00:00
sta $05F8
rts
2021-11-06 03:00:40 +00:00
;;; ============================================================
2021-11-06 00:44:04 +00:00
DoForwardSpace:
inc CH
lda CH
cmp WNDWDTH
bcs DoReturn
rts
2021-11-06 03:00:40 +00:00
;;; ============================================================
2021-11-06 00:44:04 +00:00
DoBackspace:
lda CH
2021-11-06 03:00:40 +00:00
beq :+
2021-11-06 00:44:04 +00:00
dec CH
2021-11-06 03:00:40 +00:00
rts5: rts
2021-11-06 00:44:04 +00:00
2021-11-06 03:00:40 +00:00
: lda CV
beq rts5
2021-11-06 00:44:04 +00:00
lda WNDWDTH
dec a
sta CH
2021-11-06 03:00:40 +00:00
;;; ============================================================
2021-11-06 00:44:04 +00:00
DoUp:
lda CV
2021-11-06 03:00:40 +00:00
beq rts5
2021-11-06 00:44:04 +00:00
dec CV
2021-11-10 04:55:40 +00:00
bra JumpMON_VTAB
2021-11-06 00:44:04 +00:00
2021-11-06 03:00:40 +00:00
;;; ============================================================
2021-11-06 00:44:04 +00:00
DoReturn:
stz CH
2021-11-06 03:00:40 +00:00
;; fall through
;;; ============================================================
2021-11-06 00:44:04 +00:00
DoLineFeed:
lda CV
2021-11-06 03:00:40 +00:00
cmp #23
2021-11-06 00:44:04 +00:00
bcs DoScrollUp
inc CV
2021-11-10 04:55:40 +00:00
bra JumpMON_VTAB
2021-11-06 00:44:04 +00:00
2021-11-06 03:00:40 +00:00
;;; ============================================================
2021-11-06 00:44:04 +00:00
DoHome:
lda WNDTOP
ldx #$00
2021-11-10 04:55:40 +00:00
bra SetCHCV
2021-11-06 00:44:04 +00:00
2021-11-06 03:00:40 +00:00
;;; ============================================================
2021-11-06 00:44:04 +00:00
DoClearLine:
lda CH
pha
stz CH
jsr DoClearEOL
pla
sta CH
rts
2021-11-06 03:00:40 +00:00
;;; ============================================================
2021-11-10 04:55:40 +00:00
RestoreCHCV:
lda SAVECV
ldx SAVECH
SetCHCV:
stx CH
SetCV:
sta CV
JumpMON_VTAB:
jmp DoMON_VTAB
2021-11-06 03:00:40 +00:00
;;; ============================================================
2021-11-06 00:44:04 +00:00
DoScrollUp:
lda CH
pha
jsr DoHome
2021-11-07 04:07:03 +00:00
@l1: ldy BASH
2021-11-06 00:44:04 +00:00
sty BAS2H
ldy BASL
sty BAS2L
lda WNDBTM
2021-11-07 04:07:03 +00:00
beq @l5
2021-11-06 00:44:04 +00:00
dec a
cmp CV
2021-11-07 04:07:03 +00:00
beq @l5
bcc @l5
2021-11-06 00:44:04 +00:00
inc CV
2021-11-10 04:55:40 +00:00
jsr JumpMON_VTAB
2021-11-06 00:44:04 +00:00
ldy WNDWDTH
dey
bit RD80VID
2021-11-07 04:07:03 +00:00
bmi @l3
@l2: lda (BASL),y
2021-11-06 00:44:04 +00:00
sta (BAS2L),y
dey
2021-11-07 04:07:03 +00:00
bpl @l2
bra @l1
2021-11-06 00:44:04 +00:00
2021-11-07 04:07:03 +00:00
@l3: tya
2021-11-06 00:44:04 +00:00
lsr a
tay
2021-11-07 04:07:03 +00:00
@l4: bit TXTPAGE1
2021-11-06 00:44:04 +00:00
lda (BASL),y
sta (BAS2L),y
bit TXTPAGE2
lda (BASL),y
sta (BAS2L),y
dey
2021-11-07 04:07:03 +00:00
bpl @l4
2021-11-06 00:44:04 +00:00
bit TXTPAGE1
2021-11-07 04:07:03 +00:00
bra @l1
2021-11-06 00:44:04 +00:00
2021-11-07 04:07:03 +00:00
@l5: stz CH
2021-11-06 00:44:04 +00:00
jsr DoClearEOL
plx
lda CV
2021-11-10 04:55:40 +00:00
jmp SetCHCV
2021-11-06 00:44:04 +00:00
2021-11-07 04:07:03 +00:00
;;; ============================================================
2021-11-10 04:55:40 +00:00
SaveCHCV:
lda CV
sta SAVECV
2021-11-06 00:44:04 +00:00
lda CH
2021-11-10 04:55:40 +00:00
sta SAVECH
2021-11-06 00:44:04 +00:00
rts
2021-11-06 03:00:40 +00:00
;;; ============================================================
;;; Load X,Y with address of a routine -1 (for `ROMCall`)
2021-11-06 00:44:04 +00:00
.macro LDXY addr
ldx #.hibyte(addr-1)
ldy #.lobyte(addr-1)
.endmacro
2021-11-06 03:00:40 +00:00
;;; ============================================================
2021-11-06 00:44:04 +00:00
DoBell:
LDXY BELLB
2021-11-06 03:00:40 +00:00
jmp ROMCall
;;; ============================================================
2021-11-06 00:44:04 +00:00
DoScroll:
2021-11-10 04:55:40 +00:00
jsr SaveCHCV
2021-11-06 00:44:04 +00:00
lda WNDBTM
dec a
dec a
sta $05F8
2021-11-07 04:07:03 +00:00
@l1: lda $05F8
2021-11-10 04:55:40 +00:00
jsr SetCV
2021-11-06 00:44:04 +00:00
lda BASL
sta BAS2L
lda BASH
sta BAS2H
lda $05F8
inc a
2021-11-10 04:55:40 +00:00
jsr SetCV
2021-11-06 00:44:04 +00:00
ldy WNDWDTH
dey
2021-11-07 04:07:03 +00:00
@l2: phy
2021-11-06 00:44:04 +00:00
bit TXTPAGE1
bit RD80VID
2021-11-07 04:07:03 +00:00
bpl @l3
2021-11-06 00:44:04 +00:00
tya
lsr a
tay
2021-11-07 04:07:03 +00:00
bcs @l3
2021-11-06 00:44:04 +00:00
bit TXTPAGE2
2021-11-07 04:07:03 +00:00
@l3: lda (BAS2L),y
2021-11-06 00:44:04 +00:00
sta (BASL),y
ply
dey
2021-11-07 04:07:03 +00:00
bpl @l2
2021-11-06 00:44:04 +00:00
bit TXTPAGE1
lda $05F8
cmp WNDTOP
2021-11-07 04:07:03 +00:00
beq @l4
2021-11-06 00:44:04 +00:00
dec $05F8
2021-11-07 04:07:03 +00:00
bra @l1
2021-11-06 00:44:04 +00:00
2021-11-07 04:07:03 +00:00
@l4: lda #$00
2021-11-10 04:55:40 +00:00
jsr SetCV
2021-11-06 00:44:04 +00:00
jsr DoClearLine
bit TXTPAGE1
2021-11-10 04:55:40 +00:00
jmp RestoreCHCV
2021-11-06 00:44:04 +00:00
2021-11-06 03:24:49 +00:00
;;; ============================================================
PascalInit:
jsr LC800
2021-11-06 00:44:04 +00:00
LCB47: jsr LCBC7
LCB4A: ldx CH
2021-11-10 02:17:23 +00:00
.if !INCLUDE_PATCHES
2021-11-06 00:44:04 +00:00
stx OURCH
2021-11-10 02:17:23 +00:00
.else
jsr Patch3
.endif
2021-11-06 00:44:04 +00:00
ldx #$00
rts
2021-11-06 03:24:49 +00:00
;;; ============================================================
PascalRead:
jsr InitTextWindow
2021-11-06 00:44:04 +00:00
jsr LC850
lda CHAR
bra LCB4A
2021-11-06 03:24:49 +00:00
;;; ============================================================
PascalWrite:
sta CHAR
LCB60: jsr InitTextWindow
2021-11-06 00:44:04 +00:00
jsr LCBDE
lda CHAR
ora #$80
sta CHAR
and #$7F
cmp #$15 ; right?
beq LCB4A
cmp #$0D ; return?
beq LCB7D
jsr LC8B4
bra LCB47
LCB7D: stz CH
bra LCB47
2021-11-06 03:24:49 +00:00
;;; ============================================================
PascalStatus:
cmp #$00
2021-11-07 04:07:03 +00:00
beq @l1
2021-11-06 00:44:04 +00:00
cmp #$01
2021-11-07 04:07:03 +00:00
bne @l2
2021-11-10 04:55:40 +00:00
jsr UnknownEP4
2021-11-06 00:44:04 +00:00
bra LCB4A
2021-11-07 04:07:03 +00:00
@l1: sec
2021-11-06 00:44:04 +00:00
bra LCB4A
2021-11-07 04:07:03 +00:00
@l2: ldx #$03
2021-11-06 00:44:04 +00:00
clc
rts
2021-11-06 03:24:49 +00:00
;;; ============================================================
InitTextWindow:
pha
2021-11-06 00:44:04 +00:00
lda OLDBASL
sta BASL
lda OLDBASH
sta BASH
stz WNDTOP
stz WNDLFT
lda #80
sta WNDWDTH
lda #24
sta WNDBTM
.if !INCLUDE_PATCHES
2021-11-06 00:44:04 +00:00
lda OURCH
.else
jsr Patch1
.endif
2021-11-06 00:44:04 +00:00
sta CH
pla
rts
;;; ==================================================
2021-11-06 03:24:49 +00:00
;; ???
2021-11-06 00:44:04 +00:00
sta CLRALTCHAR
Disable80Col:
sta CLR80COL
2021-11-06 00:44:04 +00:00
sta CLR80VID
rts
Enable80Col:
sta SET80COL
2021-11-06 00:44:04 +00:00
sta SET80VID
sta SETALTCHAR
rts
;;; ============================================================
2021-11-06 00:44:04 +00:00
LCBC7: lda MODE ; all mode bits set?
2021-11-10 02:17:23 +00:00
cmp #M_INACTIVE
2021-11-06 00:44:04 +00:00
beq LCBEA
2021-11-06 03:00:40 +00:00
and #M_ESC ; escape mode?
2021-11-06 00:44:04 +00:00
beq LCBEA
jsr LCEBE
sta OLDCH
and #$80
eor #$AB
bra LCBF9
2021-11-06 01:21:23 +00:00
LCBDE: lda MODE ; test high bit
2021-11-06 03:00:40 +00:00
and #M_ESC ; escape mode?
2021-11-06 00:44:04 +00:00
beq LCBEA
lda OLDCH
bra LCBF9
LCBEA: jsr LCEBE
eor #$80
2021-11-11 05:07:34 +00:00
;; If within "@ABC...XYZ[\]^_" range, map to $00-$1F
;; so it shows as inverse uppercase, not MouseText.
cmp #'@'
bcc :+
cmp #'_'+1
bcs :+
2021-11-06 00:44:04 +00:00
and #$1F
2021-11-11 05:07:34 +00:00
:
2021-11-06 00:44:04 +00:00
LCBF9: ldy CH
jmp LCECB
LCBFE: php
sei
lda WNDTOP
sta $05F8
LCC05: lda $05F8
2021-11-10 04:55:40 +00:00
jsr SetCV
2021-11-06 00:44:04 +00:00
lda BASL
sta BAS2L
lda BASH
sta BAS2H
ldy #$00
LCC15: bit TXTPAGE1
lda (BAS2L)
bit TXTPAGE2
sta (BASL),y
bit TXTPAGE1
inc BAS2L
lda (BAS2L)
sta (BASL),y
iny
inc BAS2L
cpy #$14
bcc LCC15
lda #$A0
LCC31: bit TXTPAGE2
sta (BASL),y
bit TXTPAGE1
sta (BASL),y
iny
cpy #$28
bcc LCC31
inc $05F8
lda $05F8 ; vertical position
cmp #24
bcc LCC05
LCC4A: plp
2021-11-10 04:55:40 +00:00
jmp RestoreCHCV
2021-11-06 00:44:04 +00:00
LCC4E: php
sei
sta SET80COL
lda WNDTOP
sta $05F8
LCC58: lda $05F8
2021-11-10 04:55:40 +00:00
jsr SetCV
2021-11-06 00:44:04 +00:00
ldy #$13
bit TXTPAGE1
LCC63: lda (BASL),y
pha
dey
bpl LCC63
ldy #$00
lda BASL
sta BAS2L
lda BASH
sta BAS2H
LCC73: bit TXTPAGE2
lda (BASL),y
bit TXTPAGE1
sta (BAS2L)
inc BAS2L
pla
sta (BAS2L)
inc BAS2L
iny
cpy #$14
bcc LCC73
inc $05F8 ; vertical position
lda $05F8
cmp #24
bcc LCC58
sta CLR80COL
bra LCC4A
2021-11-06 03:24:49 +00:00
;;; ============================================================
;;; XFER
DoXfer:
2021-11-06 00:44:04 +00:00
pha
2021-11-06 03:24:49 +00:00
lda XFERVEC
pha
lda XFERVEC+1
2021-11-06 00:44:04 +00:00
pha
sta RDMAINRAM
sta WRMAINRAM
2021-11-06 03:24:49 +00:00
bcc :+
2021-11-06 00:44:04 +00:00
sta RDCARDRAM
sta WRCARDRAM
2021-11-06 03:24:49 +00:00
: pla
sta XFERVEC+1
2021-11-06 00:44:04 +00:00
pla
2021-11-06 03:24:49 +00:00
sta XFERVEC
2021-11-06 00:44:04 +00:00
pla
sta ALTZPOFF
2021-11-06 03:24:49 +00:00
bvc :+
2021-11-06 00:44:04 +00:00
sta ALTZPON
2021-11-06 03:24:49 +00:00
: jmp (XFERVEC)
;;; ============================================================
2021-11-06 00:44:04 +00:00
2021-11-06 03:24:49 +00:00
DoAuxMove:
pha
2021-11-06 00:44:04 +00:00
bit RDRAMRD
php
bit RDRAMWRT
php
sta WRMAINRAM
sta RDCARDRAM
bcc LCCDA
sta RDMAINRAM
sta WRCARDRAM
2021-11-06 01:21:23 +00:00
LCCDA: lda (A1L)
sta (A4L)
inc A4L
2021-11-06 00:44:04 +00:00
bne LCCE4
2021-11-06 01:21:23 +00:00
inc A4H
LCCE4: lda A1L
cmp A2L
lda A1H
sbc A2H
inc A1L
2021-11-06 00:44:04 +00:00
bne LCCF2
2021-11-06 01:21:23 +00:00
inc A1H
2021-11-06 00:44:04 +00:00
LCCF2: bcc LCCDA
sta WRCARDRAM
plp
bmi LCCFD
sta WRMAINRAM
LCCFD: sta RDCARDRAM
plp
bmi LCD06
sta RDMAINRAM
LCD06: pla
sec
rts
2021-11-06 22:15:30 +00:00
;;; ============================================================
;;; Unknown Monitor ROM Routine
2021-11-06 22:15:30 +00:00
2021-11-10 04:55:40 +00:00
UnknownEP4:
bit $0579
bmi @l3
@l1: bit KBD
bmi @l2
2021-11-06 00:44:04 +00:00
clc
rts
@l2: sec
2021-11-06 00:44:04 +00:00
rts
@l3: jsr LCDB3
beq @l5
@l4: stz $0579
bra @l1
2021-11-06 00:44:04 +00:00
@l5: phx
2021-11-23 18:40:21 +00:00
ldx FKEYPTR
jsr ReadAuxRAM
2021-11-06 00:44:04 +00:00
lda $0200,x
2021-11-23 18:40:21 +00:00
jsr ReadPreviousRAM
2021-11-06 00:44:04 +00:00
plx
cmp #$00
beq @l4
bra @l2
;;; ============================================================
2021-11-23 18:40:21 +00:00
;;; Handle special keys (F1-12, RUN, LIST, etc)
2021-11-06 00:44:04 +00:00
2021-11-23 18:40:21 +00:00
HandleSpecialKeys:
2021-11-10 04:55:40 +00:00
bit $0579
bmi @l11
2021-11-06 00:44:04 +00:00
lda KBD
bit KBDSTRB
2021-11-23 18:40:21 +00:00
bit $C027 ; high bit clear for special keys
bpl @l3
@l1: cmp #$06
bcc @l2
2021-11-06 00:44:04 +00:00
ora #$80
@l2: rts
2021-11-06 00:44:04 +00:00
2021-11-23 18:40:21 +00:00
;; Deal with special keys
@l3: and #$7F
2021-11-23 18:40:21 +00:00
cmp #$01 ; CLRL
bne @l4
2021-11-06 00:44:04 +00:00
lda #$1A
bra @l1
2021-11-06 00:44:04 +00:00
2021-11-23 18:40:21 +00:00
@l4: cmp #$03 ; CLRS
bne @l5
2021-11-06 00:44:04 +00:00
lda #$0C
bra @l1
2021-11-06 00:44:04 +00:00
2021-11-23 18:40:21 +00:00
@l5: cmp #$04 ; HOME
bne @l6
2021-11-06 00:44:04 +00:00
lda #$19
bra @l1
2021-11-06 00:44:04 +00:00
2021-11-23 18:40:21 +00:00
;; "Macro" keys
@l6: cmp #$06 ; RUN
bne @l7
2021-11-23 18:40:21 +00:00
lda #$2C ; Like F13
bra @l9
2021-11-06 00:44:04 +00:00
2021-11-23 18:40:21 +00:00
@l7: cmp #$1F ; LIST
bne @l8
2021-11-23 18:40:21 +00:00
lda #$2D ; Like F14
bra @l9
2021-11-06 00:44:04 +00:00
2021-11-23 18:40:21 +00:00
@l8: cmp #$20 ; F1
bcc @l1
2021-11-23 18:40:21 +00:00
cmp #$2C ; F12+1
bcs @l1
2021-11-23 18:40:21 +00:00
@l9: pha ; Handle Fkeys
2021-11-06 00:44:04 +00:00
jsr LCDB3
beq @l10
2021-11-06 00:44:04 +00:00
pla
bra @l1
2021-11-06 00:44:04 +00:00
@l10: lda #$FF
2021-11-06 00:44:04 +00:00
sta $0579
pla
2021-11-23 18:40:21 +00:00
jsr FindFKEYDefnOffset
@l11: jsr LCDB3
beq @l13
@l12: stz $0579
2021-11-06 00:44:04 +00:00
lda #$A0
bra @l1
2021-11-06 00:44:04 +00:00
@l13: phx
2021-11-23 18:40:21 +00:00
ldx FKEYPTR
jsr ReadAuxRAM
2021-11-06 00:44:04 +00:00
lda $0200,x
2021-11-23 18:40:21 +00:00
jsr ReadPreviousRAM
2021-11-06 00:44:04 +00:00
plx
2021-11-23 18:40:21 +00:00
inc FKEYPTR
2021-11-06 00:44:04 +00:00
cmp #$00
beq @l12
bra @l1
;;; ============================================================
2021-11-06 00:44:04 +00:00
2021-11-23 18:40:21 +00:00
LCDB3: jsr ReadAuxRAM
2021-11-06 00:44:04 +00:00
lda #$00
phx
tax
clc
@l1: adc $0200,x
2021-11-06 00:44:04 +00:00
inx
bne @l1
2021-11-06 00:44:04 +00:00
plx
2021-11-23 18:40:21 +00:00
jsr ReadPreviousRAM
2021-11-06 00:44:04 +00:00
cmp $04F9
rts
2021-11-10 04:55:40 +00:00
;;; ============================================================
2021-11-23 18:40:21 +00:00
;;; Given FKEY in A ($20...$2D), get definition offset
;;; (from Aux $200) into FKEYPTR
2021-11-10 04:55:40 +00:00
2021-11-23 18:40:21 +00:00
FindFKEYDefnOffset:
phx
2021-11-06 00:44:04 +00:00
phy
2021-11-23 18:40:21 +00:00
jsr ReadAuxRAM
2021-11-06 00:44:04 +00:00
sec
2021-11-23 18:40:21 +00:00
sbc #$20 ; Map F1 to $00, etc
2021-11-06 00:44:04 +00:00
ldy #$00
tax
2021-11-23 18:40:21 +00:00
beq @l3
@l1: lda $0200,y
beq @l2
2021-11-06 00:44:04 +00:00
iny
2021-11-23 18:40:21 +00:00
bra @l1
2021-11-06 00:44:04 +00:00
2021-11-23 18:40:21 +00:00
@l2: iny
dex
bne @l1
@l3: jsr ReadPreviousRAM
sty FKEYPTR
2021-11-06 00:44:04 +00:00
ply
plx
rts
2021-11-07 20:52:15 +00:00
;;; ============================================================
2021-11-23 18:40:21 +00:00
;;; Initialize FKEY definitions
2021-11-07 20:52:15 +00:00
2021-11-23 18:40:21 +00:00
;;; Copied to Aux $200 by `InitFKEYDefinitions`
SpecialStrings:
2021-11-07 20:52:15 +00:00
.byte "RUN\r", 0
.byte "LIST\r", 0
.byte $ff
2021-11-06 00:44:04 +00:00
2021-11-23 18:40:21 +00:00
InitFKEYDefinitions:
2021-11-10 04:55:40 +00:00
sta WRCARDRAM
2021-11-06 00:44:04 +00:00
lda #$00
tax
2021-11-23 18:40:21 +00:00
;; F1...F12 are initially 0 length, so 12 $00 bytes
2021-11-10 04:55:40 +00:00
@l1: sta $0200,x
2021-11-06 00:44:04 +00:00
inx
2021-11-23 18:40:21 +00:00
cpx #12
2021-11-10 04:55:40 +00:00
bcc @l1
2021-11-23 18:40:21 +00:00
;; RUN and LIST are like F13 and F14, so they're next.
@l2: lda SpecialStrings - 12,x
2021-11-06 00:44:04 +00:00
cmp #$FF
2021-11-10 04:55:40 +00:00
beq @l3
2021-11-06 00:44:04 +00:00
sta $0200,x
inx
2021-11-10 04:55:40 +00:00
bra @l2
2021-11-06 00:44:04 +00:00
2021-11-10 04:55:40 +00:00
@l3: sta WRMAINRAM
2021-11-06 00:44:04 +00:00
stz $0579
2021-11-27 02:58:21 +00:00
;; fall through
2021-11-10 04:55:40 +00:00
;;; ============================================================
;;; Unknown Monitor ROM Routine
2021-11-10 04:55:40 +00:00
UnknownEP2:
jsr LCDB3
2021-11-06 00:44:04 +00:00
sta $04F9
rts
2021-11-10 04:55:40 +00:00
;;; ============================================================
2021-11-23 18:40:21 +00:00
;;; Read from Aux (saving previous state)
ReadAuxRAM:
pha
2021-11-06 00:44:04 +00:00
lda RDRAMRD
sta RDMAINRAM
sta $07F8
sta RDCARDRAM
pla
rts
2021-11-23 18:40:21 +00:00
;;; Restore previous read bank state
ReadPreviousRAM:
pha
2021-11-06 00:44:04 +00:00
sta RDMAINRAM
lda $07F8
2021-11-10 04:55:40 +00:00
bpl @l1
2021-11-06 00:44:04 +00:00
sta RDCARDRAM
2021-11-10 04:55:40 +00:00
@l1: pla
2021-11-06 00:44:04 +00:00
rts
2021-11-06 03:00:40 +00:00
;;; ============================================================
DoSETWND:
lda #0 ; set cursor to row 0
bit RDTEXT ; unless graphics mode
bmi :+
lda #20 ; then use row 20
: LDXY SETWND
bra ROMCall
;;; ============================================================
DoSETKBD:
LDXY SETKBD
bra ROMCall
;;; ============================================================
2021-11-06 00:44:04 +00:00
2021-11-06 03:00:40 +00:00
DoSETVID:
LDXY SETVID
bra ROMCall
2021-11-06 00:44:04 +00:00
2021-11-06 03:00:40 +00:00
;;; ============================================================
2021-11-06 00:44:04 +00:00
2021-11-06 03:00:40 +00:00
DoMON_VTAB:
LDXY MON_VTAB
bra ROMCall
2021-11-06 00:44:04 +00:00
2021-11-06 03:00:40 +00:00
;;; ============================================================
2021-11-06 00:44:04 +00:00
DoClearEOS:
LDXY CLREOP
2021-11-06 03:00:40 +00:00
bra ROMCall
;;; ============================================================
2021-11-06 00:44:04 +00:00
DoHomeAndClear:
LDXY HOME
2021-11-06 03:00:40 +00:00
bra ROMCall
;;; ============================================================
2021-11-06 00:44:04 +00:00
DoClearEOL:
LDXY CLREOL
2021-11-07 20:52:15 +00:00
;; fall through
2021-11-06 00:44:04 +00:00
2021-11-06 03:00:40 +00:00
;;; ============================================================
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;;; A = character, X,Y = ROM address-1 (return value to push to stack)
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ROMCall:
sta TEMP2
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bit RDLCRAM
php
bit RDLCBNK2
php
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lda #.hibyte(ROMCallReturn-1)
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pha
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lda #.lobyte(ROMCallReturn-1)
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pha
phx
phy
bit ROMIN2
lda TEMP2
rts
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ROMCallReturn:
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plp
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bpl @l2
plp
bpl @l1
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bit LCBANK2
bit LCBANK2
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bra @l4
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@l1: bit ROMIN
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bit ROMIN
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bra @l4
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@l2: plp
bpl @l3
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bit LCBANK1
bit LCBANK1
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bra @l4
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@l3: bit $C089 ; ???
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bit $C089 ; ???
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@l4: lda BASL
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sta OLDBASL
lda BASH
sta OLDBASH
lda CH
sta OURCH
rts
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;;; ============================================================
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LCEBE: ldy CH
LCEC0: phy
jsr LCED5
lda (BASL),y
LCEC6: ply
bit TXTPAGE1
rts
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;;; ============================================================
LCECB:
phy
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pha
jsr LCED5
pla
sta (BASL),y
bra LCEC6
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;;; ============================================================
LCED5:
bit RD80VID
bpl @l1
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tya
lsr a
tay
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bcc @l2
@l1: bit TXTPAGE1
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rts
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@l2: bit TXTPAGE2
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rts
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;;; ============================================================
;;; ???
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UnknownEP1:
bit RD80COL
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php
sta CLR80COL
bit RDRAMRD
php
bit RDRAMWRT
php
phx
plx
beq @l1
jmp @l13
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@l1: bcc @l5
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sta RDMAINRAM
sta WRCARDRAM
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lda A4L
ldx A4H
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sta ALTZPON
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sta A4L
stx A4H
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sta ALTZPOFF
@l2: lda (A1L)
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sta ALTZPON
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sta (A4L)
inc A4L
bne @l3
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inc A4H
@l3: sta ALTZPOFF
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lda A1L
cmp A2L
lda A1H
sbc A2H
inc A1L
bne @l4
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inc A1H
@l4: bcc @l2
bra @l9
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@l5: sta RDCARDRAM
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sta WRMAINRAM
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lda A1L
ldx A1H
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sta ALTZPON
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sta A1L
stx A1H
@l6: sta ALTZPON
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lda (A1L)
ldx A1L
ldy A1H
inc A1L
bne @l7
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inc A1H
@l7: sta ALTZPOFF
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sta (A4L)
inc A4L
bne @l8
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inc A4H
@l8: cpx A2L
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tya
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sbc A2H
bcc @l6
@l9: sta ALTZPOFF
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sta WRCARDRAM
plp
bmi @l10
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sta WRMAINRAM
@l10: sta RDCARDRAM
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plp
bmi @l11
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sta RDMAINRAM
@l11: plp
bpl @l12
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sta SET80COL
@l12: rts
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@l13: bcc @l14
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sta RDMAINRAM
sta WRCARDRAM
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lda A4L
ldy A4H
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sta ALTZPON
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sta A4L
sty A4H
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sta ALTZPOFF
ldy #$00
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: lda (A1L),y
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sta ALTZPON
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sta (A4L),y
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sta ALTZPOFF
iny
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bne :-
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inc A1H
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sta ALTZPON
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inc A4H
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sta ALTZPOFF
dex
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bne :-
bra @l15
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@l14: sta RDCARDRAM
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sta WRMAINRAM
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lda A1L
ldy A1H
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sta ALTZPON
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sta A1L
sty A1H
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ldy #$00
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: sta ALTZPON
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lda (A1L),y
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sta ALTZPOFF
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sta (A4L),y
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iny
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bne :-
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inc A4H
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sta ALTZPON
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inc A1H
sta ALTZPOFF
dex
bne :-
@l15: jmp @l9
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;;; ============================================================
.assert * = $CFE7, error, "Something changed size"
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;;; ============================================================
.if INCLUDE_PATCHES
Patch1:
lda CH
cmp XCOORD
bne :+
lda OURCH
: rts
Patch2:
sty OURCH
sty XCOORD
rts
Patch3:
stx OURCH
stx XCOORD
rts
.endif
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;;; ============================================================
.res $D000 - *, 0
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;;; ============================================================
.assert * = $D000, error, "Length changed"