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Oops, 34 ticks is the "neutral" position, not 36. Update duty cycles
during slow path. This removes the slight buzz audible during periods of silence.
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@ -437,10 +437,10 @@ recv: ; 15 cycles so far
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; pad cycles to keep ticking on 36/37 cycle cadence
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; TODO: what can we do with the luxury of 14 unused cycles?!
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@2: ; 30 so far
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STA TICK ; 4 ; 34
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; X will usually already be 0 from op_ack except during first frame when reading
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; header but reset it unconditionally
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LDX #$00 ; 2
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STA TICK ; 4 ; 36
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NOP ; 2
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STA dummy ; 4
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@ -453,7 +453,7 @@ op_nop:
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LDY WDATA ; 4
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STY @D+1 ; 4
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@D:
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JMP op_nop ; 3 ; 23 with following tick (37 in fallthrough case)
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JMP op_nop ; 3 ; 23 with following tick (39 if we fell through from checkrecv case)
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; Build macros for "fat" opcodes that do the following:
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; - tick twice, N cycles apart (N = 4 .. 66 in steps of 2)
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@ -1312,16 +1312,18 @@ op_ack:
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LDA #>S0RXRD ; 2
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STA WADRH ; 4
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LDX #<S0RXRD ; 2
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STX WADRL ; 4
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; prepare for ADC below, but reordered to allow TICK at offset 34
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CLC ; 2
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STA TICK ; 4 (36)
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STA TICK ; 4 (34)
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STX WADRL ; 4
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LDA WDATA ; 4 Read high byte
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; No need to read low byte since it's guaranteed to be 0 since we're at the end of a 2K frame.
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; Update new Received Read pointer
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; We have received an additional 2KB
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CLC ; 2
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ADC #$08 ; 2
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STX WADRL ; 4 Reset address pointer, X still has #<S0RXRD
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@ -1339,7 +1341,7 @@ op_ack:
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; - used as the low byte for resetting the W5100 address pointer when we're ready to start processing more data
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LDX #$00 ; 2 restore invariant for dispatch loop
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JMP checkrecv ; 3 (37 with following STA TICK)
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JMP checkrecv ; 3 (39 with following STA TICK)
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; Quit to ProDOS
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exit:
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