mirror of
https://github.com/KrisKennaway/ii-vision.git
synced 2025-02-28 10:29:35 +00:00
Minor cleanups:
- Use a safe ZP address instead of $00 - Use dec instead of hex for IP address bytes - Remove some unused Uthernet/W5100 defines Optimize the socket buffer management - Since we're guaranteeing 2K frame padding, the low byte is always 0 - Remove some vestiges of the Uthernet TCP demo code - AFAICT there isn't a need to compare high and low bytes of the S0RXRSR, this was just being used as a (slightly risky) check that they were both not equal (presumably to 0) - (h/t Oliver Schmidt <ol.sc@web.de>) it turns out that the W5100 automatically wraps the address pointer at the end of the 8k RX/TX buffer space, so since we're using 8k buffers we don't need any of the pointer/mask arithmetic to make sure we don't stray outside this range - Instead, we can just save the W5100 address pointer before we start doing the stream buffer management and restore it when we're ready to read from the stream again. - Moreover, since we know the low-byte is 0 we don't even need to save it. This gives us enough free cycles to implement a keypress check. For now any key will pause the video and any other key resume it. We still have a whole 16 cycles left over while maintaining the 36/37 cycle tick cadence. We've saved 73 cycles of "dead time" though, i.e. the op_ack + CHECKRECV + op_nop "slow path" now takes 2*73 rather than 3*73 cycles. This should result in better audio quality.
This commit is contained in:
kris
parent
10fa4bc72d
commit
fa6c2bb25d
184
player/main.s
184
player/main.s
@ -33,8 +33,8 @@
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.segment "HGR"
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; TODO: make these configurable
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SRCADDR: .byte $C0,$A8,$01,147 ; 192.168.1.147 W5100 IP
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FADDR: .byte $C0,$A8,$01,15 ; 192.168.1.15 FOREIGN IP
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SRCADDR: .byte 192,168,1,147 ; 192.168.1.147 W5100 IP
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FADDR: .byte 192,168,1,15 ; 192.168.1.15 FOREIGN IP
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FPORT: .byte $07,$b9 ; 1977 FOREIGN PORT
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MAC: .byte $00,$08,$DC,$01,$02,$03 ; W5100 MAC ADDRESS
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@ -52,7 +52,7 @@ WDATA = $C097
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;;;
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; some dummy addresses in order to pad cycle counts
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zpdummy = $00
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zpdummy = $08
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dummy = $ffff
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hgr = $f3e2
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@ -70,16 +70,10 @@ RMSR = $001A ; RECEIVE BUFFER SIZE
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; SOCKET 0 LOCATIONS
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S0MR = $0400 ; SOCKET 0 MODE REGISTER
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S0CR = $0401 ; COMMAND REGISTER
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S0IR = $0402 ; INTERRUPT REGISTER
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S0SR = $0403 ; STATUS REGISTER
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S0LOCALPORT = $0404 ; LOCAL PORT
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S0FORADDR = $040C ; FOREIGN ADDRESS
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S0FORPORT = $0410 ; FOREIGN PORT
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S0MSS = $0412 ; MAX SEGMENT SIZE
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S0PROTO = $0414 ; IP PROTOCOL
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S0TOS = $0415 ; DS/ECN (FORMER TOS)
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S0TTL = $0416 ; IP TIME TO LIVE
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S0TXFSR = $0420 ; TX FREE SIZE REGISTER
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S0TXRR = $0422 ; TX READ POINTER REGISTER
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S0TXWR = $0424 ; TX WRITE POINTER REGISTER
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S0RXRSR = $0426 ; RX RECEIVED SIZE REGISTER
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@ -93,25 +87,14 @@ TXMASK = RXMASK ; SOCKET 0 TX MASK
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; SOCKET COMMANDS
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SCOPEN = $01 ; OPEN
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SCLISTEN = $02 ; LISTEN
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SCCONNECT = $04 ; CONNECT
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SCDISCON = $08 ; DISCONNECT
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SCCLOSE = $10 ; CLOSE
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SCSEND = $20 ; SEND
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SCSENDMAC = $21 ; SEND MAC
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SCSENDKEEP = $22 ; SEND KEEP ALIVE
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SCRECV = $40 ; RECV
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; SOCKET STATUS
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STCLOSED = $00
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STINIT = $13
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STLISTEN = $14
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STESTABLISHED = $17
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STCLOSEWAIT = $1C
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STUDP = $22
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STIPRAW = $32
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STMAXRAW = $42
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STPPOE = $5F
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; MONITOR SUBROUTINES
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KBD = $C000
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@ -122,9 +105,6 @@ PRNTAX = $F941
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; ZERO-PAGE STORAGE
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PTR = $06 ; TODO: we only use this for connection retry count
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GETSIZE = $08 ; 2 BYTES FOR RX_RSR
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GETOFFSET = $0A ; 2 BYTES FOR OFFSET ADDR
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GETSTARTADR = $0C ; 2 BYTES FOR PHYSICAL ADDR
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; this is the main binary entrypoint (it will be linked at 0x800)
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.segment "LOWCODE"
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@ -284,6 +264,9 @@ ERRMSG: .byte $d3,$cf,$c3,$cb,$c5,$d4,$a0,$c3,$cf,$d5,$cc,$c4,$a0,$ce,$cf,$d4,$a
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.byte $8D,$00
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SETUP:
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; TODO: Read header from video
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JMP init_mainloop
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.segment "CODE"
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@ -321,7 +304,8 @@ init_mainloop:
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STA $C054 ; MAIN memory active
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; establish invariant expected by decode loop
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; establish invariants expected by decode loop
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LDY #>RXBASE ; High byte of socket 0 receive buffer
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LDX #$00
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; This is the main audio/video decode loop.
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@ -348,96 +332,76 @@ init_mainloop:
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; Somewhat magically, the cycle timings all align on multiples of 73 (with tick intervals
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; alternating 36 and 37 cycles, as in the "neutral" (i.e. 50% speaker duty cycle)
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; op_tick_36_* opcodes), without much work needed to optimize this. I'm pretty sure there's
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; still "unnecessary" work being done (e.g. low address bytes that are always 0) but there's
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; need to work harder since we'd end up having to pad them back anyway.
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; op_tick_36_* opcodes), without much work needed to optimize this.
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;
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; With a 73 cycle fundamental opcode (speaker) period and 1MHz clock speed, this gives a
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; 14364 Hz "carrier" for the audio DAC, which is slightly audible (at least to my ageing
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; ears) but quite acceptable.
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;
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; i.e. we get about 14364 player opcodes/second, with the ACK "slow path" costing 6 opcodes.
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; Each of the "fat" audio/video opcodes results in storing 4 video bytes, so we store
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; about 56KB of video data per second.
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; i.e. we get about 14364 player opcodes/second, with the op_ack + CHECKRECV + op_nop
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; "slow path" costing 2 opcodes. Each of the "fat" audio/video opcodes results in storing
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4 video bytes, so we store about 56KB of video data per second.
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;
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; With 192x40 = 7680 visible bytes on the hires screen, this means we can do about 7.5 full
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; page redraws/sec; but the effective frame rate will usually be much higher than this
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; since we only prioritize the parts of the screen that are changing between frames.
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; Check for any received data
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; Wait until we have enough received data, and
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;
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; Notice that this has the only conditional opcodes in the entire decode loop ;-)
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;
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; Calling invariants:
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; X = 0
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; Y register has the high byte of the W5100 address pointer in the RX socket code, so we
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; can't trash this until we are ready to point back there.
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CHECKRECV:
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BIT tick ; 4
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LDA #<S0RXRSR ; 2 S0 RECEIVED SIZE REGISTER
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LDA #<S0RXRSR ; 2 Socket 0 Received Size register
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STA WADRL ; 4
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LDA WDATA ; 4 HIGH BYTE OF RECEIVED SIZE
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ORA WDATA ; 4 LOW BYTE
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BNE RECV ; 2 THERE IS DATA
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LDA WDATA ; 4 High byte of received size
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CMP #$08 ; 2 expect at least 2k
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; TODO: check this doesn't cross a page bdy or it will add a cycle
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BCS RECV ; 3 There is data...we don't care exactly how much because it's at least 2K
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; Not sure whether this delay is needed?
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; TODO: Not sure whether this delay is needed?
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NOP ; Little delay ...
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NOP
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JMP CHECKRECV ; Check again
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; THERE IS DATA TO READ - COMPUTE THE PHYSICAL ADDRESS
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RECV:
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LDA #<S0RXRSR ; 2 GET RECEIVED SIZE AGAIN
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STA WADRL ; 4
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LDA WDATA ; 4
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; There is data to read - restore W5100 address pointer where we last found it
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;
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; It turns out that the W5100 automatically wraps the address pointer at the end of the 8K RX/TX buffers
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; Since we're using an 8K socket, that means we don't have to do any work to manage the read pointer!
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RECV: ; 15 cycles so far
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; expect at least 2k more data present. The decoder does not do any implicit management
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; of the TCP socket buffer, unless instructed to by the video byte stream. This
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; opcode is scheduled every 2k bytes, so we'd better not fall off the end of the stream.
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CMP #$08 ; 2 expect at least 2k
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bcs @L ; 3 branch should mostly be taken, pads out the next tick to 36 cycles
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BCC CHECKRECV ; not yet
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; point W5100 back into the RX buffer where we left off in op_ack
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STY WADRH ; 4
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STX WADRL ; 4 X=0 here from op_ack
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@L:
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BIT tick ; 4 (36 cycles)
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; Check for keypress and pause the video
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@0: BIT KBD ; 4
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; TODO: check this doesn't cross a page bdy or it will add a cycle
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BPL @2 ; 3 nope
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STA GETSIZE+1 ; 4
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LDA WDATA ; 4
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STA GETSIZE ; 4 low byte (this should be 0 i.e. we could optimize this away, but we dont need to bother because the cycle timings work out anyway)
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; Wait for second keypress to resume
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BIT KBDSTRB ; clear strobe
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@1: BIT KBD
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BPL @1
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BIT KBDSTRB ; clear strobe
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; reset address pointer to socket buffer
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; CALCULATE OFFSET ADDRESS USING READ POINTER AND RX MASK
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LDA #<S0RXRD ; 2
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STA WADRL ; 4
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; fall through - tick timings don't matter
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LDA WDATA ; 4 HIGH BYTE
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AND #>RXMASK ; 2
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STA GETOFFSET+1,X ; 5 - using X=0 to get an extra cycle before next tick
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LDA WDATA ; 4 LOW BYTE
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; pad cycles to keep ticking on 36/37 cycle cadence
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; TODO: what can we do with the luxury of 16 unused cycles?!
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@2: ; 30 so far
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NOP ; 2
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BIT tick ; 4 ; 36
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BIT tick ; 4 (37 cycles)
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AND #<RXMASK ; 2
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STA GETOFFSET ; 4
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; CALCULATE PHYSICAL ADDRESS WITHIN W5100 RX BUFFER
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CLC ; 2
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LDA GETOFFSET ; 4
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ADC #<RXBASE ; 2
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STA GETSTARTADR ; 4
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LDA GETOFFSET+1 ; 4
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ADC #>RXBASE ; 2
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STA GETSTARTADR+1 ; 4
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; SET BUFFER ADDRESS ON W5100
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LDA GETSTARTADR+1 ; 4 HIGH BYTE FIRST
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BIT tick ; 4 (36)
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STA WADRH ;4
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LDA GETSTARTADR ; 4
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STA WADRL ; 4
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; ensure invariant expected by inner loop
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; it's probably already fine, but we have 2 cycles to spare anyway ;)
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LDX #$00 ; 2
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; fall through to op_nop
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NOP ; 2
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STA dummy ; 4
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STA dummy ; 4
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STA dummy ; 4
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op_nop:
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LDY WDATA ; 4
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@ -445,7 +409,7 @@ op_nop:
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LDY WDATA ; 4
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STY @D+1 ; 4
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@D:
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JMP op_nop ; 3 ; 37 with following tick
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JMP op_nop ; 3 ; 23 with following tick (37 in fallthrough case)
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; Build macros for "fat" opcodes that do the following:
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; - tick twice, N cycles apart (N = 4 .. 66 in steps of 2)
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@ -1283,9 +1247,6 @@ op_terminate:
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; In order to simplify the buffer management we expect this ACK opcode to consume
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; the last 4 bytes in a 2K "TCP frame". i.e. we can assume that we need to consume
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; exactly 2K from the W5100 socket buffer.
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;
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; TODO: actually we are underrunning by 2 bytes currently, we've only consumed 2
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; bytes of 4 by this point.
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op_ack:
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BIT tick ; 4
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@ -1294,33 +1255,44 @@ op_ack:
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LDA WDATA ; 4
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STA @D+1 ; 4
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@D:
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STA $C054 ; 4 low-byte is modified
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STA $C0FF ; 4 low-byte is modified
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LDA WDATA ; 4 dummy read of last byte in TCP frame
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CLC ; 2
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LDA #>S0RXRD ; 2 NEED HIGH BYTE HERE
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; Save the W5100 address pointer so we can come back here later
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; We know the low-order byte is 0 because Socket RX memory is page-aligned and so is 2K frame.
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; IMPORTANT - from now on until we restore this in RECV, we can't trash the Y register!
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LDY WADRH ; 4
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; Read Received Read pointer
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LDA #>S0RXRD ; 2
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STA WADRH ; 4
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LDX #<S0RXRD ; 2
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STX WADRL ; 4
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NOP ; 2
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BIT tick ; 4 (36) ; does not affect Carry bit
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BIT tick ; 4 (36)
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; No need to read/modify low byte since it is always guaranteed to be 0 (since we are at the end of a 2K frame)
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LDA WDATA ; 4 HIGH BYTE
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LDA WDATA ; 4 Read high byte
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; No need to read low byte since it's guaranteed to be 0 since we're at the end of a 2K frame.
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ADC #$08 ; 2 Add high byte of received size (always constant
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STX WADRL ; 4 Reset address pointer, still have it in X
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STA WDATA ; 4 Store high byte (no need to store low byte since it's 0)
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; Update new Received Read pointer
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; We have received an additional 2KB
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CLC ; 2
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ADC #$08 ; 2
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; SEND THE RECV COMMAND
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STX WADRL ; 4 Reset address pointer, X still has #<S0RXRD
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STA WDATA ; 4 Store high byte
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; No need to store low byte since it's unchanged at 0
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; Send the Receive command
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LDA #<S0CR ; 2
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STA WADRL ; 4
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LDA #SCRECV ; 2
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STA WDATA ; 4
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NOP ; 2 ; see, we even have cycles left over!
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NOP ; 2
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; This will do double-duty:
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; - restoring the invariant expected by the op_tick opcodes
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; - used as the low byte for resetting the W5100 address pointer when we're ready to start processing more data
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LDX #$00 ; 2 restore invariant for dispatch loop
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JMP CHECKRECV ; 3 (37 with following BIT tick)
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