ii-vision

Commit Graph

Author	SHA1	Message	Date
kris	80402f25a5	- Allow HGR ROM entry point - Don't trap unexpected entrypoint when crossing between regions via RTS - Implement TICK handler - Improve status printing in CPU loop	2019-02-27 22:46:53 +00:00
kris	90f696b8e4	Bare-bones py65-based simulator for Apple //e with Uthernet (i.e. simulating the W5100). This will hopefully be useful for troubleshooting and testing player behaviour more precisely, e.g. - trapping read/write access to unexpected memory areas - asserting invariants on the processor state across loops - measuring cycle timing - tracing program execution This already gets as far as negotiating the TCP connect. The major remaining piece seems to be the TCP buffer management on the W5100 side.	2019-02-27 22:26:35 +00:00

Author

SHA1

Message

Date

kris

80402f25a5

- Allow HGR ROM entry point

- Don't trap unexpected entrypoint when crossing between regions via RTS
- Implement TICK handler
- Improve status printing in CPU loop

2019-02-27 22:46:53 +00:00

kris

90f696b8e4

Bare-bones py65-based simulator for Apple //e with Uthernet (i.e.

simulating the W5100).  This will hopefully be useful for
troubleshooting and testing player behaviour more precisely, e.g.

- trapping read/write access to unexpected memory areas
- asserting invariants on the processor state across loops
- measuring cycle timing
- tracing program execution

This already gets as far as negotiating the TCP connect.  The major
remaining piece seems to be the TCP buffer management on the W5100 side.

2019-02-27 22:26:35 +00:00

2 Commits