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BCD portion of CPU test
This commit is contained in:
Brendan Robert
parent
048e1b1769
commit
7b78521920
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@ -244,7 +244,7 @@ public class Full65C02Test {
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@Test
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/* Full test of ADC and SBC with binary coded decimal mode */
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public void testBCD() throws ProgramException, URISyntaxException, IOException {
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Path resource = Paths.get(getClass().getResource("/jace/bcd_test.a").toURI());
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Path resource = Paths.get(getClass().getResource("/jace/bcd_test.asm").toURI());
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String testCode = Files.readString(resource);
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TestProgram test = new TestProgram(testCode);
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test.defineError("Error when performing ADC operation");
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301
Platform/Apple/tools/jace/src/test/resources/jace/bcd_test.asm
Normal file
301
Platform/Apple/tools/jace/src/test/resources/jace/bcd_test.asm
Normal file
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@ -0,0 +1,301 @@
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; Modified and adapted from http://www.6502.org/tutorials/decimal_mode.html#B
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;
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; Verify decimal mode behavior
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; Written by Bruce Clark. This code is public domain.
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;
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; Returns:
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; ERROR = 0 if the test passed
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; ERROR = 1 if the test failed
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;
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; This routine requires 17 bytes of RAM -- 1 byte each for:
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; AR, CF, DA, DNVZC, ERROR, HA, HNVZC, N1, N1H, N1L, N2, N2L, NF, VF, and ZF
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; and 2 bytes for N2H
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;
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; Variables:
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; N1 and N2 are the two numbers to be added or subtracted
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; N1H, N1L, N2H, and N2L are the upper 4 bits and lower 4 bits of N1 and N2
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; DA and DNVZC are the actual accumulator and flag results in decimal mode
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; HA and HNVZC are the accumulator and flag results when N1 and N2 are
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; added or subtracted using binary arithmetic
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; AR, NF, VF, ZF, and CF are the predicted decimal mode accumulator and
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; flag results, calculated using binary arithmetic
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;
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; This program takes approximately 1 minute at 1 MHz (a few seconds more on
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; a 65C02 than a 6502 or 65816)
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;
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AR = $06
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NF = $07
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VF = $08
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CF = $09
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ZF = $0a
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DA = $0b
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DNVZC = $0c
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HA = $0d
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HNVZC = $0e
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N1 = $0f
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N1H = $10
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N1L = $11
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N2 = $12
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N2H = $13
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N2L = $15
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TEST ;LDY #1 ; initialize Y (used to loop through carry flag values)
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;STY ERROR ; store 1 in ERROR until the test passes
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LDA #0 ; initialize N1 and N2
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STA N1
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STA N2
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LOOP1 LDA N2 ; N2L = N2 & $0F
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AND #$0F ; [1] see text
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STA N2L
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LDA N2 ; N2H = N2 & $F0
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AND #$F0 ; [2] see text
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STA N2H
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ORA #$0F ; N2H+1 = (N2 & $F0) + $0F
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STA N2H+1
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LOOP2 LDA N1 ; N1L = N1 & $0F
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AND #$0F ; [3] see text
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STA N1L
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LDA N1 ; N1H = N1 & $F0
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AND #$F0 ; [4] see text
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STA N1H
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JSR ADD
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JSR A65C02
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JSR COMPARE
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BNE ADD_ERROR
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JSR SUB
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JSR S65C02
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JSR COMPARE
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BNE SUB_ERROR
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INC N1 ; [5] see text
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BNE LOOP2 ; loop through all 256 values of N1
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INC N2 ; [6] see text
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BNE LOOP1 ; loop through all 256 values of N2
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DEY
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BPL LOOP1 ; loop through both values of the carry flag
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SUCCESS +success
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ADD_ERROR
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CPY #1 ; Set carry based on Y reg
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LDA DA
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LDX N1
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LDY N2
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+throwError 0
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SUB_ERROR
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CPY #1 ; Set carry based on Y reg
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LDA DA
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LDX N1
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LDY N2
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+throwError 1
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; Calculate the actual decimal mode accumulator and flags, the accumulator
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; and flag results when N1 is added to N2 using binary arithmetic, the
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; predicted accumulator result, the predicted carry flag, and the predicted
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; V flag
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;
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ADD SED ; decimal mode
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CPY #1 ; set carry if Y = 1, clear carry if Y = 0
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LDA N1
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ADC N2
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STA DA ; actual accumulator result in decimal mode
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PHP
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PLA
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STA DNVZC ; actual flags result in decimal mode
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CLD ; binary mode
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CPY #1 ; set carry if Y = 1, clear carry if Y = 0
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LDA N1
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ADC N2
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STA HA ; accumulator result of N1+N2 using binary arithmetic
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PHP
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PLA
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STA HNVZC ; flags result of N1+N2 using binary arithmetic
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CPY #1
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LDA N1L
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ADC N2L
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CMP #$0A
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LDX #0
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BCC A1
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INX
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ADC #5 ; add 6 (carry is set)
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AND #$0F
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SEC
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A1 ORA N1H
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;
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; if N1L + N2L < $0A, then add N2 & $F0
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; if N1L + N2L >= $0A, then add (N2 & $F0) + $0F + 1 (carry is set)
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;
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ADC N2H,X
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PHP
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BCS A2
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CMP #$A0
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BCC A3
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A2 ADC #$5F ; add $60 (carry is set)
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SEC
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A3 STA AR ; predicted accumulator result
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PHP
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PLA
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STA CF ; predicted carry result
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PLA
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;
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; note that all 8 bits of the P register are stored in VF
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;
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STA VF ; predicted V flags
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RTS
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; Calculate the actual decimal mode accumulator and flags, and the
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; accumulator and flag results when N2 is subtracted from N1 using binary
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; arithmetic
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;
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SUB SED ; decimal mode
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CPY #1 ; set carry if Y = 1, clear carry if Y = 0
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LDA N1
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SBC N2
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STA DA ; actual accumulator result in decimal mode
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PHP
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PLA
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STA DNVZC ; actual flags result in decimal mode
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CLD ; binary mode
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CPY #1 ; set carry if Y = 1, clear carry if Y = 0
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LDA N1
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SBC N2
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STA HA ; accumulator result of N1-N2 using binary arithmetic
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PHP
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PLA
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STA HNVZC ; flags result of N1-N2 using binary arithmetic
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RTS
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; Calculate the predicted SBC accumulator result for the 6502 and 65816
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;
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SUB1 CPY #1 ; set carry if Y = 1, clear carry if Y = 0
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LDA N1L
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SBC N2L
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LDX #0
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BCS S11
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INX
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SBC #5 ; subtract 6 (carry is clear)
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AND #$0F
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CLC
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S11 ORA N1H
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;
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; if N1L - N2L >= 0, then subtract N2 & $F0
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; if N1L - N2L < 0, then subtract (N2 & $F0) + $0F + 1 (carry is clear)
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;
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SBC N2H,X
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BCS S12
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SBC #$5F ; subtract $60 (carry is clear)
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S12 STA AR
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RTS
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; Calculate the predicted SBC accumulator result for the 6502 and 65C02
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;
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SUB2 CPY #1 ; set carry if Y = 1, clear carry if Y = 0
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LDA N1L
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SBC N2L
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LDX #0
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BCS S21
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INX
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AND #$0F
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CLC
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S21 ORA N1H
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;
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; if N1L - N2L >= 0, then subtract N2 & $F0
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; if N1L - N2L < 0, then subtract (N2 & $F0) + $0F + 1 (carry is clear)
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;
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SBC N2H,X
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BCS S22
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SBC #$5F ; subtract $60 (carry is clear)
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S22 CPX #0
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BEQ S23
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SBC #6
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S23 STA AR ; predicted accumulator result
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RTS
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; Compare accumulator actual results to predicted results
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;
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; Return:
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; Z flag = 1 (BEQ branch) if same
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; Z flag = 0 (BNE branch) if different
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;
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COMPARE LDA DA
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CMP AR
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+breakpoint 1
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BNE C1
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LDA DNVZC ; [7] see text
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EOR NF
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AND #$80 ; mask off N flag
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+breakpoint 2
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BNE C1
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LDA DNVZC ; [8] see text
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EOR VF
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AND #$40 ; mask off V flag
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+breakpoint 3
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BNE C1 ; [9] see text
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LDA DNVZC
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EOR ZF ; mask off Z flag
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AND #2
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+breakpoint 4
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BNE C1 ; [10] see text
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LDA DNVZC
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EOR CF
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AND #1 ; mask off C flag
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+breakpoint 5
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C1 RTS
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; These routines store the predicted values for ADC and SBC for the 6502,
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; 65C02, and 65816 in AR, CF, NF, VF, and ZF
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A6502 LDA VF
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;
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; since all 8 bits of the P register were stored in VF, bit 7 of VF contains
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; the N flag for NF
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;
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STA NF
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LDA HNVZC
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STA ZF
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RTS
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S6502 JSR SUB1
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LDA HNVZC
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STA NF
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STA VF
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STA ZF
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STA CF
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RTS
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A65C02 LDA AR
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PHP
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PLA
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STA NF
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STA ZF
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RTS
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S65C02 JSR SUB2
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LDA AR
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PHP
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PLA
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STA NF
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STA ZF
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LDA HNVZC
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STA VF
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STA CF
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RTS
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A65816 LDA AR
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PHP
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PLA
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STA NF
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STA ZF
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RTS
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S65816 JSR SUB1
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LDA AR
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PHP
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PLA
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STA NF
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STA ZF
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LDA HNVZC
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STA VF
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STA CF
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RTS
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