From 73059bfd931944822cbfda31a79fe88b41264123 Mon Sep 17 00:00:00 2001 From: Michel Pollet Date: Sat, 28 Oct 2023 06:23:02 +0100 Subject: [PATCH] sw: Added a big soft switch bitfield These are fetched often, so might as well cache them into a bitfield, also removed the old BSR state, as it might as well be in that bitfield. Converted all the user of these soft switches to this new bitfield. Signed-off-by: Michel Pollet --- src/mii.c | 74 ++++++++++++++++++++++++------------------- src/mii.h | 5 +-- src/mii_sw.h | 83 ++++++++++++++++++++++++++++++++++++++++++++----- src/mii_video.c | 29 ++++++++++------- 4 files changed, 135 insertions(+), 56 deletions(-) diff --git a/src/mii.c b/src/mii.c index 43e142c..cb55909 100644 --- a/src/mii.c +++ b/src/mii.c @@ -157,18 +157,19 @@ mii_page_table_update( if (!mii->mem_dirty) return; mii->mem_dirty = 0; - int altzp = mii_sw(mii, SWALTPZ); - int page2 = mii_sw(mii, SWPAGE2); - int store80 = mii_sw(mii, SW80STORE); - int hires = mii_sw(mii, SWHIRES); - int ramrd = mii_sw(mii, SWRAMRD); - int ramwrt = mii_sw(mii, SWRAMWRT); - int intcxrom = mii_sw(mii, SWINTCXROM); - int slotc3rom = mii_sw(mii, SWSLOTC3ROM); + bool altzp = SW_GETSTATE(mii, SWALTPZ); + bool page2 = SW_GETSTATE(mii, SWPAGE2); + bool store80 = SW_GETSTATE(mii, SW80STORE); + bool hires = SW_GETSTATE(mii, SWHIRES); + bool ramrd = SW_GETSTATE(mii, SWRAMRD); + bool ramwrt = SW_GETSTATE(mii, SWRAMWRT); + bool intcxrom = SW_GETSTATE(mii, SWINTCXROM); + bool slotc3rom = SW_GETSTATE(mii, SWSLOTC3ROM); if (mii->trace_cpu) - printf("%04x: page table update altzp:%02x page2:%02x store80:%02x hires:%02x ramrd:%02x ramwrt:%02x intcxrom:%02x slotc3rom:%02x\n", - mii->cpu.PC, + printf("%04x: page table update altzp:%d page2:%d store80:%d " + "hires:%d ramrd:%d ramwrt:%d intcxrom:%d " + "slotc3rom:%d\n", mii->cpu.PC, altzp, page2, store80, hires, ramrd, ramwrt, intcxrom, slotc3rom); // clean slate mii_page_set(mii, MII_BANK_MAIN, MII_BANK_MAIN, 0x00, 0xc0); @@ -191,23 +192,26 @@ mii_page_table_update( mii_page_set(mii, MII_BANK_CARD_ROM, _SAME, 0xc1, 0xc7); mii_page_set(mii, slotc3rom ? MII_BANK_CARD_ROM : MII_BANK_ROM, _SAME, 0xc3, 0xc3); + bool bsrread = SW_GETSTATE(mii, BSRREAD); + bool bsrwrite = SW_GETSTATE(mii, BSRWRITE); + bool bsrpage2 = SW_GETSTATE(mii, BSRPAGE2); mii_page_set(mii, - mii->bsr_mode.read ? - altzp ? MII_BANK_AUX_BSR : MII_BANK_BSR : - MII_BANK_ROM, - mii->bsr_mode.write ? - altzp ? MII_BANK_AUX_BSR : MII_BANK_BSR : - MII_BANK_ROM, + bsrread ? + altzp ? MII_BANK_AUX_BSR : MII_BANK_BSR : + MII_BANK_ROM, + bsrwrite ? + altzp ? MII_BANK_AUX_BSR : MII_BANK_BSR : + MII_BANK_ROM, 0xd0, 0xff); // BSR P2 mii_page_set(mii, - mii->bsr_mode.read ? - (altzp ? MII_BANK_AUX_BSR : MII_BANK_BSR) + - mii->bsr_mode.page2 : MII_BANK_ROM, - mii->bsr_mode.write ? - (altzp ? MII_BANK_AUX_BSR : MII_BANK_BSR) + - mii->bsr_mode.page2 : MII_BANK_ROM, - 0xd0, 0xdf); + bsrread ? + (altzp ? MII_BANK_AUX_BSR : MII_BANK_BSR) + bsrpage2 : + MII_BANK_ROM, + bsrwrite ? + (altzp ? MII_BANK_AUX_BSR : MII_BANK_BSR) + bsrpage2 : + MII_BANK_ROM, + 0xd0, 0xdf); } void @@ -272,9 +276,9 @@ mii_access_soft_switches( static const int read_modes[4] = { 1, 0, 0, 1, }; uint8_t rd = read_modes[mode & 3]; uint8_t wr = write_modes[mode & 3]; - mii->bsr_mode.write = wr; - mii->bsr_mode.read = rd; - mii->bsr_mode.page2 = mode & 0x08 ? 0 : 1; + SW_SETSTATE(mii, BSRWRITE, wr); + SW_SETSTATE(mii, BSRREAD, rd); + SW_SETSTATE(mii, BSRPAGE2, !(mode & 0x08)); mii->mem_dirty = 1; if (mii->trace_cpu) printf("%04x: BSR mode addr %04x:%02x read:%s write:%s %s altzp:%02x\n", @@ -282,7 +286,7 @@ mii_access_soft_switches( mode, rd ? "BSR" : "ROM", wr ? "BSR" : "ROM", - mii->bsr_mode.page2 ? "page2" : "page1", + SW_GETSTATE(mii, BSRPAGE2) ? "page2" : "page1", mii_sw(mii, SWALTPZ)); } break; case 0xcfff: @@ -293,12 +297,14 @@ mii_access_soft_switches( case SWPAGE2OFF: case SWPAGE2ON: res = true; + SW_SETSTATE(mii, SWPAGE2, addr & 1); mii_bank_poke(main, SWPAGE2, (addr & 1) << 7); mii->mem_dirty = 1; break; case SWHIRESOFF: case SWHIRESON: res = true; + SW_SETSTATE(mii, SWHIRES, addr & 1); mii_bank_poke(main, SWHIRES, (addr & 1) << 7); mii->mem_dirty = 1; // printf("HIRES %s\n", (addr & 1) ? "ON" : "OFF"); @@ -319,36 +325,42 @@ mii_access_soft_switches( case SW80STOREOFF: case SW80STOREON: res = true; + SW_SETSTATE(mii, SW80STORE, addr & 1); mii_bank_poke(main, SW80STORE, (addr & 1) << 7); mii->mem_dirty = 1; break; case SWRAMRDOFF: case SWRAMRDON: res = true; + SW_SETSTATE(mii, SWRAMRD, addr & 1); mii_bank_poke(main, SWRAMRD, (addr & 1) << 7); mii->mem_dirty = 1; break; case SWRAMWRTOFF: case SWRAMWRTON: res = true; + SW_SETSTATE(mii, SWRAMWRT, addr & 1); mii_bank_poke(main, SWRAMWRT, (addr & 1) << 7); mii->mem_dirty = 1; break; case SWALTPZOFF: case SWALTPZON: res = true; + SW_SETSTATE(mii, SWALTPZ, addr & 1); mii_bank_poke(main, SWALTPZ, (addr & 1) << 7); mii->mem_dirty = 1; break; case SWINTCXROMOFF: case SWINTCXROMON: res = true; + SW_SETSTATE(mii, SWINTCXROM, addr & 1); mii_bank_poke(main, SWINTCXROM, (addr & 1) << 7); mii->mem_dirty = 1; break; case SWSLOTC3ROMOFF: case SWSLOTC3ROMON: res = true; + SW_SETSTATE(mii, SWSLOTC3ROM, addr & 1); mii_bank_poke(main, SWSLOTC3ROM, (addr & 1) << 7); mii->mem_dirty = 1; break; @@ -356,11 +368,11 @@ mii_access_soft_switches( } else { switch (addr) { case SWBSRBANK2: - *byte = mii->bsr_mode.page2 ? 0x80 : 0; + *byte = SW_GETSTATE(mii, BSRPAGE2) ? 0x80 : 0; res = true; break; case SWBSRREADRAM: - *byte = mii->bsr_mode.read ? 0x80 : 0; + *byte = SW_GETSTATE(mii, BSRREAD) ? 0x80 : 0; res = true; break; case SWRAMRD: @@ -514,10 +526,8 @@ mii_reset( { // printf("%s cold %d\n", __func__, cold); mii->cpu_state.reset = 1; - mii->bsr_mode.write = 1; - mii->bsr_mode.read = 0; - mii->bsr_mode.page2 = 1; mii_bank_t * main = &mii->bank[MII_BANK_MAIN]; + mii->sw_state = M_BSRWRITE | M_BSRPAGE2; mii_bank_poke(main, SWSLOTC3ROM, 0); mii_bank_poke(main, SWRAMRD, 0); mii_bank_poke(main, SWRAMWRT, 0); diff --git a/src/mii.h b/src/mii.h index b403a05..9efb3e8 100644 --- a/src/mii.h +++ b/src/mii.h @@ -92,10 +92,7 @@ typedef struct mii_t { uint8_t read : 4, write : 4; } mem[256]; int mem_dirty; // recalculate mem[] on next access - struct { - int write, read, page2; - } bsr_mode; - + uint32_t sw_state; // B_SW* bitfield mii_trace_t trace; int trace_cpu; mii_trap_t trap; diff --git a/src/mii_sw.h b/src/mii_sw.h index 88efa76..e69591e 100644 --- a/src/mii_sw.h +++ b/src/mii_sw.h @@ -3,20 +3,19 @@ #pragma once enum { - SW80STOREOFF = 0xc000, - SW80STOREON = 0xc001, - SWALTCHARSETOFF = 0xc00e, - SWALTCHARSETON = 0xc00f, - SW80STORE = 0xc018, SWVBL = 0xc019, + SWALTCHARSET = 0xc01e, SW80COL = 0xc01f, SWTEXT = 0xc01a, SWMIXED = 0xc01b, SWPAGE2 = 0xc01c, SWHIRES = 0xc01d, - SWALTCHARSET = 0xc01e, + SW80STOREOFF = 0xc000, + SW80STOREON = 0xc001, + SWALTCHARSETOFF = 0xc00e, + SWALTCHARSETON = 0xc00f, SW80COLOFF = 0xc00c, SW80COLON = 0xc00d, SWTEXTOFF = 0xc050, // (AKA LORES ON) @@ -29,8 +28,8 @@ enum { SWHIRESON = 0xc057, // this one is inverted, the ON is the even address - SWDHIRESOFF = 0xc05f, // AN3_ON - SWDHIRESON = 0xc05e, // AN3_OFF + SWDHIRESOFF = 0xc05f, // AN3_ON + SWDHIRESON = 0xc05e, // AN3_OFF SWAN3 = 0xc05e, // AN3 status SWAN3_REGISTER = 0xc05f, // AN3 register for video mode SWRDDHIRES = 0xc07f, @@ -47,13 +46,81 @@ enum { SWSLOTC3ROMON = 0xc00b, SWBSRBANK2 = 0xc011, SWBSRREADRAM = 0xc012, + SWRAMRD = 0xc013, SWRAMWRT = 0xc014, SWINTCXROM = 0xc015, SWALTPZ = 0xc016, SWSLOTC3ROM = 0xc017, + SWSPEAKER = 0xc030, SWKBD = 0xc000, SWAKD = 0xc010, }; + +enum { + B_SW80STORE = ( 0), +// B_SWVBL = ( 1), + B_SWALTCHARSET = ( 2), + B_SW80COL = ( 3), + B_SWTEXT = ( 4), + B_SWMIXED = ( 5), + B_SWPAGE2 = ( 6), + B_SWHIRES = ( 7), + B_SWRAMRD = ( 8), + B_SWRAMWRT = ( 9), + B_SWINTCXROM = (10), + B_SWALTPZ = (11), + B_SWSLOTC3ROM = (12), + B_BSRWRITE = (13), + B_BSRREAD = (14), + B_BSRPAGE2 = (15), + B_SWDHIRES = (16), + + M_SW80STORE = (1 << B_SW80STORE), +// M_SWVBL = (1 << B_SWVBL), + M_SWALTCHARSET = (1 << B_SWALTCHARSET), + M_SW80COL = (1 << B_SW80COL), + M_SWTEXT = (1 << B_SWTEXT), + M_SWMIXED = (1 << B_SWMIXED), + M_SWPAGE2 = (1 << B_SWPAGE2), + M_SWHIRES = (1 << B_SWHIRES), + M_SWRAMRD = (1 << B_SWRAMRD), + M_SWRAMWRT = (1 << B_SWRAMWRT), + M_SWINTCXROM = (1 << B_SWINTCXROM), + M_SWALTPZ = (1 << B_SWALTPZ), + M_SWSLOTC3ROM = (1 << B_SWSLOTC3ROM), + M_BSRWRITE = (1 << B_BSRWRITE), + M_BSRREAD = (1 << B_BSRREAD), + M_BSRPAGE2 = (1 << B_BSRPAGE2), + M_SWDHIRES = (1 << B_SWDHIRES), +}; + +// unused is to prevent the stupid warnings about unused static stuff +static const char __attribute__((unused)) *mii_sw_names[] = { + "80STORE", + "VBL", + "ALTCHARSET", + "80COL", + "TEXT", + "MIXED", + "PAGE2", + "HIRES", + "RAMRD", + "RAMWRT", + "INTCXROM", + "ALTPZ", + "SLOTC3ROM", + "BSRWRITE", + "BSRREAD", + "BSRPAGE2", + "DHIRES", + NULL, +} ; + +#define SW_SETSTATE(_mii, _sw, _state) \ + (_mii)->sw_state = ((_mii)->sw_state & ~(M_##_sw)) | \ + (!!(_state) << B_##_sw) +#define SW_GETSTATE(_mii, _sw) \ + (!!((_mii)->sw_state & M_##_sw)) diff --git a/src/mii_video.c b/src/mii_video.c index 08fc07a..1e59b10 100644 --- a/src/mii_video.c +++ b/src/mii_video.c @@ -146,13 +146,13 @@ mii_video_run( mii->video.wait = mii->cycles - mii->video.wait; } mii_bank_t * main = &mii->bank[MII_BANK_MAIN]; - bool text = !!mii_bank_peek(main, SWTEXT); - bool page2 = !!mii_bank_peek(main, SWPAGE2); - bool col80 = !!mii_bank_peek(main, SW80COL); - bool store80 = !!mii_bank_peek(main, SW80STORE); - bool mixed = !!mii_bank_peek(main, SWMIXED); - bool hires = !!mii_bank_peek(main, SWHIRES); - bool dhires = !!mii_bank_peek(main, SWRDDHIRES); + bool text = SW_GETSTATE(mii, SWTEXT); + bool page2 = SW_GETSTATE(mii, SWPAGE2); + bool col80 = SW_GETSTATE(mii, SW80COL); + bool store80 = SW_GETSTATE(mii, SW80STORE); + bool mixed = SW_GETSTATE(mii, SWMIXED); + bool hires = SW_GETSTATE(mii, SWHIRES); + bool dhires = SW_GETSTATE(mii, SWDHIRES); pt_start(mii->video.state); /* @@ -164,7 +164,6 @@ mii_video_run( mii_bank_poke(main, SWVBL, 0x80); if (mixed && !text) { text = mii->video.line >= 192 - (4 * 8); - hires = 0; } // http://www.1000bit.it/support/manuali/apple/technotes/aiie/tn.aiie.03.html if (hires && !text && col80 && dhires) { @@ -362,6 +361,7 @@ mii_access_video( case SWALTCHARSETON: if (!write) break; res = true; + SW_SETSTATE(mii, SWALTCHARSET, addr & 1); mii_bank_poke(main, SWALTCHARSET, (addr & 1) << 7); break; case SWVBL: @@ -380,8 +380,8 @@ mii_access_video( case SW80COLON: if (!write) break; res = true; + SW_SETSTATE(mii, SW80COL, addr & 1); mii_bank_poke(main, SW80COL, (addr & 1) << 7); -// printf("80COL %s\n", on ? "ON" : "OFF"); break; case SWDHIRESOFF: // 0xc05f, case SWDHIRESON: { // = 0xc05e, @@ -392,22 +392,27 @@ mii_access_video( if (an3_on && !an3) { uint8_t bit = !!mii_bank_peek(main, SW80COL); reg = ((reg << 1) | bit) & 3; - printf("VIDEO 80:%d REG now %x\n", bit, reg); + // printf("VIDEO 80:%d REG now %x\n", bit, reg); mii_bank_poke(main, SWAN3_REGISTER, reg); } mii_bank_poke(main, SWAN3, an3_on); - printf("DHRES IS %s mode:%d\n", - (addr & 1) ? "OFF" : "ON", reg); + // printf("DHRES IS %s mode:%d\n", + // (addr & 1) ? "OFF" : "ON", reg); + mii->sw_state = (mii->sw_state & ~M_SWDHIRES) | + (!(addr & 1) << B_SWDHIRES); + SW_SETSTATE(mii, SWDHIRES, !(addr & 1)); mii_bank_poke(main, SWRDDHIRES, (!(addr & 1)) << 7); } break; case SWTEXTOFF: case SWTEXTON: res = true; + SW_SETSTATE(mii, SWTEXT, addr & 1); mii_bank_poke(main, SWTEXT, (addr & 1) << 7); break; case SWMIXEDOFF: case SWMIXEDON: res = true; + SW_SETSTATE(mii, SWMIXED, addr & 1); mii_bank_poke(main, SWMIXED, (addr & 1) << 7); break; }