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cpu: Sprinkled a few cycles

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Missing cycles were a problem for timing critical disk read/writes

Signed-off-by: Michel Pollet <buserror@gmail.com>
This commit is contained in:
Michel Pollet 2024-02-12 16:55:37 +00:00
parent ad86adfea4
commit f9b604c5ba
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1 changed files with 2 additions and 1 deletions
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src/mii_65c02.c
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@ -380,6 +380,7 @@ next_instruction:
} break; } break;
case 0x4A: case 0x4A:
{ // LSR { // LSR
_FETCH(cpu->PC);
cpu->P.C = !!(cpu->A & 0x01); cpu->P.C = !!(cpu->A & 0x01);
cpu->A >>= 1; cpu->A >>= 1;
_NZ(cpu->A); _NZ(cpu->A);
@ -534,7 +535,7 @@ next_instruction:
case 0x85: case 0x95: case 0x8D: case 0x9D: case 0x85: case 0x95: case 0x8D: case 0x9D:
case 0x99: case 0x81: case 0x91: case 0x92: case 0x99: case 0x81: case 0x91: case 0x92:
{ // STA { // STA
cpu->_D = cpu->A; cpu->_D = cpu->A;cpu->cycle++;
} break; } break;
case 0x86: case 0x96: case 0x8E: case 0x86: case 0x96: case 0x8E:
{ // STX { // STX