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cpu: Sprinkled a few cycles
Missing cycles were a problem for timing critical disk read/writes Signed-off-by: Michel Pollet <buserror@gmail.com>
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@ -380,6 +380,7 @@ next_instruction:
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} break;
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case 0x4A:
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{ // LSR
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_FETCH(cpu->PC);
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cpu->P.C = !!(cpu->A & 0x01);
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cpu->A >>= 1;
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_NZ(cpu->A);
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@ -534,7 +535,7 @@ next_instruction:
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case 0x85: case 0x95: case 0x8D: case 0x9D:
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case 0x99: case 0x81: case 0x91: case 0x92:
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{ // STA
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cpu->_D = cpu->A;
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cpu->_D = cpu->A;cpu->cycle++;
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} break;
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case 0x86: case 0x96: case 0x8E:
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{ // STX
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