commit 4a622fed310d897e5b9ab7f2de3818fb8a0a3034 Author: Renee Harke Date: Sun Nov 29 15:53:51 2020 -0500 Initial commit, add code from Digital Prism diff --git a/appleii/digital_prism/README.md b/appleii/digital_prism/README.md new file mode 100644 index 0000000..bc45526 --- /dev/null +++ b/appleii/digital_prism/README.md @@ -0,0 +1,9 @@ +# Applied Engineering Digital Prism + +These are reverse-engineered dumps of the two PALs on Applied Engineering's family of RGB piggyback cards for the RamWorks. + +The AERGB PAL is present on the original RGB Card as well as the Digital Prism and the Color Link. + +The AEDP PAL is present on the Digital Prism and the Color Link. + +The originals are PAL16L8 chips, but I have successfully replaced them with ATF16V8B chips using this code, and functionality appears identical. diff --git a/appleii/digital_prism/aedp.jed b/appleii/digital_prism/aedp.jed new file mode 100644 index 0000000..ef1227b --- /dev/null +++ b/appleii/digital_prism/aedp.jed @@ -0,0 +1,55 @@ + +CUPL(WM) 5.0a Serial# 60008009 +Device g16v8ma Library DLIB-h-40-8 +Created Sun Nov 29 15:49:14 2020 +Name aedp +Partno aedp +Revision 01 +Date 11/29/2020 +Designer Renee Harke +Company None +Assembly None +Location None +*QP20 +*QF2194 +*G0 +*F0 +*L00000 11111111111111111111111111111111 +*L00032 10111011111111111111111111111111 +*L00064 10111111111110111111111111111111 +*L00096 10111111111111111111101111111111 +*L00128 10111111011111111111111111111111 +*L00160 11111011101110111111011111111111 +*L00256 11111111111111111111111111111111 +*L00288 10111111101111111111111111111111 +*L00320 10110111111101111111011111111111 +*L00352 11111111101111111111101111111111 +*L00384 11111111101101111111111111111111 +*L00416 11110111101111111111111111111111 +*L00512 11111111111111111111111111111111 +*L00544 10111111111110111111111111111111 +*L00576 10110111101111111111011111111111 +*L00608 11111111111110111111101111111111 +*L00640 11110111111110111111111111111111 +*L00672 11111111011110111111111111111111 +*L00768 11111111111111111111111111111111 +*L00800 11111011101111111111111111111111 +*L00832 11111011111110111111111111111111 +*L00864 11111011111111111111101111111111 +*L00896 01111011111111111111111111111111 +*L00928 01111111101110111111011111111111 +*L01280 11111111111111111111111111111111 +*L01312 11111111111111111011111111111011 +*L01344 11111111111111110111111111110111 +*L01536 11111111111111111111111111111111 +*L01568 11111111111111111011111111111111 +*L01792 11111111111111111111111111111111 +*L01824 11111111111111111110111111111011 +*L01856 11111111111111111101111111110111 +*L02048 00000000011000010110010101100100 +*L02080 01110000001000000000000000000000 +*L02112 00000000111111111111111111111111 +*L02144 11111111111111111111111111111111 +*L02176 111111111111111111 +*C8669 +*7044 \ No newline at end of file diff --git a/appleii/digital_prism/aedp.pld b/appleii/digital_prism/aedp.pld new file mode 100644 index 0000000..22537c1 --- /dev/null +++ b/appleii/digital_prism/aedp.pld @@ -0,0 +1,87 @@ +Name aedp ; +PartNo aedp ; +Date 11/29/2020 ; +Revision 01 ; +Designer Renee Harke ; +Company None ; +Assembly None ; +Location None ; +Device g16v8ma ; + + +/** + * This is one of two PALs from the Applied Engineering "Digital Prism" card, + * which is a piggyback card for the RamWorks series of cards for the Apple IIe. + * The card provides a digital RGB output compatible with the AppleColor Monitor + * 100, as well as a digital CGA output compatible with many PC monitors of the + * era. + * + * This same PAL is also present on the "Color Link" card, which might be + * considered a different revision of the same card, replacing the digital RGB + * output with an analog RGB output compatible with the AppleColor RGB Monitor + * from the Apple IIGS. + * + * The other PAL on this card is shared with the "RGB Card" and the "Color + * Link". + * + * The function of the PAL is not changed between the cards. It is responsible + * for mapping XRGB colors to CGA colors, and generating HSYNC/VSYNC. + * + * The PAL is generally (always?) labelled "AEDP Q" and is located near the + * top-right of the card. It is typically an MMI-branded PAL16L8. + * + * The VSYNC generator is worth calling out. Pin 13 and 15 are connected + * through a simple RC circuit which does two things: + * 1. Delay the sync signal by a few tens of microseconds. + * 2. Removes the HSYNC pulses, in principle generating one long pulse during + * VSYNC. + * + * I say "in principle" because if you watch the result on a scope, it fails + * to filter the first HSYNC pulse that occurs during VSYNC. Actually I've only + * tested this on the Color Link, but if you compare the Digital Prism and the + * Color Link, you'll note that the resistor is 3600 ohm on the Digital Prism, + * and 2200 ohm on the Color Link. I suspect that AE identified this problem + * and tried to fix it, but didn't fully succeed. + * + * Replacing the resistor with something around 1000 ohm seems to generate + * clean VSYNC. This seems more necessary if you replace the PAL16L8 with a + * ATF16V8, possibly due to different timing or other electrical properties. + * + * I claim no copyright on this code. + */ + + +/************* INPUT PINS **************/ +PIN 2 = XINTEN; /* XRGB intensity */ +PIN 3 = XBLUE; /* XRGB blue */ +PIN 4 = XRED; /* XRGB red */ +PIN 5 = XGREEN; /* XRGB green */ +PIN 6 = CSYNC; /* sync */ +PIN 7 = CLRMAP; /* sw3: color mapping */ +PIN 9 = INVSYN; /* sw4: invert sync */ +PIN 15 = SYNCB; /* RC buffered CSYNC */ + +/************* OUTPUT PINS *************/ +PIN 12 = VSYNC; /* vsync */ +PIN 13 = SYNCO; /* out to RC circuit */ +PIN 14 = HSYNC; /* hsync */ +PIN 16 = CBLUE; /* CGA blue */ +PIN 17 = CGREEN; /* CGA green */ +PIN 18 = CRED; /* CGA red */ +PIN 19 = CINTEN; /* CGA intensity */ + + +/* Use buffered CSYNC as VSYNC, inverted if switch is on */ +!VSYNC = (!INVSYN & !SYNCB) # (INVSYN & SYNCB); + +/* Send CSYNC to RC delay circuit */ +!SYNCO = (!CSYNC); + +/* Use CSYNC as HSYNC, inverted if switch is on */ +!HSYNC = (!CSYNC & !INVSYN) # (CSYNC & INVSYN); + +/* Map colors */ +!CBLUE = (!XBLUE & !XRED) # (!XBLUE & !XGREEN) # (!XBLUE & !CLRMAP) # (XINTEN & !XBLUE) # (XINTEN & !XRED & !XGREEN & CLRMAP); +!CGREEN = (!XINTEN & !XGREEN) # (!XINTEN & XBLUE & !XRED & CLRMAP) # (!XGREEN & !CLRMAP) # (XBLUE & !XGREEN) # (XRED & !XGREEN); +!CRED = (!XINTEN & !XRED) # (!XINTEN & XBLUE & XGREEN & CLRMAP) # (!XRED & !CLRMAP) # (!XRED & XGREEN) # (XBLUE & !XRED); +!CINTEN = (!XINTEN & !XBLUE) # (!XINTEN & !XGREEN) # (!XINTEN & !CLRMAP) # (!XINTEN & XRED) # (!XBLUE & !XRED & !XGREEN & CLRMAP); diff --git a/appleii/digital_prism/aergb.jed b/appleii/digital_prism/aergb.jed new file mode 100644 index 0000000..cff3f28 --- /dev/null +++ b/appleii/digital_prism/aergb.jed @@ -0,0 +1,63 @@ + +CUPL(WM) 5.0a Serial# 60008009 +Device g16v8ma Library DLIB-h-40-8 +Created Sat Nov 28 17:21:18 2020 +Name aergb +Partno aergb +Revision 01 +Date 11/28/2020 +Designer Renee Harke +Company None +Assembly None +Location None +*QP20 +*QF2194 +*G0 +*F0 +*L00000 11111111111111111111111111111111 +*L00032 11101111111111101111111110110110 +*L00064 11100111111111101111111111110110 +*L00096 11101111111111100111111110110111 +*L00128 11101101111111101111111111110111 +*L00160 10011111111111101111111111111011 +*L00192 10011110111111101111111111111111 +*L00224 11110101111111111111111111110111 +*L00512 11111111111111111111111111111111 +*L00544 10111110111111011011111111110111 +*L00576 10110111111111111111111110111011 +*L00608 10110111111111111111111111111010 +*L00640 01111110111111010111111111110111 +*L01024 11111111111111111111111111111111 +*L01056 11101111111111111111111111111011 +*L01088 11101110111111111111111111111110 +*L01120 11101101111111101111111111111111 +*L01152 11101110111111111111111101111111 +*L01184 11111111111111011111111111111011 +*L01216 11111110111111011111111111111111 +*L01280 11111111111111111111111111111111 +*L01312 11101111111101111111111111011111 +*L01344 10111111111111111111011111100111 +*L01376 11011110111111100111101111111111 +*L01408 01111111111111111111101111100111 +*L01440 11111101111101111111111111110111 +*L01472 11111111111111110111101111011011 +*L01504 11111111111111111111111101101011 +*L01536 11111111111111111111111111111111 +*L01568 11101111111111111111111111111011 +*L01600 11111111111111011111111111111011 +*L01632 11111110111111011111111111111111 +*L01792 11111111111111111111111111111111 +*L01824 11101110111111101111111111110111 +*L01856 10111010111111011111011111110111 +*L01888 10110110111111011111101111110111 +*L01920 11111101101111111111111111110111 +*L01952 11111111111111111111111111111001 +*L01984 01111010111111011111101111110111 +*L02016 01110110111111011111011111110111 +*L02048 00000000011000010110010101110010 +*L02080 01100111011000100010000000000000 +*L02112 00000000111111111111111111111111 +*L02144 11111111111111111111111111111111 +*L02176 111111111111111111 +*C958C +*AEF8 \ No newline at end of file diff --git a/appleii/digital_prism/aergb.pld b/appleii/digital_prism/aergb.pld new file mode 100644 index 0000000..3dd3c20 --- /dev/null +++ b/appleii/digital_prism/aergb.pld @@ -0,0 +1,81 @@ +Name aergb ; +PartNo aergb ; +Date 11/28/2020 ; +Revision 01 ; +Designer Renee Harke ; +Company None ; +Assembly None ; +Location None ; +Device g16v8ma ; + + +/** + * This is the PAL from the Applied Engineering "RGB Card", which is a piggyback + * card for the RamWorks series of cards for the Apple IIe. The card provides a + * digital RGB output compatible with the AppleColor Monitor 100. + * + * This same PAL (along with another one) is also present on the "Digital Prism" + * and "Color Link" cards, which might be considered as different revisions of + * the same base card. + * + * The function of the PAL is not changed between the cards. It is involved with + * converting the serial video signal from the logic board into an RGB output, + * though understanding its exact function would require more research. + * + * The PAL is generally (always?) labelled "AERGB Q" and is located near the + * bottom-left of the card. It is typically an MMI-branded PAL16L8. An ATF16V8 + * in complex mode can emulate the function of this PAL. + * + * Thanks to Robert Justice for putting me on to the idea that we have to + * express things in negative logic in order to fit the equations on the chip. + * + * I claim no copyright on this code. + */ + + +/****** INPUT PINS ******/ +PIN 1 = P1; /* 80VID */ +PIN 2 = P2; /* SEROUT */ +PIN 3 = P3; /* */ +PIN 4 = P4; /* */ +PIN 5 = P5; /* LDPS */ +PIN 6 = P6; /* */ +PIN 7 = P7; /* */ +PIN 8 = P8; /* */ +PIN 9 = P9; /* */ +PIN 11 = P11; /* */ +PIN 16 = P16; /* FRCTXT */ +PIN 18 = P18; /* SEGB */ + +/***** OUTPUT PINS ******/ +PIN 12 = P12; /* */ +PIN 13 = P13; /* */ +PIN 14 = P14; /* */ +PIN 15 = P15; /* */ +PIN 17 = P17; /* */ +PIN 19 = P19; /* */ + + +!P12 = (!P1 & P9 & !P16 & !P18) # (!P2 & !P3 & P7 & P9 & P16 & !P18) # (!P2 & P3 & !P7 & P9 & P16 & !P18) + # (!P4 & P9 & P18) # (!P9 & P11) # (P2 & !P3 & !P7 & P9 & P16 & !P18) # (P2 & P3 & P7 & P9 & P16 & !P18); + +!P13 = (!P1 & !P9) # (!P9 & P16) # (P16 & !P18); + +/** + * Feedback is necessary to express P14 in 7 product terms. + * + * You can confirm with a logic analyzer that the original PAL does this too; + * you can see P13 switch first, and then P14 lags one cycle behind. + * + * It's possible that P12 and/or P15 were involved in the original equation as + * well, but it's not necessary so they probably weren't. + */ +!P14 = (!P1 & P5 & P13) # (!P2 & P7 & P9 & !P13) # (P1 & P6 & !P7 & !P16 & !P18) # (P2 & !P7 & P9 & !P13) + # (P5 & P9 & P18) # (P6 & !P7 & !P9 & P13) # (P8 & !P9 & !P13); + +!P15 = (!P1 & !P9) # (!P1 & !P11 & !P18) # (!P1 & !P16 & P18) # (!P1 & P8 & !P18) # (!P9 & P16) # (P16 & !P18); + +!P17 = (!P2 & !P6 & P9 & P16 & !P18) # (!P2 & P3 & !P8 & !P9) # (!P2 & P3 & !P9 & !P11) # (P2 & P6 & P9 & P16 & !P18); + +!P19 = (!P1 & !P8 & P9 & !P11 & !P16) # (!P1 & P3 & P9 & !P11 & !P16) # (!P1 & P6 & !P8 & P9 & !P16) + # (!P1 & P9 & !P16 & P18) # (P1 & !P2 & !P9 & !P16) # (P1 & !P2 & !P16 & !P18) # (P3 & P9 & P18);