88 lines
3.6 KiB
Plaintext
88 lines
3.6 KiB
Plaintext
Name aedp ;
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PartNo aedp ;
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Date 11/29/2020 ;
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Revision 01 ;
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Designer Renee Harke ;
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Company None ;
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Assembly None ;
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Location None ;
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Device g16v8ma ;
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/**
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* This is one of two PALs from the Applied Engineering "Digital Prism" card,
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* which is a piggyback card for the RamWorks series of cards for the Apple IIe.
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* The card provides a digital RGB output compatible with the AppleColor Monitor
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* 100, as well as a digital CGA output compatible with many PC monitors of the
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* era.
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*
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* This same PAL is also present on the "Color Link" card, which might be
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* considered a different revision of the same card, replacing the digital RGB
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* output with an analog RGB output compatible with the AppleColor RGB Monitor
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* from the Apple IIGS.
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*
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* The other PAL on this card is shared with the "RGB Card" and the "Color
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* Link".
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*
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* The function of the PAL is not changed between the cards. It is responsible
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* for mapping XRGB colors to CGA colors, and generating HSYNC/VSYNC.
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*
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* The PAL is generally (always?) labelled "AEDP Q" and is located near the
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* top-right of the card. It is typically an MMI-branded PAL16L8.
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*
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* The VSYNC generator is worth calling out. Pin 13 and 15 are connected
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* through a simple RC circuit which does two things:
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* 1. Delay the sync signal by a few tens of microseconds.
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* 2. Removes the HSYNC pulses, in principle generating one long pulse during
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* VSYNC.
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*
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* I say "in principle" because if you watch the result on a scope, it fails
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* to filter the first HSYNC pulse that occurs during VSYNC. Actually I've only
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* tested this on the Color Link, but if you compare the Digital Prism and the
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* Color Link, you'll note that the resistor is 3600 ohm on the Digital Prism,
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* and 2200 ohm on the Color Link. I suspect that AE identified this problem
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* and tried to fix it, but didn't fully succeed.
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*
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* Replacing the resistor with something around 1000 ohm seems to generate
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* clean VSYNC. This seems more necessary if you replace the PAL16L8 with a
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* ATF16V8, possibly due to different timing or other electrical properties.
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*
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* I claim no copyright on this code.
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*/
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/************* INPUT PINS **************/
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PIN 2 = XINTEN; /* XRGB intensity */
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PIN 3 = XBLUE; /* XRGB blue */
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PIN 4 = XRED; /* XRGB red */
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PIN 5 = XGREEN; /* XRGB green */
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PIN 6 = CSYNC; /* sync */
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PIN 7 = CLRMAP; /* sw3: color mapping */
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PIN 9 = INVSYN; /* sw4: invert sync */
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PIN 15 = SYNCB; /* RC buffered CSYNC */
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/************* OUTPUT PINS *************/
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PIN 12 = VSYNC; /* vsync */
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PIN 13 = SYNCO; /* out to RC circuit */
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PIN 14 = HSYNC; /* hsync */
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PIN 16 = CBLUE; /* CGA blue */
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PIN 17 = CGREEN; /* CGA green */
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PIN 18 = CRED; /* CGA red */
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PIN 19 = CINTEN; /* CGA intensity */
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/* Use buffered CSYNC as VSYNC, inverted if switch is on */
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!VSYNC = (!INVSYN & !SYNCB) # (INVSYN & SYNCB);
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/* Send CSYNC to RC delay circuit */
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!SYNCO = (!CSYNC);
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/* Use CSYNC as HSYNC, inverted if switch is on */
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!HSYNC = (!CSYNC & !INVSYN) # (CSYNC & INVSYN);
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/* Map colors */
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!CBLUE = (!XBLUE & !XRED) # (!XBLUE & !XGREEN) # (!XBLUE & !CLRMAP) # (XINTEN & !XBLUE) # (XINTEN & !XRED & !XGREEN & CLRMAP);
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!CGREEN = (!XINTEN & !XGREEN) # (!XINTEN & XBLUE & !XRED & CLRMAP) # (!XGREEN & !CLRMAP) # (XBLUE & !XGREEN) # (XRED & !XGREEN);
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!CRED = (!XINTEN & !XRED) # (!XINTEN & XBLUE & XGREEN & CLRMAP) # (!XRED & !CLRMAP) # (!XRED & XGREEN) # (XBLUE & !XRED);
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!CINTEN = (!XINTEN & !XBLUE) # (!XINTEN & !XGREEN) # (!XINTEN & !CLRMAP) # (!XINTEN & XRED) # (!XBLUE & !XRED & !XGREEN & CLRMAP);
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