prog8/compiler/test/TestMemory.kt

177 lines
12 KiB
Kotlin
Raw Normal View History

2021-06-01 19:21:33 +00:00
package prog8tests
import io.kotest.core.spec.style.FunSpec
import io.kotest.matchers.shouldBe
2021-06-01 19:21:33 +00:00
import prog8.ast.Module
import prog8.ast.Program
import prog8.ast.base.DataType
import prog8.ast.base.Position
import prog8.ast.base.VarDeclType
2021-10-10 22:22:04 +00:00
import prog8.ast.expressions.ArrayIndexedExpression
import prog8.ast.expressions.IdentifierReference
import prog8.ast.expressions.NumericLiteralValue
import prog8.ast.expressions.PrefixExpression
2021-06-01 19:21:33 +00:00
import prog8.ast.statements.*
import prog8.compiler.target.C64Target
2021-10-29 03:28:02 +00:00
import prog8.compilerinterface.isInRegularRAMof
2021-10-13 16:55:56 +00:00
import prog8.parser.SourceCode
import prog8tests.helpers.DummyFunctions
import prog8tests.helpers.DummyMemsizer
2021-10-29 22:05:55 +00:00
import prog8tests.helpers.DummyStringEncoder
2021-06-01 19:21:33 +00:00
class TestMemory: FunSpec({
2021-10-10 22:22:04 +00:00
test("testInValidRamC64_memory_addresses") {
2021-06-01 19:21:33 +00:00
var memexpr = NumericLiteralValue.optimalInteger(0x0000, Position.DUMMY)
var target = AssignTarget(null, null, DirectMemoryWrite(memexpr, Position.DUMMY), Position.DUMMY)
target.isInRegularRAMof(C64Target.machine) shouldBe true
2021-06-01 19:21:33 +00:00
memexpr = NumericLiteralValue.optimalInteger(0x1000, Position.DUMMY)
target = AssignTarget(null, null, DirectMemoryWrite(memexpr, Position.DUMMY), Position.DUMMY)
target.isInRegularRAMof(C64Target.machine) shouldBe true
2021-06-01 19:21:33 +00:00
memexpr = NumericLiteralValue.optimalInteger(0x9fff, Position.DUMMY)
target = AssignTarget(null, null, DirectMemoryWrite(memexpr, Position.DUMMY), Position.DUMMY)
target.isInRegularRAMof(C64Target.machine) shouldBe true
2021-06-01 19:21:33 +00:00
memexpr = NumericLiteralValue.optimalInteger(0xc000, Position.DUMMY)
target = AssignTarget(null, null, DirectMemoryWrite(memexpr, Position.DUMMY), Position.DUMMY)
target.isInRegularRAMof(C64Target.machine) shouldBe true
2021-06-01 19:21:33 +00:00
memexpr = NumericLiteralValue.optimalInteger(0xcfff, Position.DUMMY)
target = AssignTarget(null, null, DirectMemoryWrite(memexpr, Position.DUMMY), Position.DUMMY)
target.isInRegularRAMof(C64Target.machine) shouldBe true
2021-06-01 19:21:33 +00:00
}
test("testNotInValidRamC64_memory_addresses") {
2021-06-01 19:21:33 +00:00
var memexpr = NumericLiteralValue.optimalInteger(0xa000, Position.DUMMY)
var target = AssignTarget(null, null, DirectMemoryWrite(memexpr, Position.DUMMY), Position.DUMMY)
target.isInRegularRAMof(C64Target.machine) shouldBe false
2021-06-01 19:21:33 +00:00
memexpr = NumericLiteralValue.optimalInteger(0xafff, Position.DUMMY)
target = AssignTarget(null, null, DirectMemoryWrite(memexpr, Position.DUMMY), Position.DUMMY)
target.isInRegularRAMof(C64Target.machine) shouldBe false
2021-06-01 19:21:33 +00:00
memexpr = NumericLiteralValue.optimalInteger(0xd000, Position.DUMMY)
target = AssignTarget(null, null, DirectMemoryWrite(memexpr, Position.DUMMY), Position.DUMMY)
target.isInRegularRAMof(C64Target.machine) shouldBe false
2021-06-01 19:21:33 +00:00
memexpr = NumericLiteralValue.optimalInteger(0xffff, Position.DUMMY)
target = AssignTarget(null, null, DirectMemoryWrite(memexpr, Position.DUMMY), Position.DUMMY)
target.isInRegularRAMof(C64Target.machine) shouldBe false
2021-06-01 19:21:33 +00:00
}
fun createTestProgramForMemoryRefViaVar(program: Program, address: Int, vartype: VarDeclType): AssignTarget {
2021-06-01 19:21:33 +00:00
val decl = VarDecl(vartype, DataType.BYTE, ZeropageWish.DONTCARE, null, "address", NumericLiteralValue.optimalInteger(address, Position.DUMMY), false, false, false, Position.DUMMY)
val memexpr = IdentifierReference(listOf("address"), Position.DUMMY)
val target = AssignTarget(null, null, DirectMemoryWrite(memexpr, Position.DUMMY), Position.DUMMY)
val assignment = Assignment(target, NumericLiteralValue.optimalInteger(0, Position.DUMMY), Position.DUMMY)
val subroutine = Subroutine("test", mutableListOf(), emptyList(), emptyList(), emptyList(), emptySet(), null, false, false, mutableListOf(decl, assignment), Position.DUMMY)
val module = Module(mutableListOf(subroutine), Position.DUMMY, SourceCode.Generated("test"))
module.linkIntoProgram(program)
2021-06-01 19:21:33 +00:00
return target
}
test("testInValidRamC64_memory_identifiers") {
val program = Program("test", DummyFunctions, DummyMemsizer, DummyStringEncoder)
var target = createTestProgramForMemoryRefViaVar(program, 0x1000, VarDeclType.VAR)
target.isInRegularRAMof(C64Target.machine) shouldBe true
target = createTestProgramForMemoryRefViaVar(program, 0xd020, VarDeclType.VAR)
target.isInRegularRAMof(C64Target.machine) shouldBe false
target = createTestProgramForMemoryRefViaVar(program, 0x1000, VarDeclType.CONST)
target.isInRegularRAMof(C64Target.machine) shouldBe true
target = createTestProgramForMemoryRefViaVar(program, 0xd020, VarDeclType.CONST)
target.isInRegularRAMof(C64Target.machine) shouldBe false
target = createTestProgramForMemoryRefViaVar(program, 0x1000, VarDeclType.MEMORY)
target.isInRegularRAMof(C64Target.machine) shouldBe false
}
2021-06-01 19:21:33 +00:00
test("testInValidRamC64_memory_expression") {
2021-06-01 19:21:33 +00:00
val memexpr = PrefixExpression("+", NumericLiteralValue.optimalInteger(0x1000, Position.DUMMY), Position.DUMMY)
val target = AssignTarget(null, null, DirectMemoryWrite(memexpr, Position.DUMMY), Position.DUMMY)
target.isInRegularRAMof(C64Target.machine) shouldBe false
2021-06-01 19:21:33 +00:00
}
test("testInValidRamC64_variable") {
2021-06-01 19:21:33 +00:00
val decl = VarDecl(VarDeclType.VAR, DataType.BYTE, ZeropageWish.DONTCARE, null, "address", null, false, false, false, Position.DUMMY)
val target = AssignTarget(IdentifierReference(listOf("address"), Position.DUMMY), null, null, Position.DUMMY)
val assignment = Assignment(target, NumericLiteralValue.optimalInteger(0, Position.DUMMY), Position.DUMMY)
val subroutine = Subroutine("test", mutableListOf(), emptyList(), emptyList(), emptyList(), emptySet(), null, false, false, mutableListOf(decl, assignment), Position.DUMMY)
val module = Module(mutableListOf(subroutine), Position.DUMMY, SourceCode.Generated("test"))
2021-10-29 22:05:55 +00:00
val program = Program("test", DummyFunctions, DummyMemsizer, DummyStringEncoder)
.addModule(module)
module.linkIntoProgram(program)
target.isInRegularRAMof(C64Target.machine) shouldBe true
2021-06-01 19:21:33 +00:00
}
test("testInValidRamC64_memmap_variable") {
2021-06-01 19:21:33 +00:00
val address = 0x1000
val decl = VarDecl(VarDeclType.MEMORY, DataType.UBYTE, ZeropageWish.DONTCARE, null, "address", NumericLiteralValue.optimalInteger(address, Position.DUMMY), false, false, false, Position.DUMMY)
val target = AssignTarget(IdentifierReference(listOf("address"), Position.DUMMY), null, null, Position.DUMMY)
val assignment = Assignment(target, NumericLiteralValue.optimalInteger(0, Position.DUMMY), Position.DUMMY)
val subroutine = Subroutine("test", mutableListOf(), emptyList(), emptyList(), emptyList(), emptySet(), null, false, false, mutableListOf(decl, assignment), Position.DUMMY)
val module = Module(mutableListOf(subroutine), Position.DUMMY, SourceCode.Generated("test"))
2021-10-29 22:05:55 +00:00
val program = Program("test", DummyFunctions, DummyMemsizer, DummyStringEncoder)
.addModule(module)
module.linkIntoProgram(program)
target.isInRegularRAMof(C64Target.machine) shouldBe true
2021-06-01 19:21:33 +00:00
}
test("testNotInValidRamC64_memmap_variable") {
2021-06-01 19:21:33 +00:00
val address = 0xd020
val decl = VarDecl(VarDeclType.MEMORY, DataType.UBYTE, ZeropageWish.DONTCARE, null, "address", NumericLiteralValue.optimalInteger(address, Position.DUMMY), false, false, false, Position.DUMMY)
val target = AssignTarget(IdentifierReference(listOf("address"), Position.DUMMY), null, null, Position.DUMMY)
val assignment = Assignment(target, NumericLiteralValue.optimalInteger(0, Position.DUMMY), Position.DUMMY)
val subroutine = Subroutine("test", mutableListOf(), emptyList(), emptyList(), emptyList(), emptySet(), null, false, false, mutableListOf(decl, assignment), Position.DUMMY)
val module = Module(mutableListOf(subroutine), Position.DUMMY, SourceCode.Generated("test"))
2021-10-29 22:05:55 +00:00
val program = Program("test", DummyFunctions, DummyMemsizer, DummyStringEncoder)
.addModule(module)
module.linkIntoProgram(program)
target.isInRegularRAMof(C64Target.machine) shouldBe false
2021-06-01 19:21:33 +00:00
}
test("testInValidRamC64_array") {
2021-06-01 19:21:33 +00:00
val decl = VarDecl(VarDeclType.VAR, DataType.ARRAY_UB, ZeropageWish.DONTCARE, null, "address", null, false, false, false, Position.DUMMY)
val arrayindexed = ArrayIndexedExpression(IdentifierReference(listOf("address"), Position.DUMMY), ArrayIndex(NumericLiteralValue.optimalInteger(1, Position.DUMMY), Position.DUMMY), Position.DUMMY)
val target = AssignTarget(null, arrayindexed, null, Position.DUMMY)
val assignment = Assignment(target, NumericLiteralValue.optimalInteger(0, Position.DUMMY), Position.DUMMY)
val subroutine = Subroutine("test", mutableListOf(), emptyList(), emptyList(), emptyList(), emptySet(), null, false, false, mutableListOf(decl, assignment), Position.DUMMY)
val module = Module(mutableListOf(subroutine), Position.DUMMY, SourceCode.Generated("test"))
2021-10-29 22:05:55 +00:00
val program = Program("test", DummyFunctions, DummyMemsizer, DummyStringEncoder)
.addModule(module)
module.linkIntoProgram(program)
target.isInRegularRAMof(C64Target.machine) shouldBe true
2021-06-01 19:21:33 +00:00
}
test("testInValidRamC64_array_memmapped") {
2021-06-01 19:21:33 +00:00
val address = 0x1000
val decl = VarDecl(VarDeclType.MEMORY, DataType.ARRAY_UB, ZeropageWish.DONTCARE, null, "address", NumericLiteralValue.optimalInteger(address, Position.DUMMY), false, false, false, Position.DUMMY)
val arrayindexed = ArrayIndexedExpression(IdentifierReference(listOf("address"), Position.DUMMY), ArrayIndex(NumericLiteralValue.optimalInteger(1, Position.DUMMY), Position.DUMMY), Position.DUMMY)
val target = AssignTarget(null, arrayindexed, null, Position.DUMMY)
val assignment = Assignment(target, NumericLiteralValue.optimalInteger(0, Position.DUMMY), Position.DUMMY)
val subroutine = Subroutine("test", mutableListOf(), emptyList(), emptyList(), emptyList(), emptySet(), null, false, false, mutableListOf(decl, assignment), Position.DUMMY)
val module = Module(mutableListOf(subroutine), Position.DUMMY, SourceCode.Generated("test"))
2021-10-29 22:05:55 +00:00
val program = Program("test", DummyFunctions, DummyMemsizer, DummyStringEncoder)
.addModule(module)
module.linkIntoProgram(program)
target.isInRegularRAMof(C64Target.machine) shouldBe true
2021-06-01 19:21:33 +00:00
}
test("testNotValidRamC64_array_memmapped") {
2021-06-01 19:21:33 +00:00
val address = 0xe000
val decl = VarDecl(VarDeclType.MEMORY, DataType.ARRAY_UB, ZeropageWish.DONTCARE, null, "address", NumericLiteralValue.optimalInteger(address, Position.DUMMY), false, false, false, Position.DUMMY)
val arrayindexed = ArrayIndexedExpression(IdentifierReference(listOf("address"), Position.DUMMY), ArrayIndex(NumericLiteralValue.optimalInteger(1, Position.DUMMY), Position.DUMMY), Position.DUMMY)
val target = AssignTarget(null, arrayindexed, null, Position.DUMMY)
val assignment = Assignment(target, NumericLiteralValue.optimalInteger(0, Position.DUMMY), Position.DUMMY)
val subroutine = Subroutine("test", mutableListOf(), emptyList(), emptyList(), emptyList(), emptySet(), null, false, false, mutableListOf(decl, assignment), Position.DUMMY)
val module = Module(mutableListOf(subroutine), Position.DUMMY, SourceCode.Generated("test"))
2021-10-29 22:05:55 +00:00
val program = Program("test", DummyFunctions, DummyMemsizer, DummyStringEncoder)
.addModule(module)
module.linkIntoProgram(program)
target.isInRegularRAMof(C64Target.machine) shouldBe false
2021-06-01 19:21:33 +00:00
}
})