2022-02-21 22:38:53 +00:00
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; Prog8 definitions for the Atari800XL
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; Including memory registers, I/O registers, Basic and Kernal subroutines.
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atari {
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2023-06-29 22:29:50 +00:00
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%option no_symbol_prefixing
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2022-02-21 22:38:53 +00:00
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&uword NMI_VEC = $FFFA ; 6502 nmi vector, determined by the kernal if banked in
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&uword RESET_VEC = $FFFC ; 6502 reset vector, determined by the kernal if banked in
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&uword IRQ_VEC = $FFFE ; 6502 interrupt vector, determined by the kernal if banked in
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2023-11-17 19:30:50 +00:00
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&uword COLCRS = 85
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&ubyte ROWCRS = 84
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romsub $F24A = getchar() -> ubyte @A
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romsub $F2B0 = outchar(ubyte character @ A)
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romsub $F2FD = waitkey() -> ubyte @A
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2022-02-21 22:38:53 +00:00
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}
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sys {
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; ------- lowlevel system routines --------
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2023-06-29 22:29:50 +00:00
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%option no_symbol_prefixing
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2022-02-21 22:38:53 +00:00
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const ubyte target = 8 ; compilation target specifier. 64 = C64, 128 = C128, 16 = CommanderX16, 8 = atari800XL
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2023-05-31 18:09:03 +00:00
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asmsub init_system() {
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; Initializes the machine to a sane starting state.
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; Called automatically by the loader program logic.
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; TODO
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%asm {{
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sei
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cld
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clc
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; TODO reset screen mode etc etc
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clv
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cli
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rts
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}}
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}
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asmsub init_system_phase2() {
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%asm {{
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rts ; no phase 2 steps on the Atari
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}}
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}
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2022-02-21 22:38:53 +00:00
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asmsub reset_system() {
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; Soft-reset the system back to initial power-on Basic prompt.
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; TODO
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%asm {{
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sei
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jmp (atari.RESET_VEC)
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}}
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}
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sub wait(uword jiffies) {
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; --- wait approximately the given number of jiffies (1/60th seconds)
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; TODO
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}
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asmsub waitvsync() clobbers(A) {
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; --- busy wait till the next vsync has occurred (approximately), without depending on custom irq handling.
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; TODO
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%asm {{
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nop
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rts
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}}
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}
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2022-04-23 00:15:51 +00:00
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asmsub internal_stringcopy(uword source @R0, uword target @AY) clobbers (A,Y) {
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; Called when the compiler wants to assign a string value to another string.
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%asm {{
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sta P8ZP_SCRATCH_W1
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sty P8ZP_SCRATCH_W1+1
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lda cx16.r0
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ldy cx16.r0+1
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jmp prog8_lib.strcpy
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}}
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}
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2022-02-21 22:38:53 +00:00
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asmsub memcopy(uword source @R0, uword target @R1, uword count @AY) clobbers(A,X,Y) {
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2022-03-02 22:31:07 +00:00
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; note: only works for NON-OVERLAPPING memory regions!
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2022-02-21 22:38:53 +00:00
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; note: can't be inlined because is called from asm as well
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%asm {{
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ldx cx16.r0
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stx P8ZP_SCRATCH_W1 ; source in ZP
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ldx cx16.r0+1
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stx P8ZP_SCRATCH_W1+1
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ldx cx16.r1
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stx P8ZP_SCRATCH_W2 ; target in ZP
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ldx cx16.r1+1
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stx P8ZP_SCRATCH_W2+1
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cpy #0
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bne _longcopy
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; copy <= 255 bytes
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tay
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bne _copyshort
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rts ; nothing to copy
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_copyshort
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; decrease source and target pointers so we can simply index by Y
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lda P8ZP_SCRATCH_W1
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bne +
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dec P8ZP_SCRATCH_W1+1
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+ dec P8ZP_SCRATCH_W1
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lda P8ZP_SCRATCH_W2
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bne +
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dec P8ZP_SCRATCH_W2+1
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+ dec P8ZP_SCRATCH_W2
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- lda (P8ZP_SCRATCH_W1),y
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sta (P8ZP_SCRATCH_W2),y
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dey
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bne -
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rts
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_longcopy
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sta P8ZP_SCRATCH_B1 ; lsb(count) = remainder in last page
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tya
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tax ; x = num pages (1+)
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ldy #0
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- lda (P8ZP_SCRATCH_W1),y
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sta (P8ZP_SCRATCH_W2),y
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iny
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bne -
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inc P8ZP_SCRATCH_W1+1
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inc P8ZP_SCRATCH_W2+1
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dex
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bne -
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ldy P8ZP_SCRATCH_B1
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bne _copyshort
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rts
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}}
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}
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asmsub memset(uword mem @R0, uword numbytes @R1, ubyte value @A) clobbers(A,X,Y) {
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%asm {{
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ldy cx16.r0
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sty P8ZP_SCRATCH_W1
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ldy cx16.r0+1
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sty P8ZP_SCRATCH_W1+1
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ldx cx16.r1
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ldy cx16.r1+1
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jmp prog8_lib.memset
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}}
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}
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asmsub memsetw(uword mem @R0, uword numwords @R1, uword value @AY) clobbers(A,X,Y) {
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%asm {{
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ldx cx16.r0
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stx P8ZP_SCRATCH_W1
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ldx cx16.r0+1
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stx P8ZP_SCRATCH_W1+1
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ldx cx16.r1
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stx P8ZP_SCRATCH_W2
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ldx cx16.r1+1
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stx P8ZP_SCRATCH_W2+1
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jmp prog8_lib.memsetw
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}}
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}
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inline asmsub read_flags() -> ubyte @A {
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%asm {{
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php
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pla
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}}
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}
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inline asmsub clear_carry() {
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%asm {{
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clc
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}}
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}
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inline asmsub set_carry() {
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%asm {{
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sec
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}}
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}
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inline asmsub clear_irqd() {
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%asm {{
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cli
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}}
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}
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inline asmsub set_irqd() {
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%asm {{
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sei
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}}
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}
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2023-05-22 19:13:20 +00:00
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inline asmsub irqsafe_set_irqd() {
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%asm {{
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php
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sei
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}}
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}
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inline asmsub irqsafe_clear_irqd() {
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%asm {{
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plp
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}}
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}
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2023-11-06 22:55:49 +00:00
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sub disable_caseswitch() {
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; no-op
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}
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sub enable_caseswitch() {
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; no-op
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}
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2023-11-21 20:31:50 +00:00
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asmsub save_prog8_internals() {
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%asm {{
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lda P8ZP_SCRATCH_B1
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sta save_SCRATCH_ZPB1
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lda P8ZP_SCRATCH_REG
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sta save_SCRATCH_ZPREG
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lda P8ZP_SCRATCH_W1
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sta save_SCRATCH_ZPWORD1
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lda P8ZP_SCRATCH_W1+1
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sta save_SCRATCH_ZPWORD1+1
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lda P8ZP_SCRATCH_W2
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sta save_SCRATCH_ZPWORD2
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lda P8ZP_SCRATCH_W2+1
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sta save_SCRATCH_ZPWORD2+1
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rts
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save_SCRATCH_ZPB1 .byte 0
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save_SCRATCH_ZPREG .byte 0
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save_SCRATCH_ZPWORD1 .word 0
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save_SCRATCH_ZPWORD2 .word 0
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}}
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}
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asmsub restore_prog8_internals() {
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%asm {{
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lda save_prog8_internals.save_SCRATCH_ZPB1
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sta P8ZP_SCRATCH_B1
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lda save_prog8_internals.save_SCRATCH_ZPREG
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sta P8ZP_SCRATCH_REG
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lda save_prog8_internals.save_SCRATCH_ZPWORD1
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sta P8ZP_SCRATCH_W1
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lda save_prog8_internals.save_SCRATCH_ZPWORD1+1
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sta P8ZP_SCRATCH_W1+1
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lda save_prog8_internals.save_SCRATCH_ZPWORD2
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sta P8ZP_SCRATCH_W2
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lda save_prog8_internals.save_SCRATCH_ZPWORD2+1
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sta P8ZP_SCRATCH_W2+1
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rts
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}}
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}
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2022-02-21 22:38:53 +00:00
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inline asmsub exit(ubyte returnvalue @A) {
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; -- immediately exit the program with a return code in the A register
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; TODO
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%asm {{
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ldx prog8_lib.orig_stackpointer
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txs
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rts ; return to original caller
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}}
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}
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inline asmsub progend() -> uword @AY {
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%asm {{
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lda #<prog8_program_end
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ldy #>prog8_program_end
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}}
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}
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}
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cx16 {
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2023-06-29 22:29:50 +00:00
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%option no_symbol_prefixing
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2022-02-21 22:38:53 +00:00
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; the sixteen virtual 16-bit registers that the CX16 has defined in the zeropage
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; they are simulated on the Atari as well but their location in memory is different
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; TODO
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&uword r0 = $1b00
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&uword r1 = $1b02
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&uword r2 = $1b04
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&uword r3 = $1b06
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&uword r4 = $1b08
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&uword r5 = $1b0a
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&uword r6 = $1b0c
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&uword r7 = $1b0e
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&uword r8 = $1b10
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&uword r9 = $1b12
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&uword r10 = $1b14
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&uword r11 = $1b16
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&uword r12 = $1b18
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&uword r13 = $1b1a
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&uword r14 = $1b1c
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&uword r15 = $1b1e
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&word r0s = $1b00
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&word r1s = $1b02
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&word r2s = $1b04
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&word r3s = $1b06
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&word r4s = $1b08
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&word r5s = $1b0a
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&word r6s = $1b0c
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&word r7s = $1b0e
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&word r8s = $1b10
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&word r9s = $1b12
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&word r10s = $1b14
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&word r11s = $1b16
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&word r12s = $1b18
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&word r13s = $1b1a
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&word r14s = $1b1c
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&word r15s = $1b1e
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&ubyte r0L = $1b00
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&ubyte r1L = $1b02
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&ubyte r2L = $1b04
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&ubyte r3L = $1b06
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&ubyte r4L = $1b08
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&ubyte r5L = $1b0a
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&ubyte r6L = $1b0c
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&ubyte r7L = $1b0e
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&ubyte r8L = $1b10
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&ubyte r9L = $1b12
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&ubyte r10L = $1b14
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&ubyte r11L = $1b16
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&ubyte r12L = $1b18
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&ubyte r13L = $1b1a
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&ubyte r14L = $1b1c
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&ubyte r15L = $1b1e
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&ubyte r0H = $1b01
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&ubyte r1H = $1b03
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&ubyte r2H = $1b05
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&ubyte r3H = $1b07
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&ubyte r4H = $1b09
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&ubyte r5H = $1b0b
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&ubyte r6H = $1b0d
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&ubyte r7H = $1b0f
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&ubyte r8H = $1b11
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&ubyte r9H = $1b13
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&ubyte r10H = $1b15
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&ubyte r11H = $1b17
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&ubyte r12H = $1b19
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&ubyte r13H = $1b1b
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&ubyte r14H = $1b1d
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&ubyte r15H = $1b1f
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&byte r0sL = $1b00
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&byte r1sL = $1b02
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&byte r2sL = $1b04
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&byte r3sL = $1b06
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&byte r4sL = $1b08
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&byte r5sL = $1b0a
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&byte r6sL = $1b0c
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&byte r7sL = $1b0e
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&byte r8sL = $1b10
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&byte r9sL = $1b12
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&byte r10sL = $1b14
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&byte r11sL = $1b16
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&byte r12sL = $1b18
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&byte r13sL = $1b1a
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&byte r14sL = $1b1c
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&byte r15sL = $1b1e
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&byte r0sH = $1b01
|
|
|
|
&byte r1sH = $1b03
|
|
|
|
&byte r2sH = $1b05
|
|
|
|
&byte r3sH = $1b07
|
|
|
|
&byte r4sH = $1b09
|
|
|
|
&byte r5sH = $1b0b
|
|
|
|
&byte r6sH = $1b0d
|
|
|
|
&byte r7sH = $1b0f
|
|
|
|
&byte r8sH = $1b11
|
|
|
|
&byte r9sH = $1b13
|
|
|
|
&byte r10sH = $1b15
|
|
|
|
&byte r11sH = $1b17
|
|
|
|
&byte r12sH = $1b19
|
|
|
|
&byte r13sH = $1b1b
|
|
|
|
&byte r14sH = $1b1d
|
|
|
|
&byte r15sH = $1b1f
|
2023-06-24 19:04:47 +00:00
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|
|
|
|
|
|
asmsub save_virtual_registers() clobbers(A,Y) {
|
|
|
|
%asm {{
|
|
|
|
ldy #31
|
|
|
|
- lda cx16.r0,y
|
|
|
|
sta _cx16_vreg_storage,y
|
|
|
|
dey
|
|
|
|
bpl -
|
|
|
|
rts
|
|
|
|
|
|
|
|
_cx16_vreg_storage
|
|
|
|
.word 0,0,0,0,0,0,0,0
|
|
|
|
.word 0,0,0,0,0,0,0,0
|
|
|
|
}}
|
|
|
|
}
|
|
|
|
|
|
|
|
asmsub restore_virtual_registers() clobbers(A,Y) {
|
|
|
|
%asm {{
|
|
|
|
ldy #31
|
|
|
|
- lda save_virtual_registers._cx16_vreg_storage,y
|
|
|
|
sta cx16.r0,y
|
|
|
|
dey
|
|
|
|
bpl -
|
|
|
|
rts
|
|
|
|
}}
|
|
|
|
}
|
|
|
|
|
2022-02-21 22:38:53 +00:00
|
|
|
}
|