From 03c5dab79db7d854975c1071b0cac68dc376c8f7 Mon Sep 17 00:00:00 2001 From: Irmen de Jong Date: Mon, 13 Mar 2023 02:21:58 +0100 Subject: [PATCH] refactor IR returnregs 2 --- .../codegen/intermediate/AssignmentGen.kt | 19 +- .../codegen/intermediate/BuiltinFuncGen.kt | 53 +- .../codegen/intermediate/ExpressionGen.kt | 636 +++++++++--------- .../prog8/codegen/intermediate/IRCodeGen.kt | 83 ++- compiler/src/prog8/compiler/Compiler.kt | 10 +- docs/source/todo.rst | 2 + 6 files changed, 409 insertions(+), 394 deletions(-) diff --git a/codeGenIntermediate/src/prog8/codegen/intermediate/AssignmentGen.kt b/codeGenIntermediate/src/prog8/codegen/intermediate/AssignmentGen.kt index 734e1cac1..4d093e31f 100644 --- a/codeGenIntermediate/src/prog8/codegen/intermediate/AssignmentGen.kt +++ b/codeGenIntermediate/src/prog8/codegen/intermediate/AssignmentGen.kt @@ -142,14 +142,14 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express // calculate the assignment value if (vmDt == IRDataType.FLOAT) { resultFpRegister = codeGen.registers.nextFreeFloat() - val tr = expressionEval.translateExpression(assignment.value, -1, resultFpRegister) + val tr = expressionEval.translateExpression(assignment.value) addToResult(result, tr, -1, resultFpRegister) } else { resultRegister = if (assignment.value is PtMachineRegister) { (assignment.value as PtMachineRegister).register } else { val reg = codeGen.registers.nextFree() - val tr = expressionEval.translateExpression(assignment.value, reg, -1) + val tr = expressionEval.translateExpression(assignment.value) addToResult(result, tr, reg, -1) reg } @@ -178,7 +178,7 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express if(array.index.type!=DataType.UBYTE) throw AssemblyError("non-array var indexing requires bytes index") val idxReg = codeGen.registers.nextFree() - val tr = expressionEval.translateExpression(array.index, idxReg, -1) + val tr = expressionEval.translateExpression(array.index) addToResult(result, tr, idxReg, -1) val code = IRCodeChunk(null, null) if(zero) { @@ -235,7 +235,7 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express result += chunk } else { val addressReg = codeGen.registers.nextFree() - val tr = expressionEval.translateExpression(memory.address, addressReg, -1) + val tr = expressionEval.translateExpression(memory.address) addToResult(result, tr, addressReg, -1) result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.STOREZI, vmDt, reg1=addressReg) } } @@ -245,7 +245,7 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express result += chunk } else { val addressReg = codeGen.registers.nextFree() - val tr = expressionEval.translateExpression(memory.address, addressReg, -1) + val tr = expressionEval.translateExpression(memory.address) addToResult(result, tr, addressReg, -1) result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.STOREI, vmDt, reg1=resultRegister, reg2=addressReg) } } @@ -258,15 +258,16 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express } private fun loadIndexReg(array: PtArrayIndexer, itemsize: Int, indexReg: Int): IRCodeChunks { + val result = mutableListOf() val tr = if(itemsize==1) { - expressionEval.translateExpression(array.index, indexReg, -1) + expressionEval.translateExpression(array.index) } else { val mult = PtBinaryExpression("*", DataType.UBYTE, array.position) mult.children += array.index mult.children += PtNumber(DataType.UBYTE, itemsize.toDouble(), array.position) - expressionEval.translateExpression(mult, indexReg, -1) + expressionEval.translateExpression(mult) } - require(tr.resultReg==indexReg && tr.resultFpReg==-1) // TODO weg - return tr.chunks + addToResult(result, tr, indexReg, -1) + return result } } \ No newline at end of file diff --git a/codeGenIntermediate/src/prog8/codegen/intermediate/BuiltinFuncGen.kt b/codeGenIntermediate/src/prog8/codegen/intermediate/BuiltinFuncGen.kt index 6713828ed..b23bfc3b7 100644 --- a/codeGenIntermediate/src/prog8/codegen/intermediate/BuiltinFuncGen.kt +++ b/codeGenIntermediate/src/prog8/codegen/intermediate/BuiltinFuncGen.kt @@ -112,9 +112,9 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe val leftRegister = codeGen.registers.nextFree() val rightRegister = codeGen.registers.nextFree() val result = mutableListOf() - var tr = exprGen.translateExpression(call.args[0], leftRegister, -1) + var tr = exprGen.translateExpression(call.args[0]) addToResult(result, tr, leftRegister, -1) - tr = exprGen.translateExpression(call.args[1], rightRegister, -1) + tr = exprGen.translateExpression(call.args[1]) addToResult(result, tr, rightRegister, -1) result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.CMP, codeGen.irType(call.args[0].type), reg1=leftRegister, reg2=rightRegister) @@ -135,7 +135,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe else -> throw IllegalArgumentException("weird type") } val result = mutableListOf() - val tr = exprGen.translateExpression(call.args[0], SyscallRegisterBase, -1) + val tr = exprGen.translateExpression(call.args[0]) addToResult(result, tr, SyscallRegisterBase, -1) result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1 = SyscallRegisterBase+1, value = array.length) @@ -159,7 +159,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe else -> throw IllegalArgumentException("weird type") } val result = mutableListOf() - val tr = exprGen.translateExpression(call.args[0], SyscallRegisterBase, -1) + val tr = exprGen.translateExpression(call.args[0]) addToResult(result, tr, SyscallRegisterBase, -1) result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1 = SyscallRegisterBase+1, value = array.length) @@ -174,7 +174,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe val sourceDt = call.args.single().type val result = mutableListOf() if(sourceDt!=DataType.UWORD) { - val tr = exprGen.translateExpression(call.args[0], resultRegister, -1) + val tr = exprGen.translateExpression(call.args[0]) addToResult(result, tr, resultRegister, -1) when (sourceDt) { DataType.UBYTE -> { @@ -214,7 +214,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe private fun funcSgn(call: PtBuiltinFunctionCall, resultRegister: Int): IRCodeChunks { val reg = codeGen.registers.nextFree() val result = mutableListOf() - val tr = exprGen.translateExpression(call.args.single(), reg, -1) + val tr = exprGen.translateExpression(call.args.single()) addToResult(result, tr, reg, -1) result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.SGN, codeGen.irType(call.type), reg1 = resultRegister, reg2 = reg) @@ -225,7 +225,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe private fun funcSqrt16(call: PtBuiltinFunctionCall, resultRegister: Int): IRCodeChunks { val reg = codeGen.registers.nextFree() val result = mutableListOf() - val tr = exprGen.translateExpression(call.args.single(), reg, -1) + val tr = exprGen.translateExpression(call.args.single()) addToResult(result, tr, reg, -1) result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.SQRT, IRDataType.WORD, reg1=resultRegister, reg2=reg) @@ -254,7 +254,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe private fun funcPush(call: PtBuiltinFunctionCall): IRCodeChunks { val result = mutableListOf() val reg = codeGen.registers.nextFree() - val tr = exprGen.translateExpression(call.args.single(), reg, -1) + val tr = exprGen.translateExpression(call.args.single()) addToResult(result, tr, reg, -1) result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.PUSH, IRDataType.BYTE, reg1=reg) @@ -265,7 +265,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe private fun funcPushw(call: PtBuiltinFunctionCall): IRCodeChunks { val result = mutableListOf() val reg = codeGen.registers.nextFree() - val tr = exprGen.translateExpression(call.args.single(), reg, -1) + val tr = exprGen.translateExpression(call.args.single()) addToResult(result, tr, reg, -1) result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.PUSH, IRDataType.WORD, reg1 = reg) @@ -284,7 +284,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe else -> throw IllegalArgumentException("weird type to reverse") } val result = mutableListOf() - val tr = exprGen.translateExpression(call.args[0], SyscallRegisterBase, -1) + val tr = exprGen.translateExpression(call.args[0]) addToResult(result, tr, SyscallRegisterBase, -1) result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1 = SyscallRegisterBase+1, value = array.length) @@ -307,7 +307,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe else -> throw IllegalArgumentException("weird type to sort") } val result = mutableListOf() - val tr = exprGen.translateExpression(call.args[0], SyscallRegisterBase, -1) + val tr = exprGen.translateExpression(call.args[0]) addToResult(result, tr, SyscallRegisterBase, -1) result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1 = SyscallRegisterBase+1, value = array.length) @@ -319,9 +319,9 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe private fun funcMkword(call: PtBuiltinFunctionCall, resultRegister: Int): IRCodeChunks { val msbReg = codeGen.registers.nextFree() val result = mutableListOf() - var tr = exprGen.translateExpression(call.args[0], msbReg, -1) + var tr = exprGen.translateExpression(call.args[0]) addToResult(result, tr, msbReg, -1) - tr = exprGen.translateExpression(call.args[1], resultRegister, -1) + tr = exprGen.translateExpression(call.args[1]) addToResult(result, tr, resultRegister, -1) result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.CONCAT, IRDataType.BYTE, reg1 = resultRegister, reg2 = msbReg) @@ -339,7 +339,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe } } else { val addressReg = codeGen.registers.nextFree() - val tr = exprGen.translateExpression(call.args[0], addressReg, -1) + val tr = exprGen.translateExpression(call.args[0]) addToResult(result, tr, addressReg, -1) result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.STOREZI, IRDataType.WORD, reg1 = addressReg) @@ -349,16 +349,16 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe val valueReg = codeGen.registers.nextFree() if (call.args[0] is PtNumber) { val address = (call.args[0] as PtNumber).number.toInt() - val tr = exprGen.translateExpression(call.args[1], valueReg, -1) + val tr = exprGen.translateExpression(call.args[1]) addToResult(result, tr, valueReg, -1) result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.STOREM, IRDataType.WORD, reg1 = valueReg, value = address) } } else { val addressReg = codeGen.registers.nextFree() - var tr = exprGen.translateExpression(call.args[0], addressReg, -1) + var tr = exprGen.translateExpression(call.args[0]) addToResult(result, tr, addressReg, -1) - tr = exprGen.translateExpression(call.args[1], valueReg, -1) + tr = exprGen.translateExpression(call.args[1]) addToResult(result, tr, valueReg, -1) result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.STOREI, IRDataType.WORD, reg1 = valueReg, reg2 = addressReg) @@ -378,7 +378,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe } } else { val addressReg = codeGen.registers.nextFree() - val tr = exprGen.translateExpression(call.args[0], addressReg, -1) + val tr = exprGen.translateExpression(call.args[0]) addToResult(result, tr, addressReg, -1) result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.STOREZI, IRDataType.BYTE, reg1 = addressReg) @@ -388,16 +388,16 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe val valueReg = codeGen.registers.nextFree() if (call.args[0] is PtNumber) { val address = (call.args[0] as PtNumber).number.toInt() - val tr = exprGen.translateExpression(call.args[1], valueReg, -1) + val tr = exprGen.translateExpression(call.args[1]) addToResult(result, tr, valueReg, -1) result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.STOREM, IRDataType.BYTE, reg1 = valueReg, value = address) } } else { val addressReg = codeGen.registers.nextFree() - var tr = exprGen.translateExpression(call.args[0], addressReg, -1) + var tr = exprGen.translateExpression(call.args[0]) addToResult(result, tr, addressReg, -1) - tr = exprGen.translateExpression(call.args[1], valueReg, -1) + tr = exprGen.translateExpression(call.args[1]) addToResult(result, tr, valueReg, -1) result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.STOREI, IRDataType.BYTE, reg1 = valueReg, reg2 = addressReg) @@ -416,7 +416,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe } } else { val addressReg = codeGen.registers.nextFree() - val tr = exprGen.translateExpression(call.args.single(), addressReg, -1) + val tr = exprGen.translateExpression(call.args.single()) addToResult(result, tr, addressReg, -1) result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.LOADI, IRDataType.WORD, reg1 = resultRegister, reg2 = addressReg) @@ -434,7 +434,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe } } else { val addressReg = codeGen.registers.nextFree() - val tr = exprGen.translateExpression(call.args.single(), addressReg, -1) + val tr = exprGen.translateExpression(call.args.single()) addToResult(result, tr, addressReg, -1) result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.LOADI, IRDataType.BYTE, reg1 = resultRegister, reg2 = addressReg) @@ -451,15 +451,14 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe } private fun funcLsb(call: PtBuiltinFunctionCall): ExpressionCodeResult { - val resultRegister = codeGen.registers.nextFree() - return exprGen.translateExpression(call.args.single(), resultRegister, -1) + return exprGen.translateExpression(call.args.single()) // note: if a word result is needed, the upper byte is cleared by the typecast that follows. No need to do it here. } private fun funcMsb(call: PtBuiltinFunctionCall): ExpressionCodeResult { val result = mutableListOf() val resultRegister = codeGen.registers.nextFree() - val tr = exprGen.translateExpression(call.args.single(), resultRegister, -1) + val tr = exprGen.translateExpression(call.args.single()) addToResult(result, tr, resultRegister, -1) result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.MSIG, IRDataType.BYTE, reg1 = resultRegister, reg2 = resultRegister) @@ -471,7 +470,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe private fun funcRolRor(opcode: Opcode, call: PtBuiltinFunctionCall, resultRegister: Int): IRCodeChunks { val vmDt = codeGen.irType(call.args[0].type) val result = mutableListOf() - val tr = exprGen.translateExpression(call.args[0], resultRegister, -1) + val tr = exprGen.translateExpression(call.args[0]) addToResult(result, tr, resultRegister, -1) result += IRCodeChunk(null, null).also { it += IRInstruction(opcode, vmDt, reg1 = resultRegister) diff --git a/codeGenIntermediate/src/prog8/codegen/intermediate/ExpressionGen.kt b/codeGenIntermediate/src/prog8/codegen/intermediate/ExpressionGen.kt index bff25e4dd..5e3aa0ade 100644 --- a/codeGenIntermediate/src/prog8/codegen/intermediate/ExpressionGen.kt +++ b/codeGenIntermediate/src/prog8/codegen/intermediate/ExpressionGen.kt @@ -16,36 +16,30 @@ internal class ExpressionCodeResult(val chunks: IRCodeChunks, val dt: IRDataType companion object { val EMPTY: ExpressionCodeResult = ExpressionCodeResult(emptyList(), IRDataType.BYTE, -1, -1) } + + init { + if(resultReg!=-1) require(resultFpReg==-1) + if(resultFpReg!=-1) require(resultReg==-1) + } } internal class ExpressionGen(private val codeGen: IRCodeGen) { - fun translateExpression(expr: PtExpression, resultRegister: Int, resultFpRegister: Int): ExpressionCodeResult { - require(codeGen.registers.peekNext() > resultRegister || resultRegister >= SyscallRegisterBase) { - "no more registers for expression ${expr.position}" - } - require((expr.type!=DataType.FLOAT && resultRegister>=0) || (expr.type==DataType.FLOAT && resultFpRegister>=0)) { - "mismatched result register for expression datatype ${expr.type} ${expr.position}" - } + fun translateExpression(expr: PtExpression): ExpressionCodeResult { return when (expr) { is PtMachineRegister -> { - if(resultRegister!=expr.register) { - val vmDt = codeGen.irType(expr.type) - val code = IRCodeChunk(null, null) - code += IRInstruction(Opcode.LOADR, vmDt, reg1=resultRegister, reg2=expr.register) - ExpressionCodeResult(code, vmDt, resultRegister, -1) - } else { - ExpressionCodeResult.EMPTY - } + ExpressionCodeResult(emptyList(), codeGen.irType(expr.type), expr.register, -1) } is PtNumber -> { val vmDt = codeGen.irType(expr.type) val code = IRCodeChunk(null, null) if(vmDt==IRDataType.FLOAT) { + val resultFpRegister = codeGen.registers.nextFreeFloat() code += IRInstruction(Opcode.LOAD, vmDt, fpReg1 = resultFpRegister, fpValue = expr.number.toFloat()) ExpressionCodeResult(code, vmDt,-1, resultFpRegister) } else { + val resultRegister = codeGen.registers.nextFree() code += IRInstruction(Opcode.LOAD, vmDt, reg1 = resultRegister, value = expr.number.toInt()) ExpressionCodeResult(code, vmDt, resultRegister, -1) } @@ -55,15 +49,18 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { val code = IRCodeChunk(null, null) if (expr.type in PassByValueDatatypes) { if(vmDt==IRDataType.FLOAT) { + val resultFpRegister = codeGen.registers.nextFreeFloat() code += IRInstruction(Opcode.LOADM, vmDt, fpReg1 = resultFpRegister, labelSymbol = expr.name) ExpressionCodeResult(code, vmDt, -1, resultFpRegister) } else { + val resultRegister = codeGen.registers.nextFree() code += IRInstruction(Opcode.LOADM, vmDt, reg1 = resultRegister, labelSymbol = expr.name) ExpressionCodeResult(code, vmDt, resultRegister, -1) } } else { // for strings and arrays etc., load the *address* of the value instead + val resultRegister = codeGen.registers.nextFree() code += IRInstruction(Opcode.LOAD, vmDt, reg1 = resultRegister, labelSymbol = expr.name) ExpressionCodeResult(code, vmDt, resultRegister, -1) } @@ -73,6 +70,7 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { val symbol = expr.identifier.name // note: LOAD gets you the address of the symbol, whereas LOADM would get you the value stored at that location val code = IRCodeChunk(null, null) + val resultRegister = codeGen.registers.nextFree() code += IRInstruction(Opcode.LOAD, vmDt, reg1=resultRegister, labelSymbol = symbol) ExpressionCodeResult(code, vmDt, resultRegister, -1) } @@ -80,22 +78,23 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { val result = mutableListOf() if(expr.address is PtNumber) { val address = (expr.address as PtNumber).number.toInt() + val resultRegister = codeGen.registers.nextFree() addInstr(result, IRInstruction(Opcode.LOADM, IRDataType.BYTE, reg1=resultRegister, value = address), null) + ExpressionCodeResult(result, IRDataType.BYTE, resultRegister, -1) } else { - val addressRegister = codeGen.registers.nextFree() - val translated = translateExpression(expr.address, addressRegister, -1) - addToResult(result, translated, addressRegister, -1) - addInstr(result, IRInstruction(Opcode.LOADI, IRDataType.BYTE, reg1=resultRegister, reg2=addressRegister), null) + val tr = translateExpression(expr.address) + addToResult(result, tr, tr.resultReg, -1) + addInstr(result, IRInstruction(Opcode.LOADI, IRDataType.BYTE, reg1=tr.resultReg, reg2=tr.resultReg), null) + ExpressionCodeResult(result, IRDataType.BYTE, tr.resultReg, -1) } - ExpressionCodeResult(result, IRDataType.BYTE, resultRegister, -1) } - is PtTypeCast -> translate(expr, resultRegister, resultFpRegister) - is PtPrefix -> translate(expr, resultRegister, resultFpRegister) - is PtArrayIndexer -> translate(expr, resultRegister, resultFpRegister) - is PtBinaryExpression -> translate(expr, resultRegister, resultFpRegister) + is PtTypeCast -> translate(expr) + is PtPrefix -> translate(expr) + is PtArrayIndexer -> translate(expr) + is PtBinaryExpression -> translate(expr) is PtBuiltinFunctionCall -> codeGen.translateBuiltinFunc(expr) - is PtFunctionCall -> translate(expr, resultRegister, resultFpRegister) - is PtContainmentCheck -> translate(expr, resultRegister, resultFpRegister) + is PtFunctionCall -> translate(expr) + is PtContainmentCheck -> translate(expr) is PtRange, is PtArray, is PtString -> throw AssemblyError("range/arrayliteral/string should no longer occur as expression") @@ -103,58 +102,56 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { } } - private fun translate(check: PtContainmentCheck, resultRegister: Int, resultFpRegister: Int): ExpressionCodeResult { + private fun translate(check: PtContainmentCheck): ExpressionCodeResult { val result = mutableListOf() - var translated = translateExpression(check.element, resultRegister, -1) // load the element to check in resultRegister - addToResult(result, translated, resultRegister, -1) + var tr = translateExpression(check.element) + addToResult(result, tr, tr.resultReg, -1) val iterable = codeGen.symbolTable.flat.getValue(check.iterable.name) as StStaticVariable when(iterable.dt) { DataType.STR -> { - translated = translateExpression(check.element, SyscallRegisterBase, -1) - addToResult(result, translated, SyscallRegisterBase, -1) - translated = translateExpression(check.iterable, SyscallRegisterBase+1, -1) - addToResult(result, translated, SyscallRegisterBase+1, -1) + tr = translateExpression(check.element) + addToResult(result, tr, SyscallRegisterBase, -1) + tr = translateExpression(check.iterable) + addToResult(result, tr, SyscallRegisterBase+1, -1) result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.SYSCALL, value = IMSyscall.STRING_CONTAINS.number) - if(resultRegister!=0) - it += IRInstruction(Opcode.LOADR, IRDataType.BYTE, reg1=resultRegister, reg2=0) } + // SysCall call convention: return value in register r0 + return ExpressionCodeResult(result, IRDataType.BYTE, 0, -1) } DataType.ARRAY_UB, DataType.ARRAY_B -> { - translated = translateExpression(check.element, SyscallRegisterBase, -1) - addToResult(result, translated, SyscallRegisterBase, -1) - translated = translateExpression(check.iterable, SyscallRegisterBase+1, -1) - addToResult(result, translated, SyscallRegisterBase+1, -1) + tr = translateExpression(check.element) + addToResult(result, tr, SyscallRegisterBase, -1) + tr = translateExpression(check.iterable) + addToResult(result, tr, SyscallRegisterBase+1, -1) result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=SyscallRegisterBase+2, value = iterable.length!!) it += IRInstruction(Opcode.SYSCALL, value = IMSyscall.BYTEARRAY_CONTAINS.number) - if(resultRegister!=0) - it += IRInstruction(Opcode.LOADR, IRDataType.BYTE, reg1=resultRegister, reg2=0) } + // SysCall call convention: return value in register r0 + return ExpressionCodeResult(result, IRDataType.BYTE, 0, -1) } DataType.ARRAY_UW, DataType.ARRAY_W -> { - translated = translateExpression(check.element, SyscallRegisterBase, -1) - addToResult(result, translated, SyscallRegisterBase, -1) - translated = translateExpression(check.iterable, SyscallRegisterBase+1, -1) - addToResult(result, translated, SyscallRegisterBase+1, -1) + tr = translateExpression(check.element) + addToResult(result, tr, SyscallRegisterBase, -1) + tr = translateExpression(check.iterable) + addToResult(result, tr, SyscallRegisterBase+1, -1) result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=SyscallRegisterBase+2, value = iterable.length!!) it += IRInstruction(Opcode.SYSCALL, value = IMSyscall.WORDARRAY_CONTAINS.number) - if(resultRegister!=0) - it += IRInstruction(Opcode.LOADR, IRDataType.BYTE, reg1=resultRegister, reg2=0) } + // SysCall call convention: return value in register r0 + return ExpressionCodeResult(result, IRDataType.BYTE, 0, -1) } DataType.ARRAY_F -> throw AssemblyError("containment check in float-array not supported") else -> throw AssemblyError("weird iterable dt ${iterable.dt} for ${check.iterable.name}") } - return ExpressionCodeResult(result, IRDataType.BYTE, resultRegister, -1) } - private fun translate(arrayIx: PtArrayIndexer, resultRegister: Int, resultFpRegister: Int): ExpressionCodeResult { + private fun translate(arrayIx: PtArrayIndexer): ExpressionCodeResult { val eltSize = codeGen.program.memsizer.memorySize(arrayIx.type) val vmDt = codeGen.irType(arrayIx.type) val result = mutableListOf() - val idxReg = codeGen.registers.nextFree() val arrayVarSymbol = arrayIx.variable.name if(arrayIx.variable.type==DataType.UWORD) { @@ -163,81 +160,93 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { throw AssemblyError("non-array var indexing requires bytes dt") if(arrayIx.index.type!=DataType.UBYTE) throw AssemblyError("non-array var indexing requires bytes index") - val translated = translateExpression(arrayIx.index, idxReg, -1) - addToResult(result, translated, idxReg, -1) - addInstr(result, IRInstruction(Opcode.LOADIX, vmDt, reg1=resultRegister, reg2=idxReg, labelSymbol = arrayVarSymbol), null) - return ExpressionCodeResult(result, vmDt, resultRegister, resultFpRegister) + val tr = translateExpression(arrayIx.index) + addToResult(result, tr, tr.resultReg, -1) + addInstr(result, IRInstruction(Opcode.LOADIX, vmDt, reg1=tr.resultReg, reg2=tr.resultReg, labelSymbol = arrayVarSymbol), null) + return ExpressionCodeResult(result, vmDt, tr.resultReg, -1) } + var resultRegister = -1 + var resultFpRegister = -1 if(arrayIx.index is PtNumber) { val memOffset = ((arrayIx.index as PtNumber).number.toInt() * eltSize).toString() - if(vmDt==IRDataType.FLOAT) + if(vmDt==IRDataType.FLOAT) { + resultFpRegister = codeGen.registers.nextFreeFloat() addInstr(result, IRInstruction(Opcode.LOADM, IRDataType.FLOAT, fpReg1=resultFpRegister, labelSymbol = "$arrayVarSymbol+$memOffset"), null) - else + } + else { + resultRegister = codeGen.registers.nextFree() addInstr(result, IRInstruction(Opcode.LOADM, vmDt, reg1=resultRegister, labelSymbol = "$arrayVarSymbol+$memOffset"), null) + } } else { - val translated = translateExpression(arrayIx.index, idxReg, -1) - addToResult(result, translated, idxReg, -1) + val tr = translateExpression(arrayIx.index) + addToResult(result, tr, tr.resultReg, -1) if(eltSize>1) - result += codeGen.multiplyByConst(IRDataType.BYTE, idxReg, eltSize) - if(vmDt==IRDataType.FLOAT) - addInstr(result, IRInstruction(Opcode.LOADX, IRDataType.FLOAT, fpReg1 = resultFpRegister, reg1=idxReg, labelSymbol = arrayVarSymbol), null) - else - addInstr(result, IRInstruction(Opcode.LOADX, vmDt, reg1=resultRegister, reg2=idxReg, labelSymbol = arrayVarSymbol), null) + result += codeGen.multiplyByConst(IRDataType.BYTE, tr.resultReg, eltSize) + if(vmDt==IRDataType.FLOAT) { + resultFpRegister = codeGen.registers.nextFreeFloat() + addInstr(result, IRInstruction(Opcode.LOADX, IRDataType.FLOAT, fpReg1 = resultFpRegister, reg1=tr.resultReg, labelSymbol = arrayVarSymbol), null) + } + else { + resultRegister = tr.resultReg + addInstr(result, IRInstruction(Opcode.LOADX, vmDt, reg1=resultRegister, reg2=tr.resultReg, labelSymbol = arrayVarSymbol), null) + } } return ExpressionCodeResult(result, vmDt, resultRegister, resultFpRegister) } - private fun translate(expr: PtPrefix, resultRegister: Int, resultFpRegister: Int): ExpressionCodeResult { + private fun translate(expr: PtPrefix): ExpressionCodeResult { val result = mutableListOf() - val translated = translateExpression(expr.value, resultRegister, resultFpRegister) - addToResult(result, translated, resultRegister, resultFpRegister) + val tr = translateExpression(expr.value) + addToResult(result, tr, tr.resultReg, tr.resultFpReg) val vmDt = codeGen.irType(expr.type) when(expr.operator) { "+" -> { } "-" -> { if(vmDt==IRDataType.FLOAT) - addInstr(result, IRInstruction(Opcode.NEG, vmDt, fpReg1 = resultFpRegister), null) + addInstr(result, IRInstruction(Opcode.NEG, vmDt, fpReg1 = tr.resultFpReg), null) else - addInstr(result, IRInstruction(Opcode.NEG, vmDt, reg1 = resultRegister), null) + addInstr(result, IRInstruction(Opcode.NEG, vmDt, reg1 = tr.resultReg), null) } "~" -> { val mask = if(vmDt==IRDataType.BYTE) 0x00ff else 0xffff - addInstr(result, IRInstruction(Opcode.XOR, vmDt, reg1 = resultRegister, value = mask), null) + addInstr(result, IRInstruction(Opcode.XOR, vmDt, reg1 = tr.resultReg, value = mask), null) } else -> throw AssemblyError("weird prefix operator") } - return ExpressionCodeResult(result, vmDt, resultRegister, resultFpRegister) + return ExpressionCodeResult(result, vmDt, tr.resultReg, tr.resultFpReg) } - private fun translate(cast: PtTypeCast, resultRegister: Int, resultFpRegister: Int): ExpressionCodeResult { + private fun translate(cast: PtTypeCast): ExpressionCodeResult { if(cast.type==cast.value.type) return ExpressionCodeResult.EMPTY val result = mutableListOf() - val actualResultFpReg = if(resultFpRegister>=0) resultFpRegister else codeGen.registers.nextFreeFloat() - val actualResultReg = if(resultRegister>=0) resultRegister else codeGen.registers.nextFree() - result += if(cast.value.type==DataType.FLOAT) { - // a cast from float to integer, so evaluate the value into a float register first - val translated = translateExpression(cast.value, -1, actualResultFpReg) - require(translated.resultReg==-1 && translated.resultFpReg==actualResultFpReg) - translated.chunks - } else { - val translated = translateExpression(cast.value, actualResultReg, -1) - require(translated.resultReg==actualResultReg && translated.resultFpReg==-1) - translated.chunks - } + val tr = translateExpression(cast.value) + addToResult(result, tr, tr.resultReg, tr.resultFpReg) + var actualResultReg2 = -1 + var actualResultFpReg2 = -1 when(cast.type) { DataType.UBYTE -> { when(cast.value.type) { - DataType.BYTE, DataType.UWORD, DataType.WORD -> { /* just keep the LSB as it is */ } - DataType.FLOAT -> addInstr(result, IRInstruction(Opcode.FTOUB, IRDataType.FLOAT, reg1=actualResultReg, fpReg1 = actualResultFpReg), null) + DataType.BYTE, DataType.UWORD, DataType.WORD -> { + actualResultReg2 = tr.resultReg // just keep the LSB as it is + } + DataType.FLOAT -> { + actualResultReg2 = codeGen.registers.nextFree() + addInstr(result, IRInstruction(Opcode.FTOUB, IRDataType.FLOAT, reg1=actualResultReg2, fpReg1 = tr.resultFpReg), null) + } else -> throw AssemblyError("weird cast value type") } } DataType.BYTE -> { when(cast.value.type) { - DataType.UBYTE, DataType.UWORD, DataType.WORD -> { /* just keep the LSB as it is */ } - DataType.FLOAT -> addInstr(result, IRInstruction(Opcode.FTOSB, IRDataType.FLOAT, reg1=actualResultReg, fpReg1 = actualResultFpReg), null) + DataType.UBYTE, DataType.UWORD, DataType.WORD -> { + actualResultReg2 = tr.resultReg // just keep the LSB as it is + } + DataType.FLOAT -> { + actualResultReg2 = codeGen.registers.nextFree() + addInstr(result, IRInstruction(Opcode.FTOSB, IRDataType.FLOAT, reg1=actualResultReg2, fpReg1 = tr.resultFpReg), null) + } else -> throw AssemblyError("weird cast value type") } } @@ -245,15 +254,18 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { when(cast.value.type) { DataType.BYTE -> { // byte -> uword: sign extend - addInstr(result, IRInstruction(Opcode.EXTS, type = IRDataType.BYTE, reg1 = actualResultReg), null) + actualResultReg2 = tr.resultReg + addInstr(result, IRInstruction(Opcode.EXTS, type = IRDataType.BYTE, reg1 = actualResultReg2), null) } DataType.UBYTE -> { // ubyte -> uword: sign extend - addInstr(result, IRInstruction(Opcode.EXT, type = IRDataType.BYTE, reg1 = actualResultReg), null) + actualResultReg2 = tr.resultReg + addInstr(result, IRInstruction(Opcode.EXT, type = IRDataType.BYTE, reg1 = actualResultReg2), null) } DataType.WORD -> { } DataType.FLOAT -> { - addInstr(result, IRInstruction(Opcode.FTOUW, IRDataType.FLOAT, reg1=actualResultReg, fpReg1 = actualResultFpReg), null) + actualResultReg2 = codeGen.registers.nextFree() + addInstr(result, IRInstruction(Opcode.FTOUW, IRDataType.FLOAT, reg1=actualResultReg2, fpReg1 = tr.resultFpReg), null) } else -> throw AssemblyError("weird cast value type") } @@ -262,37 +274,50 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { when(cast.value.type) { DataType.BYTE -> { // byte -> word: sign extend - addInstr(result, IRInstruction(Opcode.EXTS, type = IRDataType.BYTE, reg1 = actualResultReg), null) + actualResultReg2 = tr.resultReg + addInstr(result, IRInstruction(Opcode.EXTS, type = IRDataType.BYTE, reg1 = actualResultReg2), null) } DataType.UBYTE -> { // byte -> word: sign extend - addInstr(result, IRInstruction(Opcode.EXT, type = IRDataType.BYTE, reg1 = actualResultReg), null) + actualResultReg2 = tr.resultReg + addInstr(result, IRInstruction(Opcode.EXT, type = IRDataType.BYTE, reg1 = actualResultReg2), null) } DataType.UWORD -> { } DataType.FLOAT -> { - addInstr(result, IRInstruction(Opcode.FTOSW, IRDataType.FLOAT, reg1=actualResultReg, fpReg1 = actualResultFpReg), null) + actualResultReg2 = codeGen.registers.nextFree() + addInstr(result, IRInstruction(Opcode.FTOSW, IRDataType.FLOAT, reg1=actualResultReg2, fpReg1 = tr.resultFpReg), null) } else -> throw AssemblyError("weird cast value type") } } DataType.FLOAT -> { - val instr = when(cast.value.type) { - DataType.UBYTE -> IRInstruction(Opcode.FFROMUB, IRDataType.FLOAT, reg1=actualResultReg, fpReg1 = actualResultFpReg) - DataType.BYTE -> IRInstruction(Opcode.FFROMSB, IRDataType.FLOAT, reg1=actualResultReg, fpReg1 = actualResultFpReg) - DataType.UWORD -> IRInstruction(Opcode.FFROMUW, IRDataType.FLOAT, reg1=actualResultReg, fpReg1 = actualResultFpReg) - DataType.WORD -> IRInstruction(Opcode.FFROMSW, IRDataType.FLOAT, reg1=actualResultReg, fpReg1 = actualResultFpReg) + actualResultFpReg2 = codeGen.registers.nextFreeFloat() + when(cast.value.type) { + DataType.UBYTE -> { + addInstr(result, IRInstruction(Opcode.FFROMUB, IRDataType.FLOAT, reg1=tr.resultReg, fpReg1 = actualResultFpReg2), null) + } + DataType.BYTE -> { + addInstr(result, IRInstruction(Opcode.FFROMSB, IRDataType.FLOAT, reg1=tr.resultReg, fpReg1 = actualResultFpReg2), null) + } + DataType.UWORD -> { + addInstr(result, IRInstruction(Opcode.FFROMUW, IRDataType.FLOAT, reg1=tr.resultReg, fpReg1 = actualResultFpReg2), null) + } + DataType.WORD -> { + addInstr(result, IRInstruction(Opcode.FFROMSW, IRDataType.FLOAT, reg1=tr.resultReg, fpReg1 = actualResultFpReg2), null) + } else -> throw AssemblyError("weird cast value type") } - addInstr(result, instr, null) } else -> throw AssemblyError("weird cast type") } - return ExpressionCodeResult(result, codeGen.irType(cast.type), actualResultReg, actualResultFpReg) + return ExpressionCodeResult(result, codeGen.irType(cast.type), actualResultReg2, actualResultFpReg2) } - private fun translate(binExpr: PtBinaryExpression, resultRegister: Int, resultFpRegister: Int): ExpressionCodeResult { + private fun translate(binExpr: PtBinaryExpression): ExpressionCodeResult { val vmDt = codeGen.irType(binExpr.left.type) val signed = binExpr.left.type in SignedDatatypes + val resultRegister = if(vmDt==IRDataType.FLOAT) -1 else codeGen.registers.nextFree() // TODO weg + val resultFpRegister = if(vmDt!=IRDataType.FLOAT) -1 else codeGen.registers.nextFreeFloat() // TODO weg // TODO fix the operator methods return type as well val code = when(binExpr.operator) { "+" -> operatorPlus(binExpr, vmDt, resultRegister, resultFpRegister) @@ -313,10 +338,13 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { ">=" -> operatorGreaterThan(binExpr, vmDt, resultRegister, signed, true) else -> throw AssemblyError("weird operator ${binExpr.operator}") } - return ExpressionCodeResult(code, vmDt, resultRegister, resultFpRegister) + return if(vmDt==IRDataType.FLOAT) + ExpressionCodeResult(code, vmDt, -1, resultFpRegister) + else + ExpressionCodeResult(code, vmDt, resultRegister, -1) } - fun translate(fcall: PtFunctionCall, resultRegister: Int, resultFpRegister: Int): ExpressionCodeResult { + fun translate(fcall: PtFunctionCall): ExpressionCodeResult { when (val callTarget = codeGen.symbolTable.flat.getValue(fcall.name)) { is StSub -> { val result = mutableListOf() @@ -327,27 +355,31 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { addInstr(result, IRInstruction(Opcode.STOREZM, paramDt, labelSymbol = symbol), null) } else { if (paramDt == IRDataType.FLOAT) { - val argFpReg = codeGen.registers.nextFreeFloat() - val translated = translateExpression(arg, -1, argFpReg) - addToResult(result, translated, -1, argFpReg) - addInstr(result, IRInstruction(Opcode.STOREM, paramDt, fpReg1 = argFpReg, labelSymbol = symbol), null) + val tr = translateExpression(arg) + addToResult(result, tr, -1, tr.resultFpReg) + addInstr(result, IRInstruction(Opcode.STOREM, paramDt, fpReg1 = tr.resultFpReg, labelSymbol = symbol), null) } else { - val argReg = codeGen.registers.nextFree() - val translated = translateExpression(arg, argReg, -1) - addToResult(result, translated, argReg, -1) - addInstr(result, IRInstruction(Opcode.STOREM, paramDt, reg1 = argReg, labelSymbol = symbol), null) + val tr = translateExpression(arg) + addToResult(result, tr, tr.resultReg, -1) + addInstr(result, IRInstruction(Opcode.STOREM, paramDt, reg1 = tr.resultReg, labelSymbol = symbol), null) } } } - if(fcall.void) - addInstr(result, IRInstruction(Opcode.CALL, labelSymbol=fcall.name), null) - else { - if(fcall.type==DataType.FLOAT) - addInstr(result, IRInstruction(Opcode.CALLRVAL, IRDataType.FLOAT, fpReg1=resultFpRegister, labelSymbol=fcall.name), null) - else - addInstr(result, IRInstruction(Opcode.CALLRVAL, codeGen.irType(fcall.type), reg1=resultRegister, labelSymbol=fcall.name), null) + return if(fcall.void) { + addInstr(result, IRInstruction(Opcode.CALL, labelSymbol = fcall.name), null) + ExpressionCodeResult(result, IRDataType.BYTE, -1, -1) + } else { + var resultReg = -1 + var resultFpReg = -1 + if(fcall.type==DataType.FLOAT) { + resultFpReg = codeGen.registers.nextFreeFloat() + addInstr(result, IRInstruction(Opcode.CALLRVAL, IRDataType.FLOAT, fpReg1=resultFpReg, labelSymbol=fcall.name), null) + } else { + resultReg = codeGen.registers.nextFree() + addInstr(result, IRInstruction(Opcode.CALLRVAL, codeGen.irType(fcall.type), reg1=resultReg, labelSymbol=fcall.name), null) + } + ExpressionCodeResult(result, codeGen.irType(fcall.type), resultReg, resultFpReg) } - return ExpressionCodeResult(result, if(fcall.void) IRDataType.BYTE else codeGen.irType(fcall.type), resultRegister, resultFpRegister) } is StRomSub -> { val result = mutableListOf() @@ -359,14 +391,14 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { } else { if (paramDt == IRDataType.FLOAT) throw AssemblyError("doesn't support float register argument in asm romsub") - val argReg = codeGen.registers.nextFree() - val translated = translateExpression(arg, argReg, -1) - addToResult(result, translated, argReg, -1) - addInstr(result, IRInstruction(Opcode.STORECPU, paramDt, reg1 = argReg, labelSymbol = paramRegStr), null) + val tr = translateExpression(arg) + addToResult(result, tr, tr.resultReg, -1) + addInstr(result, IRInstruction(Opcode.STORECPU, paramDt, reg1 = tr.resultReg, labelSymbol = paramRegStr), null) } } // just a regular call without using Vm register call convention: the value is returned in CPU registers! addInstr(result, IRInstruction(Opcode.CALL, value=callTarget.address.toInt()), null) + val resultReg = codeGen.registers.nextFree() if(!fcall.void) { when(callTarget.returns.size) { 0 -> throw AssemblyError("expect a return value") @@ -375,20 +407,20 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { throw AssemblyError("doesn't support float register result in asm romsub") val returns = callTarget.returns.single() val regStr = if(returns.register.registerOrPair!=null) returns.register.registerOrPair.toString() else returns.register.statusflag.toString() - addInstr(result, IRInstruction(Opcode.LOADCPU, codeGen.irType(fcall.type), reg1=resultRegister, labelSymbol = regStr), null) + addInstr(result, IRInstruction(Opcode.LOADCPU, codeGen.irType(fcall.type), reg1=resultReg, labelSymbol = regStr), null) } else -> { val returnRegister = callTarget.returns.singleOrNull{ it.register.registerOrPair!=null } if(returnRegister!=null) { // we skip the other values returned in the status flags. val regStr = returnRegister.register.registerOrPair.toString() - addInstr(result, IRInstruction(Opcode.LOADCPU, codeGen.irType(fcall.type), reg1=resultRegister, labelSymbol = regStr), null) + addInstr(result, IRInstruction(Opcode.LOADCPU, codeGen.irType(fcall.type), reg1=resultReg, labelSymbol = regStr), null) } else { val firstReturnRegister = callTarget.returns.firstOrNull{ it.register.registerOrPair!=null } if(firstReturnRegister!=null) { // we just take the first register return value and ignore the rest. val regStr = firstReturnRegister.register.registerOrPair.toString() - addInstr(result, IRInstruction(Opcode.LOADCPU, codeGen.irType(fcall.type), reg1=resultRegister, labelSymbol = regStr), null) + addInstr(result, IRInstruction(Opcode.LOADCPU, codeGen.irType(fcall.type), reg1=resultReg, labelSymbol = regStr), null) } else { throw AssemblyError("invalid number of return values from call") } @@ -396,7 +428,7 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { } } } - return ExpressionCodeResult(result, if(fcall.void) IRDataType.BYTE else codeGen.irType(fcall.type), resultRegister, resultFpRegister) + return ExpressionCodeResult(result, if(fcall.void) IRDataType.BYTE else codeGen.irType(fcall.type), resultReg, -1) } else -> throw AssemblyError("invalid node type") } @@ -411,14 +443,13 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { ): IRCodeChunks { val result = mutableListOf() if(vmDt==IRDataType.FLOAT) { - val leftFpReg = codeGen.registers.nextFreeFloat() - val rightFpReg = codeGen.registers.nextFreeFloat() + val leftTr = translateExpression(binExpr.left) + addToResult(result, leftTr, -1, leftTr.resultFpReg) + val rightTr = translateExpression(binExpr.right) + require(rightTr.resultFpReg!=leftTr.resultFpReg) + addToResult(result, rightTr, -1, rightTr.resultFpReg) + addInstr(result, IRInstruction(Opcode.FCOMP, IRDataType.FLOAT, reg1=resultRegister, fpReg1 = leftTr.resultFpReg, fpReg2 = rightTr.resultFpReg), null) val zeroRegister = codeGen.registers.nextFree() - var translated = translateExpression(binExpr.left, -1, leftFpReg) - addToResult(result, translated, -1, leftFpReg) - translated = translateExpression(binExpr.right, -1, rightFpReg) - addToResult(result, translated, -1, rightFpReg) - addInstr(result, IRInstruction(Opcode.FCOMP, IRDataType.FLOAT, reg1=resultRegister, fpReg1 = leftFpReg, fpReg2 = rightFpReg), null) addInstr(result, IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=zeroRegister, value=0), null) val ins = if (signed) { if (greaterEquals) Opcode.SGES else Opcode.SGTS @@ -428,10 +459,10 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { addInstr(result, IRInstruction(ins, IRDataType.BYTE, reg1 = resultRegister, reg2 = zeroRegister), null) } else { if(binExpr.left.type==DataType.STR && binExpr.right.type==DataType.STR) { - var translated = translateExpression(binExpr.left, SyscallRegisterBase, -1) - addToResult(result, translated, SyscallRegisterBase, -1) - translated = translateExpression(binExpr.right, SyscallRegisterBase+1, -1) - addToResult(result, translated, SyscallRegisterBase+1, -1) + var tr = translateExpression(binExpr.left) + addToResult(result, tr, SyscallRegisterBase, -1) + tr = translateExpression(binExpr.right) + addToResult(result, tr, SyscallRegisterBase+1, -1) result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.SYSCALL, value = IMSyscall.COMPARE_STRINGS.number) if(resultRegister!=0) @@ -444,10 +475,10 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { } } else { val rightResultReg = codeGen.registers.nextFree() - var translated = translateExpression(binExpr.left, resultRegister, -1) - addToResult(result, translated, resultRegister, -1) - translated = translateExpression(binExpr.right, rightResultReg, -1) - addToResult(result, translated, rightResultReg, -1) + var tr = translateExpression(binExpr.left) + addToResult(result, tr, resultRegister, -1) + tr = translateExpression(binExpr.right) + addToResult(result, tr, rightResultReg, -1) val ins = if (signed) { if (greaterEquals) Opcode.SGES else Opcode.SGTS } else { @@ -468,14 +499,13 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { ): IRCodeChunks { val result = mutableListOf() if(vmDt==IRDataType.FLOAT) { - val leftFpReg = codeGen.registers.nextFreeFloat() - val rightFpReg = codeGen.registers.nextFreeFloat() + val leftTr = translateExpression(binExpr.left) + addToResult(result, leftTr, -1, leftTr.resultFpReg) + val rightTr = translateExpression(binExpr.right) + require(rightTr.resultFpReg!=leftTr.resultFpReg) + addToResult(result, rightTr, -1, rightTr.resultFpReg) + addInstr(result, IRInstruction(Opcode.FCOMP, IRDataType.FLOAT, reg1=resultRegister, fpReg1 = leftTr.resultFpReg, fpReg2 = rightTr.resultFpReg), null) val zeroRegister = codeGen.registers.nextFree() - var tr = translateExpression(binExpr.left, -1, leftFpReg) - addToResult(result, tr, -1, leftFpReg) - tr = translateExpression(binExpr.right, -1, rightFpReg) - addToResult(result, tr, -1, rightFpReg) - addInstr(result, IRInstruction(Opcode.FCOMP, IRDataType.FLOAT, reg1=resultRegister, fpReg1 = leftFpReg, fpReg2 = rightFpReg), null) addInstr(result, IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=zeroRegister, value=0), null) val ins = if (signed) { if (lessEquals) Opcode.SLES else Opcode.SLTS @@ -485,9 +515,9 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { addInstr(result, IRInstruction(ins, IRDataType.BYTE, reg1 = resultRegister, reg2 = zeroRegister), null) } else { if(binExpr.left.type==DataType.STR && binExpr.right.type==DataType.STR) { - var tr = translateExpression(binExpr.left, SyscallRegisterBase, -1) + var tr = translateExpression(binExpr.left) addToResult(result, tr, SyscallRegisterBase, -1) - tr = translateExpression(binExpr.right, SyscallRegisterBase+1, -1) + tr = translateExpression(binExpr.right) addToResult(result, tr, SyscallRegisterBase+1, -1) result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.SYSCALL, value = IMSyscall.COMPARE_STRINGS.number) @@ -501,9 +531,9 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { } } else { val rightResultReg = codeGen.registers.nextFree() - var tr = translateExpression(binExpr.left, resultRegister, -1) + var tr = translateExpression(binExpr.left) addToResult(result, tr, resultRegister, -1) - tr = translateExpression(binExpr.right, rightResultReg, -1) + tr = translateExpression(binExpr.right) addToResult(result, tr, rightResultReg, -1) val ins = if (signed) { if (lessEquals) Opcode.SLES else Opcode.SLTS @@ -519,28 +549,27 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { private fun operatorEquals(binExpr: PtBinaryExpression, vmDt: IRDataType, resultRegister: Int, notEquals: Boolean): IRCodeChunks { val result = mutableListOf() if(vmDt==IRDataType.FLOAT) { - val leftFpReg = codeGen.registers.nextFreeFloat() - val rightFpReg = codeGen.registers.nextFreeFloat() - var tr = translateExpression(binExpr.left, -1, leftFpReg) - addToResult(result, tr, -1, leftFpReg) - tr = translateExpression(binExpr.right, -1, rightFpReg) - addToResult(result, tr, -1, rightFpReg) + val leftTr = translateExpression(binExpr.left) + addToResult(result, leftTr, -1, leftTr.resultFpReg) + val rightTr = translateExpression(binExpr.right) + require(rightTr.resultFpReg!=leftTr.resultFpReg) + addToResult(result, rightTr, -1, rightTr.resultFpReg) if (notEquals) { - addInstr(result, IRInstruction(Opcode.FCOMP, IRDataType.FLOAT, reg1=resultRegister, fpReg1 = leftFpReg, fpReg2 = rightFpReg), null) + addInstr(result, IRInstruction(Opcode.FCOMP, IRDataType.FLOAT, reg1=resultRegister, fpReg1 = leftTr.resultFpReg, fpReg2 = rightTr.resultFpReg), null) } else { val label = codeGen.createLabelName() val valueReg = codeGen.registers.nextFree() addInstr(result, IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=resultRegister, value=1), null) - addInstr(result, IRInstruction(Opcode.FCOMP, IRDataType.FLOAT, reg1=valueReg, fpReg1 = leftFpReg, fpReg2 = rightFpReg), null) + addInstr(result, IRInstruction(Opcode.FCOMP, IRDataType.FLOAT, reg1=valueReg, fpReg1 = leftTr.resultFpReg, fpReg2 = rightTr.resultFpReg), null) addInstr(result, IRInstruction(Opcode.BZ, IRDataType.BYTE, reg1=valueReg, labelSymbol = label), null) addInstr(result, IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=resultRegister, value=0), null) result += IRCodeChunk(label, null) } } else { if(binExpr.left.type==DataType.STR && binExpr.right.type==DataType.STR) { - var tr = translateExpression(binExpr.left, SyscallRegisterBase, -1) + var tr = translateExpression(binExpr.left) addToResult(result, tr, SyscallRegisterBase, -1) - tr = translateExpression(binExpr.right, SyscallRegisterBase+1, -1) + tr = translateExpression(binExpr.right) addToResult(result, tr, SyscallRegisterBase+1, -1) result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.SYSCALL, value = IMSyscall.COMPARE_STRINGS.number) @@ -552,15 +581,15 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { } } else { if(constValue(binExpr.right)==0.0) { - val tr = translateExpression(binExpr.left, resultRegister, -1) + val tr = translateExpression(binExpr.left) addToResult(result, tr, resultRegister, -1) val opcode = if (notEquals) Opcode.SNZ else Opcode.SZ addInstr(result, IRInstruction(opcode, vmDt, reg1 = resultRegister, reg2 = resultRegister), null) } else { val rightResultReg = codeGen.registers.nextFree() - var tr = translateExpression(binExpr.left, resultRegister, -1) + var tr = translateExpression(binExpr.left) addToResult(result, tr, resultRegister, -1) - tr = translateExpression(binExpr.right, rightResultReg, -1) + tr = translateExpression(binExpr.right) addToResult(result, tr, rightResultReg, -1) val opcode = if (notEquals) Opcode.SNE else Opcode.SEQ addInstr(result, IRInstruction(opcode, vmDt, reg1 = resultRegister, reg2 = rightResultReg), null) @@ -573,15 +602,15 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { private fun operatorShiftRight(binExpr: PtBinaryExpression, vmDt: IRDataType, resultRegister: Int, signed: Boolean): IRCodeChunks { val result = mutableListOf() if(codeGen.isOne(binExpr.right)) { - val tr = translateExpression(binExpr.left, resultRegister, -1) + val tr = translateExpression(binExpr.left) addToResult(result, tr, resultRegister, -1) val opc = if (signed) Opcode.ASR else Opcode.LSR addInstr(result, IRInstruction(opc, vmDt, reg1 = resultRegister), null) } else { val rightResultReg = codeGen.registers.nextFree() - var tr = translateExpression(binExpr.left, resultRegister, -1) + var tr = translateExpression(binExpr.left) addToResult(result, tr, resultRegister, -1) - tr = translateExpression(binExpr.right, rightResultReg, -1) + tr = translateExpression(binExpr.right) addToResult(result, tr, rightResultReg, -1) val opc = if (signed) Opcode.ASRN else Opcode.LSRN addInstr(result, IRInstruction(opc, vmDt, reg1 = resultRegister, reg2 = rightResultReg), null) @@ -599,14 +628,13 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { IRInstruction(opc, vmDt, labelSymbol = symbol) addInstr(result, ins, null) } else { - val operandReg = codeGen.registers.nextFree() - val tr = translateExpression(operand, operandReg, -1) - addToResult(result, tr, operandReg, -1) + val tr = translateExpression(operand) + addToResult(result, tr, tr.resultReg, -1) val opc = if (signed) Opcode.ASRNM else Opcode.LSRNM val ins = if(knownAddress!=null) - IRInstruction(opc, vmDt, reg1 = operandReg, value=knownAddress) + IRInstruction(opc, vmDt, reg1 = tr.resultReg, value=knownAddress) else - IRInstruction(opc, vmDt, reg1 = operandReg, labelSymbol = symbol) + IRInstruction(opc, vmDt, reg1 = tr.resultReg, labelSymbol = symbol) addInstr(result, ins, null) } return result @@ -615,14 +643,14 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { private fun operatorShiftLeft(binExpr: PtBinaryExpression, vmDt: IRDataType, resultRegister: Int): IRCodeChunks { val result = mutableListOf() if(codeGen.isOne(binExpr.right)){ - val tr = translateExpression(binExpr.left, resultRegister, -1) + val tr = translateExpression(binExpr.left) addToResult(result, tr, resultRegister, -1) addInstr(result, IRInstruction(Opcode.LSL, vmDt, reg1=resultRegister), null) } else { val rightResultReg = codeGen.registers.nextFree() - var tr = translateExpression(binExpr.left, resultRegister, -1) + var tr = translateExpression(binExpr.left) addToResult(result, tr, resultRegister, -1) - tr = translateExpression(binExpr.right, rightResultReg, -1) + tr = translateExpression(binExpr.right) addToResult(result, tr, rightResultReg, -1) addInstr(result, IRInstruction(Opcode.LSLN, vmDt, reg1=resultRegister, rightResultReg), null) } @@ -638,14 +666,13 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { IRInstruction(Opcode.LSLM, vmDt, labelSymbol = symbol) , null) } else { - val operandReg = codeGen.registers.nextFree() - val tr = translateExpression(operand, operandReg, -1) - addToResult(result, tr, operandReg, -1) + val tr = translateExpression(operand) + addToResult(result, tr, tr.resultReg, -1) addInstr(result, if(knownAddress!=null) - IRInstruction(Opcode.LSLNM, vmDt, reg1=operandReg, value=knownAddress) - else - IRInstruction(Opcode.LSLNM, vmDt, reg1=operandReg, labelSymbol = symbol) - ,null) + IRInstruction(Opcode.LSLNM, vmDt, reg1=tr.resultReg, value=knownAddress) + else + IRInstruction(Opcode.LSLNM, vmDt, reg1=tr.resultReg, labelSymbol = symbol) + ,null) } return result } @@ -653,14 +680,14 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { private fun operatorXor(binExpr: PtBinaryExpression, vmDt: IRDataType, resultRegister: Int): IRCodeChunks { val result = mutableListOf() if(binExpr.right is PtNumber) { - val tr = translateExpression(binExpr.left, resultRegister, -1) + val tr = translateExpression(binExpr.left) addToResult(result, tr, resultRegister, -1) addInstr(result, IRInstruction(Opcode.XOR, vmDt, reg1 = resultRegister, value=(binExpr.right as PtNumber).number.toInt()), null) } else { val rightResultReg = codeGen.registers.nextFree() - var tr = translateExpression(binExpr.left, resultRegister, -1) + var tr = translateExpression(binExpr.left) addToResult(result, tr, resultRegister, -1) - tr = translateExpression(binExpr.right, rightResultReg, -1) + tr = translateExpression(binExpr.right) addToResult(result, tr, rightResultReg, -1) addInstr(result, IRInstruction(Opcode.XORR, vmDt, reg1 = resultRegister, reg2 = rightResultReg), null) } @@ -669,28 +696,27 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { internal fun operatorXorInplace(knownAddress: Int?, symbol: String?, vmDt: IRDataType, operand: PtExpression): IRCodeChunks { val result = mutableListOf() - val operandReg = codeGen.registers.nextFree() - val tr = translateExpression(operand, operandReg, -1) - addToResult(result, tr, operandReg, -1) + val tr = translateExpression(operand) + addToResult(result, tr, tr.resultReg, -1) addInstr(result, if(knownAddress!=null) - IRInstruction(Opcode.XORM, vmDt, reg1=operandReg, value = knownAddress) - else - IRInstruction(Opcode.XORM, vmDt, reg1=operandReg, labelSymbol = symbol) - ,null) + IRInstruction(Opcode.XORM, vmDt, reg1=tr.resultReg, value = knownAddress) + else + IRInstruction(Opcode.XORM, vmDt, reg1=tr.resultReg, labelSymbol = symbol) + ,null) return result } private fun operatorAnd(binExpr: PtBinaryExpression, vmDt: IRDataType, resultRegister: Int): IRCodeChunks { val result = mutableListOf() if(binExpr.right is PtNumber) { - val tr = translateExpression(binExpr.left, resultRegister, -1) + val tr = translateExpression(binExpr.left) addToResult(result, tr, resultRegister, -1) addInstr(result, IRInstruction(Opcode.AND, vmDt, reg1 = resultRegister, value=(binExpr.right as PtNumber).number.toInt()), null) } else { val rightResultReg = codeGen.registers.nextFree() - var tr = translateExpression(binExpr.left, resultRegister, -1) + var tr = translateExpression(binExpr.left) addToResult(result, tr, resultRegister, -1) - tr= translateExpression(binExpr.right, rightResultReg, -1) + tr= translateExpression(binExpr.right) addToResult(result, tr, rightResultReg, -1) addInstr(result, IRInstruction(Opcode.ANDR, vmDt, reg1 = resultRegister, reg2 = rightResultReg), null) } @@ -699,28 +725,27 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { internal fun operatorAndInplace(knownAddress: Int?, symbol: String?, vmDt: IRDataType, operand: PtExpression): IRCodeChunks { val result = mutableListOf() - val operandReg = codeGen.registers.nextFree() - val tr = translateExpression(operand, operandReg, -1) - addToResult(result, tr, operandReg, -1) + val tr = translateExpression(operand) + addToResult(result, tr, tr.resultReg, -1) addInstr(result, if(knownAddress!=null) - IRInstruction(Opcode.ANDM, vmDt, reg1=operandReg, value=knownAddress) - else - IRInstruction(Opcode.ANDM, vmDt, reg1=operandReg, labelSymbol = symbol) - ,null) + IRInstruction(Opcode.ANDM, vmDt, reg1=tr.resultReg, value=knownAddress) + else + IRInstruction(Opcode.ANDM, vmDt, reg1=tr.resultReg, labelSymbol = symbol) + ,null) return result } private fun operatorOr(binExpr: PtBinaryExpression, vmDt: IRDataType, resultRegister: Int): IRCodeChunks { val result = mutableListOf() if(binExpr.right is PtNumber) { - val tr = translateExpression(binExpr.left, resultRegister, -1) + val tr = translateExpression(binExpr.left) addToResult(result, tr, resultRegister, -1) addInstr(result, IRInstruction(Opcode.OR, vmDt, reg1 = resultRegister, value=(binExpr.right as PtNumber).number.toInt()), null) } else { val rightResultReg = codeGen.registers.nextFree() - var tr = translateExpression(binExpr.left, resultRegister, -1) + var tr = translateExpression(binExpr.left) addToResult(result, tr, resultRegister, -1) - tr = translateExpression(binExpr.right, rightResultReg, -1) + tr = translateExpression(binExpr.right) addToResult(result, tr, rightResultReg, -1) addInstr(result, IRInstruction(Opcode.ORR, vmDt, reg1 = resultRegister, reg2 = rightResultReg), null) } @@ -729,14 +754,13 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { internal fun operatorOrInplace(knownAddress: Int?, symbol: String?, vmDt: IRDataType, operand: PtExpression): IRCodeChunks { val result = mutableListOf() - val operandReg = codeGen.registers.nextFree() - val tr = translateExpression(operand, operandReg, -1) - addToResult(result, tr, operandReg, -1) + val tr = translateExpression(operand) + addToResult(result, tr, tr.resultReg, -1) addInstr(result, if(knownAddress!=null) - IRInstruction(Opcode.ORM, vmDt, reg1=operandReg, value = knownAddress) - else - IRInstruction(Opcode.ORM, vmDt, reg1=operandReg, labelSymbol = symbol) - , null) + IRInstruction(Opcode.ORM, vmDt, reg1=tr.resultReg, value = knownAddress) + else + IRInstruction(Opcode.ORM, vmDt, reg1=tr.resultReg, labelSymbol = symbol) + , null) return result } @@ -745,13 +769,13 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { val result = mutableListOf() val rightResultReg = codeGen.registers.nextFree() if(binExpr.right is PtNumber) { - val tr = translateExpression(binExpr.left, resultRegister, -1) + val tr = translateExpression(binExpr.left) addToResult(result, tr, resultRegister, -1) addInstr(result, IRInstruction(Opcode.MOD, vmDt, reg1 = resultRegister, value=(binExpr.right as PtNumber).number.toInt()), null) } else { - var tr = translateExpression(binExpr.left, resultRegister, -1) + var tr = translateExpression(binExpr.left) addToResult(result, tr, resultRegister, -1) - tr = translateExpression(binExpr.right, rightResultReg, -1) + tr = translateExpression(binExpr.right) addToResult(result, tr, rightResultReg, -1) addInstr(result, IRInstruction(Opcode.MODR, vmDt, reg1 = resultRegister, reg2 = rightResultReg), null) } @@ -767,48 +791,48 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { val constFactorRight = binExpr.right as? PtNumber if(vmDt==IRDataType.FLOAT) { if(constFactorRight!=null && constFactorRight.type!=DataType.FLOAT) { - val tr = translateExpression(binExpr.left, -1, resultFpRegister) + val tr = translateExpression(binExpr.left) addToResult(result, tr, -1, resultFpRegister) val factor = constFactorRight.number.toFloat() result += codeGen.divideByConstFloat(resultFpRegister, factor) } else { val rightResultFpReg = codeGen.registers.nextFreeFloat() - var tr = translateExpression(binExpr.left, -1, resultFpRegister) + var tr = translateExpression(binExpr.left) addToResult(result, tr, -1, resultFpRegister) - tr = translateExpression(binExpr.right, -1, rightResultFpReg) + tr = translateExpression(binExpr.right) addToResult(result, tr, -1, rightResultFpReg) addInstr(result, if(signed) - IRInstruction(Opcode.DIVSR, vmDt, fpReg1 = resultFpRegister, fpReg2=rightResultFpReg) - else - IRInstruction(Opcode.DIVR, vmDt, fpReg1 = resultFpRegister, fpReg2=rightResultFpReg) - , null) + IRInstruction(Opcode.DIVSR, vmDt, fpReg1 = resultFpRegister, fpReg2=rightResultFpReg) + else + IRInstruction(Opcode.DIVR, vmDt, fpReg1 = resultFpRegister, fpReg2=rightResultFpReg) + , null) } } else { if(constFactorRight!=null && constFactorRight.type!=DataType.FLOAT) { - val tr = translateExpression(binExpr.left, resultRegister, -1) + val tr = translateExpression(binExpr.left) addToResult(result, tr, resultRegister, -1) val factor = constFactorRight.number.toInt() result += codeGen.divideByConst(vmDt, resultRegister, factor, signed) } else { val rightResultReg = codeGen.registers.nextFree() if(binExpr.right is PtNumber) { - val tr = translateExpression(binExpr.left, resultRegister, -1) + val tr = translateExpression(binExpr.left) addToResult(result, tr, resultRegister, -1) addInstr(result, if (signed) - IRInstruction(Opcode.DIVS, vmDt, reg1 = resultRegister, value=(binExpr.right as PtNumber).number.toInt()) - else - IRInstruction(Opcode.DIV, vmDt, reg1 = resultRegister, value=(binExpr.right as PtNumber).number.toInt()) - , null) + IRInstruction(Opcode.DIVS, vmDt, reg1 = resultRegister, value=(binExpr.right as PtNumber).number.toInt()) + else + IRInstruction(Opcode.DIV, vmDt, reg1 = resultRegister, value=(binExpr.right as PtNumber).number.toInt()) + , null) } else { - var tr = translateExpression(binExpr.left, resultRegister, -1) + var tr = translateExpression(binExpr.left) addToResult(result, tr, resultRegister, -1) - tr = translateExpression(binExpr.right, rightResultReg, -1) + tr = translateExpression(binExpr.right) addToResult(result, tr, rightResultReg, -1) addInstr(result, if (signed) - IRInstruction(Opcode.DIVSR, vmDt, reg1 = resultRegister, reg2 = rightResultReg) - else - IRInstruction(Opcode.DIVR, vmDt, reg1 = resultRegister, reg2 = rightResultReg) - , null) + IRInstruction(Opcode.DIVSR, vmDt, reg1 = resultRegister, reg2 = rightResultReg) + else + IRInstruction(Opcode.DIVR, vmDt, reg1 = resultRegister, reg2 = rightResultReg) + , null) } } } @@ -823,20 +847,19 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { val factor = constFactorRight.number.toFloat() result += codeGen.divideByConstFloatInplace(knownAddress, symbol, factor) } else { - val operandFpReg = codeGen.registers.nextFreeFloat() - val tr = translateExpression(operand, -1, operandFpReg) - addToResult(result, tr, -1, operandFpReg) + val tr = translateExpression(operand) + addToResult(result, tr, -1, tr.resultFpReg) val ins = if(signed) { if(knownAddress!=null) - IRInstruction(Opcode.DIVSM, vmDt, fpReg1 = operandFpReg, value = knownAddress) + IRInstruction(Opcode.DIVSM, vmDt, fpReg1 = tr.resultFpReg, value = knownAddress) else - IRInstruction(Opcode.DIVSM, vmDt, fpReg1 = operandFpReg, labelSymbol = symbol) + IRInstruction(Opcode.DIVSM, vmDt, fpReg1 = tr.resultFpReg, labelSymbol = symbol) } else { if(knownAddress!=null) - IRInstruction(Opcode.DIVM, vmDt, fpReg1 = operandFpReg, value = knownAddress) + IRInstruction(Opcode.DIVM, vmDt, fpReg1 = tr.resultFpReg, value = knownAddress) else - IRInstruction(Opcode.DIVM, vmDt, fpReg1 = operandFpReg, labelSymbol = symbol) + IRInstruction(Opcode.DIVM, vmDt, fpReg1 = tr.resultFpReg, labelSymbol = symbol) } addInstr(result, ins, null) } @@ -845,20 +868,19 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { val factor = constFactorRight.number.toInt() result += codeGen.divideByConstInplace(vmDt, knownAddress, symbol, factor, signed) } else { - val operandReg = codeGen.registers.nextFree() - val tr = translateExpression(operand, operandReg, -1) - addToResult(result, tr, operandReg, -1) + val tr = translateExpression(operand) + addToResult(result, tr, tr.resultReg, -1) val ins = if(signed) { if(knownAddress!=null) - IRInstruction(Opcode.DIVSM, vmDt, reg1 = operandReg, value = knownAddress) + IRInstruction(Opcode.DIVSM, vmDt, reg1 = tr.resultReg, value = knownAddress) else - IRInstruction(Opcode.DIVSM, vmDt, reg1 = operandReg, labelSymbol = symbol) + IRInstruction(Opcode.DIVSM, vmDt, reg1 = tr.resultReg, labelSymbol = symbol) } else { if(knownAddress!=null) - IRInstruction(Opcode.DIVM, vmDt, reg1 = operandReg, value = knownAddress) + IRInstruction(Opcode.DIVM, vmDt, reg1 = tr.resultReg, value = knownAddress) else - IRInstruction(Opcode.DIVM, vmDt, reg1 = operandReg, labelSymbol = symbol) + IRInstruction(Opcode.DIVM, vmDt, reg1 = tr.resultReg, labelSymbol = symbol) } addInstr(result, ins, null) } @@ -872,39 +894,39 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { val constFactorRight = binExpr.right as? PtNumber if(vmDt==IRDataType.FLOAT) { if(constFactorLeft!=null) { - val tr = translateExpression(binExpr.right, -1, resultFpRegister) + val tr = translateExpression(binExpr.right) addToResult(result, tr, -1, resultFpRegister) val factor = constFactorLeft.number.toFloat() result += codeGen.multiplyByConstFloat(resultFpRegister, factor) } else if(constFactorRight!=null) { - val tr = translateExpression(binExpr.left, -1, resultFpRegister) + val tr = translateExpression(binExpr.left) addToResult(result, tr, -1, resultFpRegister) val factor = constFactorRight.number.toFloat() result += codeGen.multiplyByConstFloat(resultFpRegister, factor) } else { val rightResultFpReg = codeGen.registers.nextFreeFloat() - var tr = translateExpression(binExpr.left, -1, resultFpRegister) + var tr = translateExpression(binExpr.left) addToResult(result, tr, -1, resultFpRegister) - tr = translateExpression(binExpr.right, -1, rightResultFpReg) + tr = translateExpression(binExpr.right) addToResult(result, tr, -1, rightResultFpReg) addInstr(result, IRInstruction(Opcode.MULR, vmDt, fpReg1 = resultFpRegister, fpReg2 = rightResultFpReg), null) } } else { if(constFactorLeft!=null && constFactorLeft.type!=DataType.FLOAT) { - val tr = translateExpression(binExpr.right, resultRegister, -1) + val tr = translateExpression(binExpr.right) addToResult(result, tr, resultRegister, -1) val factor = constFactorLeft.number.toInt() result += codeGen.multiplyByConst(vmDt, resultRegister, factor) } else if(constFactorRight!=null && constFactorRight.type!=DataType.FLOAT) { - val tr = translateExpression(binExpr.left, resultRegister, -1) + val tr = translateExpression(binExpr.left) addToResult(result, tr, resultRegister, -1) val factor = constFactorRight.number.toInt() result += codeGen.multiplyByConst(vmDt, resultRegister, factor) } else { val rightResultReg = codeGen.registers.nextFree() - var tr = translateExpression(binExpr.left, resultRegister, -1) + var tr = translateExpression(binExpr.left) addToResult(result, tr, resultRegister, -1) - tr = translateExpression(binExpr.right, rightResultReg, -1) + tr = translateExpression(binExpr.right) addToResult(result, tr, rightResultReg, -1) addInstr(result, IRInstruction(Opcode.MULR, vmDt, reg1 = resultRegister, reg2 = rightResultReg), null) } @@ -920,13 +942,12 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { val factor = constFactorRight.number.toFloat() result += codeGen.multiplyByConstFloatInplace(knownAddress, symbol, factor) } else { - val operandFpReg = codeGen.registers.nextFreeFloat() - val tr = translateExpression(operand, -1, operandFpReg) - addToResult(result, tr, -1, operandFpReg) + val tr = translateExpression(operand) + addToResult(result, tr, -1, tr.resultFpReg) addInstr(result, if(knownAddress!=null) - IRInstruction(Opcode.MULM, vmDt, fpReg1 = operandFpReg, value = knownAddress) + IRInstruction(Opcode.MULM, vmDt, fpReg1 = tr.resultFpReg, value = knownAddress) else - IRInstruction(Opcode.MULM, vmDt, fpReg1 = operandFpReg, labelSymbol = symbol) + IRInstruction(Opcode.MULM, vmDt, fpReg1 = tr.resultFpReg, labelSymbol = symbol) , null) } } else { @@ -934,13 +955,12 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { val factor = constFactorRight.number.toInt() result += codeGen.multiplyByConstInplace(vmDt, knownAddress, symbol, factor) } else { - val operandReg = codeGen.registers.nextFree() - val tr = translateExpression(operand, operandReg, -1) - addToResult(result, tr, operandReg, -1) + val tr = translateExpression(operand) + addToResult(result, tr, tr.resultReg, -1) addInstr(result, if(knownAddress!=null) - IRInstruction(Opcode.MULM, vmDt, reg1=operandReg, value = knownAddress) + IRInstruction(Opcode.MULM, vmDt, reg1=tr.resultReg, value = knownAddress) else - IRInstruction(Opcode.MULM, vmDt, reg1=operandReg, labelSymbol = symbol) + IRInstruction(Opcode.MULM, vmDt, reg1=tr.resultReg, labelSymbol = symbol) , null) } } @@ -951,40 +971,40 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { val result = mutableListOf() if(vmDt==IRDataType.FLOAT) { if((binExpr.right as? PtNumber)?.number==1.0) { - val tr = translateExpression(binExpr.left, -1, resultFpRegister) + val tr = translateExpression(binExpr.left) addToResult(result, tr, -1, resultFpRegister) addInstr(result, IRInstruction(Opcode.DEC, vmDt, fpReg1 = resultFpRegister), null) } else { if(binExpr.right is PtNumber) { - val tr = translateExpression(binExpr.left, -1, resultFpRegister) + val tr = translateExpression(binExpr.left) addToResult(result, tr, -1, resultFpRegister) addInstr(result, IRInstruction(Opcode.SUB, vmDt, fpReg1 = resultFpRegister, fpValue = (binExpr.right as PtNumber).number.toFloat()), null) } else { val rightResultFpReg = codeGen.registers.nextFreeFloat() - var tr = translateExpression(binExpr.left, -1, resultFpRegister) + var tr = translateExpression(binExpr.left) addToResult(result, tr, -1, resultFpRegister) - tr = translateExpression(binExpr.right, -1, rightResultFpReg) + tr = translateExpression(binExpr.right) addToResult(result, tr, -1, rightResultFpReg) addInstr(result, IRInstruction(Opcode.SUBR, vmDt, fpReg1 = resultFpRegister, fpReg2 = rightResultFpReg), null) } } } else { if((binExpr.right as? PtNumber)?.number==1.0) { - val tr = translateExpression(binExpr.left, resultRegister, -1) + val tr = translateExpression(binExpr.left) addToResult(result, tr, resultRegister, -1) addInstr(result, IRInstruction(Opcode.DEC, vmDt, reg1=resultRegister), null) } else { if(binExpr.right is PtNumber) { - val tr = translateExpression(binExpr.left, resultRegister, -1) + val tr = translateExpression(binExpr.left,) addToResult(result, tr, resultRegister, -1) addInstr(result, IRInstruction(Opcode.SUB, vmDt, reg1 = resultRegister, value = (binExpr.right as PtNumber).number.toInt()), null) } else { val rightResultReg = codeGen.registers.nextFree() - var tr = translateExpression(binExpr.left, resultRegister, -1) + var tr = translateExpression(binExpr.left) addToResult(result, tr, resultRegister, -1) - tr = translateExpression(binExpr.right, rightResultReg, -1) + tr = translateExpression(binExpr.right) addToResult(result, tr, rightResultReg, -1) addInstr(result, IRInstruction(Opcode.SUBR, vmDt, reg1 = resultRegister, reg2 = rightResultReg), null) } @@ -1004,13 +1024,12 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { , null) } else { - val operandFpReg = codeGen.registers.nextFreeFloat() - val tr = translateExpression(operand, -1, operandFpReg) - addToResult(result, tr, -1, operandFpReg) + val tr = translateExpression(operand) + addToResult(result, tr, -1, tr.resultFpReg) addInstr(result, if(knownAddress!=null) - IRInstruction(Opcode.SUBM, vmDt, fpReg1=operandFpReg, value=knownAddress) + IRInstruction(Opcode.SUBM, vmDt, fpReg1=tr.resultFpReg, value=knownAddress) else - IRInstruction(Opcode.SUBM, vmDt, fpReg1=operandFpReg, labelSymbol = symbol) + IRInstruction(Opcode.SUBM, vmDt, fpReg1=tr.resultFpReg, labelSymbol = symbol) , null) } } else { @@ -1022,13 +1041,12 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { , null) } else { - val operandReg = codeGen.registers.nextFree() - val tr = translateExpression(operand, operandReg, -1) - addToResult(result, tr, operandReg, -1) + val tr = translateExpression(operand) + addToResult(result, tr, tr.resultReg, -1) addInstr(result, if(knownAddress!=null) - IRInstruction(Opcode.SUBM, vmDt, reg1=operandReg, value = knownAddress) + IRInstruction(Opcode.SUBM, vmDt, reg1=tr.resultReg, value = knownAddress) else - IRInstruction(Opcode.SUBM, vmDt, reg1=operandReg, labelSymbol = symbol) + IRInstruction(Opcode.SUBM, vmDt, reg1=tr.resultReg, labelSymbol = symbol) , null) } } @@ -1039,50 +1057,50 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { val result = mutableListOf() if(vmDt==IRDataType.FLOAT) { if((binExpr.left as? PtNumber)?.number==1.0) { - val tr = translateExpression(binExpr.right, -1, resultFpRegister) + val tr = translateExpression(binExpr.right) addToResult(result, tr, -1, resultFpRegister) addInstr(result, IRInstruction(Opcode.INC, vmDt, fpReg1=resultFpRegister), null) } else if((binExpr.right as? PtNumber)?.number==1.0) { - val tr = translateExpression(binExpr.left, -1, resultFpRegister) + val tr = translateExpression(binExpr.left) addToResult(result, tr, -1, resultFpRegister) addInstr(result, IRInstruction(Opcode.INC, vmDt, fpReg1=resultFpRegister), null) } else { if(binExpr.right is PtNumber) { - val tr = translateExpression(binExpr.left, -1, resultFpRegister) + val tr = translateExpression(binExpr.left) addToResult(result, tr, -1, resultFpRegister) addInstr(result, IRInstruction(Opcode.ADD, vmDt, fpReg1 = resultFpRegister, fpValue = (binExpr.right as PtNumber).number.toFloat()), null) } else { val rightResultFpReg = codeGen.registers.nextFreeFloat() - var tr = translateExpression(binExpr.left, -1, resultFpRegister) + var tr = translateExpression(binExpr.left) addToResult(result, tr, -1, resultFpRegister) - tr = translateExpression(binExpr.right, -1, rightResultFpReg) + tr = translateExpression(binExpr.right) addToResult(result, tr, -1, rightResultFpReg) addInstr(result, IRInstruction(Opcode.ADDR, vmDt, fpReg1 = resultFpRegister, fpReg2 = rightResultFpReg), null) } } } else { if((binExpr.left as? PtNumber)?.number==1.0) { - val tr = translateExpression(binExpr.right, resultRegister, -1) + val tr = translateExpression(binExpr.right) addToResult(result, tr, resultRegister, -1) addInstr(result, IRInstruction(Opcode.INC, vmDt, reg1=resultRegister), null) } else if((binExpr.right as? PtNumber)?.number==1.0) { - val tr = translateExpression(binExpr.left, resultRegister, -1) + val tr = translateExpression(binExpr.left) addToResult(result, tr, resultRegister, -1) addInstr(result, IRInstruction(Opcode.INC, vmDt, reg1=resultRegister), null) } else { if(binExpr.right is PtNumber) { - val tr = translateExpression(binExpr.left, resultRegister, -1) + val tr = translateExpression(binExpr.left) addToResult(result, tr, resultRegister, -1) addInstr(result, IRInstruction(Opcode.ADD, vmDt, reg1 = resultRegister, value=(binExpr.right as PtNumber).number.toInt()), null) } else { val rightResultReg = codeGen.registers.nextFree() - var tr = translateExpression(binExpr.left, resultRegister, -1) + var tr = translateExpression(binExpr.left) addToResult(result, tr, resultRegister, -1) - tr = translateExpression(binExpr.right, rightResultReg, -1) + tr = translateExpression(binExpr.right) addToResult(result, tr, rightResultReg, -1) addInstr(result, IRInstruction(Opcode.ADDR, vmDt, reg1 = resultRegister, reg2 = rightResultReg), null) } @@ -1102,14 +1120,13 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { , null) } else { - val operandFpReg = codeGen.registers.nextFreeFloat() - val tr = translateExpression(operand, -1, operandFpReg) - addToResult(result, tr, -1, operandFpReg) + val tr = translateExpression(operand) + addToResult(result, tr, -1, tr.resultFpReg) addInstr(result, if(knownAddress!=null) - IRInstruction(Opcode.ADDM, vmDt, fpReg1=operandFpReg, value = knownAddress) - else - IRInstruction(Opcode.ADDM, vmDt, fpReg1=operandFpReg, labelSymbol = symbol) - , null) + IRInstruction(Opcode.ADDM, vmDt, fpReg1=tr.resultFpReg, value = knownAddress) + else + IRInstruction(Opcode.ADDM, vmDt, fpReg1=tr.resultFpReg, labelSymbol = symbol) + , null) } } else { if((operand as? PtNumber)?.number==1.0) { @@ -1120,13 +1137,12 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { , null) } else { - val operandReg = codeGen.registers.nextFree() - val tr = translateExpression(operand, operandReg, -1) - addToResult(result, tr, operandReg, -1) + val tr = translateExpression(operand) + addToResult(result, tr, tr.resultReg, -1) addInstr(result, if(knownAddress!=null) - IRInstruction(Opcode.ADDM, vmDt, reg1=operandReg, value=knownAddress) - else - IRInstruction(Opcode.ADDM, vmDt, reg1=operandReg, labelSymbol = symbol) + IRInstruction(Opcode.ADDM, vmDt, reg1=tr.resultReg, value=knownAddress) + else + IRInstruction(Opcode.ADDM, vmDt, reg1=tr.resultReg, labelSymbol = symbol) , null) } } @@ -1157,7 +1173,7 @@ internal fun addToResult( } if(requiredResultFpReg>=0 && requiredResultFpReg!=codeResult.resultFpReg) { println("RESULT FPREG DIFFERENCE: GOT ${codeResult.resultFpReg} WANTED $requiredResultFpReg ${codeResult.dt}") - codeResult.chunks.last().instructions += IRInstruction(Opcode.LOADR, IRDataType.FLOAT, fpReg1 = requiredResultReg, fpReg2 = codeResult.resultReg) + codeResult.chunks.last().instructions += IRInstruction(Opcode.LOADR, IRDataType.FLOAT, fpReg1 = requiredResultFpReg, fpReg2 = codeResult.resultFpReg) } result += codeResult.chunks } diff --git a/codeGenIntermediate/src/prog8/codegen/intermediate/IRCodeGen.kt b/codeGenIntermediate/src/prog8/codegen/intermediate/IRCodeGen.kt index d28b1efc9..913d95086 100644 --- a/codeGenIntermediate/src/prog8/codegen/intermediate/IRCodeGen.kt +++ b/codeGenIntermediate/src/prog8/codegen/intermediate/IRCodeGen.kt @@ -240,12 +240,11 @@ class IRCodeGen( is PtNodeGroup -> translateGroup(node.children) is PtBuiltinFunctionCall -> { val result = translateBuiltinFunc(node) - result.chunks // it's not an expression so no result value. + result.chunks // it's not an expression so no result value. } is PtFunctionCall -> { - val result = expressionEval.translate(node, 0, 0) - require(result.resultReg==0 && result.resultFpReg==0) // TODO weg - result.chunks + val result = expressionEval.translate(node) + result.chunks // it's not an expression so no result value } is PtNop -> emptyList() is PtReturn -> translate(node) @@ -405,7 +404,7 @@ class IRCodeGen( val valueReg = registers.nextFree() val choiceReg = registers.nextFree() val valueDt = irType(whenStmt.value.type) - val tr = expressionEval.translateExpression(whenStmt.value, valueReg, -1) + val tr = expressionEval.translateExpression(whenStmt.value) addToResult(result, tr, valueReg, -1) val choices = whenStmt.choices.children.map {it as PtWhenChoice } val endLabel = createLabelName() @@ -531,9 +530,9 @@ class IRCodeGen( val loopLabel = createLabelName() val result = mutableListOf() - var tr = expressionEval.translateExpression(iterable.to, endvalueReg, -1) + var tr = expressionEval.translateExpression(iterable.to) addToResult(result, tr, endvalueReg, -1) - tr = expressionEval.translateExpression(iterable.from, indexReg, -1) + tr = expressionEval.translateExpression(iterable.from) addToResult(result, tr, indexReg, -1) val labelAfterFor = createLabelName() @@ -916,15 +915,13 @@ class IRCodeGen( private fun translateIfFollowedByJustGoto(ifElse: PtIfElse, goto: PtJump, irDtLeft: IRDataType, signed: Boolean): MutableList { val result = mutableListOf() if(irDtLeft==IRDataType.FLOAT) { - val leftFpRegNum = registers.nextFreeFloat() - val rightFpRegNum = registers.nextFreeFloat() - val compResultReg = registers.nextFree() - var tr = expressionEval.translateExpression(ifElse.condition.left, -1, leftFpRegNum) - addToResult(result, tr, -1, leftFpRegNum) - tr = expressionEval.translateExpression(ifElse.condition.right, -1, rightFpRegNum) - addToResult(result, tr, -1, rightFpRegNum) + val leftTr = expressionEval.translateExpression(ifElse.condition.left) + addToResult(result, leftTr, -1, leftTr.resultFpReg) + val rightTr = expressionEval.translateExpression(ifElse.condition.right) + addToResult(result, rightTr, -1, rightTr.resultFpReg) result += IRCodeChunk(null,null).also { - it += IRInstruction(Opcode.FCOMP, IRDataType.FLOAT, reg1=compResultReg, fpReg1 = leftFpRegNum, fpReg2 = rightFpRegNum) + val compResultReg = registers.nextFree() + it += IRInstruction(Opcode.FCOMP, IRDataType.FLOAT, reg1=compResultReg, fpReg1 = leftTr.resultFpReg, fpReg2 = rightTr.resultFpReg) val gotoOpcode = when (ifElse.condition.operator) { "==" -> Opcode.BZ "!=" -> Opcode.BNZ @@ -942,47 +939,45 @@ class IRCodeGen( IRInstruction(gotoOpcode, IRDataType.BYTE, reg1 = compResultReg, labelSymbol = goto.identifier!!.name) } } else { - val leftRegNum = registers.nextFree() - val rightRegNum = registers.nextFree() - var tr = expressionEval.translateExpression(ifElse.condition.left, leftRegNum, -1) - addToResult(result, tr, leftRegNum, -1) - tr = expressionEval.translateExpression(ifElse.condition.right, rightRegNum, -1) - addToResult(result, tr, rightRegNum, -1) + val leftTr = expressionEval.translateExpression(ifElse.condition.left) + addToResult(result, leftTr, leftTr.resultReg, -1) + val rightTr = expressionEval.translateExpression(ifElse.condition.right) + addToResult(result, rightTr, rightTr.resultReg, -1) val opcode: Opcode val firstReg: Int val secondReg: Int when (ifElse.condition.operator) { "==" -> { opcode = Opcode.BEQ - firstReg = leftRegNum - secondReg = rightRegNum + firstReg = leftTr.resultReg + secondReg = rightTr.resultReg } "!=" -> { opcode = Opcode.BNE - firstReg = leftRegNum - secondReg = rightRegNum + firstReg = leftTr.resultReg + secondReg = rightTr.resultReg } "<" -> { // swapped '>' opcode = if (signed) Opcode.BGTS else Opcode.BGT - firstReg = rightRegNum - secondReg = leftRegNum + firstReg = rightTr.resultReg + secondReg = leftTr.resultReg } ">" -> { opcode = if (signed) Opcode.BGTS else Opcode.BGT - firstReg = leftRegNum - secondReg = rightRegNum + firstReg = leftTr.resultReg + secondReg = rightTr.resultReg } "<=" -> { // swapped '>=' opcode = if (signed) Opcode.BGES else Opcode.BGE - firstReg = rightRegNum - secondReg = leftRegNum + firstReg = rightTr.resultReg + secondReg = leftTr.resultReg } ">=" -> { opcode = if (signed) Opcode.BGES else Opcode.BGE - firstReg = leftRegNum - secondReg = rightRegNum + firstReg = leftTr.resultReg + secondReg = rightTr.resultReg } else -> throw AssemblyError("invalid comparison operator") } @@ -1006,7 +1001,7 @@ class IRCodeGen( val leftFpReg = registers.nextFreeFloat() val rightFpReg = registers.nextFreeFloat() compResultReg = registers.nextFree() - val tr = expressionEval.translateExpression(ifElse.condition.left, -1, leftFpReg) + val tr = expressionEval.translateExpression(ifElse.condition.left) addToResult(result, tr, -1, leftFpReg) result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.LOAD, IRDataType.FLOAT, fpReg1 = rightFpReg, fpValue = 0f) @@ -1025,7 +1020,7 @@ class IRCodeGen( // integer comparisons branchDt = irDtLeft compResultReg = registers.nextFree() - val tr = expressionEval.translateExpression(ifElse.condition.left, compResultReg, -1) + val tr = expressionEval.translateExpression(ifElse.condition.left) addToResult(result, tr, compResultReg, -1) elseBranch = when (ifElse.condition.operator) { "==" -> Opcode.BNZ @@ -1068,9 +1063,9 @@ class IRCodeGen( val leftFpRegNum = registers.nextFreeFloat() val rightFpRegNum = registers.nextFreeFloat() val compResultReg = registers.nextFree() - var tr = expressionEval.translateExpression(ifElse.condition.left, -1, leftFpRegNum) + var tr = expressionEval.translateExpression(ifElse.condition.left) addToResult(result, tr, -1, leftFpRegNum) - tr = expressionEval.translateExpression(ifElse.condition.right, -1, rightFpRegNum) + tr = expressionEval.translateExpression(ifElse.condition.right) addToResult(result, tr, -1, rightFpRegNum) addInstr(result, IRInstruction(Opcode.FCOMP, IRDataType.FLOAT, reg1=compResultReg, fpReg1 = leftFpRegNum, fpReg2 = rightFpRegNum), null) val elseBranch = when (ifElse.condition.operator) { @@ -1103,9 +1098,9 @@ class IRCodeGen( branchDt = irDtLeft val leftRegNum = registers.nextFree() val rightRegNum = registers.nextFree() - var tr = expressionEval.translateExpression(ifElse.condition.left, leftRegNum, -1) + var tr = expressionEval.translateExpression(ifElse.condition.left) addToResult(result, tr, leftRegNum, -1) - tr = expressionEval.translateExpression(ifElse.condition.right, rightRegNum, -1) + tr = expressionEval.translateExpression(ifElse.condition.right) addToResult(result, tr, rightRegNum, -1) when (ifElse.condition.operator) { "==" -> { @@ -1197,7 +1192,7 @@ class IRCodeGen( } else { val incReg = registers.nextFree() val addressReg = registers.nextFree() - val tr = expressionEval.translateExpression(memory.address, addressReg, -1) + val tr = expressionEval.translateExpression(memory.address,) addToResult(result, tr, addressReg, -1) val chunk = IRCodeChunk(null, null) chunk += IRInstruction(Opcode.LOADI, irDt, reg1 = incReg, reg2 = addressReg) @@ -1215,7 +1210,7 @@ class IRCodeGen( } else { val incReg = registers.nextFree() val indexReg = registers.nextFree() - val tr = expressionEval.translateExpression(array.index, indexReg, -1) + val tr = expressionEval.translateExpression(array.index) addToResult(result, tr, indexReg, -1) val chunk = IRCodeChunk(null, null) chunk += IRInstruction(Opcode.LOADX, irDt, reg1=incReg, reg2=indexReg, labelSymbol=variable) @@ -1244,7 +1239,7 @@ class IRCodeGen( val counterReg = registers.nextFree() val irDt = irType(repeat.count.type) val result = mutableListOf() - val tr = expressionEval.translateExpression(repeat.count, counterReg, -1) + val tr = expressionEval.translateExpression(repeat.count) addToResult(result, tr, counterReg, -1) addInstr(result, IRInstruction(Opcode.BZ, irDt, reg1=counterReg, labelSymbol = skipRepeatLabel), null) result += labelFirstChunk(translateNode(repeat.statements), repeatLabel) @@ -1286,13 +1281,13 @@ class IRCodeGen( } else { if(value.type==DataType.FLOAT) { val reg = registers.nextFreeFloat() - val tr = expressionEval.translateExpression(value, -1, reg) + val tr = expressionEval.translateExpression(value) addToResult(result, tr, -1, reg) addInstr(result, IRInstruction(Opcode.RETURNREG, IRDataType.FLOAT, fpReg1 = reg), null) } else { val reg = registers.nextFree() - val tr = expressionEval.translateExpression(value, reg, -1) + val tr = expressionEval.translateExpression(value) addToResult(result, tr, reg, -1) addInstr(result, IRInstruction(Opcode.RETURNREG, irType(value.type) , reg1=reg), null) } diff --git a/compiler/src/prog8/compiler/Compiler.kt b/compiler/src/prog8/compiler/Compiler.kt index d8f5a13a6..072a1e25e 100644 --- a/compiler/src/prog8/compiler/Compiler.kt +++ b/compiler/src/prog8/compiler/Compiler.kt @@ -6,9 +6,11 @@ import prog8.ast.Program import prog8.ast.base.AstException import prog8.ast.expressions.Expression import prog8.ast.expressions.NumericLiteral +import prog8.ast.printProgram import prog8.ast.statements.Directive import prog8.code.SymbolTableMaker import prog8.code.ast.PtProgram +import prog8.code.ast.printAst import prog8.code.core.* import prog8.code.target.* import prog8.codegen.vm.VmCodeGen @@ -115,10 +117,10 @@ fun compileProgram(args: CompilerArguments): CompilationResult? { args.errors.report() val intermediateAst = IntermediateAstMaker(program, compilationOptions).transform() -// println("*********** COMPILER AST RIGHT BEFORE ASM GENERATION *************") -// printProgram(program) -// println("*********** AST RIGHT BEFORE ASM GENERATION *************") -// printAst(intermediateAst, ::println) + println("*********** COMPILER AST RIGHT BEFORE ASM GENERATION *************") + printProgram(program) + println("*********** AST RIGHT BEFORE ASM GENERATION *************") + printAst(intermediateAst, ::println) if(!createAssemblyAndAssemble(intermediateAst, args.errors, compilationOptions)) { System.err.println("Error in codegeneration or assembler") diff --git a/docs/source/todo.rst b/docs/source/todo.rst index 18b1b532d..3c4f86172 100644 --- a/docs/source/todo.rst +++ b/docs/source/todo.rst @@ -3,6 +3,8 @@ TODO For next minor release ^^^^^^^^^^^^^^^^^^^^^^ +- fix IR/VM crashing in bouncegfx and textelite +- reduce the usage of register.nextFree() in IR codegen - get rid of ResultRegister in IR codegen? as the calls now encode this into the new opcodes... ...