mirror of
https://github.com/irmen/prog8.git
synced 2024-11-29 17:50:35 +00:00
refactor IR returnregs 2
This commit is contained in:
Irmen de Jong
parent
1fdee861e8
commit
03c5dab79d
@ -142,14 +142,14 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
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// calculate the assignment value
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if (vmDt == IRDataType.FLOAT) {
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resultFpRegister = codeGen.registers.nextFreeFloat()
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val tr = expressionEval.translateExpression(assignment.value, -1, resultFpRegister)
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val tr = expressionEval.translateExpression(assignment.value)
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addToResult(result, tr, -1, resultFpRegister)
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} else {
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resultRegister = if (assignment.value is PtMachineRegister) {
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(assignment.value as PtMachineRegister).register
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} else {
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val reg = codeGen.registers.nextFree()
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val tr = expressionEval.translateExpression(assignment.value, reg, -1)
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val tr = expressionEval.translateExpression(assignment.value)
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addToResult(result, tr, reg, -1)
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reg
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}
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@ -178,7 +178,7 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
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if(array.index.type!=DataType.UBYTE)
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throw AssemblyError("non-array var indexing requires bytes index")
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val idxReg = codeGen.registers.nextFree()
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val tr = expressionEval.translateExpression(array.index, idxReg, -1)
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val tr = expressionEval.translateExpression(array.index)
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addToResult(result, tr, idxReg, -1)
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val code = IRCodeChunk(null, null)
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if(zero) {
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@ -235,7 +235,7 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
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result += chunk
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} else {
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val addressReg = codeGen.registers.nextFree()
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val tr = expressionEval.translateExpression(memory.address, addressReg, -1)
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val tr = expressionEval.translateExpression(memory.address)
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addToResult(result, tr, addressReg, -1)
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result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.STOREZI, vmDt, reg1=addressReg) }
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}
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@ -245,7 +245,7 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
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result += chunk
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} else {
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val addressReg = codeGen.registers.nextFree()
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val tr = expressionEval.translateExpression(memory.address, addressReg, -1)
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val tr = expressionEval.translateExpression(memory.address)
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addToResult(result, tr, addressReg, -1)
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result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.STOREI, vmDt, reg1=resultRegister, reg2=addressReg) }
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}
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@ -258,15 +258,16 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
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}
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private fun loadIndexReg(array: PtArrayIndexer, itemsize: Int, indexReg: Int): IRCodeChunks {
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val result = mutableListOf<IRCodeChunkBase>()
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val tr = if(itemsize==1) {
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expressionEval.translateExpression(array.index, indexReg, -1)
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expressionEval.translateExpression(array.index)
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} else {
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val mult = PtBinaryExpression("*", DataType.UBYTE, array.position)
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mult.children += array.index
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mult.children += PtNumber(DataType.UBYTE, itemsize.toDouble(), array.position)
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expressionEval.translateExpression(mult, indexReg, -1)
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expressionEval.translateExpression(mult)
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}
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require(tr.resultReg==indexReg && tr.resultFpReg==-1) // TODO weg
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return tr.chunks
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addToResult(result, tr, indexReg, -1)
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return result
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}
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}
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@ -112,9 +112,9 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
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val leftRegister = codeGen.registers.nextFree()
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val rightRegister = codeGen.registers.nextFree()
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val result = mutableListOf<IRCodeChunkBase>()
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var tr = exprGen.translateExpression(call.args[0], leftRegister, -1)
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var tr = exprGen.translateExpression(call.args[0])
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addToResult(result, tr, leftRegister, -1)
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tr = exprGen.translateExpression(call.args[1], rightRegister, -1)
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tr = exprGen.translateExpression(call.args[1])
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addToResult(result, tr, rightRegister, -1)
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.CMP, codeGen.irType(call.args[0].type), reg1=leftRegister, reg2=rightRegister)
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@ -135,7 +135,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
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else -> throw IllegalArgumentException("weird type")
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}
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val result = mutableListOf<IRCodeChunkBase>()
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val tr = exprGen.translateExpression(call.args[0], SyscallRegisterBase, -1)
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val tr = exprGen.translateExpression(call.args[0])
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addToResult(result, tr, SyscallRegisterBase, -1)
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1 = SyscallRegisterBase+1, value = array.length)
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@ -159,7 +159,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
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else -> throw IllegalArgumentException("weird type")
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}
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val result = mutableListOf<IRCodeChunkBase>()
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val tr = exprGen.translateExpression(call.args[0], SyscallRegisterBase, -1)
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val tr = exprGen.translateExpression(call.args[0])
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addToResult(result, tr, SyscallRegisterBase, -1)
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1 = SyscallRegisterBase+1, value = array.length)
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@ -174,7 +174,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
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val sourceDt = call.args.single().type
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val result = mutableListOf<IRCodeChunkBase>()
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if(sourceDt!=DataType.UWORD) {
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val tr = exprGen.translateExpression(call.args[0], resultRegister, -1)
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val tr = exprGen.translateExpression(call.args[0])
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addToResult(result, tr, resultRegister, -1)
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when (sourceDt) {
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DataType.UBYTE -> {
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@ -214,7 +214,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
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private fun funcSgn(call: PtBuiltinFunctionCall, resultRegister: Int): IRCodeChunks {
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val reg = codeGen.registers.nextFree()
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val result = mutableListOf<IRCodeChunkBase>()
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val tr = exprGen.translateExpression(call.args.single(), reg, -1)
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val tr = exprGen.translateExpression(call.args.single())
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addToResult(result, tr, reg, -1)
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.SGN, codeGen.irType(call.type), reg1 = resultRegister, reg2 = reg)
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@ -225,7 +225,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
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private fun funcSqrt16(call: PtBuiltinFunctionCall, resultRegister: Int): IRCodeChunks {
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val reg = codeGen.registers.nextFree()
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val result = mutableListOf<IRCodeChunkBase>()
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val tr = exprGen.translateExpression(call.args.single(), reg, -1)
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val tr = exprGen.translateExpression(call.args.single())
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addToResult(result, tr, reg, -1)
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.SQRT, IRDataType.WORD, reg1=resultRegister, reg2=reg)
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@ -254,7 +254,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
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private fun funcPush(call: PtBuiltinFunctionCall): IRCodeChunks {
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val result = mutableListOf<IRCodeChunkBase>()
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val reg = codeGen.registers.nextFree()
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val tr = exprGen.translateExpression(call.args.single(), reg, -1)
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val tr = exprGen.translateExpression(call.args.single())
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addToResult(result, tr, reg, -1)
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.PUSH, IRDataType.BYTE, reg1=reg)
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@ -265,7 +265,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
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private fun funcPushw(call: PtBuiltinFunctionCall): IRCodeChunks {
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val result = mutableListOf<IRCodeChunkBase>()
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val reg = codeGen.registers.nextFree()
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val tr = exprGen.translateExpression(call.args.single(), reg, -1)
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val tr = exprGen.translateExpression(call.args.single())
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addToResult(result, tr, reg, -1)
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.PUSH, IRDataType.WORD, reg1 = reg)
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@ -284,7 +284,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
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else -> throw IllegalArgumentException("weird type to reverse")
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}
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val result = mutableListOf<IRCodeChunkBase>()
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val tr = exprGen.translateExpression(call.args[0], SyscallRegisterBase, -1)
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val tr = exprGen.translateExpression(call.args[0])
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addToResult(result, tr, SyscallRegisterBase, -1)
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1 = SyscallRegisterBase+1, value = array.length)
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@ -307,7 +307,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
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else -> throw IllegalArgumentException("weird type to sort")
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}
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val result = mutableListOf<IRCodeChunkBase>()
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val tr = exprGen.translateExpression(call.args[0], SyscallRegisterBase, -1)
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val tr = exprGen.translateExpression(call.args[0])
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addToResult(result, tr, SyscallRegisterBase, -1)
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1 = SyscallRegisterBase+1, value = array.length)
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@ -319,9 +319,9 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
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private fun funcMkword(call: PtBuiltinFunctionCall, resultRegister: Int): IRCodeChunks {
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val msbReg = codeGen.registers.nextFree()
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val result = mutableListOf<IRCodeChunkBase>()
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var tr = exprGen.translateExpression(call.args[0], msbReg, -1)
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var tr = exprGen.translateExpression(call.args[0])
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addToResult(result, tr, msbReg, -1)
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tr = exprGen.translateExpression(call.args[1], resultRegister, -1)
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tr = exprGen.translateExpression(call.args[1])
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addToResult(result, tr, resultRegister, -1)
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.CONCAT, IRDataType.BYTE, reg1 = resultRegister, reg2 = msbReg)
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@ -339,7 +339,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
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}
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} else {
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val addressReg = codeGen.registers.nextFree()
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val tr = exprGen.translateExpression(call.args[0], addressReg, -1)
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val tr = exprGen.translateExpression(call.args[0])
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addToResult(result, tr, addressReg, -1)
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.STOREZI, IRDataType.WORD, reg1 = addressReg)
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@ -349,16 +349,16 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
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val valueReg = codeGen.registers.nextFree()
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if (call.args[0] is PtNumber) {
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val address = (call.args[0] as PtNumber).number.toInt()
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val tr = exprGen.translateExpression(call.args[1], valueReg, -1)
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val tr = exprGen.translateExpression(call.args[1])
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addToResult(result, tr, valueReg, -1)
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.STOREM, IRDataType.WORD, reg1 = valueReg, value = address)
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}
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} else {
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val addressReg = codeGen.registers.nextFree()
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var tr = exprGen.translateExpression(call.args[0], addressReg, -1)
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var tr = exprGen.translateExpression(call.args[0])
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addToResult(result, tr, addressReg, -1)
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tr = exprGen.translateExpression(call.args[1], valueReg, -1)
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tr = exprGen.translateExpression(call.args[1])
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addToResult(result, tr, valueReg, -1)
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.STOREI, IRDataType.WORD, reg1 = valueReg, reg2 = addressReg)
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@ -378,7 +378,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
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}
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} else {
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val addressReg = codeGen.registers.nextFree()
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val tr = exprGen.translateExpression(call.args[0], addressReg, -1)
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val tr = exprGen.translateExpression(call.args[0])
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addToResult(result, tr, addressReg, -1)
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.STOREZI, IRDataType.BYTE, reg1 = addressReg)
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@ -388,16 +388,16 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
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val valueReg = codeGen.registers.nextFree()
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if (call.args[0] is PtNumber) {
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val address = (call.args[0] as PtNumber).number.toInt()
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val tr = exprGen.translateExpression(call.args[1], valueReg, -1)
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val tr = exprGen.translateExpression(call.args[1])
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addToResult(result, tr, valueReg, -1)
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.STOREM, IRDataType.BYTE, reg1 = valueReg, value = address)
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}
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} else {
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val addressReg = codeGen.registers.nextFree()
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var tr = exprGen.translateExpression(call.args[0], addressReg, -1)
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var tr = exprGen.translateExpression(call.args[0])
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addToResult(result, tr, addressReg, -1)
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tr = exprGen.translateExpression(call.args[1], valueReg, -1)
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tr = exprGen.translateExpression(call.args[1])
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addToResult(result, tr, valueReg, -1)
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.STOREI, IRDataType.BYTE, reg1 = valueReg, reg2 = addressReg)
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@ -416,7 +416,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
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}
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} else {
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val addressReg = codeGen.registers.nextFree()
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val tr = exprGen.translateExpression(call.args.single(), addressReg, -1)
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val tr = exprGen.translateExpression(call.args.single())
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addToResult(result, tr, addressReg, -1)
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LOADI, IRDataType.WORD, reg1 = resultRegister, reg2 = addressReg)
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@ -434,7 +434,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
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}
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} else {
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val addressReg = codeGen.registers.nextFree()
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val tr = exprGen.translateExpression(call.args.single(), addressReg, -1)
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val tr = exprGen.translateExpression(call.args.single())
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addToResult(result, tr, addressReg, -1)
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LOADI, IRDataType.BYTE, reg1 = resultRegister, reg2 = addressReg)
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@ -451,15 +451,14 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
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}
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private fun funcLsb(call: PtBuiltinFunctionCall): ExpressionCodeResult {
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val resultRegister = codeGen.registers.nextFree()
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return exprGen.translateExpression(call.args.single(), resultRegister, -1)
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return exprGen.translateExpression(call.args.single())
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// note: if a word result is needed, the upper byte is cleared by the typecast that follows. No need to do it here.
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}
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private fun funcMsb(call: PtBuiltinFunctionCall): ExpressionCodeResult {
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val result = mutableListOf<IRCodeChunkBase>()
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val resultRegister = codeGen.registers.nextFree()
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val tr = exprGen.translateExpression(call.args.single(), resultRegister, -1)
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val tr = exprGen.translateExpression(call.args.single())
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addToResult(result, tr, resultRegister, -1)
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.MSIG, IRDataType.BYTE, reg1 = resultRegister, reg2 = resultRegister)
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@ -471,7 +470,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
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private fun funcRolRor(opcode: Opcode, call: PtBuiltinFunctionCall, resultRegister: Int): IRCodeChunks {
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val vmDt = codeGen.irType(call.args[0].type)
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val result = mutableListOf<IRCodeChunkBase>()
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val tr = exprGen.translateExpression(call.args[0], resultRegister, -1)
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val tr = exprGen.translateExpression(call.args[0])
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addToResult(result, tr, resultRegister, -1)
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(opcode, vmDt, reg1 = resultRegister)
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File diff suppressed because it is too large
Load Diff
@ -243,9 +243,8 @@ class IRCodeGen(
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result.chunks // it's not an expression so no result value.
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}
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is PtFunctionCall -> {
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val result = expressionEval.translate(node, 0, 0)
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require(result.resultReg==0 && result.resultFpReg==0) // TODO weg
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result.chunks
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val result = expressionEval.translate(node)
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result.chunks // it's not an expression so no result value
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}
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is PtNop -> emptyList()
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is PtReturn -> translate(node)
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@ -405,7 +404,7 @@ class IRCodeGen(
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val valueReg = registers.nextFree()
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val choiceReg = registers.nextFree()
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val valueDt = irType(whenStmt.value.type)
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val tr = expressionEval.translateExpression(whenStmt.value, valueReg, -1)
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val tr = expressionEval.translateExpression(whenStmt.value)
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addToResult(result, tr, valueReg, -1)
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val choices = whenStmt.choices.children.map {it as PtWhenChoice }
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val endLabel = createLabelName()
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@ -531,9 +530,9 @@ class IRCodeGen(
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val loopLabel = createLabelName()
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val result = mutableListOf<IRCodeChunkBase>()
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var tr = expressionEval.translateExpression(iterable.to, endvalueReg, -1)
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var tr = expressionEval.translateExpression(iterable.to)
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addToResult(result, tr, endvalueReg, -1)
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tr = expressionEval.translateExpression(iterable.from, indexReg, -1)
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tr = expressionEval.translateExpression(iterable.from)
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addToResult(result, tr, indexReg, -1)
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val labelAfterFor = createLabelName()
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@ -916,15 +915,13 @@ class IRCodeGen(
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private fun translateIfFollowedByJustGoto(ifElse: PtIfElse, goto: PtJump, irDtLeft: IRDataType, signed: Boolean): MutableList<IRCodeChunkBase> {
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val result = mutableListOf<IRCodeChunkBase>()
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if(irDtLeft==IRDataType.FLOAT) {
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val leftFpRegNum = registers.nextFreeFloat()
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val rightFpRegNum = registers.nextFreeFloat()
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val compResultReg = registers.nextFree()
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var tr = expressionEval.translateExpression(ifElse.condition.left, -1, leftFpRegNum)
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addToResult(result, tr, -1, leftFpRegNum)
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tr = expressionEval.translateExpression(ifElse.condition.right, -1, rightFpRegNum)
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addToResult(result, tr, -1, rightFpRegNum)
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val leftTr = expressionEval.translateExpression(ifElse.condition.left)
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addToResult(result, leftTr, -1, leftTr.resultFpReg)
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val rightTr = expressionEval.translateExpression(ifElse.condition.right)
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addToResult(result, rightTr, -1, rightTr.resultFpReg)
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result += IRCodeChunk(null,null).also {
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it += IRInstruction(Opcode.FCOMP, IRDataType.FLOAT, reg1=compResultReg, fpReg1 = leftFpRegNum, fpReg2 = rightFpRegNum)
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val compResultReg = registers.nextFree()
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it += IRInstruction(Opcode.FCOMP, IRDataType.FLOAT, reg1=compResultReg, fpReg1 = leftTr.resultFpReg, fpReg2 = rightTr.resultFpReg)
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val gotoOpcode = when (ifElse.condition.operator) {
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"==" -> Opcode.BZ
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"!=" -> Opcode.BNZ
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@ -942,47 +939,45 @@ class IRCodeGen(
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IRInstruction(gotoOpcode, IRDataType.BYTE, reg1 = compResultReg, labelSymbol = goto.identifier!!.name)
|
||||
}
|
||||
} else {
|
||||
val leftRegNum = registers.nextFree()
|
||||
val rightRegNum = registers.nextFree()
|
||||
var tr = expressionEval.translateExpression(ifElse.condition.left, leftRegNum, -1)
|
||||
addToResult(result, tr, leftRegNum, -1)
|
||||
tr = expressionEval.translateExpression(ifElse.condition.right, rightRegNum, -1)
|
||||
addToResult(result, tr, rightRegNum, -1)
|
||||
val leftTr = expressionEval.translateExpression(ifElse.condition.left)
|
||||
addToResult(result, leftTr, leftTr.resultReg, -1)
|
||||
val rightTr = expressionEval.translateExpression(ifElse.condition.right)
|
||||
addToResult(result, rightTr, rightTr.resultReg, -1)
|
||||
val opcode: Opcode
|
||||
val firstReg: Int
|
||||
val secondReg: Int
|
||||
when (ifElse.condition.operator) {
|
||||
"==" -> {
|
||||
opcode = Opcode.BEQ
|
||||
firstReg = leftRegNum
|
||||
secondReg = rightRegNum
|
||||
firstReg = leftTr.resultReg
|
||||
secondReg = rightTr.resultReg
|
||||
}
|
||||
"!=" -> {
|
||||
opcode = Opcode.BNE
|
||||
firstReg = leftRegNum
|
||||
secondReg = rightRegNum
|
||||
firstReg = leftTr.resultReg
|
||||
secondReg = rightTr.resultReg
|
||||
}
|
||||
"<" -> {
|
||||
// swapped '>'
|
||||
opcode = if (signed) Opcode.BGTS else Opcode.BGT
|
||||
firstReg = rightRegNum
|
||||
secondReg = leftRegNum
|
||||
firstReg = rightTr.resultReg
|
||||
secondReg = leftTr.resultReg
|
||||
}
|
||||
">" -> {
|
||||
opcode = if (signed) Opcode.BGTS else Opcode.BGT
|
||||
firstReg = leftRegNum
|
||||
secondReg = rightRegNum
|
||||
firstReg = leftTr.resultReg
|
||||
secondReg = rightTr.resultReg
|
||||
}
|
||||
"<=" -> {
|
||||
// swapped '>='
|
||||
opcode = if (signed) Opcode.BGES else Opcode.BGE
|
||||
firstReg = rightRegNum
|
||||
secondReg = leftRegNum
|
||||
firstReg = rightTr.resultReg
|
||||
secondReg = leftTr.resultReg
|
||||
}
|
||||
">=" -> {
|
||||
opcode = if (signed) Opcode.BGES else Opcode.BGE
|
||||
firstReg = leftRegNum
|
||||
secondReg = rightRegNum
|
||||
firstReg = leftTr.resultReg
|
||||
secondReg = rightTr.resultReg
|
||||
}
|
||||
else -> throw AssemblyError("invalid comparison operator")
|
||||
}
|
||||
@ -1006,7 +1001,7 @@ class IRCodeGen(
|
||||
val leftFpReg = registers.nextFreeFloat()
|
||||
val rightFpReg = registers.nextFreeFloat()
|
||||
compResultReg = registers.nextFree()
|
||||
val tr = expressionEval.translateExpression(ifElse.condition.left, -1, leftFpReg)
|
||||
val tr = expressionEval.translateExpression(ifElse.condition.left)
|
||||
addToResult(result, tr, -1, leftFpReg)
|
||||
result += IRCodeChunk(null, null).also {
|
||||
it += IRInstruction(Opcode.LOAD, IRDataType.FLOAT, fpReg1 = rightFpReg, fpValue = 0f)
|
||||
@ -1025,7 +1020,7 @@ class IRCodeGen(
|
||||
// integer comparisons
|
||||
branchDt = irDtLeft
|
||||
compResultReg = registers.nextFree()
|
||||
val tr = expressionEval.translateExpression(ifElse.condition.left, compResultReg, -1)
|
||||
val tr = expressionEval.translateExpression(ifElse.condition.left)
|
||||
addToResult(result, tr, compResultReg, -1)
|
||||
elseBranch = when (ifElse.condition.operator) {
|
||||
"==" -> Opcode.BNZ
|
||||
@ -1068,9 +1063,9 @@ class IRCodeGen(
|
||||
val leftFpRegNum = registers.nextFreeFloat()
|
||||
val rightFpRegNum = registers.nextFreeFloat()
|
||||
val compResultReg = registers.nextFree()
|
||||
var tr = expressionEval.translateExpression(ifElse.condition.left, -1, leftFpRegNum)
|
||||
var tr = expressionEval.translateExpression(ifElse.condition.left)
|
||||
addToResult(result, tr, -1, leftFpRegNum)
|
||||
tr = expressionEval.translateExpression(ifElse.condition.right, -1, rightFpRegNum)
|
||||
tr = expressionEval.translateExpression(ifElse.condition.right)
|
||||
addToResult(result, tr, -1, rightFpRegNum)
|
||||
addInstr(result, IRInstruction(Opcode.FCOMP, IRDataType.FLOAT, reg1=compResultReg, fpReg1 = leftFpRegNum, fpReg2 = rightFpRegNum), null)
|
||||
val elseBranch = when (ifElse.condition.operator) {
|
||||
@ -1103,9 +1098,9 @@ class IRCodeGen(
|
||||
branchDt = irDtLeft
|
||||
val leftRegNum = registers.nextFree()
|
||||
val rightRegNum = registers.nextFree()
|
||||
var tr = expressionEval.translateExpression(ifElse.condition.left, leftRegNum, -1)
|
||||
var tr = expressionEval.translateExpression(ifElse.condition.left)
|
||||
addToResult(result, tr, leftRegNum, -1)
|
||||
tr = expressionEval.translateExpression(ifElse.condition.right, rightRegNum, -1)
|
||||
tr = expressionEval.translateExpression(ifElse.condition.right)
|
||||
addToResult(result, tr, rightRegNum, -1)
|
||||
when (ifElse.condition.operator) {
|
||||
"==" -> {
|
||||
@ -1197,7 +1192,7 @@ class IRCodeGen(
|
||||
} else {
|
||||
val incReg = registers.nextFree()
|
||||
val addressReg = registers.nextFree()
|
||||
val tr = expressionEval.translateExpression(memory.address, addressReg, -1)
|
||||
val tr = expressionEval.translateExpression(memory.address,)
|
||||
addToResult(result, tr, addressReg, -1)
|
||||
val chunk = IRCodeChunk(null, null)
|
||||
chunk += IRInstruction(Opcode.LOADI, irDt, reg1 = incReg, reg2 = addressReg)
|
||||
@ -1215,7 +1210,7 @@ class IRCodeGen(
|
||||
} else {
|
||||
val incReg = registers.nextFree()
|
||||
val indexReg = registers.nextFree()
|
||||
val tr = expressionEval.translateExpression(array.index, indexReg, -1)
|
||||
val tr = expressionEval.translateExpression(array.index)
|
||||
addToResult(result, tr, indexReg, -1)
|
||||
val chunk = IRCodeChunk(null, null)
|
||||
chunk += IRInstruction(Opcode.LOADX, irDt, reg1=incReg, reg2=indexReg, labelSymbol=variable)
|
||||
@ -1244,7 +1239,7 @@ class IRCodeGen(
|
||||
val counterReg = registers.nextFree()
|
||||
val irDt = irType(repeat.count.type)
|
||||
val result = mutableListOf<IRCodeChunkBase>()
|
||||
val tr = expressionEval.translateExpression(repeat.count, counterReg, -1)
|
||||
val tr = expressionEval.translateExpression(repeat.count)
|
||||
addToResult(result, tr, counterReg, -1)
|
||||
addInstr(result, IRInstruction(Opcode.BZ, irDt, reg1=counterReg, labelSymbol = skipRepeatLabel), null)
|
||||
result += labelFirstChunk(translateNode(repeat.statements), repeatLabel)
|
||||
@ -1286,13 +1281,13 @@ class IRCodeGen(
|
||||
} else {
|
||||
if(value.type==DataType.FLOAT) {
|
||||
val reg = registers.nextFreeFloat()
|
||||
val tr = expressionEval.translateExpression(value, -1, reg)
|
||||
val tr = expressionEval.translateExpression(value)
|
||||
addToResult(result, tr, -1, reg)
|
||||
addInstr(result, IRInstruction(Opcode.RETURNREG, IRDataType.FLOAT, fpReg1 = reg), null)
|
||||
}
|
||||
else {
|
||||
val reg = registers.nextFree()
|
||||
val tr = expressionEval.translateExpression(value, reg, -1)
|
||||
val tr = expressionEval.translateExpression(value)
|
||||
addToResult(result, tr, reg, -1)
|
||||
addInstr(result, IRInstruction(Opcode.RETURNREG, irType(value.type) , reg1=reg), null)
|
||||
}
|
||||
|
||||
@ -6,9 +6,11 @@ import prog8.ast.Program
|
||||
import prog8.ast.base.AstException
|
||||
import prog8.ast.expressions.Expression
|
||||
import prog8.ast.expressions.NumericLiteral
|
||||
import prog8.ast.printProgram
|
||||
import prog8.ast.statements.Directive
|
||||
import prog8.code.SymbolTableMaker
|
||||
import prog8.code.ast.PtProgram
|
||||
import prog8.code.ast.printAst
|
||||
import prog8.code.core.*
|
||||
import prog8.code.target.*
|
||||
import prog8.codegen.vm.VmCodeGen
|
||||
@ -115,10 +117,10 @@ fun compileProgram(args: CompilerArguments): CompilationResult? {
|
||||
args.errors.report()
|
||||
|
||||
val intermediateAst = IntermediateAstMaker(program, compilationOptions).transform()
|
||||
// println("*********** COMPILER AST RIGHT BEFORE ASM GENERATION *************")
|
||||
// printProgram(program)
|
||||
// println("*********** AST RIGHT BEFORE ASM GENERATION *************")
|
||||
// printAst(intermediateAst, ::println)
|
||||
println("*********** COMPILER AST RIGHT BEFORE ASM GENERATION *************")
|
||||
printProgram(program)
|
||||
println("*********** AST RIGHT BEFORE ASM GENERATION *************")
|
||||
printAst(intermediateAst, ::println)
|
||||
|
||||
if(!createAssemblyAndAssemble(intermediateAst, args.errors, compilationOptions)) {
|
||||
System.err.println("Error in codegeneration or assembler")
|
||||
|
||||
@ -3,6 +3,8 @@ TODO
|
||||
|
||||
For next minor release
|
||||
^^^^^^^^^^^^^^^^^^^^^^
|
||||
- fix IR/VM crashing in bouncegfx and textelite
|
||||
- reduce the usage of register.nextFree() in IR codegen
|
||||
- get rid of ResultRegister in IR codegen? as the calls now encode this into the new opcodes...
|
||||
|
||||
...
|
||||
|
||||
Loading…
Reference in New Issue
Block a user