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fix long argument @R0R1 register usage in regular subroutines

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Irmen de Jong
2026-02-15 14:49:15 +01:00
parent d1383813d2
commit 07be7f0154
9 changed files with 34 additions and 14 deletions
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codeGenIntermediate/src/prog8/codegen/intermediate/ExpressionGen.kt
+1 -1
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@@ -924,7 +924,7 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
else
argRegisters.add(FunctionCallArgs.ArgumentSpec(parameter.name, null, FunctionCallArgs.RegSpec(paramDt, tr.resultReg, null)))
} else {
require(parameter.register in Cx16VirtualRegisters) { "can only use R0-R15 'registers' here" }
require(parameter.register in Cx16VirtualRegisters || parameter.register in CombinedLongRegisters) { "can only use R0-R15 'registers' here" }
val regname = parameter.register!!.asScopedNameVirtualReg(parameter.type).joinToString(".")
val assign = PtAssignment(fcall.position)
val target = PtAssignTarget(false, fcall.position)
codeGenIntermediate/src/prog8/codegen/intermediate/IRCodeGen.kt
+1 -1
View File
@@ -1934,7 +1934,7 @@ class IRCodeGen(
result += IRSubroutine.IRParam(it.name, orig.dt)
} else {
val reg = it.register
require(reg in Cx16VirtualRegisters) { "can only use R0-R15 'registers' here" }
require(reg in Cx16VirtualRegisters || reg in CombinedLongRegisters) { "can only use R0-R15 'registers' here" }
val regname = it.register!!.asScopedNameVirtualReg(it.type).joinToString(".")
val targetVar = symbolTable.lookup(regname) as StMemVar
result += IRSubroutine.IRParam(regname, targetVar.dt)