mirror of
https://github.com/irmen/prog8.git
synced 2024-12-24 16:29:21 +00:00
added for loop over constant ranges
This commit is contained in:
Irmen de Jong
parent
0dc592b819
commit
0a0c58d450
@ -126,8 +126,8 @@ class PtRange(type: DataType, position: Position) : PtExpression(type, position)
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get() = children[0] as PtExpression
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val to: PtExpression
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get() = children[1] as PtExpression
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val step: PtExpression
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get() = children[2] as PtExpression
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val step: PtNumber
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get() = children[2] as PtNumber
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override fun printProperties() {}
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}
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@ -54,6 +54,8 @@ class CodeGen(internal val program: PtProgram,
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vmprog.addBlock(translate(block))
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}
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println("Vm codegen: amount of vm registers=${vmRegisters.peekNext()}")
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return vmprog
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}
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@ -103,7 +105,7 @@ class CodeGen(internal val program: PtProgram,
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is PtConditionalBranch -> throw AssemblyError("conditional branches not supported in vm target due to lack of cpu flags ${node.position}")
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else -> TODO("missing codegen for $node")
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}
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if(code.lines.isNotEmpty())
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if(code.lines.isNotEmpty() && node.position.line!=0)
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code.lines.add(0, VmCodeComment(node.position.toString()))
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return code
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}
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@ -114,9 +116,10 @@ class CodeGen(internal val program: PtProgram,
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val code = VmCodeChunk()
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when(iterable) {
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is PtRange -> {
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TODO("forloop ${loopvar.dt} ${loopvar.scopedName} in range ${iterable} ")
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iterable.printIndented(0)
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TODO("forloop over range")
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if(iterable.from is PtNumber && iterable.to is PtNumber)
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code += translateForInConstantRange(forLoop, loopvar)
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else
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code += translateForInNonConstantRange(forLoop, loopvar)
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}
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is PtIdentifier -> {
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val arrayAddress = allocations.get(iterable.targetName)
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@ -139,19 +142,9 @@ class CodeGen(internal val program: PtProgram,
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} else {
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// iterate over array
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val elementDt = ArrayToElementTypes.getValue(iterable.type)
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val elementSize = program.memsizer.memorySize(elementDt).toUInt()
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val lengthBytes = iterableVar.length!! * elementSize.toInt()
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val elementSize = program.memsizer.memorySize(elementDt)
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val lengthBytes = iterableVar.length!! * elementSize
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val lengthReg = vmRegisters.nextFree()
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/*
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index = 0
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_loop:
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if index==(length * <element_size>) goto _end
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loopvar = read_mem(iterable+index)
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<statements>
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index += <elementsize>
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goto _loop
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_end: ...
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*/
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code += VmCodeInstruction(Opcode.LOAD, VmDataType.BYTE, reg1=indexReg, value=0)
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code += VmCodeInstruction(Opcode.LOAD, VmDataType.BYTE, reg1=lengthReg, value=lengthBytes)
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code += VmCodeLabel(loopLabel)
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@ -159,7 +152,7 @@ class CodeGen(internal val program: PtProgram,
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code += VmCodeInstruction(Opcode.LOADX, vmType(elementDt), reg1=0, reg2=indexReg, value=arrayAddress)
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code += VmCodeInstruction(Opcode.STOREM, vmType(elementDt), reg1=0, value = loopvarAddress)
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code += translateNode(forLoop.statements)
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code += addConst(VmDataType.BYTE, indexReg, elementSize)
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code += addConstReg(VmDataType.BYTE, indexReg, elementSize)
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code += VmCodeInstruction(Opcode.JUMP, symbol = loopLabel)
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code += VmCodeLabel(endLabel)
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}
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@ -169,17 +162,111 @@ class CodeGen(internal val program: PtProgram,
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return code
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}
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private fun addConst(dt: VmDataType, reg: Int, value: UInt): VmCodeChunk {
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private fun translateForInNonConstantRange(forLoop: PtForLoop, loopvar: StStaticVariable): VmCodeChunk {
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val iterable = forLoop.iterable as PtRange
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TODO("forloop ${loopvar.dt} ${loopvar.scopedName} in non-constant range ${iterable} ")
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iterable.printIndented(0)
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}
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private fun translateForInConstantRange(forLoop: PtForLoop, loopvar: StStaticVariable): VmCodeChunk {
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val iterable = forLoop.iterable as PtRange
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val step = iterable.step.number.toInt()
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val range = IntProgression.fromClosedRange(
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(iterable.from as PtNumber).number.toInt(),
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(iterable.to as PtNumber).number.toInt() + step,
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step)
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if (range.isEmpty() || range.step==0)
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throw AssemblyError("empty range or step 0")
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val loopLabel = createLabelName()
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val loopvarAddress = allocations.get(loopvar.scopedName)
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val indexReg = vmRegisters.nextFree()
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val endvalueReg = vmRegisters.nextFree()
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val vmDt = vmType(loopvar.dt)
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val code = VmCodeChunk()
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code += VmCodeInstruction(Opcode.LOAD, vmDt, reg1=endvalueReg, value=range.last)
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code += VmCodeInstruction(Opcode.LOAD, vmDt, reg1=indexReg, value=range.first)
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code += VmCodeInstruction(Opcode.STOREM, vmDt, reg1=indexReg, value=loopvarAddress)
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code += VmCodeLabel(loopLabel)
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code += translateNode(forLoop.statements)
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if(range.step==1 || range.step==2) {
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code += addConstMem(vmDt, loopvarAddress.toUInt(), range.step)
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code += VmCodeInstruction(Opcode.LOADM, vmDt, reg1 = indexReg, value = loopvarAddress)
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} else {
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code += VmCodeInstruction(Opcode.LOADM, vmDt, reg1 = indexReg, value = loopvarAddress)
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code += addConstReg(vmDt, indexReg, range.step)
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code += VmCodeInstruction(Opcode.STOREM, vmDt, reg1 = indexReg, value = loopvarAddress)
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}
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code += VmCodeInstruction(Opcode.BNE, vmDt, reg1=indexReg, reg2=endvalueReg, symbol=loopLabel)
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return code
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}
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private fun addConstReg(dt: VmDataType, reg: Int, value: Int): VmCodeChunk {
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val code = VmCodeChunk()
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when(value) {
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0u -> { /* do nothing */ }
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1u -> {
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0 -> { /* do nothing */ }
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1 -> {
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code += VmCodeInstruction(Opcode.INC, dt, reg1=reg)
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}
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2 -> {
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code += VmCodeInstruction(Opcode.INC, dt, reg1=reg)
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code += VmCodeInstruction(Opcode.INC, dt, reg1=reg)
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}
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-1 -> {
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code += VmCodeInstruction(Opcode.DEC, dt, reg1=reg)
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}
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-2 -> {
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code += VmCodeInstruction(Opcode.DEC, dt, reg1=reg)
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code += VmCodeInstruction(Opcode.DEC, dt, reg1=reg)
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}
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else -> {
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val valueReg = vmRegisters.nextFree()
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code += VmCodeInstruction(Opcode.LOAD, dt, reg1=valueReg, value=value.toInt())
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code += VmCodeInstruction(Opcode.ADD, dt, reg1=reg, reg2=reg, reg3=valueReg)
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if(value>0) {
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code += VmCodeInstruction(Opcode.LOAD, dt, reg1=valueReg, value= value)
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code += VmCodeInstruction(Opcode.ADD, dt, reg1 = reg, reg2 = reg, reg3 = valueReg)
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}
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else {
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code += VmCodeInstruction(Opcode.LOAD, dt, reg1=valueReg, value= -value)
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code += VmCodeInstruction(Opcode.SUB, dt, reg1 = reg, reg2 = reg, reg3 = valueReg)
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}
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}
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}
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return code
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}
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private fun addConstMem(dt: VmDataType, address: UInt, value: Int): VmCodeChunk {
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val code = VmCodeChunk()
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when(value) {
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0 -> { /* do nothing */ }
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1 -> {
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code += VmCodeInstruction(Opcode.INCM, dt, value=address.toInt())
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}
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2 -> {
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code += VmCodeInstruction(Opcode.INCM, dt, value=address.toInt())
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code += VmCodeInstruction(Opcode.INCM, dt, value=address.toInt())
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}
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-1 -> {
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code += VmCodeInstruction(Opcode.DECM, dt, value=address.toInt())
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}
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-2 -> {
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code += VmCodeInstruction(Opcode.DECM, dt, value=address.toInt())
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code += VmCodeInstruction(Opcode.DECM, dt, value=address.toInt())
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}
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else -> {
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val valueReg = vmRegisters.nextFree()
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val operandReg = vmRegisters.nextFree()
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if(value>0) {
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code += VmCodeInstruction(Opcode.LOADM, dt, reg1=valueReg, value=address.toInt())
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code += VmCodeInstruction(Opcode.LOAD, dt, reg1=operandReg, value=value)
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code += VmCodeInstruction(Opcode.ADD, dt, reg1 = valueReg, reg2 = valueReg, reg3 = operandReg)
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code += VmCodeInstruction(Opcode.STOREM, dt, reg1=valueReg, value=address.toInt())
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}
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else {
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code += VmCodeInstruction(Opcode.LOADM, dt, reg1=valueReg, value=address.toInt())
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code += VmCodeInstruction(Opcode.LOAD, dt, reg1=operandReg, value=-value)
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code += VmCodeInstruction(Opcode.SUB, dt, reg1 = valueReg, reg2 = valueReg, reg3 = operandReg)
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code += VmCodeInstruction(Opcode.STOREM, dt, reg1=valueReg, value=address.toInt())
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}
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}
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}
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return code
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@ -483,7 +483,7 @@ class IntermediateAstMaker(val program: Program) {
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val range=PtRange(type, srcRange.position)
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range.add(transformExpression(srcRange.from))
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range.add(transformExpression(srcRange.to))
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range.add(transformExpression(srcRange.step))
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range.add(transformExpression(srcRange.step) as PtNumber)
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return range
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}
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@ -34,8 +34,11 @@ main {
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txt.print_uw(ww) ; 11
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txt.nl()
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for bc in 10 to 20 step 3 {
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; 10,13,16,19
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const ubyte rfrom = 10
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const ubyte rto = 17
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for bc in rfrom to rto step 2 {
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; 10,12,14,16
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txt.print_ub(bc)
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txt.spc()
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ww++
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@ -43,7 +46,7 @@ main {
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txt.print_uw(ww) ; 15
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txt.nl()
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for bc in 30 to 10 step -4 {
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for bc in 30 to 0 step -4 {
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; 30,26,22,18,14,10,6,2
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txt.print_ub(bc)
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txt.spc()
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@ -61,28 +61,28 @@ BRANCHING
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---------
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All have type b or w.
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bz reg1, value - branch if reg1 is zero
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bnz reg1, value - branch if reg1 is not zero
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beq reg1, reg2, value - jump to location in program given by value, if reg1 == reg2
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bne reg1, reg2, value - jump to location in program given by value, if reg1 != reg2
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blt reg1, reg2, value - jump to location in program given by value, if reg1 < reg2 (unsigned)
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blts reg1, reg2, value - jump to location in program given by value, if reg1 < reg2 (signed)
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ble reg1, reg2, value - jump to location in program given by value, if reg1 <= reg2 (unsigned)
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bles reg1, reg2, value - jump to location in program given by value, if reg1 <= reg2 (signed)
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bgt reg1, reg2, value - jump to location in program given by value, if reg1 > reg2 (unsigned)
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bgts reg1, reg2, value - jump to location in program given by value, if reg1 > reg2 (signed)
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bge reg1, reg2, value - jump to location in program given by value, if reg1 >= reg2 (unsigned)
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bges reg1, reg2, value - jump to location in program given by value, if reg1 >= reg2 (signed)
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seq reg1, reg2, reg3 - set reg=1 if reg2 == reg3, otherwise set reg1=0
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sne reg1, reg2, reg3 - set reg=1 if reg2 != reg3, otherwise set reg1=0
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slt reg1, reg2, reg3 - set reg=1 if reg2 < reg3 (unsigned), otherwise set reg1=0
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slts reg1, reg2, reg3 - set reg=1 if reg2 < reg3 (signed), otherwise set reg1=0
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sle reg1, reg2, reg3 - set reg=1 if reg2 <= reg3 (unsigned), otherwise set reg1=0
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sles reg1, reg2, reg3 - set reg=1 if reg2 <= reg3 (signed), otherwise set reg1=0
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sgt reg1, reg2, reg3 - set reg=1 if reg2 > reg3 (unsigned), otherwise set reg1=0
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sgts reg1, reg2, reg3 - set reg=1 if reg2 > reg3 (signed), otherwise set reg1=0
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sge reg1, reg2, reg3 - set reg=1 if reg2 >= reg3 (unsigned), otherwise set reg1=0
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sges reg1, reg2, reg3 - set reg=1 if reg2 >= reg3 (signed), otherwise set reg1=0
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bz reg1, location - branch to location if reg1 is zero
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bnz reg1, location - branch to location if reg1 is not zero
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beq reg1, reg2, location - jump to location in program given by location, if reg1 == reg2
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bne reg1, reg2, location - jump to location in program given by location, if reg1 != reg2
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blt reg1, reg2, location - jump to location in program given by location, if reg1 < reg2 (unsigned)
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blts reg1, reg2, location - jump to location in program given by location, if reg1 < reg2 (signed)
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ble reg1, reg2, location - jump to location in program given by location, if reg1 <= reg2 (unsigned)
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bles reg1, reg2, location - jump to location in program given by location, if reg1 <= reg2 (signed)
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bgt reg1, reg2, location - jump to location in program given by location, if reg1 > reg2 (unsigned)
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bgts reg1, reg2, location - jump to location in program given by location, if reg1 > reg2 (signed)
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bge reg1, reg2, location - jump to location in program given by location, if reg1 >= reg2 (unsigned)
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bges reg1, reg2, location - jump to location in program given by location, if reg1 >= reg2 (signed)
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seq reg1, reg2, reg3 - set reg=1 if reg2 == reg3, otherwise set reg1=0
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sne reg1, reg2, reg3 - set reg=1 if reg2 != reg3, otherwise set reg1=0
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slt reg1, reg2, reg3 - set reg=1 if reg2 < reg3 (unsigned), otherwise set reg1=0
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slts reg1, reg2, reg3 - set reg=1 if reg2 < reg3 (signed), otherwise set reg1=0
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sle reg1, reg2, reg3 - set reg=1 if reg2 <= reg3 (unsigned), otherwise set reg1=0
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sles reg1, reg2, reg3 - set reg=1 if reg2 <= reg3 (signed), otherwise set reg1=0
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sgt reg1, reg2, reg3 - set reg=1 if reg2 > reg3 (unsigned), otherwise set reg1=0
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sgts reg1, reg2, reg3 - set reg=1 if reg2 > reg3 (signed), otherwise set reg1=0
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sge reg1, reg2, reg3 - set reg=1 if reg2 >= reg3 (unsigned), otherwise set reg1=0
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sges reg1, reg2, reg3 - set reg=1 if reg2 >= reg3 (signed), otherwise set reg1=0
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TODO: support for the prog8 special branching instructions if_XX (bcc, bcs etc.)
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but we don't have any 'processor flags' whatsoever in the vm so it's a bit weird
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@ -95,7 +95,9 @@ All have type b or w. Note: result types are the same as operand types! E.g. byt
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ext reg1 - reg1 = unsigned extension of reg1 (which in practice just means clearing the MSB / MSW) (latter not yet implemented as we don't have longs yet)
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exts reg1 - reg1 = signed extension of reg1 (byte to word, or word to long) (note: latter ext.w, not yet implemented as we don't have longs yet)
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inc reg1 - reg1 = reg1+1
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incm address - memory at address += 1
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dec reg1 - reg1 = reg1-1
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decm address - memory at address -= 1
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neg reg1 - reg1 = sign negation of reg1
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add reg1, reg2, reg3 - reg1 = reg2+reg3 (unsigned + signed)
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sub reg1, reg2, reg3 - reg1 = reg2-reg3 (unsigned + signed)
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@ -181,7 +183,9 @@ enum class Opcode {
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SGES,
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INC,
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INCM,
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DEC,
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DECM,
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NEG,
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ADD,
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SUB,
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@ -225,19 +229,22 @@ data class Instruction(
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val value: Int?=null, // 0-$ffff
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val symbol: List<String>?=null // alternative to value
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) {
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override fun toString(): String {
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val result = mutableListOf(opcode.name.lowercase())
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init {
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val format = instructionFormats.getValue(opcode)
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if(format.datatypes.isNotEmpty() && type==null)
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throw IllegalArgumentException("missing type")
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if(format.reg1 && reg1==null ||
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format.reg2 && reg2==null ||
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format.reg3 && reg3==null)
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format.reg2 && reg2==null ||
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format.reg3 && reg3==null)
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throw IllegalArgumentException("missing a register")
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if(format.value && (value==null && symbol==null))
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throw IllegalArgumentException("missing a value or symbol")
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}
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override fun toString(): String {
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val result = mutableListOf(opcode.name.lowercase())
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when(type) {
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VmDataType.BYTE -> result.add(".b ")
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@ -320,7 +327,9 @@ val instructionFormats = mutableMapOf(
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Opcode.SGES to InstructionFormat(BW, true, true, true, false),
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Opcode.INC to InstructionFormat(BW, true, false, false, false),
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Opcode.INCM to InstructionFormat(BW, false, false, false, true ),
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Opcode.DEC to InstructionFormat(BW, true, false, false, false),
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Opcode.DECM to InstructionFormat(BW, false, false, false, true ),
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Opcode.NEG to InstructionFormat(BW, true, false, false, false),
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Opcode.ADD to InstructionFormat(BW, true, true, true, false),
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Opcode.SUB to InstructionFormat(BW, true, true, true, false),
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@ -121,7 +121,9 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
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Opcode.SGES -> InsSGES(ins)
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Opcode.INC -> InsINC(ins)
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Opcode.INCM -> InsINCM(ins)
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Opcode.DEC -> InsDEC(ins)
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Opcode.DECM -> InsDECM(ins)
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Opcode.NEG -> InsNEG(ins)
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Opcode.ADD -> InsADD(ins)
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Opcode.SUB -> InsSUB(ins)
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@ -507,6 +509,14 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
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pc++
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}
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private fun InsINCM(i: Instruction) {
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when(i.type!!) {
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VmDataType.BYTE -> memory.setUB(i.value!!, (memory.getUB(i.value)+1u).toUByte())
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VmDataType.WORD -> memory.setUW(i.value!!, (memory.getUW(i.value)+1u).toUShort())
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}
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pc++
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}
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private fun InsDEC(i: Instruction) {
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when(i.type!!) {
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VmDataType.BYTE -> registers.setUB(i.reg1!!, (registers.getUB(i.reg1)-1u).toUByte())
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@ -515,6 +525,14 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
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pc++
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}
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private fun InsDECM(i: Instruction) {
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when(i.type!!) {
|
||||
VmDataType.BYTE -> memory.setUB(i.value!!, (memory.getUB(i.value)-1u).toUByte())
|
||||
VmDataType.WORD -> memory.setUW(i.value!!, (memory.getUW(i.value)-1u).toUShort())
|
||||
}
|
||||
pc++
|
||||
}
|
||||
|
||||
private fun InsNEG(i: Instruction) {
|
||||
when(i.type!!) {
|
||||
VmDataType.BYTE -> registers.setUB(i.reg1!!, (-registers.getUB(i.reg1).toInt()).toUByte())
|
||||
|
||||
@ -47,23 +47,20 @@ class TestInstructions: FunSpec({
|
||||
}
|
||||
|
||||
test("missing type should fail") {
|
||||
val ins = Instruction(Opcode.BZ, reg1=42, value=9999)
|
||||
shouldThrow<IllegalArgumentException> {
|
||||
ins.toString()
|
||||
Instruction(Opcode.BZ, reg1=42, value=9999)
|
||||
}
|
||||
}
|
||||
|
||||
test("missing registers should fail") {
|
||||
val ins = Instruction(Opcode.BZ, VmDataType.BYTE, value=9999)
|
||||
shouldThrow<IllegalArgumentException> {
|
||||
ins.toString()
|
||||
Instruction(Opcode.BZ, VmDataType.BYTE, value=9999)
|
||||
}
|
||||
}
|
||||
|
||||
test("missing value should fail") {
|
||||
val ins = Instruction(Opcode.BZ, VmDataType.BYTE, reg1=42)
|
||||
shouldThrow<IllegalArgumentException> {
|
||||
ins.toString()
|
||||
Instruction(Opcode.BZ, VmDataType.BYTE, reg1=42)
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user