Apple-2-SW/prog8
1
0
Fork 0
mirror of https://github.com/irmen/prog8.git synced 2026-04-21 17:16:33 +00:00
Code Issues Projects Releases Wiki Activity

BSSHIGHRAM_END more clearly defined (to be inclusive)

Browse Source
This commit is contained in:
Irmen de Jong
2023-12-23 19:05:06 +01:00
parent 4cd9bb8f99
commit 0e0fac8c4b
5 changed files with 14 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files
codeCore/src/prog8/code/target/c64/C64MachineDefinition.kt
+1 -1
View File
@@ -17,7 +17,7 @@ class C64MachineDefinition: IMachineDefinition {
override val PROGRAM_LOAD_ADDRESS = 0x0801u
override val BSSHIGHRAM_START = 0xc000u
override val BSSHIGHRAM_END = 0xd000u
override val BSSHIGHRAM_END = 0xcfffu
override lateinit var zeropage: Zeropage
override lateinit var golden: GoldenRam
codeCore/src/prog8/code/target/cx16/CX16MachineDefinition.kt
+1 -1
View File
@@ -16,7 +16,7 @@ class CX16MachineDefinition: IMachineDefinition {
override val PROGRAM_LOAD_ADDRESS = 0x0801u
override val BSSHIGHRAM_START = 0xa000u // hiram bank 1, 8Kb, assumed to be active
override val BSSHIGHRAM_END = 0xc000u // rom starts here.
override val BSSHIGHRAM_END = 0xbfffu // Rom starts at $c000
override lateinit var zeropage: Zeropage
override lateinit var golden: GoldenRam
codeCore/src/prog8/code/target/pet/PETMachineDefinition.kt
+2 -2
View File
@@ -15,8 +15,8 @@ class PETMachineDefinition: IMachineDefinition {
override val FLOAT_MEM_SIZE = Mflpt5.FLOAT_MEM_SIZE
override val PROGRAM_LOAD_ADDRESS = 0x0401u
override val BSSHIGHRAM_START = 0xffffu
override val BSSHIGHRAM_END = 0xffffu
override val BSSHIGHRAM_START = 0u
override val BSSHIGHRAM_END = 0u
override lateinit var zeropage: Zeropage
override lateinit var golden: GoldenRam