mirror of
https://github.com/irmen/prog8.git
synced 2026-04-19 04:17:08 +00:00
vm: simple optimizations for +/-/*/div with constants
This commit is contained in:
Irmen de Jong
@@ -370,10 +370,10 @@ class CodeGen(internal val program: PtProgram,
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return code
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}
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private val powersOfTwo = (0..16).map { 2.0.pow(it.toDouble()).toInt() }
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internal val powersOfTwo = (0..16).map { 2.0.pow(it.toDouble()).toInt() }
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internal fun multiplyByConst(dt: VmDataType, reg: Int, factor: Int): VmCodeChunk {
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require(factor>=0)
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// TODO support floating-point factors
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val code = VmCodeChunk()
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if(factor==1)
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return code
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@@ -386,7 +386,7 @@ class CodeGen(internal val program: PtProgram,
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// just shift multiple bits
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val pow2reg = vmRegisters.nextFree()
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code += VmCodeInstruction(Opcode.LOAD, dt, reg1=pow2reg, value=pow2)
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code += VmCodeInstruction(Opcode.LSLM, dt, reg1=reg, reg2=reg, reg3=pow2reg)
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code += VmCodeInstruction(Opcode.LSLX, dt, reg1=reg, reg2=reg, reg3=pow2reg)
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} else {
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if (factor == 0) {
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code += VmCodeInstruction(Opcode.LOAD, dt, reg1=reg, value=0)
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@@ -400,6 +400,34 @@ class CodeGen(internal val program: PtProgram,
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return code
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}
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internal fun divideByConst(dt: VmDataType, reg: Int, factor: Int): VmCodeChunk {
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// TODO support floating-point factors
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val code = VmCodeChunk()
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if(factor==1)
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return code
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val pow2 = powersOfTwo.indexOf(factor)
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if(pow2==1) {
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// just shift 1 bit
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code += VmCodeInstruction(Opcode.LSR, dt, reg1=reg)
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}
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else if(pow2>=1) {
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// just shift multiple bits
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val pow2reg = vmRegisters.nextFree()
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code += VmCodeInstruction(Opcode.LOAD, dt, reg1=pow2reg, value=pow2)
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code += VmCodeInstruction(Opcode.LSRX, dt, reg1=reg, reg2=reg, reg3=pow2reg)
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} else {
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if (factor == 0) {
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code += VmCodeInstruction(Opcode.LOAD, dt, reg1=reg, value=0)
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}
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else {
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val factorReg = vmRegisters.nextFree()
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code += VmCodeInstruction(Opcode.LOAD, dt, reg1=factorReg, value= factor)
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code += VmCodeInstruction(Opcode.DIV, dt, reg1=reg, reg2=reg, reg3=factorReg)
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}
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}
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return code
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}
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private fun translate(ifElse: PtIfElse): VmCodeChunk {
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var branch = Opcode.BZ
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var condition = ifElse.condition
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@@ -264,73 +264,214 @@ internal class ExpressionGen(private val codeGen: CodeGen) {
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}
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private fun translate(binExpr: PtBinaryExpression, resultRegister: Int): VmCodeChunk {
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val vmDt = codeGen.vmType(binExpr.left.type)
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val signed = binExpr.left.type in SignedDatatypes
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return when(binExpr.operator) {
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"+" -> operatorPlus(binExpr, vmDt, resultRegister)
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"-" -> operatorMinus(binExpr, vmDt, resultRegister)
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"*" -> operatorMultiply(binExpr, vmDt, resultRegister)
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"/" -> operatorDivide(binExpr, vmDt, resultRegister)
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"%" -> operatorModulo(binExpr, vmDt, resultRegister)
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"|", "or" -> operatorOr(binExpr, vmDt, resultRegister)
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"&", "and" -> operatorAnd(binExpr, vmDt, resultRegister)
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"^", "xor" -> operatorXor(binExpr, vmDt, resultRegister)
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"<<" -> operatorShiftLeft(binExpr, vmDt, resultRegister)
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">>" -> operatorShiftRight(binExpr, vmDt, resultRegister, signed)
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"==" -> operatorEquals(binExpr, vmDt, resultRegister, true)
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"!=" -> operatorEquals(binExpr, vmDt, resultRegister, false)
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"<" -> operatorLessThan(binExpr, vmDt, resultRegister, signed, false)
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">" -> operatorGreaterThan(binExpr, vmDt, resultRegister, signed, false)
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"<=" -> operatorLessThan(binExpr, vmDt, resultRegister, signed, true)
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">=" -> operatorGreaterThan(binExpr, vmDt, resultRegister, signed, true)
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else -> throw AssemblyError("weird operator ${binExpr.operator}")
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}
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}
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private fun operatorGreaterThan(
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binExpr: PtBinaryExpression,
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vmDt: VmDataType,
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resultRegister: Int,
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signed: Boolean,
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greaterEquals: Boolean
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): VmCodeChunk {
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val code = VmCodeChunk()
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val leftResultReg = codeGen.vmRegisters.nextFree()
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val rightResultReg = codeGen.vmRegisters.nextFree()
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// TODO: optimized codegen when left or right operand is known 0 or 1 or whatever. But only if this would result in a different opcode such as ADD 1 -> INC, MUL 1 -> NOP
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// actually optimizing the code should not be done here but in a tailored code optimizer step.
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// multiplyByConst()
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val leftCode = translateExpression(binExpr.left, leftResultReg)
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val rightCode = translateExpression(binExpr.right, rightResultReg)
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code += leftCode
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code += rightCode
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val vmDt = codeGen.vmType(binExpr.left.type)
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val signed = binExpr.left.type in SignedDatatypes
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when(binExpr.operator) {
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"+" -> {
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code += VmCodeInstruction(Opcode.ADD, vmDt, reg1=resultRegister, reg2=leftResultReg, reg3=rightResultReg)
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}
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"-" -> {
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code += VmCodeInstruction(Opcode.SUB, vmDt, reg1=resultRegister, reg2=leftResultReg, reg3=rightResultReg)
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}
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"*" -> {
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code += VmCodeInstruction(Opcode.MUL, vmDt, reg1=resultRegister, reg2=leftResultReg, reg3=rightResultReg)
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}
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"/" -> {
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code += VmCodeInstruction(Opcode.DIV, vmDt, reg1=resultRegister, reg2=leftResultReg, reg3=rightResultReg)
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}
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"%" -> {
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code += VmCodeInstruction(Opcode.MOD, vmDt, reg1=resultRegister, reg2=leftResultReg, reg3=rightResultReg)
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}
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"|", "or" -> {
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code += VmCodeInstruction(Opcode.OR, vmDt, reg1=resultRegister, reg2=leftResultReg, reg3=rightResultReg)
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}
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"&", "and" -> {
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code += VmCodeInstruction(Opcode.AND, vmDt, reg1=resultRegister, reg2=leftResultReg, reg3=rightResultReg)
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}
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"^", "xor" -> {
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code += VmCodeInstruction(Opcode.XOR, vmDt, reg1=resultRegister, reg2=leftResultReg, reg3=rightResultReg)
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}
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"<<" -> {
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code += VmCodeInstruction(Opcode.LSLM, vmDt, reg1=resultRegister, reg2=leftResultReg, reg3=rightResultReg)
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}
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">>" -> {
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val opc = if(signed) Opcode.ASRM else Opcode.LSRM
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code += VmCodeInstruction(opc, vmDt, reg1=resultRegister, reg2=leftResultReg, reg3=rightResultReg)
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}
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"==" -> {
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code += VmCodeInstruction(Opcode.SEQ, vmDt, reg1=resultRegister, reg2=leftResultReg, reg3=rightResultReg)
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}
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"!=" -> {
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code += VmCodeInstruction(Opcode.SNE, vmDt, reg1=resultRegister, reg2=leftResultReg, reg3=rightResultReg)
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}
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"<" -> {
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val ins = if(signed) Opcode.SLTS else Opcode.SLT
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code += VmCodeInstruction(ins, vmDt, reg1=resultRegister, reg2=leftResultReg, reg3=rightResultReg)
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}
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">" -> {
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val ins = if(signed) Opcode.SGTS else Opcode.SGT
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code += VmCodeInstruction(ins, vmDt, reg1=resultRegister, reg2=leftResultReg, reg3=rightResultReg)
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}
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"<=" -> {
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val ins = if(signed) Opcode.SLES else Opcode.SLE
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code += VmCodeInstruction(ins, vmDt, reg1=resultRegister, reg2=leftResultReg, reg3=rightResultReg)
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}
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">=" -> {
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val ins = if(signed) Opcode.SGES else Opcode.SGE
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code += VmCodeInstruction(ins, vmDt, reg1=resultRegister, reg2=leftResultReg, reg3=rightResultReg)
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}
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else -> throw AssemblyError("weird operator ${binExpr.operator}")
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code += translateExpression(binExpr.left, leftResultReg)
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code += translateExpression(binExpr.right, rightResultReg)
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val ins = if(signed) {
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if(greaterEquals) Opcode.SGES else Opcode.SGTS
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} else {
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if(greaterEquals) Opcode.SGE else Opcode.SGT
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}
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code += VmCodeInstruction(ins, vmDt, reg1=resultRegister, reg2=leftResultReg, reg3=rightResultReg)
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return code
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}
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private fun operatorLessThan(
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binExpr: PtBinaryExpression,
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vmDt: VmDataType,
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resultRegister: Int,
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signed: Boolean,
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lessEquals: Boolean
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): VmCodeChunk {
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val code = VmCodeChunk()
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val leftResultReg = codeGen.vmRegisters.nextFree()
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val rightResultReg = codeGen.vmRegisters.nextFree()
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code += translateExpression(binExpr.left, leftResultReg)
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code += translateExpression(binExpr.right, rightResultReg)
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val ins = if(signed) {
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if(lessEquals) Opcode.SLES else Opcode.SLTS
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} else {
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if(lessEquals) Opcode.SLE else Opcode.SLT
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}
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code += VmCodeInstruction(ins, vmDt, reg1=resultRegister, reg2=leftResultReg, reg3=rightResultReg)
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return code
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}
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private fun operatorEquals(binExpr: PtBinaryExpression, vmDt: VmDataType, resultRegister: Int, notEquals: Boolean): VmCodeChunk {
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val code = VmCodeChunk()
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val leftResultReg = codeGen.vmRegisters.nextFree()
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val rightResultReg = codeGen.vmRegisters.nextFree()
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code += translateExpression(binExpr.left, leftResultReg)
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code += translateExpression(binExpr.right, rightResultReg)
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val opcode = if(notEquals) Opcode.SNE else Opcode.SEQ
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code += VmCodeInstruction(opcode, vmDt, reg1=resultRegister, reg2=leftResultReg, reg3=rightResultReg)
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return code
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}
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private fun operatorShiftRight(binExpr: PtBinaryExpression, vmDt: VmDataType, resultRegister: Int, signed: Boolean): VmCodeChunk {
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val code = VmCodeChunk()
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val leftResultReg = codeGen.vmRegisters.nextFree()
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val rightResultReg = codeGen.vmRegisters.nextFree()
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code += translateExpression(binExpr.left, leftResultReg)
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code += translateExpression(binExpr.right, rightResultReg)
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val opc = if(signed) Opcode.ASRX else Opcode.LSRX
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code += VmCodeInstruction(opc, vmDt, reg1=resultRegister, reg2=leftResultReg, reg3=rightResultReg)
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return code
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}
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private fun operatorShiftLeft(binExpr: PtBinaryExpression, vmDt: VmDataType, resultRegister: Int): VmCodeChunk {
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val code = VmCodeChunk()
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val leftResultReg = codeGen.vmRegisters.nextFree()
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val rightResultReg = codeGen.vmRegisters.nextFree()
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code += translateExpression(binExpr.left, leftResultReg)
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code += translateExpression(binExpr.right, rightResultReg)
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code += VmCodeInstruction(Opcode.LSLX, vmDt, reg1=resultRegister, reg2=leftResultReg, reg3=rightResultReg)
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return code
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}
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private fun operatorXor(binExpr: PtBinaryExpression, vmDt: VmDataType, resultRegister: Int): VmCodeChunk {
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val code = VmCodeChunk()
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val leftResultReg = codeGen.vmRegisters.nextFree()
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val rightResultReg = codeGen.vmRegisters.nextFree()
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code += translateExpression(binExpr.left, leftResultReg)
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code += translateExpression(binExpr.right, rightResultReg)
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code += VmCodeInstruction(Opcode.XOR, vmDt, reg1=resultRegister, reg2=leftResultReg, reg3=rightResultReg)
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return code
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}
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private fun operatorAnd(binExpr: PtBinaryExpression, vmDt: VmDataType, resultRegister: Int): VmCodeChunk {
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val code = VmCodeChunk()
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val leftResultReg = codeGen.vmRegisters.nextFree()
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val rightResultReg = codeGen.vmRegisters.nextFree()
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code += translateExpression(binExpr.left, leftResultReg)
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code += translateExpression(binExpr.right, rightResultReg)
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code += VmCodeInstruction(Opcode.AND, vmDt, reg1=resultRegister, reg2=leftResultReg, reg3=rightResultReg)
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return code
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}
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private fun operatorOr(binExpr: PtBinaryExpression, vmDt: VmDataType, resultRegister: Int): VmCodeChunk {
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val code = VmCodeChunk()
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val leftResultReg = codeGen.vmRegisters.nextFree()
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val rightResultReg = codeGen.vmRegisters.nextFree()
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code += translateExpression(binExpr.left, leftResultReg)
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code += translateExpression(binExpr.right, rightResultReg)
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code += VmCodeInstruction(Opcode.OR, vmDt, reg1=resultRegister, reg2=leftResultReg, reg3=rightResultReg)
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return code
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}
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private fun operatorModulo(binExpr: PtBinaryExpression, vmDt: VmDataType, resultRegister: Int): VmCodeChunk {
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val code = VmCodeChunk()
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val leftResultReg = codeGen.vmRegisters.nextFree()
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val rightResultReg = codeGen.vmRegisters.nextFree()
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code += translateExpression(binExpr.left, leftResultReg)
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code += translateExpression(binExpr.right, rightResultReg)
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code += VmCodeInstruction(Opcode.MOD, vmDt, reg1=resultRegister, reg2=leftResultReg, reg3=rightResultReg)
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return code
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}
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private fun operatorDivide(binExpr: PtBinaryExpression, vmDt: VmDataType, resultRegister: Int): VmCodeChunk {
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val code = VmCodeChunk()
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val constFactorRight = binExpr.right as? PtNumber
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if(constFactorRight!=null && constFactorRight.type!=DataType.FLOAT) {
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code += translateExpression(binExpr.left, resultRegister)
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val factor = constFactorRight.number.toInt()
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code += codeGen.divideByConst(vmDt, resultRegister, factor)
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} else {
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val leftResultReg = codeGen.vmRegisters.nextFree()
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val rightResultReg = codeGen.vmRegisters.nextFree()
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code += translateExpression(binExpr.left, leftResultReg)
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code += translateExpression(binExpr.right, rightResultReg)
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code += VmCodeInstruction(Opcode.DIV, vmDt, reg1=resultRegister, reg2=leftResultReg, reg3=rightResultReg)
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}
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return code
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}
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private fun operatorMultiply(binExpr: PtBinaryExpression, vmDt: VmDataType, resultRegister: Int): VmCodeChunk {
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val code = VmCodeChunk()
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val constFactorLeft = binExpr.left as? PtNumber
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val constFactorRight = binExpr.right as? PtNumber
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if(constFactorLeft!=null && constFactorLeft.type!=DataType.FLOAT) {
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code += translateExpression(binExpr.right, resultRegister)
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val factor = constFactorLeft.number.toInt()
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code += codeGen.multiplyByConst(vmDt, resultRegister, factor)
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} else if(constFactorRight!=null && constFactorRight.type!=DataType.FLOAT) {
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code += translateExpression(binExpr.left, resultRegister)
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val factor = constFactorRight.number.toInt()
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code += codeGen.multiplyByConst(vmDt, resultRegister, factor)
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} else {
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val leftResultReg = codeGen.vmRegisters.nextFree()
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val rightResultReg = codeGen.vmRegisters.nextFree()
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code += translateExpression(binExpr.left, leftResultReg)
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code += translateExpression(binExpr.right, rightResultReg)
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code += VmCodeInstruction(Opcode.MUL, vmDt, reg1=resultRegister, reg2=leftResultReg, reg3=rightResultReg)
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}
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return code
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}
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private fun operatorMinus(binExpr: PtBinaryExpression, vmDt: VmDataType, resultRegister: Int): VmCodeChunk {
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val code = VmCodeChunk()
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if((binExpr.right as? PtNumber)?.number==1.0) {
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code += translateExpression(binExpr.left, resultRegister)
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code += VmCodeInstruction(Opcode.DEC, vmDt, reg1=resultRegister)
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}
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else {
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val leftResultReg = codeGen.vmRegisters.nextFree()
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val rightResultReg = codeGen.vmRegisters.nextFree()
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code += translateExpression(binExpr.left, leftResultReg)
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code += translateExpression(binExpr.right, rightResultReg)
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code += VmCodeInstruction(Opcode.SUB, vmDt, reg1=resultRegister, reg2=leftResultReg, reg3=rightResultReg)
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}
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return code
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}
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private fun operatorPlus(binExpr: PtBinaryExpression, vmDt: VmDataType, resultRegister: Int): VmCodeChunk {
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val code = VmCodeChunk()
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if((binExpr.left as? PtNumber)?.number==1.0) {
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code += translateExpression(binExpr.right, resultRegister)
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code += VmCodeInstruction(Opcode.INC, vmDt, reg1=resultRegister)
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}
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else if((binExpr.right as? PtNumber)?.number==1.0) {
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code += translateExpression(binExpr.left, resultRegister)
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code += VmCodeInstruction(Opcode.INC, vmDt, reg1=resultRegister)
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}
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else {
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val leftResultReg = codeGen.vmRegisters.nextFree()
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val rightResultReg = codeGen.vmRegisters.nextFree()
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code += translateExpression(binExpr.left, leftResultReg)
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code += translateExpression(binExpr.right, rightResultReg)
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code += VmCodeInstruction(Opcode.ADD, vmDt, reg1=resultRegister, reg2=leftResultReg, reg3=rightResultReg)
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}
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return code
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}
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