mirror of
https://github.com/irmen/prog8.git
synced 2025-01-11 13:29:45 +00:00
split intermediate representation into separate module
This commit is contained in:
parent
97f4316653
commit
101b33c381
2
.idea/misc.xml
generated
2
.idea/misc.xml
generated
@ -19,7 +19,7 @@
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<component name="FrameworkDetectionExcludesConfiguration">
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<type id="Python" />
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</component>
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<component name="ProjectRootManager" version="2" languageLevel="JDK_11" project-jdk-name="11" project-jdk-type="JavaSDK">
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<component name="ProjectRootManager" version="2" languageLevel="JDK_11" default="true" project-jdk-name="11" project-jdk-type="JavaSDK">
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<output url="file://$PROJECT_DIR$/out" />
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</component>
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</project>
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1
.idea/modules.xml
generated
1
.idea/modules.xml
generated
@ -14,6 +14,7 @@
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<module fileurl="file://$PROJECT_DIR$/docs/docs.iml" filepath="$PROJECT_DIR$/docs/docs.iml" />
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<module fileurl="file://$PROJECT_DIR$/examples/examples.iml" filepath="$PROJECT_DIR$/examples/examples.iml" />
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<module fileurl="file://$PROJECT_DIR$/httpCompilerService/httpCompilerService.iml" filepath="$PROJECT_DIR$/httpCompilerService/httpCompilerService.iml" />
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<module fileurl="file://$PROJECT_DIR$/intermediate/intermediate.iml" filepath="$PROJECT_DIR$/intermediate/intermediate.iml" />
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<module fileurl="file://$PROJECT_DIR$/parser/parser.iml" filepath="$PROJECT_DIR$/parser/parser.iml" />
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<module fileurl="file://$PROJECT_DIR$/virtualmachine/virtualmachine.iml" filepath="$PROJECT_DIR$/virtualmachine/virtualmachine.iml" />
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</modules>
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@ -26,6 +26,7 @@ compileTestKotlin {
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dependencies {
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implementation project(':codeAst')
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implementation project(':codeCore')
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implementation project(':intermediate')
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implementation project(':virtualmachine')
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implementation "org.jetbrains.kotlin:kotlin-stdlib-jdk8"
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// implementation "org.jetbrains.kotlin:kotlin-reflect"
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@ -13,5 +13,6 @@
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<orderEntry type="module" module-name="codeAst" />
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<orderEntry type="module" module-name="codeCore" />
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<orderEntry type="module" module-name="virtualmachine" />
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<orderEntry type="module" module-name="intermediate" />
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</component>
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</module>
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@ -1,9 +1,14 @@
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package prog8.codegen.experimental
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import prog8.code.ast.*
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import prog8.code.core.*
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import prog8.vm.Opcode
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import prog8.vm.VmDataType
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import prog8.code.core.AssemblyError
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import prog8.code.core.DataType
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import prog8.code.core.Position
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import prog8.code.core.SignedDatatypes
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import prog8.intermediate.IRCodeChunk
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import prog8.intermediate.IRCodeInstruction
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import prog8.intermediate.Opcode
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import prog8.intermediate.VmDataType
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internal class AssignmentGen(private val codeGen: CodeGen, private val expressionEval: ExpressionGen) {
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@ -5,9 +5,9 @@ import prog8.code.ast.*
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import prog8.code.core.AssemblyError
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import prog8.code.core.DataType
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import prog8.code.core.Position
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import prog8.vm.Opcode
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import prog8.intermediate.*
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import prog8.vm.Syscall
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import prog8.vm.VmDataType
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internal class BuiltinFuncGen(private val codeGen: CodeGen, private val exprGen: ExpressionGen) {
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@ -5,8 +5,7 @@ import prog8.code.StStaticVariable
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import prog8.code.SymbolTable
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import prog8.code.ast.*
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import prog8.code.core.*
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import prog8.vm.Opcode
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import prog8.vm.VmDataType
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import prog8.intermediate.*
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import kotlin.math.pow
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@ -773,8 +772,8 @@ class CodeGen(internal val program: PtProgram,
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is PtScopeVarsDecls -> { /* vars should be looked up via symbol table */ }
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is PtSub -> {
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val vmsub = IRSubroutine(child.scopedName, child.returntype, child.position)
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for (child in child.children) {
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vmsub += translateNode(child)
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for (line in child.children) {
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vmsub += translateNode(line)
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}
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vmblock += vmsub
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}
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@ -5,8 +5,7 @@ import prog8.code.StStaticVariable
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import prog8.code.StSub
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import prog8.code.ast.*
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import prog8.code.core.*
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import prog8.vm.Opcode
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import prog8.vm.VmDataType
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import prog8.intermediate.*
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internal class ExpressionGen(private val codeGen: CodeGen) {
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@ -27,6 +27,7 @@ compileTestKotlin {
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dependencies {
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implementation project(':codeAst')
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implementation project(':codeCore')
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implementation project(':intermediate')
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implementation project(':virtualmachine')
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implementation "org.jetbrains.kotlin:kotlin-stdlib-jdk8"
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// implementation "org.jetbrains.kotlin:kotlin-reflect"
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@ -15,5 +15,6 @@
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<orderEntry type="module" module-name="codeAst" />
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<orderEntry type="module" module-name="codeCore" />
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<orderEntry type="module" module-name="virtualmachine" />
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<orderEntry type="module" module-name="intermediate" />
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</component>
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</module>
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@ -3,10 +3,10 @@ package prog8.codegen.virtual
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import prog8.code.core.AssemblyError
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import prog8.code.core.CompilationOptions
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import prog8.code.core.IAssemblyProgram
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import prog8.vm.Instruction
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import prog8.vm.Opcode
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import prog8.vm.OpcodesWithAddress
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import prog8.vm.VmDataType
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import prog8.intermediate.Instruction
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import prog8.intermediate.Opcode
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import prog8.intermediate.OpcodesWithAddress
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import prog8.intermediate.VmDataType
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import java.io.BufferedWriter
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import java.nio.file.Path
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import kotlin.io.path.bufferedWriter
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@ -1,9 +1,11 @@
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package prog8.codegen.virtual
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import prog8.code.ast.*
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import prog8.code.core.*
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import prog8.vm.Opcode
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import prog8.vm.VmDataType
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import prog8.code.core.AssemblyError
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import prog8.code.core.DataType
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import prog8.code.core.SignedDatatypes
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import prog8.intermediate.Opcode
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import prog8.intermediate.VmDataType
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internal class AssignmentGen(private val codeGen: CodeGen, private val expressionEval: ExpressionGen) {
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@ -4,9 +4,9 @@ import prog8.code.StStaticVariable
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import prog8.code.ast.*
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import prog8.code.core.AssemblyError
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import prog8.code.core.DataType
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import prog8.vm.Opcode
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import prog8.intermediate.Opcode
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import prog8.intermediate.VmDataType
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import prog8.vm.Syscall
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import prog8.vm.VmDataType
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internal class BuiltinFuncGen(private val codeGen: CodeGen, private val exprGen: ExpressionGen) {
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@ -4,8 +4,8 @@ import prog8.code.StStaticVariable
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import prog8.code.SymbolTable
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import prog8.code.ast.*
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import prog8.code.core.*
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import prog8.vm.Opcode
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import prog8.vm.VmDataType
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import prog8.intermediate.Opcode
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import prog8.intermediate.VmDataType
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import kotlin.math.pow
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@ -5,8 +5,8 @@ import prog8.code.StStaticVariable
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import prog8.code.StSub
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import prog8.code.ast.*
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import prog8.code.core.*
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import prog8.vm.Opcode
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import prog8.vm.VmDataType
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import prog8.intermediate.Opcode
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import prog8.intermediate.VmDataType
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internal class ExpressionGen(private val codeGen: CodeGen) {
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@ -1,9 +1,8 @@
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package prog8.codegen.virtual
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import prog8.vm.Instruction
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import prog8.vm.Opcode
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import prog8.vm.VmDataType
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import prog8.intermediate.Instruction
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import prog8.intermediate.Opcode
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import prog8.intermediate.VmDataType
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class VmPeepholeOptimizer(private val vmprog: AssemblyProgram) {
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fun optimize() {
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@ -5,8 +5,8 @@ import io.kotest.matchers.shouldBe
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import prog8.code.SymbolTable
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import prog8.code.ast.PtProgram
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import prog8.codegen.virtual.*
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import prog8.vm.Opcode
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import prog8.vm.VmDataType
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import prog8.intermediate.Opcode
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import prog8.intermediate.VmDataType
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import prog8tests.vm.helpers.DummyMemsizer
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import prog8tests.vm.helpers.DummyStringEncoder
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@ -6,7 +6,10 @@ import prog8.ast.Program
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import prog8.ast.base.FatalAstException
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import prog8.ast.expressions.*
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import prog8.ast.maySwapOperandOrder
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import prog8.ast.statements.*
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import prog8.ast.statements.AnonymousScope
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import prog8.ast.statements.Assignment
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import prog8.ast.statements.IfElse
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import prog8.ast.statements.Jump
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import prog8.ast.walk.AstWalker
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import prog8.ast.walk.IAstModification
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import prog8.code.core.*
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@ -1,8 +1,11 @@
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package prog8.compiler.astprocessing
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import prog8.ast.*
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import prog8.ast.IStatementContainer
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import prog8.ast.Node
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import prog8.ast.Program
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import prog8.ast.base.FatalAstException
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import prog8.ast.expressions.*
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import prog8.ast.getTempVar
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import prog8.ast.statements.*
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import prog8.ast.walk.AstWalker
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import prog8.ast.walk.IAstModification
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62
intermediate/build.gradle
Normal file
62
intermediate/build.gradle
Normal file
@ -0,0 +1,62 @@
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plugins {
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id 'java'
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id 'application'
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id "org.jetbrains.kotlin.jvm"
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id "io.kotest" version "0.3.9"
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}
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java {
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toolchain {
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languageVersion = JavaLanguageVersion.of(javaVersion)
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}
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}
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compileKotlin {
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kotlinOptions {
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jvmTarget = javaVersion
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}
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}
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compileTestKotlin {
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kotlinOptions {
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jvmTarget = javaVersion
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}
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}
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dependencies {
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implementation project(':codeCore')
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implementation project(':codeAst')
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implementation "org.jetbrains.kotlin:kotlin-stdlib-jdk8"
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testImplementation 'io.kotest:kotest-runner-junit5-jvm:5.3.2'
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}
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sourceSets {
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main {
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java {
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srcDirs = ["${project.projectDir}/src"]
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}
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resources {
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srcDirs = ["${project.projectDir}/res"]
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}
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}
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test {
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java {
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srcDir "${project.projectDir}/test"
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}
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}
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}
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test {
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// Enable JUnit 5 (Gradle 4.6+).
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useJUnitPlatform()
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// Always run tests, even when nothing changed.
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dependsOn 'cleanTest'
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// Show test results.
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testLogging {
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events "skipped", "failed"
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}
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}
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17
intermediate/intermediate.iml
Normal file
17
intermediate/intermediate.iml
Normal file
@ -0,0 +1,17 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<module type="JAVA_MODULE" version="4">
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<component name="NewModuleRootManager" inherit-compiler-output="true">
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<exclude-output />
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<content url="file://$MODULE_DIR$">
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<sourceFolder url="file://$MODULE_DIR$/src" isTestSource="false" />
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<sourceFolder url="file://$MODULE_DIR$/test" isTestSource="true" />
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</content>
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<orderEntry type="inheritedJdk" />
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<orderEntry type="sourceFolder" forTests="false" />
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<orderEntry type="library" name="KotlinJavaRuntime" level="project" />
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<orderEntry type="module" module-name="codeAst" />
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<orderEntry type="module" module-name="codeCore" />
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<orderEntry type="library" name="io.kotest.assertions.core.jvm" level="project" />
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<orderEntry type="library" name="io.kotest.runner.junit5.jvm" level="project" />
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</component>
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</module>
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@ -1,4 +1,4 @@
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package prog8.codegen.experimental
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package prog8.intermediate
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import prog8.code.core.*
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import java.io.BufferedWriter
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@ -1,9 +1,4 @@
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package prog8.codegen.experimental
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import prog8.vm.Instruction
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import prog8.vm.Opcode
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import prog8.vm.VmDataType
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package prog8.intermediate
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class IRPeepholeOptimizer(private val vmprog: IRProgram) {
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fun optimize() {
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@ -192,13 +187,3 @@ class IRPeepholeOptimizer(private val vmprog: IRProgram) {
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return changed
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}
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}
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private interface ICodeChange { // TODO not used? remove?
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fun perform(block: IRCodeChunk)
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class Remove(val idx: Int): ICodeChange {
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override fun perform(block: IRCodeChunk) {
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block.lines.removeAt(idx)
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}
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}
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}
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@ -1,4 +1,4 @@
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package prog8.codegen.experimental
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package prog8.intermediate
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import prog8.code.SymbolTable
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import prog8.code.ast.PtBlock
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@ -6,10 +6,6 @@ import prog8.code.core.CompilationOptions
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import prog8.code.core.DataType
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import prog8.code.core.IStringEncoding
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import prog8.code.core.Position
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import prog8.vm.Instruction
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import prog8.vm.Opcode
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import prog8.vm.OpcodesWithAddress
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import prog8.vm.VmDataType
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import java.nio.file.Path
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// TODO: move this Intermedate Representation into the actual compiler core, code gen modules can receive it as input rather than an Ast.
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@ -76,7 +72,7 @@ class IRCodeInstruction(
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fpReg2: Int?=null, // 0-$ffff
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value: Int?=null, // 0-$ffff
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fpValue: Float?=null,
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labelSymbol: List<String>?=null // alternative to value for branch/call/jump labels
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labelSymbol: List<String>?=null // alternative to value
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): IRCodeLine() {
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val ins = Instruction(opcode, type, reg1, reg2, fpReg1, fpReg2, value, fpValue, labelSymbol)
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@ -1,4 +1,4 @@
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package prog8.vm
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package prog8.intermediate
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/*
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@ -2,7 +2,7 @@ import io.kotest.assertions.throwables.shouldThrow
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import io.kotest.core.spec.style.FunSpec
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import io.kotest.matchers.shouldBe
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import io.kotest.matchers.shouldNotBe
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import prog8.vm.*
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import prog8.intermediate.*
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class TestInstructions: FunSpec({
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@ -2,6 +2,7 @@ include(
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':parser',
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':codeCore',
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':codeAst',
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':intermediate',
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':compilerAst',
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':codeOptimizers',
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':virtualmachine',
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@ -26,6 +26,7 @@ compileTestKotlin {
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dependencies {
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implementation project(':codeCore')
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implementation project(':intermediate')
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implementation "org.jetbrains.kotlin:kotlin-stdlib-jdk8"
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implementation "com.michael-bull.kotlin-result:kotlin-result-jvm:1.1.16"
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testImplementation 'io.kotest:kotest-runner-junit5-jvm:5.3.2'
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|
@ -1,6 +1,7 @@
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package prog8.vm
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import prog8.code.core.unescape
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import prog8.intermediate.*
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class Assembler {
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@ -1,6 +1,9 @@
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package prog8.vm
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import prog8.code.target.virtual.IVirtualMachineRunner
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import prog8.intermediate.Instruction
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import prog8.intermediate.Opcode
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import prog8.intermediate.VmDataType
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import java.awt.Color
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import java.awt.Toolkit
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import java.util.*
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@ -269,7 +272,7 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
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throw IllegalArgumentException("can't POP a float")
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}
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}
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setResultReg(i.reg1!!, value, i.type)
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setResultReg(i.reg1!!, value, i.type!!)
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pc++
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}
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@ -669,9 +672,9 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
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private fun InsINC(i: Instruction) {
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when(i.type!!) {
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VmDataType.BYTE -> registers.setUB(i.reg1!!, (registers.getUB(i.reg1)+1u).toUByte())
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VmDataType.WORD -> registers.setUW(i.reg1!!, (registers.getUW(i.reg1)+1u).toUShort())
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VmDataType.FLOAT -> registers.setFloat(i.fpReg1!!, registers.getFloat(i.fpReg1)+1f)
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VmDataType.BYTE -> registers.setUB(i.reg1!!, (registers.getUB(i.reg1!!)+1u).toUByte())
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VmDataType.WORD -> registers.setUW(i.reg1!!, (registers.getUW(i.reg1!!)+1u).toUShort())
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VmDataType.FLOAT -> registers.setFloat(i.fpReg1!!, registers.getFloat(i.fpReg1!!)+1f)
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}
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pc++
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}
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@ -688,27 +691,27 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
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private fun InsDEC(i: Instruction) {
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when(i.type!!) {
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VmDataType.BYTE -> registers.setUB(i.reg1!!, (registers.getUB(i.reg1)-1u).toUByte())
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VmDataType.WORD -> registers.setUW(i.reg1!!, (registers.getUW(i.reg1)-1u).toUShort())
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VmDataType.FLOAT -> registers.setFloat(i.fpReg1!!, registers.getFloat(i.fpReg1)-1f)
|
||||
VmDataType.BYTE -> registers.setUB(i.reg1!!, (registers.getUB(i.reg1!!)-1u).toUByte())
|
||||
VmDataType.WORD -> registers.setUW(i.reg1!!, (registers.getUW(i.reg1!!)-1u).toUShort())
|
||||
VmDataType.FLOAT -> registers.setFloat(i.fpReg1!!, registers.getFloat(i.fpReg1!!)-1f)
|
||||
}
|
||||
pc++
|
||||
}
|
||||
|
||||
private fun InsDECM(i: Instruction) {
|
||||
when(i.type!!) {
|
||||
VmDataType.BYTE -> memory.setUB(i.value!!, (memory.getUB(i.value)-1u).toUByte())
|
||||
VmDataType.WORD -> memory.setUW(i.value!!, (memory.getUW(i.value)-1u).toUShort())
|
||||
VmDataType.FLOAT -> memory.setFloat(i.value!!, memory.getFloat(i.value)-1f)
|
||||
VmDataType.BYTE -> memory.setUB(i.value!!, (memory.getUB(i.value!!)-1u).toUByte())
|
||||
VmDataType.WORD -> memory.setUW(i.value!!, (memory.getUW(i.value!!)-1u).toUShort())
|
||||
VmDataType.FLOAT -> memory.setFloat(i.value!!, memory.getFloat(i.value!!)-1f)
|
||||
}
|
||||
pc++
|
||||
}
|
||||
|
||||
private fun InsNEG(i: Instruction) {
|
||||
when(i.type!!) {
|
||||
VmDataType.BYTE -> registers.setUB(i.reg1!!, (-registers.getUB(i.reg1).toInt()).toUByte())
|
||||
VmDataType.WORD -> registers.setUW(i.reg1!!, (-registers.getUW(i.reg1).toInt()).toUShort())
|
||||
VmDataType.FLOAT -> registers.setFloat(i.fpReg1!!, -registers.getFloat(i.fpReg1))
|
||||
VmDataType.BYTE -> registers.setUB(i.reg1!!, (-registers.getUB(i.reg1!!).toInt()).toUByte())
|
||||
VmDataType.WORD -> registers.setUW(i.reg1!!, (-registers.getUW(i.reg1!!).toInt()).toUShort())
|
||||
VmDataType.FLOAT -> registers.setFloat(i.fpReg1!!, -registers.getFloat(i.fpReg1!!))
|
||||
}
|
||||
pc++
|
||||
}
|
||||
@ -731,7 +734,7 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
||||
val left = registers.getFloat(i.fpReg1!!)
|
||||
val right = registers.getFloat(i.fpReg2!!)
|
||||
val result = arithFloat(left, "+", right)
|
||||
registers.setFloat(i.fpReg1, result)
|
||||
registers.setFloat(i.fpReg1!!, result)
|
||||
}
|
||||
}
|
||||
pc++
|
||||
@ -744,7 +747,7 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
||||
VmDataType.FLOAT -> {
|
||||
val left = registers.getFloat(i.fpReg1!!)
|
||||
val result = arithFloat(left, "+", i.fpValue!!)
|
||||
registers.setFloat(i.fpReg1, result)
|
||||
registers.setFloat(i.fpReg1!!, result)
|
||||
}
|
||||
}
|
||||
pc++
|
||||
@ -773,7 +776,7 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
||||
val left = registers.getFloat(i.fpReg1!!)
|
||||
val right = registers.getFloat(i.fpReg2!!)
|
||||
val result = arithFloat(left, "-", right)
|
||||
registers.setFloat(i.fpReg1, result)
|
||||
registers.setFloat(i.fpReg1!!, result)
|
||||
}
|
||||
}
|
||||
pc++
|
||||
@ -786,7 +789,7 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
||||
VmDataType.FLOAT -> {
|
||||
val left = registers.getFloat(i.fpReg1!!)
|
||||
val result = arithFloat(left, "-", i.fpValue!!)
|
||||
registers.setFloat(i.fpReg1, result)
|
||||
registers.setFloat(i.fpReg1!!, result)
|
||||
}
|
||||
}
|
||||
pc++
|
||||
@ -815,7 +818,7 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
||||
val left = registers.getFloat(i.fpReg1!!)
|
||||
val right = registers.getFloat(i.fpReg2!!)
|
||||
val result = arithFloat(left, "*", right)
|
||||
registers.setFloat(i.fpReg1, result)
|
||||
registers.setFloat(i.fpReg1!!, result)
|
||||
}
|
||||
}
|
||||
pc++
|
||||
@ -828,7 +831,7 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
||||
VmDataType.FLOAT -> {
|
||||
val left = registers.getFloat(i.fpReg1!!)
|
||||
val result = arithFloat(left, "*", i.fpValue!!)
|
||||
registers.setFloat(i.fpReg1, result)
|
||||
registers.setFloat(i.fpReg1!!, result)
|
||||
}
|
||||
}
|
||||
pc++
|
||||
@ -885,7 +888,7 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
||||
val left = registers.getFloat(i.fpReg1!!)
|
||||
val right = registers.getFloat(i.fpReg2!!)
|
||||
val result = arithFloat(left, "/", right)
|
||||
registers.setFloat(i.fpReg1, result)
|
||||
registers.setFloat(i.fpReg1!!, result)
|
||||
}
|
||||
}
|
||||
pc++
|
||||
@ -898,7 +901,7 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
||||
VmDataType.FLOAT -> {
|
||||
val left = registers.getFloat(i.fpReg1!!)
|
||||
val result = arithFloat(left, "/", i.fpValue!!)
|
||||
registers.setFloat(i.fpReg1, result)
|
||||
registers.setFloat(i.fpReg1!!, result)
|
||||
}
|
||||
}
|
||||
pc++
|
||||
@ -1281,7 +1284,7 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
||||
|
||||
private fun InsEXT(i: Instruction) {
|
||||
when(i.type!!){
|
||||
VmDataType.BYTE -> registers.setUW(i.reg1!!, registers.getUB(i.reg1).toUShort())
|
||||
VmDataType.BYTE -> registers.setUW(i.reg1!!, registers.getUB(i.reg1!!).toUShort())
|
||||
VmDataType.WORD -> throw IllegalArgumentException("ext.w not yet supported, requires 32 bits registers")
|
||||
VmDataType.FLOAT -> throw IllegalArgumentException("invalid float type for this instruction $i")
|
||||
}
|
||||
@ -1290,7 +1293,7 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
||||
|
||||
private fun InsEXTS(i: Instruction) {
|
||||
when(i.type!!){
|
||||
VmDataType.BYTE -> registers.setSW(i.reg1!!, registers.getSB(i.reg1).toShort())
|
||||
VmDataType.BYTE -> registers.setSW(i.reg1!!, registers.getSB(i.reg1!!).toShort())
|
||||
VmDataType.WORD -> throw IllegalArgumentException("exts.w not yet supported, requires 32 bits registers")
|
||||
VmDataType.FLOAT -> throw IllegalArgumentException("invalid float type for this instruction $i")
|
||||
}
|
||||
@ -1309,8 +1312,8 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
||||
|
||||
private fun InsAND(i: Instruction) {
|
||||
when(i.type!!) {
|
||||
VmDataType.BYTE -> registers.setUB(i.reg1!!, registers.getUB(i.reg1) and i.value!!.toUByte())
|
||||
VmDataType.WORD -> registers.setUW(i.reg1!!, registers.getUW(i.reg1) and i.value!!.toUShort())
|
||||
VmDataType.BYTE -> registers.setUB(i.reg1!!, registers.getUB(i.reg1!!) and i.value!!.toUByte())
|
||||
VmDataType.WORD -> registers.setUW(i.reg1!!, registers.getUW(i.reg1!!) and i.value!!.toUShort())
|
||||
VmDataType.FLOAT -> throw IllegalArgumentException("invalid float type for this instruction $i")
|
||||
}
|
||||
pc++
|
||||
@ -1346,8 +1349,8 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
||||
|
||||
private fun InsOR(i: Instruction) {
|
||||
when(i.type!!) {
|
||||
VmDataType.BYTE -> registers.setUB(i.reg1!!, registers.getUB(i.reg1) or i.value!!.toUByte())
|
||||
VmDataType.WORD -> registers.setUW(i.reg1!!, registers.getUW(i.reg1) or i.value!!.toUShort())
|
||||
VmDataType.BYTE -> registers.setUB(i.reg1!!, registers.getUB(i.reg1!!) or i.value!!.toUByte())
|
||||
VmDataType.WORD -> registers.setUW(i.reg1!!, registers.getUW(i.reg1!!) or i.value!!.toUShort())
|
||||
VmDataType.FLOAT -> throw IllegalArgumentException("invalid float type for this instruction $i")
|
||||
}
|
||||
pc++
|
||||
@ -1383,8 +1386,8 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
||||
|
||||
private fun InsXOR(i: Instruction) {
|
||||
when(i.type!!) {
|
||||
VmDataType.BYTE -> registers.setUB(i.reg1!!, registers.getUB(i.reg1) xor i.value!!.toUByte())
|
||||
VmDataType.WORD -> registers.setUW(i.reg1!!, registers.getUW(i.reg1) xor i.value!!.toUShort())
|
||||
VmDataType.BYTE -> registers.setUB(i.reg1!!, registers.getUB(i.reg1!!) xor i.value!!.toUByte())
|
||||
VmDataType.WORD -> registers.setUW(i.reg1!!, registers.getUW(i.reg1!!) xor i.value!!.toUShort())
|
||||
VmDataType.FLOAT -> throw IllegalArgumentException("invalid float type for this instruction $i")
|
||||
}
|
||||
pc++
|
||||
@ -1410,8 +1413,8 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
||||
|
||||
private fun InsINV(i: Instruction) {
|
||||
when(i.type!!) {
|
||||
VmDataType.BYTE -> registers.setUB(i.reg1!!, registers.getUB(i.reg1).inv())
|
||||
VmDataType.WORD -> registers.setUW(i.reg1!!, registers.getUW(i.reg1).inv())
|
||||
VmDataType.BYTE -> registers.setUB(i.reg1!!, registers.getUB(i.reg1!!).inv())
|
||||
VmDataType.WORD -> registers.setUW(i.reg1!!, registers.getUW(i.reg1!!).inv())
|
||||
VmDataType.FLOAT -> throw IllegalArgumentException("invalid float type for this instruction $i")
|
||||
}
|
||||
pc++
|
||||
@ -1462,12 +1465,12 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
||||
VmDataType.BYTE -> {
|
||||
val value = registers.getSB(i.reg1!!).toInt()
|
||||
statusCarry = (value and 1)!=0
|
||||
registers.setSB(i.reg1, (value shr 1).toByte())
|
||||
registers.setSB(i.reg1!!, (value shr 1).toByte())
|
||||
}
|
||||
VmDataType.WORD -> {
|
||||
val value = registers.getSW(i.reg1!!).toInt()
|
||||
statusCarry = (value and 1)!=0
|
||||
registers.setSW(i.reg1, (value shr 1).toShort())
|
||||
registers.setSW(i.reg1!!, (value shr 1).toShort())
|
||||
}
|
||||
VmDataType.FLOAT -> throw IllegalArgumentException("invalid float type for this instruction $i")
|
||||
}
|
||||
@ -1527,12 +1530,12 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
||||
VmDataType.BYTE -> {
|
||||
val value = registers.getUB(i.reg1!!).toInt()
|
||||
statusCarry = (value and 1)!=0
|
||||
registers.setUB(i.reg1, (value shr 1).toUByte())
|
||||
registers.setUB(i.reg1!!, (value shr 1).toUByte())
|
||||
}
|
||||
VmDataType.WORD -> {
|
||||
val value = registers.getUW(i.reg1!!).toInt()
|
||||
statusCarry = (value and 1)!=0
|
||||
registers.setUW(i.reg1, (value shr 1).toUShort())
|
||||
registers.setUW(i.reg1!!, (value shr 1).toUShort())
|
||||
}
|
||||
VmDataType.FLOAT -> throw IllegalArgumentException("invalid float type for this instruction $i")
|
||||
}
|
||||
@ -1597,12 +1600,12 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
||||
VmDataType.BYTE -> {
|
||||
val value = registers.getUB(i.reg1!!).toInt()
|
||||
statusCarry = (value and 0x80)!=0
|
||||
registers.setUB(i.reg1, (value shl 1).toUByte())
|
||||
registers.setUB(i.reg1!!, (value shl 1).toUByte())
|
||||
}
|
||||
VmDataType.WORD -> {
|
||||
val value = registers.getUW(i.reg1!!).toInt()
|
||||
statusCarry = (value and 0x8000)!=0
|
||||
registers.setUW(i.reg1, (value shl 1).toUShort())
|
||||
registers.setUW(i.reg1!!, (value shl 1).toUShort())
|
||||
}
|
||||
VmDataType.FLOAT -> throw IllegalArgumentException("invalid float type for this instruction $i")
|
||||
}
|
||||
@ -1638,7 +1641,7 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
||||
(orig.toUInt().rotateRight(1) or carry).toUByte()
|
||||
} else
|
||||
orig.rotateRight(1)
|
||||
registers.setUB(i.reg1, rotated)
|
||||
registers.setUB(i.reg1!!, rotated)
|
||||
}
|
||||
VmDataType.WORD -> {
|
||||
val orig = registers.getUW(i.reg1!!)
|
||||
@ -1648,7 +1651,7 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
||||
(orig.toUInt().rotateRight(1) or carry).toUShort()
|
||||
} else
|
||||
orig.rotateRight(1)
|
||||
registers.setUW(i.reg1, rotated)
|
||||
registers.setUW(i.reg1!!, rotated)
|
||||
}
|
||||
VmDataType.FLOAT -> {
|
||||
throw IllegalArgumentException("can't ROR a float")
|
||||
@ -1701,7 +1704,7 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
||||
(orig.toUInt().rotateLeft(1) or carry).toUByte()
|
||||
} else
|
||||
orig.rotateLeft(1)
|
||||
registers.setUB(i.reg1, rotated)
|
||||
registers.setUB(i.reg1!!, rotated)
|
||||
}
|
||||
VmDataType.WORD -> {
|
||||
val orig = registers.getUW(i.reg1!!)
|
||||
@ -1711,7 +1714,7 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
||||
(orig.toUInt().rotateLeft(1) or carry).toUShort()
|
||||
} else
|
||||
orig.rotateLeft(1)
|
||||
registers.setUW(i.reg1, rotated)
|
||||
registers.setUW(i.reg1!!, rotated)
|
||||
}
|
||||
VmDataType.FLOAT -> {
|
||||
throw IllegalArgumentException("can't ROL a float")
|
||||
@ -1771,7 +1774,7 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
||||
VmDataType.BYTE -> {
|
||||
val lsb = registers.getUB(i.reg1!!)
|
||||
val msb = registers.getUB(i.reg2!!)
|
||||
registers.setUW(i.reg1, ((msb.toInt() shl 8) or lsb.toInt()).toUShort())
|
||||
registers.setUW(i.reg1!!, ((msb.toInt() shl 8) or lsb.toInt()).toUShort())
|
||||
}
|
||||
VmDataType.WORD -> throw IllegalArgumentException("concat.w not yet supported, requires 32-bits registers")
|
||||
VmDataType.FLOAT -> throw IllegalArgumentException("invalid float type for this instruction $i")
|
||||
@ -1822,7 +1825,7 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
||||
private fun InsFPOW(i: Instruction) {
|
||||
val value = registers.getFloat(i.fpReg1!!)
|
||||
val exponent = registers.getFloat(i.fpReg2!!)
|
||||
registers.setFloat(i.fpReg1, value.pow(exponent))
|
||||
registers.setFloat(i.fpReg1!!, value.pow(exponent))
|
||||
pc++
|
||||
}
|
||||
|
||||
|
@ -13,5 +13,6 @@
|
||||
<orderEntry type="library" name="io.kotest.assertions.core.jvm" level="project" />
|
||||
<orderEntry type="library" name="io.kotest.runner.junit5.jvm" level="project" />
|
||||
<orderEntry type="module" module-name="codeCore" />
|
||||
<orderEntry type="module" module-name="intermediate" />
|
||||
</component>
|
||||
</module>
|
Loading…
x
Reference in New Issue
Block a user