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https://github.com/irmen/prog8.git
synced 2024-12-24 16:29:21 +00:00
vm: implemented some self-assign instructions
This commit is contained in:
Irmen de Jong
parent
4e1184a400
commit
181b98ef9e
@ -12,27 +12,24 @@ sealed class PtExpression(val type: DataType, position: Position) : PtNode(posit
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print(type)
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}
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infix fun isSameTargetAs(other: PtExpression): Boolean = when(this) {
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is PtArrayIndexer -> {
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if(other is PtArrayIndexer && other.type==type) {
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if(other.variable isSameTargetAs variable) {
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other.index isSameTargetAs index
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}
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}
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false
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infix fun isSameAs(other: PtExpression): Boolean {
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return when(this) {
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is PtAddressOf -> other is PtAddressOf && other.type==type && other.identifier isSameAs identifier
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is PtArrayIndexer -> other is PtArrayIndexer && other.type==type && other.variable isSameAs variable && other.index isSameAs index
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is PtBinaryExpression -> other is PtBinaryExpression && other.left isSameAs left && other.right isSameAs right
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is PtContainmentCheck -> other is PtContainmentCheck && other.type==type && other.element isSameAs element && other.iterable isSameAs iterable
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is PtIdentifier -> other is PtIdentifier && other.type==type && other.targetName==targetName
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is PtMachineRegister -> other is PtMachineRegister && other.type==type && other.register==register
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is PtMemoryByte -> other is PtMemoryByte && other.address isSameAs address
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is PtNumber -> other is PtNumber && other.type==type && other.number==number
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is PtPrefix -> other is PtPrefix && other.type==type && other.operator==operator && other.value isSameAs value
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is PtRange -> other is PtRange && other.type==type && other.from==from && other.to==to && other.step==step
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is PtTypeCast -> other is PtTypeCast && other.type==type && other.value isSameAs value
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else -> false
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}
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is PtIdentifier -> other is PtIdentifier && other.type==type && other.targetName==targetName
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is PtMachineRegister -> other is PtMachineRegister && other.register==register
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is PtMemoryByte -> other is PtMemoryByte && address isSameTargetAs other.address
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is PtNumber -> other is PtNumber && other.type == type && other.number==number
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is PtAddressOf -> other is PtAddressOf && other.identifier isSameTargetAs identifier
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is PtPrefix -> other is PtPrefix && other.operator==operator && other.value isSameTargetAs value
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is PtTypeCast -> other is PtTypeCast && other.type==type && other.value isSameTargetAs value
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else -> false
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}
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}
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class PtAddressOf(position: Position) : PtExpression(DataType.UWORD, position) {
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val identifier: PtIdentifier
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get() = children.single() as PtIdentifier
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@ -48,14 +48,33 @@ class PtAssignment(position: Position) : PtNode(position) {
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val isInplaceAssign: Boolean by lazy {
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val target = target.children.single() as PtExpression
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if(value is PtBinaryExpression) {
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target isSameTargetAs (value as PtBinaryExpression).left
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} else
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target isSameTargetAs value
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when(val source = value) {
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is PtArrayIndexer -> {
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if(target is PtArrayIndexer && source.type==target.type) {
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if(target.variable isSameAs source.variable) {
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target.index isSameAs source.index
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}
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}
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false
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}
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is PtIdentifier -> target is PtIdentifier && target.type==source.type && target.targetName==source.targetName
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is PtMachineRegister -> target is PtMachineRegister && target.register==source.register
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is PtMemoryByte -> target is PtMemoryByte && target.address isSameAs source.address
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is PtNumber -> target is PtNumber && target.type == source.type && target.number==source.number
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is PtAddressOf -> target is PtAddressOf && target.identifier isSameAs source.identifier
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is PtPrefix -> {
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(target is PtPrefix && target.operator==source.operator && target.value isSameAs source.value)
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||
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(target is PtIdentifier && (source.value as? PtIdentifier)?.targetName==target.targetName)
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}
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is PtTypeCast -> target is PtTypeCast && target.type==source.type && target.value isSameAs source.value
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is PtBinaryExpression ->
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target isSameAs source.left
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else -> false
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}
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}
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}
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class PtAssignTarget(position: Position) : PtNode(position) {
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val identifier: PtIdentifier?
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get() = children.single() as? PtIdentifier
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@ -81,9 +81,9 @@ internal class VmCodeInstruction(
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fpReg2: Int?=null, // 0-$ffff
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value: Int?=null, // 0-$ffff
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fpValue: Float?=null,
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symbol: List<String>?=null // alternative to value
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labelSymbol: List<String>?=null // alternative to value for branch/call/jump labels
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): VmCodeLine() {
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val ins = Instruction(opcode, type, reg1, reg2, fpReg1, fpReg2, value, fpValue, symbol)
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val ins = Instruction(opcode, type, reg1, reg2, fpReg1, fpReg2, value, fpValue, labelSymbol)
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init {
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if(reg1!=null && (reg1<0 || reg1>65536))
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@ -3,12 +3,16 @@ package prog8.codegen.virtual
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import prog8.code.ast.*
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import prog8.code.core.AssemblyError
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import prog8.code.core.DataType
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import prog8.code.core.Position
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import prog8.vm.Opcode
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import prog8.vm.VmDataType
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internal class AssignmentGen(private val codeGen: CodeGen, private val expressionEval: ExpressionGen) {
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internal fun translate(assignment: PtAssignment): VmCodeChunk {
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if(assignment.target.children.single() is PtMachineRegister)
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throw AssemblyError("assigning to a register should be done by just evaluating the expression into resultregister")
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return if (assignment.isInplaceAssign)
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translateInplaceAssign(assignment)
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else
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@ -16,14 +20,104 @@ internal class AssignmentGen(private val codeGen: CodeGen, private val expressio
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}
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private fun translateInplaceAssign(assignment: PtAssignment): VmCodeChunk {
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// TODO can in-place assignments be optimized more? use special memory versions of instructions instead of register ones?
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return translateRegularAssign(assignment)
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val ident = assignment.target.identifier
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val memory = assignment.target.memory
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val array = assignment.target.array
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return if(ident!=null) {
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val address = codeGen.allocations.get(ident.targetName)
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assignSelfInMemory(address, assignment.value, assignment.position, assignment)
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} else if(memory != null) {
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if(memory.address is PtNumber) {
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assignSelfInMemory((memory.address as PtNumber).number.toInt(), assignment.value, assignment.position, assignment)
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} else {
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fallbackAssign(assignment)
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}
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} else if(array!=null) {
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// TODO in-place array element assignment?
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fallbackAssign(assignment)
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} else {
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fallbackAssign(assignment)
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}
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}
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private fun assignSelfInMemory(
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targetAddress: Int,
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value: PtExpression,
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position: Position,
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origAssign: PtAssignment
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): VmCodeChunk {
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val vmDt = codeGen.vmType(value.type)
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val code = VmCodeChunk()
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when(value) {
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is PtIdentifier -> return code // do nothing, x=x null assignment.
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is PtMachineRegister -> return code // do nothing, reg=reg null assignment
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is PtPrefix -> return inplacePrefix(value.operator, vmDt, targetAddress)
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is PtBinaryExpression -> return inplaceBinexpr(value.operator, value.right, vmDt, targetAddress, origAssign)
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is PtMemoryByte -> {
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return if (!codeGen.options.compTarget.machine.isIOAddress(targetAddress.toUInt()))
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code // do nothing, mem=mem null assignment.
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else {
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// read and write a (i/o) memory location to itself.
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code += VmCodeInstruction(Opcode.LOADM, vmDt, reg1 = 0, value = targetAddress.toInt())
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code += VmCodeInstruction(Opcode.STOREM, vmDt, reg1 = 0, value = targetAddress.toInt())
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code
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}
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}
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else -> return fallbackAssign(origAssign)
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}
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}
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private fun fallbackAssign(origAssign: PtAssignment): VmCodeChunk {
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if (codeGen.options.slowCodegenWarnings)
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codeGen.errors.warn("indirect code for in-place assignment", origAssign.position)
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return translateRegularAssign(origAssign)
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}
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private fun inplaceBinexpr(
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operator: String,
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right: PtExpression,
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vmDt: VmDataType,
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targetAddress: Int,
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origAssign: PtAssignment
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): VmCodeChunk {
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when(operator) {
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"+" -> { /* TODO */ }
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"-" -> { /* TODO */ }
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"*" -> { /* TODO */ }
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"/" -> { /* TODO */ }
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"|" -> { /* TODO */ }
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"&" -> { /* TODO */ }
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"^" -> { /* TODO */ }
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else -> {}
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}
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return fallbackAssign(origAssign)
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}
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private fun inplacePrefix(operator: String, vmDt: VmDataType, address: Int): VmCodeChunk {
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val code= VmCodeChunk()
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when(operator) {
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"+" -> { }
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"-" -> {
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code += VmCodeInstruction(Opcode.NEGM, vmDt, value = address)
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}
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"~" -> {
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val regMask = codeGen.vmRegisters.nextFree()
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val mask = if(vmDt==VmDataType.BYTE) 0x00ff else 0xffff
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code += VmCodeInstruction(Opcode.LOAD, vmDt, reg1=regMask, value = mask)
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code += VmCodeInstruction(Opcode.XORM, vmDt, reg1=regMask, value = address)
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}
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"not" -> {
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code += VmCodeInstruction(Opcode.NOTM, vmDt, value = address)
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}
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else -> throw AssemblyError("weird prefix operator")
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}
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return code
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}
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private fun translateRegularAssign(assignment: PtAssignment): VmCodeChunk {
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// note: assigning array and string values is done via an explicit memcopy/stringcopy function call.
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if(assignment.target.children.single() is PtMachineRegister)
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throw AssemblyError("assigning to a register should be done by just evaluating the expression into resultregister")
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val ident = assignment.target.identifier
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val memory = assignment.target.memory
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val array = assignment.target.array
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@ -116,7 +116,7 @@ internal class BuiltinFuncGen(private val codeGen: CodeGen, private val exprGen:
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val notNegativeLabel = codeGen.createLabelName()
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code += VmCodeInstruction(Opcode.LOAD, VmDataType.BYTE, reg1=andReg, value=0x80)
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code += VmCodeInstruction(Opcode.AND, VmDataType.BYTE, reg1=andReg, reg2=resultRegister)
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code += VmCodeInstruction(Opcode.BZ, VmDataType.BYTE, reg1=andReg, symbol = notNegativeLabel)
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code += VmCodeInstruction(Opcode.BZ, VmDataType.BYTE, reg1=andReg, labelSymbol = notNegativeLabel)
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code += VmCodeInstruction(Opcode.NEG, VmDataType.BYTE, reg1=resultRegister)
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code += VmCodeInstruction(Opcode.EXT, VmDataType.BYTE, reg1=resultRegister)
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code += VmCodeLabel(notNegativeLabel)
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@ -126,7 +126,7 @@ internal class BuiltinFuncGen(private val codeGen: CodeGen, private val exprGen:
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val notNegativeLabel = codeGen.createLabelName()
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code += VmCodeInstruction(Opcode.LOAD, VmDataType.WORD, reg1=andReg, value=0x8000)
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code += VmCodeInstruction(Opcode.AND, VmDataType.WORD, reg1=andReg, reg2=resultRegister)
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code += VmCodeInstruction(Opcode.BZ, VmDataType.WORD, reg1=andReg, symbol = notNegativeLabel)
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code += VmCodeInstruction(Opcode.BZ, VmDataType.WORD, reg1=andReg, labelSymbol = notNegativeLabel)
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code += VmCodeInstruction(Opcode.NEG, VmDataType.WORD, reg1=resultRegister)
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code += VmCodeLabel(notNegativeLabel)
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}
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@ -123,19 +123,19 @@ class CodeGen(internal val program: PtProgram,
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val elseLabel = createLabelName()
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// note that the branch opcode used is the opposite as the branch condition, because the generated code jumps to the 'else' part
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code += when(branch.condition) {
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BranchCondition.CS -> VmCodeInstruction(Opcode.BSTCC, symbol = elseLabel)
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BranchCondition.CC -> VmCodeInstruction(Opcode.BSTCS, symbol = elseLabel)
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BranchCondition.EQ, BranchCondition.Z -> VmCodeInstruction(Opcode.BSTNE, symbol = elseLabel)
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BranchCondition.NE, BranchCondition.NZ -> VmCodeInstruction(Opcode.BSTEQ, symbol = elseLabel)
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BranchCondition.MI, BranchCondition.NEG -> VmCodeInstruction(Opcode.BSTPOS, symbol = elseLabel)
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BranchCondition.PL, BranchCondition.POS -> VmCodeInstruction(Opcode.BSTNEG, symbol = elseLabel)
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BranchCondition.CS -> VmCodeInstruction(Opcode.BSTCC, labelSymbol = elseLabel)
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BranchCondition.CC -> VmCodeInstruction(Opcode.BSTCS, labelSymbol = elseLabel)
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BranchCondition.EQ, BranchCondition.Z -> VmCodeInstruction(Opcode.BSTNE, labelSymbol = elseLabel)
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BranchCondition.NE, BranchCondition.NZ -> VmCodeInstruction(Opcode.BSTEQ, labelSymbol = elseLabel)
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BranchCondition.MI, BranchCondition.NEG -> VmCodeInstruction(Opcode.BSTPOS, labelSymbol = elseLabel)
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BranchCondition.PL, BranchCondition.POS -> VmCodeInstruction(Opcode.BSTNEG, labelSymbol = elseLabel)
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BranchCondition.VC,
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BranchCondition.VS -> throw AssemblyError("conditional branch ${branch.condition} not supported in vm target due to lack of cpu V flag ${branch.position}")
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}
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code += translateNode(branch.trueScope)
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if(branch.falseScope.children.isNotEmpty()) {
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val endLabel = createLabelName()
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code += VmCodeInstruction(Opcode.JUMP, symbol = endLabel)
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code += VmCodeInstruction(Opcode.JUMP, labelSymbol = endLabel)
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code += VmCodeLabel(elseLabel)
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code += translateNode(branch.falseScope)
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code += VmCodeLabel(endLabel)
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@ -163,21 +163,21 @@ class CodeGen(internal val program: PtProgram,
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val values = choice.values.children.map {it as PtNumber}
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if(values.size==1) {
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code += VmCodeInstruction(Opcode.LOAD, valueDt, reg1=choiceReg, value=values[0].number.toInt())
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code += VmCodeInstruction(Opcode.BNE, valueDt, reg1=valueReg, reg2=choiceReg, symbol = skipLabel)
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code += VmCodeInstruction(Opcode.BNE, valueDt, reg1=valueReg, reg2=choiceReg, labelSymbol = skipLabel)
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code += translateNode(choice.statements)
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if(choice.statements.children.last() !is PtReturn)
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code += VmCodeInstruction(Opcode.JUMP, symbol = endLabel)
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code += VmCodeInstruction(Opcode.JUMP, labelSymbol = endLabel)
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} else {
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val matchLabel = createLabelName()
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for (value in values) {
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code += VmCodeInstruction(Opcode.LOAD, valueDt, reg1=choiceReg, value=value.number.toInt())
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code += VmCodeInstruction(Opcode.BEQ, valueDt, reg1=valueReg, reg2=choiceReg, symbol = matchLabel)
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code += VmCodeInstruction(Opcode.BEQ, valueDt, reg1=valueReg, reg2=choiceReg, labelSymbol = matchLabel)
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}
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code += VmCodeInstruction(Opcode.JUMP, symbol = skipLabel)
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code += VmCodeInstruction(Opcode.JUMP, labelSymbol = skipLabel)
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code += VmCodeLabel(matchLabel)
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code += translateNode(choice.statements)
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if(choice.statements.children.last() !is PtReturn)
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code += VmCodeInstruction(Opcode.JUMP, symbol = endLabel)
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code += VmCodeInstruction(Opcode.JUMP, labelSymbol = endLabel)
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}
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code += VmCodeLabel(skipLabel)
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}
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@ -209,11 +209,11 @@ class CodeGen(internal val program: PtProgram,
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code += VmCodeInstruction(Opcode.LOAD, VmDataType.BYTE, reg1=indexReg, value=0)
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code += VmCodeLabel(loopLabel)
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code += VmCodeInstruction(Opcode.LOADX, VmDataType.BYTE, reg1=0, reg2=indexReg, value = arrayAddress)
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code += VmCodeInstruction(Opcode.BZ, VmDataType.BYTE, reg1=0, symbol = endLabel)
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code += VmCodeInstruction(Opcode.BZ, VmDataType.BYTE, reg1=0, labelSymbol = endLabel)
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code += VmCodeInstruction(Opcode.STOREM, VmDataType.BYTE, reg1=0, value = loopvarAddress)
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code += translateNode(forLoop.statements)
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code += VmCodeInstruction(Opcode.INC, VmDataType.BYTE, reg1=indexReg)
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code += VmCodeInstruction(Opcode.JUMP, symbol = loopLabel)
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code += VmCodeInstruction(Opcode.JUMP, labelSymbol = loopLabel)
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code += VmCodeLabel(endLabel)
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} else {
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// iterate over array
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@ -224,12 +224,12 @@ class CodeGen(internal val program: PtProgram,
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code += VmCodeInstruction(Opcode.LOAD, VmDataType.BYTE, reg1=indexReg, value=0)
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code += VmCodeInstruction(Opcode.LOAD, VmDataType.BYTE, reg1=lengthReg, value=lengthBytes)
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code += VmCodeLabel(loopLabel)
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code += VmCodeInstruction(Opcode.BEQ, VmDataType.BYTE, reg1=indexReg, reg2=lengthReg, symbol = endLabel)
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code += VmCodeInstruction(Opcode.BEQ, VmDataType.BYTE, reg1=indexReg, reg2=lengthReg, labelSymbol = endLabel)
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code += VmCodeInstruction(Opcode.LOADX, vmType(elementDt), reg1=0, reg2=indexReg, value=arrayAddress)
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code += VmCodeInstruction(Opcode.STOREM, vmType(elementDt), reg1=0, value = loopvarAddress)
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code += translateNode(forLoop.statements)
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code += addConstReg(VmDataType.BYTE, indexReg, elementSize)
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code += VmCodeInstruction(Opcode.JUMP, symbol = loopLabel)
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code += VmCodeInstruction(Opcode.JUMP, labelSymbol = loopLabel)
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code += VmCodeLabel(endLabel)
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}
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}
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@ -264,7 +264,7 @@ class CodeGen(internal val program: PtProgram,
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code += VmCodeInstruction(Opcode.STOREM, loopvarDt, reg1 = indexReg, value = loopvarAddress)
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}
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val branchOpcode = if(loopvar.dt in SignedDatatypes) Opcode.BLES else Opcode.BLE
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code += VmCodeInstruction(branchOpcode, loopvarDt, reg1=indexReg, reg2=endvalueReg, symbol=loopLabel)
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code += VmCodeInstruction(branchOpcode, loopvarDt, reg1=indexReg, reg2=endvalueReg, labelSymbol=loopLabel)
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return code
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}
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@ -303,9 +303,9 @@ class CodeGen(internal val program: PtProgram,
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code += VmCodeInstruction(Opcode.STOREM, loopvarDt, reg1 = indexReg, value = loopvarAddress)
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}
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code += if(rangeEndWrapped==0) {
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VmCodeInstruction(Opcode.BNZ, loopvarDt, reg1 = indexReg, symbol = loopLabel)
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VmCodeInstruction(Opcode.BNZ, loopvarDt, reg1 = indexReg, labelSymbol = loopLabel)
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} else {
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VmCodeInstruction(Opcode.BNE, loopvarDt, reg1 = indexReg, reg2 = endvalueReg, symbol = loopLabel)
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VmCodeInstruction(Opcode.BNE, loopvarDt, reg1 = indexReg, reg2 = endvalueReg, labelSymbol = loopLabel)
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}
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return code
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}
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@ -492,16 +492,16 @@ class CodeGen(internal val program: PtProgram,
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// if and else parts
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val elseLabel = createLabelName()
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val afterIfLabel = createLabelName()
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code += VmCodeInstruction(elseBranch, vmDt, reg1=leftReg, reg2=rightReg, symbol = elseLabel)
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code += VmCodeInstruction(elseBranch, vmDt, reg1=leftReg, reg2=rightReg, labelSymbol = elseLabel)
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code += translateNode(ifElse.ifScope)
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code += VmCodeInstruction(Opcode.JUMP, symbol = afterIfLabel)
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code += VmCodeInstruction(Opcode.JUMP, labelSymbol = afterIfLabel)
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code += VmCodeLabel(elseLabel)
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code += translateNode(ifElse.elseScope)
|
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code += VmCodeLabel(afterIfLabel)
|
||||
} else {
|
||||
// only if part
|
||||
val afterIfLabel = createLabelName()
|
||||
code += VmCodeInstruction(elseBranch, vmDt, reg1=leftReg, reg2=rightReg, symbol = afterIfLabel)
|
||||
code += VmCodeInstruction(elseBranch, vmDt, reg1=leftReg, reg2=rightReg, labelSymbol = afterIfLabel)
|
||||
code += translateNode(ifElse.ifScope)
|
||||
code += VmCodeLabel(afterIfLabel)
|
||||
}
|
||||
@ -516,16 +516,16 @@ class CodeGen(internal val program: PtProgram,
|
||||
// if and else parts
|
||||
val elseLabel = createLabelName()
|
||||
val afterIfLabel = createLabelName()
|
||||
code += VmCodeInstruction(elseBranch, vmDt, reg1=leftReg, symbol = elseLabel)
|
||||
code += VmCodeInstruction(elseBranch, vmDt, reg1=leftReg, labelSymbol = elseLabel)
|
||||
code += translateNode(ifElse.ifScope)
|
||||
code += VmCodeInstruction(Opcode.JUMP, symbol = afterIfLabel)
|
||||
code += VmCodeInstruction(Opcode.JUMP, labelSymbol = afterIfLabel)
|
||||
code += VmCodeLabel(elseLabel)
|
||||
code += translateNode(ifElse.elseScope)
|
||||
code += VmCodeLabel(afterIfLabel)
|
||||
} else {
|
||||
// only if part
|
||||
val afterIfLabel = createLabelName()
|
||||
code += VmCodeInstruction(elseBranch, vmDt, reg1=leftReg, symbol = afterIfLabel)
|
||||
code += VmCodeInstruction(elseBranch, vmDt, reg1=leftReg, labelSymbol = afterIfLabel)
|
||||
code += translateNode(ifElse.ifScope)
|
||||
code += VmCodeLabel(afterIfLabel)
|
||||
}
|
||||
@ -629,7 +629,7 @@ class CodeGen(internal val program: PtProgram,
|
||||
code += VmCodeLabel(repeatLabel)
|
||||
code += translateNode(repeat.statements)
|
||||
code += VmCodeInstruction(Opcode.DEC, vmDt, reg1=counterReg)
|
||||
code += VmCodeInstruction(Opcode.BNZ, vmDt, reg1=counterReg, symbol = repeatLabel)
|
||||
code += VmCodeInstruction(Opcode.BNZ, vmDt, reg1=counterReg, labelSymbol = repeatLabel)
|
||||
return code
|
||||
}
|
||||
|
||||
@ -638,9 +638,9 @@ class CodeGen(internal val program: PtProgram,
|
||||
if(jump.address!=null)
|
||||
throw AssemblyError("cannot jump to memory location in the vm target")
|
||||
code += if(jump.generatedLabel!=null)
|
||||
VmCodeInstruction(Opcode.JUMP, symbol = listOf(jump.generatedLabel!!))
|
||||
VmCodeInstruction(Opcode.JUMP, labelSymbol = listOf(jump.generatedLabel!!))
|
||||
else if(jump.identifier!=null)
|
||||
VmCodeInstruction(Opcode.JUMP, symbol = jump.identifier!!.targetName)
|
||||
VmCodeInstruction(Opcode.JUMP, labelSymbol = jump.identifier!!.targetName)
|
||||
else
|
||||
throw AssemblyError("weird jump")
|
||||
return code
|
||||
|
||||
@ -410,7 +410,7 @@ internal class ExpressionGen(private val codeGen: CodeGen) {
|
||||
val valueReg = codeGen.vmRegisters.nextFree()
|
||||
code += VmCodeInstruction(Opcode.LOAD, VmDataType.BYTE, reg1=resultRegister, value=1)
|
||||
code += VmCodeInstruction(Opcode.FCOMP, VmDataType.FLOAT, reg1=valueReg, fpReg1 = leftFpReg, fpReg2 = rightFpReg)
|
||||
code += VmCodeInstruction(Opcode.BZ, VmDataType.BYTE, reg1=valueReg, symbol = label)
|
||||
code += VmCodeInstruction(Opcode.BZ, VmDataType.BYTE, reg1=valueReg, labelSymbol = label)
|
||||
code += VmCodeInstruction(Opcode.LOAD, VmDataType.BYTE, reg1=resultRegister, value=0)
|
||||
code += VmCodeLabel(label)
|
||||
}
|
||||
@ -664,7 +664,7 @@ internal class ExpressionGen(private val codeGen: CodeGen) {
|
||||
}
|
||||
}
|
||||
}
|
||||
code += VmCodeInstruction(Opcode.CALL, symbol=fcall.functionName)
|
||||
code += VmCodeInstruction(Opcode.CALL, labelSymbol=fcall.functionName)
|
||||
if(fcall.type==DataType.FLOAT) {
|
||||
if (!fcall.void && resultFpRegister != 0) {
|
||||
// Call convention: result value is in fr0, so put it in the required register instead.
|
||||
|
||||
@ -3,8 +3,8 @@ TODO
|
||||
|
||||
For next release
|
||||
^^^^^^^^^^^^^^^^
|
||||
- vm: implement the sin/cos functions in math.p8 and make an example 'shader' that uses them
|
||||
- vm: add more instructions operating directly on memory instead of only registers? (translate assignment self-assigns in AssignmentGen)
|
||||
- vm: implement the missing in-place operators in inplaceBinexpr()
|
||||
- vm: implement the new in-memory instructions in the VirtualMachine eval loop itself.
|
||||
- complete the Inliner
|
||||
- add McCarthy evaluation to shortcircuit and/or expressions. First do ifs by splitting them up? Then do expressions that compute a value?
|
||||
|
||||
@ -23,6 +23,7 @@ Future Things and Ideas
|
||||
Compiler:
|
||||
|
||||
- vm: codeGen: various TODOs to tweak code
|
||||
- vm: implement remaining sin/cos functions in math.p8
|
||||
- vm: somehow deal with asmsubs otherwise the vm IR can't fully encode all of prog8
|
||||
- vm: don't store symbol names in instructions to make optimizing the IR easier? but what about jumps to labels. And it's no longer readable by humans.
|
||||
- vm: how to remove all unused subroutines? (in the assembly codegen, we let 64tass solve this for us)
|
||||
|
||||
@ -4,19 +4,26 @@
|
||||
|
||||
main {
|
||||
sub start() {
|
||||
byte xx
|
||||
byte yy
|
||||
ubyte ubx
|
||||
|
||||
; a "pixelshader":
|
||||
sys.gfx_enable(0) ; enable lo res screen
|
||||
xx = xx
|
||||
xx = xx*9
|
||||
xx = yy*9
|
||||
xx = xx+3*yy
|
||||
xx = xx/yy
|
||||
xx = -xx
|
||||
@($4000) = @($4000)
|
||||
@($4000) = @($4000) + 2
|
||||
xx = xx | yy
|
||||
xx = xx & yy
|
||||
xx = xx ^ yy
|
||||
xx = (not xx) as byte
|
||||
xx = (~xx) as byte
|
||||
xx++
|
||||
|
||||
ubyte angle
|
||||
|
||||
for angle in 0 to 180 {
|
||||
ubyte xx = math.sinr8u(angle)
|
||||
ubyte yy = math.cosr8u(angle) / 2
|
||||
sys.gfx_plot(xx, yy, 255)
|
||||
}
|
||||
|
||||
repeat {
|
||||
}
|
||||
ubx = not ubx
|
||||
ubx = ~ubx
|
||||
}
|
||||
}
|
||||
|
||||
@ -15,8 +15,6 @@ Currently NO support for 24 or 32 bits integers.
|
||||
Floating point operations are just 'f' typed regular instructions, and additionally there are
|
||||
a few fp conversion instructions to
|
||||
|
||||
*only* LOAD AND STORE instructions have a possible memory operand, all other instructions use only registers or immediate value.
|
||||
|
||||
|
||||
LOAD/STORE
|
||||
----------
|
||||
@ -96,6 +94,7 @@ incm address - memory at address += 1
|
||||
dec reg1 - reg1 = reg1-1
|
||||
decm address - memory at address -= 1
|
||||
neg reg1 - reg1 = sign negation of reg1
|
||||
negm address - sign negate memory at address
|
||||
add reg1, reg2 - reg1 += reg2 (unsigned + signed)
|
||||
sub reg1, reg2 - reg1 -= reg2 (unsigned + signed)
|
||||
mul reg1, reg2 - unsigned multiply reg1 *= reg2 note: byte*byte->byte, no type extension to word!
|
||||
@ -116,7 +115,9 @@ All have type b or w.
|
||||
and reg1, reg2 - reg1 = reg1 bitwise and reg2
|
||||
or reg1, reg2 - reg1 = reg1 bitwise or reg2
|
||||
xor reg1, reg2 - reg1 = reg1 bitwise xor reg2
|
||||
xorm reg1, address - memory = memory bitwise xor reg1
|
||||
not reg1 - reg1 = boolean not of reg1 (0->1 , ~0 -> 0)
|
||||
notm address - memory = boolean not of that memory (0->1 , ~0 -> 0)
|
||||
lsrn reg1, reg2 - reg1 = multi-shift reg1 right by reg2 bits + set Carry to shifted bit
|
||||
asrn reg1, reg2 - reg1 = multi-shift reg1 right by reg2 bits (signed) + set Carry to shifted bit
|
||||
lsln reg1, reg2 - reg1 = multi-shift reg1 left by reg2 bits + set Carry to shifted bit
|
||||
@ -211,6 +212,7 @@ enum class Opcode {
|
||||
DEC,
|
||||
DECM,
|
||||
NEG,
|
||||
NEGM,
|
||||
ADD,
|
||||
SUB,
|
||||
MUL,
|
||||
@ -226,7 +228,9 @@ enum class Opcode {
|
||||
AND,
|
||||
OR,
|
||||
XOR,
|
||||
XORM,
|
||||
NOT,
|
||||
NOTM,
|
||||
ASRN,
|
||||
LSRN,
|
||||
LSLN,
|
||||
@ -277,7 +281,10 @@ val OpcodesWithAddress = setOf(
|
||||
Opcode.STOREZM,
|
||||
Opcode.STOREZX,
|
||||
Opcode.INCM,
|
||||
Opcode.DECM
|
||||
Opcode.DECM,
|
||||
Opcode.NEGM,
|
||||
Opcode.NOTM,
|
||||
Opcode.XORM
|
||||
)
|
||||
|
||||
|
||||
@ -297,7 +304,7 @@ data class Instruction(
|
||||
val fpReg2: Int?=null, // 0-$ffff
|
||||
val value: Int?=null, // 0-$ffff
|
||||
val fpValue: Float?=null,
|
||||
val symbol: List<String>?=null // alternative to value
|
||||
val labelSymbol: List<String>?=null // symbolic label name as alternative to value (so only for Branch/jump/call Instructions!)
|
||||
) {
|
||||
init {
|
||||
val formats = instructionFormats.getValue(opcode)
|
||||
@ -318,11 +325,11 @@ data class Instruction(
|
||||
throw IllegalArgumentException("too many registers (float)")
|
||||
|
||||
if (type==VmDataType.FLOAT) {
|
||||
if(format.fpValue && (fpValue==null && symbol==null))
|
||||
throw IllegalArgumentException("$opcode: missing a fp-value or symbol")
|
||||
if(format.fpValue && (fpValue==null && labelSymbol==null))
|
||||
throw IllegalArgumentException("$opcode: missing a fp-value or labelsymbol")
|
||||
} else {
|
||||
if(format.value && (value==null && symbol==null))
|
||||
throw IllegalArgumentException("$opcode: missing a value or symbol")
|
||||
if(format.value && (value==null && labelSymbol==null))
|
||||
throw IllegalArgumentException("$opcode: missing a value or labelsymbol")
|
||||
if (fpReg1 != null || fpReg2 != null)
|
||||
throw java.lang.IllegalArgumentException("$opcode: integer point instruction can't use floating point registers")
|
||||
}
|
||||
@ -361,7 +368,7 @@ data class Instruction(
|
||||
result.add(it.toString())
|
||||
result.add(",")
|
||||
}
|
||||
symbol?.let {
|
||||
labelSymbol?.let {
|
||||
result.add("_" + it.joinToString("."))
|
||||
}
|
||||
if(result.last() == ",")
|
||||
@ -464,6 +471,7 @@ val instructionFormats = mutableMapOf(
|
||||
Opcode.DEC to InstructionFormat.from("BW,r1"),
|
||||
Opcode.DECM to InstructionFormat.from("BW,v"),
|
||||
Opcode.NEG to InstructionFormat.from("BW,r1 | F,fr1"),
|
||||
Opcode.NEGM to InstructionFormat.from("BW,v | F,v"),
|
||||
Opcode.ADD to InstructionFormat.from("BW,r1,r2 | F,fr1,fr2"),
|
||||
Opcode.SUB to InstructionFormat.from("BW,r1,r2 | F,fr1,fr2"),
|
||||
Opcode.MUL to InstructionFormat.from("BW,r1,r2 | F,fr1,fr2"),
|
||||
@ -478,7 +486,9 @@ val instructionFormats = mutableMapOf(
|
||||
Opcode.AND to InstructionFormat.from("BW,r1,r2"),
|
||||
Opcode.OR to InstructionFormat.from("BW,r1,r2"),
|
||||
Opcode.XOR to InstructionFormat.from("BW,r1,r2"),
|
||||
Opcode.XORM to InstructionFormat.from("BW,r1,v"),
|
||||
Opcode.NOT to InstructionFormat.from("BW,r1"),
|
||||
Opcode.NOTM to InstructionFormat.from("BW,v"),
|
||||
Opcode.ASRN to InstructionFormat.from("BW,r1,r2"),
|
||||
Opcode.LSRN to InstructionFormat.from("BW,r1,r2"),
|
||||
Opcode.LSLN to InstructionFormat.from("BW,r1,r2"),
|
||||
|
||||
@ -17,7 +17,7 @@ class TestInstructions: FunSpec({
|
||||
ins.reg1 shouldBe null
|
||||
ins.reg2 shouldBe null
|
||||
ins.value shouldBe null
|
||||
ins.symbol shouldBe null
|
||||
ins.labelSymbol shouldBe null
|
||||
ins.toString() shouldBe "nop"
|
||||
}
|
||||
|
||||
@ -28,18 +28,18 @@ class TestInstructions: FunSpec({
|
||||
ins.reg1 shouldBe 42
|
||||
ins.reg2 shouldBe null
|
||||
ins.value shouldBe 9999
|
||||
ins.symbol shouldBe null
|
||||
ins.labelSymbol shouldBe null
|
||||
ins.toString() shouldBe "bz.b r42,9999"
|
||||
}
|
||||
|
||||
test("with label") {
|
||||
val ins = Instruction(Opcode.BZ, VmDataType.WORD, reg1=11, symbol = listOf("a","b","c"))
|
||||
val ins = Instruction(Opcode.BZ, VmDataType.WORD, reg1=11, labelSymbol = listOf("a","b","c"))
|
||||
ins.opcode shouldBe Opcode.BZ
|
||||
ins.type shouldBe VmDataType.WORD
|
||||
ins.reg1 shouldBe 11
|
||||
ins.reg2 shouldBe null
|
||||
ins.value shouldBe null
|
||||
ins.symbol shouldBe listOf("a","b","c")
|
||||
ins.labelSymbol shouldBe listOf("a","b","c")
|
||||
ins.toString() shouldBe "bz.w r11,_a.b.c"
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user