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https://github.com/irmen/prog8.git
synced 2024-11-26 11:49:22 +00:00
implement the missing in-place array operators for split word arrays and numeric operand
This commit is contained in:
Irmen de Jong
parent
3535c1acda
commit
1fc79ff6dd
@ -222,7 +222,7 @@ internal class AugmentableAssignmentAsmGen(private val program: PtProgram,
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val index = indexNum.number.toInt()
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if(target.array.splitWords) {
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when(value.kind) {
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SourceStorageKind.LITERALNUMBER -> inplacemodificationSplitWordWithLiteralval(target.asmVarname, index, operator, value.number!!.number.toInt())
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SourceStorageKind.LITERALNUMBER -> inplacemodificationSplitWordWithLiteralval(target.asmVarname, target.datatype, index, operator, value.number!!.number.toInt())
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else -> {
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// TODO: more optimized code for VARIABLE, REGISTER, MEMORY, ARRAY, EXPRESSION in the case of split-word arrays
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val scope = target.origAstTarget?.definingSub()
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@ -672,77 +672,9 @@ internal class AugmentableAssignmentAsmGen(private val program: PtProgram,
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}
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}
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private fun inplacemodificationSplitWordWithLiteralval(arrayVar: String, index: Int, operator: String, value: Int) {
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private fun inplacemodificationSplitWordWithLiteralval(arrayVar: String, dt: DataType, index: Int, operator: String, value: Int) {
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// note: this contains special optimized cases because we know the exact value. Don't replace this with another routine.
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when (operator) {
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"+" -> {
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when {
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value==0 -> {}
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value==1 -> {
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asmgen.out("""
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inc ${arrayVar}_lsb+$index
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bne +
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inc ${arrayVar}_msb+$index
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+""")
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}
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value in 1..0xff -> asmgen.out("""
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lda ${arrayVar}_lsb+$index
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clc
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adc #$value
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sta ${arrayVar}_lsb+$index
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bcc +
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inc ${arrayVar}_msb+$index
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+""")
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value==0x0100 -> asmgen.out(" inc ${arrayVar}_msb+$index")
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value==0x0200 -> asmgen.out(" inc ${arrayVar}_msb+$index | inc ${arrayVar}_msb+$index")
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value==0x0300 -> asmgen.out(" inc ${arrayVar}_msb+$index | inc ${arrayVar}_msb+$index | inc ${arrayVar}_msb+$index")
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value==0x0400 -> asmgen.out(" inc ${arrayVar}_msb+$index | inc ${arrayVar}_msb+$index | inc ${arrayVar}_msb+$index | inc ${arrayVar}_msb+$index")
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value and 255==0 -> asmgen.out(" lda ${arrayVar}_msb+$index | clc | adc #>$value | sta ${arrayVar}_msb+$index")
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else -> asmgen.out("""
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lda ${arrayVar}_lsb+$index
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clc
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adc #<$value
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sta ${arrayVar}_lsb+$index
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lda ${arrayVar}_msb+$index
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adc #>$value
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sta ${arrayVar}_msb+$index""")
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}
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}
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"-" -> {
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when {
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value==0 -> {}
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value==1 -> {
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asmgen.out("""
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lda ${arrayVar}_lsb+$index
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bne +
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dec ${arrayVar}_msb+$index
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+ dec ${arrayVar}_lsb+$index""")
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}
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value in 1..0xff -> asmgen.out("""
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lda ${arrayVar}_lsb+$index
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sec
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sbc #$value
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sta ${arrayVar}_lsb+$index
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bcs +
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dec ${arrayVar}_msb+$index
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+""")
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value==0x0100 -> asmgen.out(" dec ${arrayVar}_msb+$index")
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value==0x0200 -> asmgen.out(" dec ${arrayVar}_msb+$index | dec ${arrayVar}_msb+$index")
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value==0x0300 -> asmgen.out(" dec ${arrayVar}_msb+$index | dec ${arrayVar}_msb+$index | dec ${arrayVar}_msb+$index")
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value==0x0400 -> asmgen.out(" dec ${arrayVar}_msb+$index | dec ${arrayVar}_msb+$index | dec ${arrayVar}_msb+$index | dec ${arrayVar}_msb+$index")
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value and 255==0 -> asmgen.out(" lda ${arrayVar}_msb+$index | sec | sbc #>$value | sta ${arrayVar}_msb+$index")
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else -> asmgen.out("""
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lda ${arrayVar}_lsb+$index
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sec
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sbc #<$value
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sta ${arrayVar}_lsb+$index
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lda ${arrayVar}_msb+$index
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sbc #>$value
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sta ${arrayVar}_msb+$index""")
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}
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}
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else -> TODO("in-place modify split-words array value for operator $operator")
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}
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inplacemodificationSomeWordWithLiteralval("${arrayVar}_lsb+$index", "${arrayVar}_msb+$index", dt, operator, value, null)
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}
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private fun inplacemodificationRegisterAXwithVariable(operator: String, variable: String, varDt: DataType): Boolean {
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@ -1767,40 +1699,46 @@ $shortcutLabel:""")
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}
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}
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private fun inplacemodificationWordWithLiteralval(name: String, dt: DataType, operator: String, value: Int, block: PtBlock?) {
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// note: this contains special optimized cases because we know the exact value. Don't replace this with another routine.
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inplacemodificationSomeWordWithLiteralval(name, name + "+1", dt, operator, value, block)
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}
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private fun inplacemodificationSomeWordWithLiteralval(lsb: String, msb: String, dt: DataType, operator: String, value: Int, block: PtBlock?) {
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when (operator) {
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"+" -> {
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when {
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value==0 -> {}
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value==1 -> {
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asmgen.out("""
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inc $name
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inc $lsb
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bne +
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inc $name+1
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inc $msb
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+""")
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}
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value in 1..0xff -> asmgen.out("""
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lda $name
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lda $lsb
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clc
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adc #$value
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sta $name
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sta $lsb
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bcc +
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inc $name+1
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inc $msb
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+""")
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value==0x0100 -> asmgen.out(" inc $name+1")
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value==0x0200 -> asmgen.out(" inc $name+1 | inc $name+1")
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value==0x0300 -> asmgen.out(" inc $name+1 | inc $name+1 | inc $name+1")
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value==0x0400 -> asmgen.out(" inc $name+1 | inc $name+1 | inc $name+1 | inc $name+1")
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value and 255==0 -> asmgen.out(" lda $name+1 | clc | adc #>$value | sta $name+1")
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value==0x0100 -> asmgen.out(" inc $msb")
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value==0x0200 -> asmgen.out(" inc $msb | inc $msb")
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value==0x0300 -> asmgen.out(" inc $msb | inc $msb | inc $msb")
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value==0x0400 -> asmgen.out(" inc $msb | inc $msb | inc $msb | inc $msb")
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value and 255==0 -> asmgen.out(" lda $msb | clc | adc #>$value | sta $msb")
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else -> asmgen.out("""
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lda $name
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lda $lsb
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clc
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adc #<$value
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sta $name
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lda $name+1
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sta $lsb
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lda $msb
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adc #>$value
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sta $name+1""")
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sta $msb""")
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}
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}
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"-" -> {
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@ -1808,44 +1746,44 @@ $shortcutLabel:""")
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value==0 -> {}
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value==1 -> {
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asmgen.out("""
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lda $name
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lda $lsb
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bne +
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dec $name+1
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+ dec $name""")
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dec $msb
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+ dec $lsb""")
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}
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value in 1..0xff -> asmgen.out("""
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lda $name
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lda $lsb
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sec
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sbc #$value
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sta $name
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sta $lsb
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bcs +
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dec $name+1
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dec $msb
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+""")
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value==0x0100 -> asmgen.out(" dec $name+1")
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value==0x0200 -> asmgen.out(" dec $name+1 | dec $name+1")
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value==0x0300 -> asmgen.out(" dec $name+1 | dec $name+1 | dec $name+1")
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value==0x0400 -> asmgen.out(" dec $name+1 | dec $name+1 | dec $name+1 | dec $name+1")
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value and 255==0 -> asmgen.out(" lda $name+1 | sec | sbc #>$value | sta $name+1")
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value==0x0100 -> asmgen.out(" dec $msb")
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value==0x0200 -> asmgen.out(" dec $msb | dec $msb")
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value==0x0300 -> asmgen.out(" dec $msb | dec $msb | dec $msb")
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value==0x0400 -> asmgen.out(" dec $msb | dec $msb | dec $msb | dec $msb")
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value and 255==0 -> asmgen.out(" lda $msb | sec | sbc #>$value | sta $msb")
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else -> asmgen.out("""
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lda $name
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lda $lsb
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sec
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sbc #<$value
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sta $name
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lda $name+1
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sta $lsb
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lda $msb
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sbc #>$value
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sta $name+1""")
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sta $msb""")
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}
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}
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"*" -> {
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// the mul code works for both signed and unsigned
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if(value in asmgen.optimizedWordMultiplications) {
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asmgen.out(" lda $name | ldy $name+1 | jsr math.mul_word_$value | sta $name | sty $name+1")
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asmgen.out(" lda $lsb | ldy $msb | jsr math.mul_word_$value | sta $lsb | sty $msb")
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} else {
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if(block?.options?.veraFxMuls==true)
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// cx16 verafx hardware mul
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asmgen.out("""
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lda $name
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ldy $name+1
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lda $lsb
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ldy $msb
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sta cx16.r0
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sty cx16.r0+1
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lda #<$value
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@ -1853,19 +1791,19 @@ $shortcutLabel:""")
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sta cx16.r1
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sty cx16.r1+1
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jsr verafx.muls
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sta $name
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sty $name+1""")
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sta $lsb
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sty $msb""")
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else
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asmgen.out("""
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lda $name
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lda $lsb
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sta math.multiply_words.multiplier
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lda $name+1
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lda $msb
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sta math.multiply_words.multiplier+1
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lda #<$value
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ldy #>$value
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jsr math.multiply_words
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sta $name
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sty $name+1""")
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sta $lsb
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sty $msb""")
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}
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}
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"/" -> {
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@ -1873,28 +1811,28 @@ $shortcutLabel:""")
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throw AssemblyError("division by zero")
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if(dt==DataType.WORD) {
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asmgen.out("""
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lda $name
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ldy $name+1
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lda $lsb
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ldy $msb
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sta P8ZP_SCRATCH_W1
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sty P8ZP_SCRATCH_W1+1
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lda #<$value
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ldy #>$value
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jsr math.divmod_w_asm
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sta $name
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sty $name+1
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sta $lsb
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sty $msb
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""")
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}
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else {
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asmgen.out("""
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lda $name
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ldy $name+1
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lda $lsb
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ldy $msb
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sta P8ZP_SCRATCH_W1
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sty P8ZP_SCRATCH_W1+1
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lda #<$value
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ldy #>$value
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jsr math.divmod_uw_asm
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sta $name
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sty $name+1
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sta $lsb
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sty $msb
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""")
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}
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}
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@ -1904,8 +1842,8 @@ $shortcutLabel:""")
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if(dt==DataType.WORD)
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throw AssemblyError("remainder of signed integers is not properly defined/implemented, use unsigned instead")
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asmgen.out("""
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lda $name
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ldy $name+1
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lda $lsb
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ldy $msb
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sta P8ZP_SCRATCH_W1
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sty P8ZP_SCRATCH_W1+1
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lda #<$value
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@ -1913,33 +1851,33 @@ $shortcutLabel:""")
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jsr math.divmod_uw_asm
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lda P8ZP_SCRATCH_W2
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ldy P8ZP_SCRATCH_W2+1
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sta $name
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sty $name+1
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sta $lsb
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sty $msb
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""")
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}
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"<<" -> {
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when {
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value>=16 -> {
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if(asmgen.isTargetCpu(CpuType.CPU65c02))
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asmgen.out(" stz $name | stz $name+1")
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asmgen.out(" stz $lsb | stz $msb")
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else
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asmgen.out(" lda #0 | sta $name | sta $name+1")
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asmgen.out(" lda #0 | sta $lsb | sta $msb")
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}
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value==8 -> {
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asmgen.out(" lda $name | sta $name+1")
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asmgen.out(" lda $lsb | sta $msb")
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if(asmgen.isTargetCpu(CpuType.CPU65c02))
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asmgen.out(" stz $name")
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asmgen.out(" stz $lsb")
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else
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asmgen.out(" lda #0 | sta $name")
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asmgen.out(" lda #0 | sta $lsb")
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}
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value>3 -> asmgen.out("""
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ldy #$value
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- asl $name
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rol $name+1
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- asl $lsb
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rol $msb
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dey
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bne -
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""")
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else -> repeat(value) { asmgen.out(" asl $name | rol $name+1") }
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else -> repeat(value) { asmgen.out(" asl $lsb | rol $msb") }
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}
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}
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">>" -> {
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@ -1948,54 +1886,54 @@ $shortcutLabel:""")
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when {
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value>=16 -> {
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if(asmgen.isTargetCpu(CpuType.CPU65c02))
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asmgen.out(" stz $name | stz $name+1")
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asmgen.out(" stz $lsb | stz $msb")
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else
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asmgen.out(" lda #0 | sta $name | sta $name+1")
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asmgen.out(" lda #0 | sta $lsb | sta $msb")
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}
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value==8 -> {
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asmgen.out(" lda $name+1 | sta $name")
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asmgen.out(" lda $msb | sta $lsb")
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if(asmgen.isTargetCpu(CpuType.CPU65c02))
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asmgen.out(" stz $name+1")
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asmgen.out(" stz $msb")
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else
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asmgen.out(" lda #0 | sta $name+1")
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asmgen.out(" lda #0 | sta $msb")
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}
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value>2 -> asmgen.out("""
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ldy #$value
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- lsr $name+1
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ror $name
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- lsr $msb
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ror $lsb
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dey
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bne -""")
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else -> repeat(value) { asmgen.out(" lsr $name+1 | ror $name")}
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else -> repeat(value) { asmgen.out(" lsr $msb | ror $lsb")}
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}
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} else {
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when {
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value>=16 -> asmgen.out("""
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lda $name+1
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lda $msb
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bmi +
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lda #0
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beq ++
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+ lda #-1
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+ sta $name
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sta $name+1""")
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+ sta $lsb
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sta $msb""")
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value==8 -> asmgen.out("""
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lda $name+1
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sta $name
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lda $msb
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sta $lsb
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bmi +
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lda #0
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- sta $name+1
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- sta $msb
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beq ++
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+ lda #-1
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sta $name+1
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sta $msb
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+""")
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value>2 -> asmgen.out("""
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ldy #$value
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- lda $name+1
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- lda $msb
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asl a
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ror $name+1
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ror $name
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ror $msb
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ror $lsb
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dey
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bne -""")
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else -> repeat(value) { asmgen.out(" lda $name+1 | asl a | ror $name+1 | ror $name") }
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else -> repeat(value) { asmgen.out(" lda $msb | asl a | ror $msb | ror $lsb") }
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}
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}
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}
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@ -2004,165 +1942,165 @@ $shortcutLabel:""")
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when {
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value == 0 -> {
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if(asmgen.isTargetCpu(CpuType.CPU65c02))
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asmgen.out(" stz $name | stz $name+1")
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asmgen.out(" stz $lsb | stz $msb")
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else
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asmgen.out(" lda #0 | sta $name | sta $name+1")
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asmgen.out(" lda #0 | sta $lsb | sta $msb")
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}
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value == 0x00ff -> {
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if(asmgen.isTargetCpu(CpuType.CPU65c02))
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asmgen.out(" stz $name+1")
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asmgen.out(" stz $msb")
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else
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asmgen.out(" lda #0 | sta $name+1")
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asmgen.out(" lda #0 | sta $msb")
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}
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value == 0xff00 -> {
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if(asmgen.isTargetCpu(CpuType.CPU65c02))
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asmgen.out(" stz $name")
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asmgen.out(" stz $lsb")
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else
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asmgen.out(" lda #0 | sta $name")
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asmgen.out(" lda #0 | sta $lsb")
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}
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value and 255 == 0 -> {
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if(asmgen.isTargetCpu(CpuType.CPU65c02))
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asmgen.out(" stz $name")
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asmgen.out(" stz $lsb")
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else
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asmgen.out(" lda #0 | sta $name")
|
||||
asmgen.out(" lda $name+1 | and #>$value | sta $name+1")
|
||||
asmgen.out(" lda #0 | sta $lsb")
|
||||
asmgen.out(" lda $msb | and #>$value | sta $msb")
|
||||
}
|
||||
value < 0x0100 -> {
|
||||
immediateAndInplace(name, value)
|
||||
immediateAndInplace(lsb, value)
|
||||
if(asmgen.isTargetCpu(CpuType.CPU65c02))
|
||||
asmgen.out(" stz $name+1")
|
||||
asmgen.out(" stz $msb")
|
||||
else
|
||||
asmgen.out(" lda #0 | sta $name+1")
|
||||
asmgen.out(" lda #0 | sta $msb")
|
||||
}
|
||||
else -> asmgen.out(" lda $name | and #<$value | sta $name | lda $name+1 | and #>$value | sta $name+1")
|
||||
else -> asmgen.out(" lda $lsb | and #<$value | sta $lsb | lda $msb | and #>$value | sta $msb")
|
||||
}
|
||||
}
|
||||
"|" -> {
|
||||
when {
|
||||
value == 0 -> {}
|
||||
value and 255 == 0 -> asmgen.out(" lda $name+1 | ora #>$value | sta $name+1")
|
||||
value < 0x0100 -> immediateOrInplace(name, value)
|
||||
else -> asmgen.out(" lda $name | ora #<$value | sta $name | lda $name+1 | ora #>$value | sta $name+1")
|
||||
value and 255 == 0 -> asmgen.out(" lda $msb | ora #>$value | sta $msb")
|
||||
value < 0x0100 -> immediateOrInplace(lsb, value)
|
||||
else -> asmgen.out(" lda $lsb | ora #<$value | sta $lsb | lda $msb | ora #>$value | sta $msb")
|
||||
}
|
||||
}
|
||||
"^" -> {
|
||||
when {
|
||||
value == 0 -> {}
|
||||
value and 255 == 0 -> asmgen.out(" lda $name+1 | eor #>$value | sta $name+1")
|
||||
value < 0x0100 -> asmgen.out(" lda $name | eor #$value | sta $name")
|
||||
else -> asmgen.out(" lda $name | eor #<$value | sta $name | lda $name+1 | eor #>$value | sta $name+1")
|
||||
value and 255 == 0 -> asmgen.out(" lda $msb | eor #>$value | sta $msb")
|
||||
value < 0x0100 -> asmgen.out(" lda $lsb | eor #$value | sta $lsb")
|
||||
else -> asmgen.out(" lda $lsb | eor #<$value | sta $lsb | lda $msb | eor #>$value | sta $msb")
|
||||
}
|
||||
}
|
||||
"==" -> {
|
||||
asmgen.out("""
|
||||
lda $name
|
||||
lda $lsb
|
||||
cmp #<$value
|
||||
bne +
|
||||
lda $name+1
|
||||
lda $msb
|
||||
cmp #>$value
|
||||
bne +
|
||||
lda #1
|
||||
bne ++
|
||||
+ lda #0
|
||||
+ sta $name
|
||||
+ sta $lsb
|
||||
lda #0
|
||||
sta $name+1""")
|
||||
sta $msb""")
|
||||
}
|
||||
"!=" -> {
|
||||
asmgen.out("""
|
||||
lda $name
|
||||
lda $lsb
|
||||
cmp #<$value
|
||||
bne +
|
||||
lda $name+1
|
||||
lda $msb
|
||||
cmp #>$value
|
||||
bne +
|
||||
lda #0
|
||||
beq ++
|
||||
+ lda #1
|
||||
+ sta $name
|
||||
+ sta $lsb
|
||||
lda #0
|
||||
sta $name+1""")
|
||||
sta $msb""")
|
||||
}
|
||||
"<" -> {
|
||||
if(dt==DataType.UWORD) {
|
||||
asmgen.out("""
|
||||
lda $name+1
|
||||
lda $msb
|
||||
cmp #>$value
|
||||
bcc ++
|
||||
bne +
|
||||
lda $name
|
||||
lda $lsb
|
||||
cmp #<$value
|
||||
bcc ++
|
||||
+ lda #0 ; false
|
||||
sta $name
|
||||
sta $name+1
|
||||
sta $lsb
|
||||
sta $msb
|
||||
beq ++
|
||||
+ lda #1 ; true
|
||||
sta $name
|
||||
sta $lsb
|
||||
lda #0
|
||||
sta $name+1
|
||||
sta $msb
|
||||
+""")
|
||||
}
|
||||
else {
|
||||
// signed
|
||||
asmgen.out("""
|
||||
lda $name
|
||||
lda $lsb
|
||||
cmp #<$value
|
||||
lda $name+1
|
||||
lda $msb
|
||||
sbc #>$value
|
||||
bvc +
|
||||
eor #$80
|
||||
+ bmi +
|
||||
lda #0
|
||||
sta $name
|
||||
sta $name+1
|
||||
sta $lsb
|
||||
sta $msb
|
||||
beq ++
|
||||
+ lda #1 ; true
|
||||
sta $name
|
||||
sta $lsb
|
||||
lda #0
|
||||
sta $name+1
|
||||
sta $msb
|
||||
+""")
|
||||
}
|
||||
}
|
||||
"<=" -> {
|
||||
if(dt==DataType.UWORD) {
|
||||
asmgen.out("""
|
||||
lda $name+1
|
||||
lda $msb
|
||||
cmp #>$value
|
||||
beq +
|
||||
bcc ++
|
||||
- lda #0 ; false
|
||||
sta $name
|
||||
sta $name+1
|
||||
sta $lsb
|
||||
sta $msb
|
||||
beq +++
|
||||
+ lda $name ; next
|
||||
+ lda $lsb ; next
|
||||
cmp #<$value
|
||||
bcc +
|
||||
bne -
|
||||
+ lda #1 ; true
|
||||
sta $name
|
||||
sta $lsb
|
||||
lda #0
|
||||
sta $name+1
|
||||
sta $msb
|
||||
+""")
|
||||
}
|
||||
else {
|
||||
// signed
|
||||
asmgen.out("""
|
||||
lda #<$value
|
||||
cmp $name
|
||||
cmp $lsb
|
||||
lda #>$value
|
||||
sbc $name+1
|
||||
sbc $msb
|
||||
bvc +
|
||||
eor #$80
|
||||
+ bpl +
|
||||
lda #0
|
||||
sta $name
|
||||
sta $name+1
|
||||
sta $lsb
|
||||
sta $msb
|
||||
beq ++
|
||||
+ lda #1
|
||||
sta $name
|
||||
sta $lsb
|
||||
lda #0
|
||||
sta $name+1
|
||||
sta $msb
|
||||
+""")
|
||||
}
|
||||
}
|
||||
@ -2171,40 +2109,40 @@ $shortcutLabel:""")
|
||||
if(dt==DataType.UWORD) {
|
||||
asmgen.out("""
|
||||
lda #>$value
|
||||
cmp $name+1
|
||||
cmp $msb
|
||||
bcc ++
|
||||
bne +
|
||||
lda #<$value
|
||||
cmp $name
|
||||
cmp $lsb
|
||||
bcc ++
|
||||
+ lda #0 ; false
|
||||
sta $name
|
||||
sta $name+1
|
||||
sta $lsb
|
||||
sta $msb
|
||||
beq ++
|
||||
+ lda #1 ; true
|
||||
sta $name
|
||||
sta $lsb
|
||||
lda #0
|
||||
sta $name+1
|
||||
sta $msb
|
||||
+""")
|
||||
}
|
||||
else {
|
||||
// signed
|
||||
asmgen.out("""
|
||||
lda #<$value
|
||||
cmp $name
|
||||
cmp $lsb
|
||||
lda #>$value
|
||||
sbc $name+1
|
||||
sbc $msb
|
||||
bvc +
|
||||
eor #$80
|
||||
+ bmi +
|
||||
lda #0
|
||||
sta $name
|
||||
sta $name+1
|
||||
sta $lsb
|
||||
sta $msb
|
||||
beq ++
|
||||
+ lda #1 ; true
|
||||
sta $name
|
||||
sta $lsb
|
||||
lda #0
|
||||
sta $name+1
|
||||
sta $msb
|
||||
+""")
|
||||
}
|
||||
}
|
||||
@ -2213,41 +2151,41 @@ $shortcutLabel:""")
|
||||
if(dt==DataType.UWORD) {
|
||||
asmgen.out("""
|
||||
lda #>$value
|
||||
cmp $name+1
|
||||
cmp $msb
|
||||
beq +
|
||||
bcc ++
|
||||
- lda #0 ; false
|
||||
sta $name
|
||||
sta $name+1
|
||||
sta $lsb
|
||||
sta $msb
|
||||
beq +++
|
||||
+ lda #<$value ; next
|
||||
cmp $name
|
||||
cmp $lsb
|
||||
bcc +
|
||||
bne -
|
||||
+ lda #1 ; true
|
||||
sta $name
|
||||
sta $lsb
|
||||
lda #0
|
||||
sta $name+1
|
||||
sta $msb
|
||||
+""")
|
||||
}
|
||||
else {
|
||||
// signed
|
||||
asmgen.out("""
|
||||
lda $name
|
||||
lda $lsb
|
||||
cmp #<$value
|
||||
lda $name+1
|
||||
lda $msb
|
||||
sbc #>$value
|
||||
bvc +
|
||||
eor #$80
|
||||
+ bpl +
|
||||
lda #0
|
||||
sta $name
|
||||
sta $name+1
|
||||
sta $lsb
|
||||
sta $msb
|
||||
beq ++
|
||||
+ lda #1
|
||||
sta $name
|
||||
sta $lsb
|
||||
lda #0
|
||||
sta $name+1
|
||||
sta $msb
|
||||
+""")
|
||||
}
|
||||
}
|
||||
|
||||
@ -1,9 +1,6 @@
|
||||
TODO
|
||||
====
|
||||
|
||||
make bitshift2.p8 runnable on VM
|
||||
bitshift2.p8 has many errors (was ok on 10.2 before bool merge)
|
||||
|
||||
...
|
||||
|
||||
|
||||
@ -12,6 +9,7 @@ Future Things and Ideas
|
||||
Compiler:
|
||||
|
||||
- IR: add TEST instruction to test memory content and set N/Z flags, without affecting any register. Replace all LOADM+CMPI #0 / LOAD #0+LOADM+CMP+BRANCH by this instruction
|
||||
- IR: implement missing operators in AssignmentGen (array shifts etc)
|
||||
- can we support signed % (remainder) somehow?
|
||||
- instead of copy-pasting inline asmsubs, make them into a 64tass macro and use that instead.
|
||||
that will allow them to be reused from custom user written assembly code as well.
|
||||
|
||||
@ -3,23 +3,25 @@
|
||||
%option no_sysinit
|
||||
|
||||
main {
|
||||
bool @shared var1, var2
|
||||
bool[2] barray = [false, true]
|
||||
ubyte success
|
||||
|
||||
sub start() {
|
||||
no_else()
|
||||
}
|
||||
uword[3] uwarray = [1111,2222,3333]
|
||||
uword[3] @split uwarray_s = [1111,2222,3333]
|
||||
ubyte[3] array = [11,22,33]
|
||||
|
||||
sub no_else() {
|
||||
txt.print("bool no_else: ")
|
||||
success=0
|
||||
rol(array[1])
|
||||
array[1] <<=1
|
||||
ror(array[1])
|
||||
array[1] >>=1
|
||||
|
||||
var1=true
|
||||
var2=false
|
||||
rol(uwarray[1])
|
||||
uwarray[1] <<=1
|
||||
ror(uwarray[1])
|
||||
uwarray[1] >>=1
|
||||
|
||||
if var1!=var2
|
||||
txt.print("yes")
|
||||
rol(uwarray_s[1])
|
||||
uwarray_s[1] *=3
|
||||
ror(uwarray_s[1])
|
||||
uwarray_s[1] *=3
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user